From patchwork Thu Apr 18 17:10:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nirmoy Das X-Patchwork-Id: 13635156 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BE76AC04FF8 for ; Thu, 18 Apr 2024 17:25:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DC264113E4A; Thu, 18 Apr 2024 17:24:59 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="dIbg1GZm"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 334EE113E49; Thu, 18 Apr 2024 17:24:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713461098; x=1744997098; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=NzulTEbpYhzMpFTXlJcvih1nCohXnoYCUt+j0mfdPsM=; b=dIbg1GZmmUi+VDvzeKTu+jAcwmbS5qPsHpCNFehtdlX/J/7JaxbVTMuk 01KEQSQkEwmZwgtI/WPqSdpDWAh8zde7BLdN8MaYQSzDKrAW23Cug7BfO 0G0It5bk/OifZKIfyf1mjGhUKai2+yGlybMqZIU6ucNRQ5LZAVI82vyPd B/2oRRUKgdFVxpWpf7z6a4dmTbTDM2yM93fDmhSCzyawj2TWp0w7WNFSo CXzKNVI0x6uFl0/KVZjsqir0lgH0yb/S041pERut+kSPPWusH7oG2fk0l VIt53KIc9dqL4xl5UAk7LoPNw48srCO54+jEL9xOr1YjYHccz0s2Qizkk w==; X-CSE-ConnectionGUID: lBDWLPUwSQCvGdFvzoZ6WQ== X-CSE-MsgGUID: Knq+D79/QKSPvBMvzvW5NA== X-IronPort-AV: E=McAfee;i="6600,9927,11047"; a="34424184" X-IronPort-AV: E=Sophos;i="6.07,212,1708416000"; d="scan'208";a="34424184" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2024 10:24:57 -0700 X-CSE-ConnectionGUID: 0Ca4RiXNSV2T+TsxGQbyvA== X-CSE-MsgGUID: DEZlZcehQX+jSMK6N/lIyQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,212,1708416000"; d="scan'208";a="27881192" Received: from nirmoyda-desk.igk.intel.com ([10.102.138.190]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2024 10:24:56 -0700 From: Nirmoy Das To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, John.C.Harrison@Intel.com, Nirmoy Das Subject: [PATCH 1/3] drm/i915: Refactor confusing __intel_gt_reset() Date: Thu, 18 Apr 2024 19:10:53 +0200 Message-ID: <20240418171055.31371-1-nirmoy.das@intel.com> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 Organization: Intel Deutschland GmbH, Registered Address: Am Campeon 10, 85579 Neubiberg, Germany, Commercial Register: Amtsgericht Muenchen HRB 186928 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" __intel_gt_reset() is really for resetting engines though the name might suggest something else. So add two helper functions to remove confusions with no functional changes. Signed-off-by: Nirmoy Das --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- .../drm/i915/gt/intel_execlists_submission.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 +- drivers/gpu/drm/i915/gt/intel_reset.c | 43 ++++++++++++++----- drivers/gpu/drm/i915/gt/intel_reset.h | 3 +- drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +- drivers/gpu/drm/i915/i915_driver.c | 2 +- 8 files changed, 41 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index 8c44af1c3451..5c8e9ee3b008 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -678,7 +678,7 @@ void intel_engines_release(struct intel_gt *gt) */ GEM_BUG_ON(intel_gt_pm_is_awake(gt)); if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) - __intel_gt_reset(gt, ALL_ENGINES); + intel_gt_reset_all_engines(gt); /* Decouple the backend; but keep the layout for late GPU resets */ for_each_engine(engine, gt, id) { diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 355aab5b38ba..21829439e686 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2898,7 +2898,7 @@ static void enable_error_interrupt(struct intel_engine_cs *engine) drm_err(&engine->i915->drm, "engine '%s' resumed still in error: %08x\n", engine->name, status); - __intel_gt_reset(engine->gt, engine->mask); + intel_gt_reset_engine(engine); } /* diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 580b5141ce1e..626b166e67ef 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -832,7 +832,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt) /* Scrub all HW state upon release */ with_intel_runtime_pm(gt->uncore->rpm, wakeref) - __intel_gt_reset(gt, ALL_ENGINES); + intel_gt_reset_all_engines(gt); } void intel_gt_driver_release(struct intel_gt *gt) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c index 220ac4f92edf..c08fdb65cc69 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c @@ -159,7 +159,7 @@ static bool reset_engines(struct intel_gt *gt) if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) return false; - return __intel_gt_reset(gt, ALL_ENGINES) == 0; + return intel_gt_reset_all_engines(gt) == 0; } static void gt_sanitize(struct intel_gt *gt, bool force) diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index c8e9aa41fdea..b825daace58e 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -764,7 +764,7 @@ wa_14015076503_end(struct intel_gt *gt, intel_engine_mask_t engine_mask) HECI_H_GS1_ER_PREP, 0); } -int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask) +static int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask) { const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1; reset_func reset; @@ -795,6 +795,34 @@ int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask) return ret; } +/** + * intel_gt_reset_all_engines() - Reset all engines in the given gt. + * @gt: the GT to reset all engines for. + * + * This function resets all engines within the given gt. + * + * Returns: + * Zero on success, negative error code on failure. + */ +int intel_gt_reset_all_engines(struct intel_gt *gt) +{ + return __intel_gt_reset(gt, ALL_ENGINES); +} + +/** + * intel_gt_reset_engine() - Reset a specific engine within a gt. + * @engine: engine to be reset. + * + * This function resets the specified engine within a gt. + * + * Returns: + * Zero on success, negative error code on failure. + */ +int intel_gt_reset_engine(struct intel_engine_cs *engine) +{ + return __intel_gt_reset(engine->gt, engine->mask); +} + bool intel_has_gpu_reset(const struct intel_gt *gt) { if (!gt->i915->params.reset) @@ -978,7 +1006,7 @@ static void __intel_gt_set_wedged(struct intel_gt *gt) /* Even if the GPU reset fails, it should still stop the engines */ if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) - __intel_gt_reset(gt, ALL_ENGINES); + intel_gt_reset_all_engines(gt); for_each_engine(engine, gt, id) engine->submit_request = nop_submit_request; @@ -1089,7 +1117,7 @@ static bool __intel_gt_unset_wedged(struct intel_gt *gt) /* We must reset pending GPU events before restoring our submission */ ok = !HAS_EXECLISTS(gt->i915); /* XXX better agnosticism desired */ if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) - ok = __intel_gt_reset(gt, ALL_ENGINES) == 0; + ok = intel_gt_reset_all_engines(gt) == 0; if (!ok) { /* * Warn CI about the unrecoverable wedged condition. @@ -1133,10 +1161,10 @@ static int do_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask) { int err, i; - err = __intel_gt_reset(gt, ALL_ENGINES); + err = intel_gt_reset_all_engines(gt); for (i = 0; err && i < RESET_MAX_RETRIES; i++) { msleep(10 * (i + 1)); - err = __intel_gt_reset(gt, ALL_ENGINES); + err = intel_gt_reset_all_engines(gt); } if (err) return err; @@ -1270,11 +1298,6 @@ void intel_gt_reset(struct intel_gt *gt, goto finish; } -static int intel_gt_reset_engine(struct intel_engine_cs *engine) -{ - return __intel_gt_reset(engine->gt, engine->mask); -} - int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg) { struct intel_gt *gt = engine->gt; diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h index f615b30b81c5..c00de353075c 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.h +++ b/drivers/gpu/drm/i915/gt/intel_reset.h @@ -54,7 +54,8 @@ int intel_gt_terminally_wedged(struct intel_gt *gt); void intel_gt_set_wedged_on_init(struct intel_gt *gt); void intel_gt_set_wedged_on_fini(struct intel_gt *gt); -int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask); +int intel_gt_reset_engine(struct intel_engine_cs *engine); +int intel_gt_reset_all_engines(struct intel_gt *gt); int intel_reset_guc(struct intel_gt *gt); diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c index f40de408cd3a..2cfc23c58e90 100644 --- a/drivers/gpu/drm/i915/gt/selftest_reset.c +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c @@ -281,7 +281,7 @@ static int igt_atomic_reset(void *arg) awake = reset_prepare(gt); p->critical_section_begin(); - err = __intel_gt_reset(gt, ALL_ENGINES); + err = intel_gt_reset_all_engines(gt); p->critical_section_end(); reset_finish(gt, awake); diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index 4b9233c07a22..622a24305bc2 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -202,7 +202,7 @@ static void sanitize_gpu(struct drm_i915_private *i915) unsigned int i; for_each_gt(gt, i915, i) - __intel_gt_reset(gt, ALL_ENGINES); + intel_gt_reset_all_engines(gt); } } From patchwork Thu Apr 18 17:10:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nirmoy Das X-Patchwork-Id: 13635157 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46510C4345F for ; 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X-CSE-ConnectionGUID: EWW/Ub+gQXiwir68erHy4g== X-CSE-MsgGUID: 9dclE1o3S+CnQLiuZTq7Fg== X-IronPort-AV: E=McAfee;i="6600,9927,11047"; a="34424187" X-IronPort-AV: E=Sophos;i="6.07,212,1708416000"; d="scan'208";a="34424187" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2024 10:24:58 -0700 X-CSE-ConnectionGUID: 8VJbQQm6RXSIKmQeyUempw== X-CSE-MsgGUID: 6HFtN6qST/OInAACMH8gjA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,212,1708416000"; d="scan'208";a="27881196" Received: from nirmoyda-desk.igk.intel.com ([10.102.138.190]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2024 10:24:58 -0700 From: Nirmoy Das To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, John.C.Harrison@Intel.com, Nirmoy Das Subject: [PATCH 2/3] drm/i915 Rename intel_engine_reset to intel_gt_engine_recover Date: Thu, 18 Apr 2024 19:10:54 +0200 Message-ID: <20240418171055.31371-2-nirmoy.das@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240418171055.31371-1-nirmoy.das@intel.com> References: <20240418171055.31371-1-nirmoy.das@intel.com> MIME-Version: 1.0 Organization: Intel Deutschland GmbH, Registered Address: Am Campeon 10, 85579 Neubiberg, Germany, Commercial Register: Amtsgericht Muenchen HRB 186928 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" intel_engine_reset() not only reset a engine but also tries to recover it so give it a proper name without any functional changes. Signed-off-by: Nirmoy Das --- .../drm/i915/gem/selftests/i915_gem_context.c | 2 +- .../drm/i915/gt/intel_execlists_submission.c | 2 +- drivers/gpu/drm/i915/gt/intel_reset.c | 4 ++-- drivers/gpu/drm/i915/gt/intel_reset.h | 4 ++-- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 20 +++++++++---------- drivers/gpu/drm/i915/gt/selftest_mocs.c | 4 ++-- drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +- .../gpu/drm/i915/gt/selftest_workarounds.c | 6 +++--- 8 files changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c index 89d4dc8b60c6..4f4cde55f621 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c @@ -1171,7 +1171,7 @@ __sseu_finish(const char *name, int ret = 0; if (flags & TEST_RESET) { - ret = intel_engine_reset(ce->engine, "sseu"); + ret = intel_gt_engine_recover(ce->engine, "sseu"); if (ret) goto out; } diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 21829439e686..9485a622a704 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2404,7 +2404,7 @@ static void execlists_reset(struct intel_engine_cs *engine, const char *msg) ring_set_paused(engine, 1); /* Freeze the current request in place */ execlists_capture(engine); - intel_engine_reset(engine, msg); + intel_gt_engine_recover(engine, msg); tasklet_enable(&engine->sched_engine->tasklet); clear_and_wake_up_bit(bit, lock); diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index b825daace58e..6504e8ba9c58 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -1348,7 +1348,7 @@ int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg) } /** - * intel_engine_reset - reset GPU engine to recover from a hang + * intel_gt_engine_recover - reset GPU engine to recover from a hang * @engine: engine to reset * @msg: reason for GPU reset; or NULL for no drm_notice() * @@ -1360,7 +1360,7 @@ int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg) * - reset engine (which will force the engine to idle) * - re-init/configure engine */ -int intel_engine_reset(struct intel_engine_cs *engine, const char *msg) +int intel_gt_engine_recover(struct intel_engine_cs *engine, const char *msg) { int err; diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h index c00de353075c..be984357bf27 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.h +++ b/drivers/gpu/drm/i915/gt/intel_reset.h @@ -31,8 +31,8 @@ void intel_gt_handle_error(struct intel_gt *gt, void intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask, const char *reason); -int intel_engine_reset(struct intel_engine_cs *engine, - const char *reason); +int intel_gt_engine_recover(struct intel_engine_cs *engine, + const char *reason); int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *reason); diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c index 9ce8ff1c04fe..9bfda3f2bd24 100644 --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c @@ -495,9 +495,9 @@ static int igt_reset_nop_engine(void *arg) i915_request_add(rq); } - err = intel_engine_reset(engine, NULL); + err = intel_gt_engine_recover(engine, NULL); if (err) { - pr_err("intel_engine_reset(%s) failed, err:%d\n", + pr_err("intel_gt_engine_recover(%s) failed, err:%d\n", engine->name, err); break; } @@ -574,7 +574,7 @@ static int igt_reset_fail_engine(void *arg) >->reset.flags)); force_reset_timeout(engine); - err = intel_engine_reset(engine, NULL); + err = intel_gt_engine_recover(engine, NULL); cancel_reset_timeout(engine); if (err == 0) /* timeouts only generated on gen8+ */ goto skip; @@ -623,9 +623,9 @@ static int igt_reset_fail_engine(void *arg) } if (count & 1) { - err = intel_engine_reset(engine, NULL); + err = intel_gt_engine_recover(engine, NULL); if (err) { - GEM_TRACE_ERR("intel_engine_reset(%s) failed, err:%d\n", + GEM_TRACE_ERR("intel_gt_engine_recover(%s) failed, err:%d\n", engine->name, err); GEM_TRACE_DUMP(); i915_request_put(last); @@ -633,10 +633,10 @@ static int igt_reset_fail_engine(void *arg) } } else { force_reset_timeout(engine); - err = intel_engine_reset(engine, NULL); + err = intel_gt_engine_recover(engine, NULL); cancel_reset_timeout(engine); if (err != -ETIMEDOUT) { - pr_err("intel_engine_reset(%s) did not fail, err:%d\n", + pr_err("intel_gt_engine_recover(%s) did not fail, err:%d\n", engine->name, err); i915_request_put(last); break; @@ -765,9 +765,9 @@ static int __igt_reset_engine(struct intel_gt *gt, bool active) } if (!using_guc) { - err = intel_engine_reset(engine, NULL); + err = intel_gt_engine_recover(engine, NULL); if (err) { - pr_err("intel_engine_reset(%s) failed, err:%d\n", + pr_err("intel_gt_engine_recover(%s) failed, err:%d\n", engine->name, err); goto skip; } @@ -1085,7 +1085,7 @@ static int __igt_reset_engines(struct intel_gt *gt, } if (!using_guc) { - err = intel_engine_reset(engine, NULL); + err = intel_gt_engine_recover(engine, NULL); if (err) { pr_err("i915_reset_engine(%s:%s): failed, err=%d\n", engine->name, test_name, err); diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c index d73e438fb85f..b7b15dd3163f 100644 --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c @@ -336,7 +336,7 @@ static int active_engine_reset(struct intel_context *ce, err = request_add_spin(rq, &spin); if (err == 0 && !using_guc) - err = intel_engine_reset(ce->engine, reason); + err = intel_gt_engine_recover(ce->engine, reason); /* Ensure the reset happens and kills the engine */ if (err == 0) @@ -356,7 +356,7 @@ static int __live_mocs_reset(struct live_mocs *mocs, if (intel_has_reset_engine(gt)) { if (!using_guc) { - err = intel_engine_reset(ce->engine, "mocs"); + err = intel_gt_engine_recover(ce->engine, "mocs"); if (err) return err; diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c index 2cfc23c58e90..9eaa1aed9f58 100644 --- a/drivers/gpu/drm/i915/gt/selftest_reset.c +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c @@ -115,7 +115,7 @@ __igt_reset_stolen(struct intel_gt *gt, } else { for_each_engine(engine, gt, id) { if (mask & engine->mask) - intel_engine_reset(engine, NULL); + intel_gt_engine_recover(engine, NULL); } } diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index 14a8b25b6204..eb7516c7cb56 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -256,7 +256,7 @@ static int do_device_reset(struct intel_engine_cs *engine) static int do_engine_reset(struct intel_engine_cs *engine) { - return intel_engine_reset(engine, "live_workarounds"); + return intel_gt_engine_recover(engine, "live_workarounds"); } static int do_guc_reset(struct intel_engine_cs *engine) @@ -1282,7 +1282,7 @@ live_engine_reset_workarounds(void *arg) goto err; } - ret = intel_engine_reset(engine, "live_workarounds:idle"); + ret = intel_gt_engine_recover(engine, "live_workarounds:idle"); if (ret) { pr_err("%s: Reset failed while idle\n", engine->name); goto err; @@ -1320,7 +1320,7 @@ live_engine_reset_workarounds(void *arg) } if (!using_guc) { - ret = intel_engine_reset(engine, "live_workarounds:active"); + ret = intel_gt_engine_recover(engine, "live_workarounds:active"); if (ret) { pr_err("%s: Reset failed on an active spinner\n", engine->name); From patchwork Thu Apr 18 17:10:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nirmoy Das X-Patchwork-Id: 13635158 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 27CEAC4345F for ; Thu, 18 Apr 2024 17:25:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 30455113E4D; Thu, 18 Apr 2024 17:25:08 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Mp0T9OKe"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6714A113E4B; Thu, 18 Apr 2024 17:25:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713461100; x=1744997100; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vf74C2S4H0v6XCcLPinYzE4nwsFxaMi/ZbRHUe9X3Gk=; b=Mp0T9OKetzo3N111QvEJgtU0i3x2TaRsezKPH7tImcFA41W++jU2nFpp 6XHNdq4qNVAydr4sOtc+XwL7tG+IkLwPnQvH9c8GWnOg6q8La2tWHKNW4 RuBl+izpmcwiCSevQn0weoefLuI1620+S6xwN36wmK2v9sS5elrTHgIUj V+BnX9vYEJ0MfzE/MKqFY+p3DYvrr29VJqh0PCEBiRSa13Bluq0kfdNpW Ior6yGhs+q2/+sM8meODaboI6lvhOsNaGPGqyBFL/Bgf3AqXjl9mDSWrF 5SJuuClxCIHncWvvNjg5Chy2Wz+iBrYWGp7x0a4XEDg9AJro97tLJXAyB w==; X-CSE-ConnectionGUID: 16YJK0wpRZmb+mgG5XM/YA== X-CSE-MsgGUID: QPqFsYVUQfG2MGE/ukkCcg== X-IronPort-AV: E=McAfee;i="6600,9927,11047"; a="34424194" X-IronPort-AV: E=Sophos;i="6.07,212,1708416000"; d="scan'208";a="34424194" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2024 10:25:00 -0700 X-CSE-ConnectionGUID: 7gQm9DH9SHu67bH1sc80vw== X-CSE-MsgGUID: r/rl2OzjQDieyKYFB/bEZg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,212,1708416000"; d="scan'208";a="27881207" Received: from nirmoyda-desk.igk.intel.com ([10.102.138.190]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Apr 2024 10:24:59 -0700 From: Nirmoy Das To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, John.C.Harrison@Intel.com, Nirmoy Das Subject: [PATCH 3/3] drm/i915: Fix gt reset with GuC submission disabled Date: Thu, 18 Apr 2024 19:10:55 +0200 Message-ID: <20240418171055.31371-3-nirmoy.das@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240418171055.31371-1-nirmoy.das@intel.com> References: <20240418171055.31371-1-nirmoy.das@intel.com> MIME-Version: 1.0 Organization: Intel Deutschland GmbH, Registered Address: Am Campeon 10, 85579 Neubiberg, Germany, Commercial Register: Amtsgericht Muenchen HRB 186928 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Currently intel_gt_reset() happens as follows: reset_prepare() ---> Sends GDRST to GuC, GuC is in GS_MIA_IN_RESET do_reset() intel_gt_reset_all_engines() *_engine_reset_prepare() -->RESET_CTL expects running GuC *_reset_engines() intel_gt_init_hw() --> GuC comes out of GS_MIA_IN_RESET with FW loaded. Fix the issue by sanitizing the GuC only after resetting requested engines and before intel_gt_init_hw(). Note intel_uc_reset_finish() and intel_uc_reset() are nop when guc submission is disabled. Signed-off-by: Nirmoy Das --- drivers/gpu/drm/i915/gt/intel_reset.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index 6504e8ba9c58..bd166f5aca4b 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -907,8 +907,17 @@ static intel_engine_mask_t reset_prepare(struct intel_gt *gt) intel_engine_mask_t awake = 0; enum intel_engine_id id; - /* For GuC mode, ensure submission is disabled before stopping ring */ - intel_uc_reset_prepare(>->uc); + /** + * For GuC mode with submission enabled, ensure submission + * is disabled before stopping ring. + * + * For GuC mode with submission disabled, ensure that GuC is not + * sanitized, do that at the end in reset_finish(). reset_prepare() + * is followed by engine reset which in this mode requires GuC to + * be functional to process engine reset events. + */ + if (intel_uc_uses_guc_submission(>->uc)) + intel_uc_reset_prepare(>->uc); for_each_engine(engine, gt, id) { if (intel_engine_pm_get_if_awake(engine)) @@ -1255,6 +1264,9 @@ void intel_gt_reset(struct intel_gt *gt, intel_overlay_reset(gt->i915); + /* sanitize uC after engine reset */ + if (!intel_uc_uses_guc_submission(>->uc)) + intel_uc_reset_prepare(>->uc); /* * Next we need to restore the context, but we don't use those * yet either...