From patchwork Mon Apr 22 08:34:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13637901 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DB0FC4345F for ; Mon, 22 Apr 2024 08:35:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 803B61128B5; Mon, 22 Apr 2024 08:35:04 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="dfnXXK7p"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id A00651128B5 for ; Mon, 22 Apr 2024 08:35:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713774902; x=1745310902; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=yDyKBdEKr7iRxGmHsLghViis/yD9b2diLRRUqgM6B7E=; b=dfnXXK7pIqfGFuLYPp7huv0Yd1xzyYLm5yN0Mf8GAL45K2XT3PfwMyGJ c2XER0o9doocxg3kxWdFX4XB2JDlN5jJ2leFMco8tv3ZEjbB0zdadCcAC lVwVp33qnlbzkxrxKpgjmeoQNi5DpFtEpvnIgS9HYSm+U/IxmfF/CUKcV moA65d8c0Gw8J3WHn+28Qa4wVZDxCX0hhvuQz2KTIQcmr2yfH6xAmWAFs mSHycfIy1BCP1MVJ8RXie6IDR2vToDslbp+YKX8SRsnBQWXEsiZg1nrcH JzFMn0NsH3s+wQByWlkdbRXh4kC/dkCNQ1YdaKvdOducN18rq+gcLWfFL g==; X-CSE-ConnectionGUID: L7fQSD/4S0WW5NpoOHApYQ== X-CSE-MsgGUID: y/eqo4knTZ+kXCMbd4jYbQ== X-IronPort-AV: E=McAfee;i="6600,9927,11051"; a="9453446" X-IronPort-AV: E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="9453446" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Apr 2024 01:35:02 -0700 X-CSE-ConnectionGUID: C2wbEHBXQNmTJOvtU4nEJQ== X-CSE-MsgGUID: JCBfi2FRSnO39M6Ng9Xkcw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="24021718" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Apr 2024 01:35:00 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 22 Apr 2024 11:34:59 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 01/14] drm/i915/dpio: Remove pointless VLV_PCS01_DW8 read Date: Mon, 22 Apr 2024 11:34:44 +0300 Message-ID: <20240422083457.23815-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240422083457.23815-1-ville.syrjala@linux.intel.com> References: <20240422083457.23815-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We don't use the result of the VLV_PCS01_DW8 read at all, so don't read. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index c72b76b61dff..6cbee88e608f 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -1134,7 +1134,6 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, vlv_dpio_get(dev_priv); /* Enable clock channels for this port */ - val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(port)); val = 0; if (pipe) val |= (1<<21); From patchwork Mon Apr 22 08:34:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13637902 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15B5FC4345F for ; Mon, 22 Apr 2024 08:35:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 902651128BB; Mon, 22 Apr 2024 08:35:07 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="B89/s86o"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 69C451128B7 for ; Mon, 22 Apr 2024 08:35:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713774905; x=1745310905; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=SpT56uh13v67g9cUfrOF0BZgPFVTzdaIezbzPlIfbb8=; b=B89/s86oIMrKHceL/y5kQEq1WrLwUhUe51sVhznr4sKo9Wc+yP4WaqbH XZacFGs5JEZQCXhja3b20WwEGiA0VN8BvNtI+bsB6nmOCWjFLv4PfevjW IaBl/W8QPbBmA17pW9Pj8iS73Wt0OVzfRW7fsz9tjRd50oSrBXG9P0DlI CScHJo39i2GWKaJkbkzv4q+Ig82DGF7uuRI+Vtwi9C/e6pwn7qXszLSMp IYgpJlCzRdJ3qQJgagwlowgskNsvyXwU9KLVPZ0HabZUX0f+8dB0dZnZh gMVX7Uj56kBA1p8Ail8VgtcZSCEo+xede08dji2uAx9pMSHSb8KAdN496 w==; X-CSE-ConnectionGUID: paNH6KKxSFOBO99x9pib4g== X-CSE-MsgGUID: lLv+ryrDQbGuWB16xdx9GA== X-IronPort-AV: E=McAfee;i="6600,9927,11051"; a="9453451" X-IronPort-AV: E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="9453451" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Apr 2024 01:35:05 -0700 X-CSE-ConnectionGUID: m3/kCydBQIGLwpqVCtUokA== X-CSE-MsgGUID: Pl3PL9sqSCqUOICZcV2Gyw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="24021766" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Apr 2024 01:35:03 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 22 Apr 2024 11:35:02 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 02/14] drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/ Date: Mon, 22 Apr 2024 11:34:45 +0300 Message-ID: <20240422083457.23815-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240422083457.23815-1-ville.syrjala@linux.intel.com> References: <20240422083457.23815-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Our VLV_REF_DW13 is actually VLV_REF_DW11. Rename it. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dpll.c | 8 ++++---- drivers/gpu/drm/i915/i915_reg.h | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 49274d632716..6693beafe9c0 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -1880,19 +1880,19 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, reg_val |= 0x00000030; vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val); - reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13); + reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11); reg_val &= 0x00ffffff; reg_val |= 0x8c000000; - vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val); + vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val); reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1)); reg_val &= 0xffffff00; vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val); - reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13); + reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11); reg_val &= 0x00ffffff; reg_val |= 0xb0000000; - vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val); + vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val); } static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8eb6c2bf4557..a2fadcbe0932 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -246,8 +246,8 @@ #define _VLV_PLL_DW11_CH1 0x806c #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) -/* Spec for ref block start counts at DW10 */ -#define VLV_REF_DW13 0x80ac +/* Spec for ref block start counts at DW8 */ +#define VLV_REF_DW11 0x80ac #define VLV_CMN_DW0 0x8100 From patchwork Mon Apr 22 08:34:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13637903 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A856AC4345F for ; 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X-CSE-ConnectionGUID: C9b15qtfTruDxMlV2Q9abA== X-CSE-MsgGUID: sT9Cb2aSSBuHRcmgvGVPcw== X-IronPort-AV: E=McAfee;i="6600,9927,11051"; a="9453452" X-IronPort-AV: E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="9453452" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Apr 2024 01:35:08 -0700 X-CSE-ConnectionGUID: PqYLhk4uSx6vEvaxuLV/Ug== X-CSE-MsgGUID: gvGRck89R6Wi685Eb1hp0A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="24021784" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Apr 2024 01:35:06 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 22 Apr 2024 11:35:05 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 03/14] drm/i915/dpio: s/VLV_PLL_DW9_BCAST/VLV_PCS_DW17_BCAST/ Date: Mon, 22 Apr 2024 11:34:46 +0300 Message-ID: <20240422083457.23815-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240422083457.23815-1-ville.syrjala@linux.intel.com> References: <20240422083457.23815-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä VLV_PLL_DW9_BCAST is actually VLV_PCS_DW17_BCAST. The address does kinda look like it goes to the PLL block on a first glance, but broadcast is special and doesn't even exist for the PLL (only PCS and TX have it). The fact that we use a broadcast write here is a bit sketchy IMO since we're now blasting the register to all PCS splines across the whole PHY. So the PCS registers in the other channel (ie. other pipe/port) will also be written. But I guess the fact that we always write the same value should make this a nop even if the other channel is already enabled (assuming the VBIOS/GOP didn't screw up and use some other value...). Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dpll.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 6693beafe9c0..7e8aca3c87ec 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -1920,7 +1920,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) vlv_pllb_recal_opamp(dev_priv, phy); /* Set up Tx target for periodic Rcomp update */ - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9_BCAST, 0x0100000f); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f); /* Disable target IRef on PLL */ reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW8(pipe)); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a2fadcbe0932..8f3c83d2ab8d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -233,7 +233,6 @@ #define _VLV_PLL_DW8_CH1 0x8060 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) -#define VLV_PLL_DW9_BCAST 0xc044 #define _VLV_PLL_DW9_CH0 0x8044 #define _VLV_PLL_DW9_CH1 0x8064 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) @@ -370,6 +369,8 @@ #define _VLV_PCS_DW14_CH1 0x8438 #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) +#define VLV_PCS_DW17_BCAST 0xc044 + #define _VLV_PCS_DW23_CH0 0x825c #define _VLV_PCS_DW23_CH1 0x845c #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) From patchwork Mon Apr 22 08:34:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13637904 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9DB3C4345F for ; Mon, 22 Apr 2024 08:35:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6741A1128BD; Mon, 22 Apr 2024 08:35:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="CFzTGWAe"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id B278B1128C0 for ; Mon, 22 Apr 2024 08:35:10 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="24021793" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Apr 2024 01:35:08 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 22 Apr 2024 11:35:08 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 04/14] drm/i915/dpio: Fix VLV DPIO PLL register dword numbering Date: Mon, 22 Apr 2024 11:34:47 +0300 Message-ID: <20240422083457.23815-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240422083457.23815-1-ville.syrjala@linux.intel.com> References: <20240422083457.23815-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The spreadsheet defines the PLL register block as having the dwords in the following order: block dwords offsets PLL1 0x0-0x7 0x00-0x1f PLL2 0x0-0x7 0x20-0x2f PLL1ext 0x10-0x1f 0x40-0x5f PLL2ext 0x10-0x1f 0x60-0x7f So dword indexes 0x8-0xf don't even exist. Renumber our register defines to match. Note that the spreadsheet used hex numbering whereas our defiens are in decimal. Perhaps we should change that? Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dpll.c | 18 ++++++++--------- drivers/gpu/drm/i915/i915_reg.h | 24 +++++++++++------------ 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 7e8aca3c87ec..b95032651da0 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -1875,19 +1875,19 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, * PLLB opamp always calibrates to max value of 0x3f, force enable it * and set it to a reasonable value instead. */ - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1)); + reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1)); reg_val &= 0xffffff00; reg_val |= 0x00000030; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val); + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val); reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11); reg_val &= 0x00ffffff; reg_val |= 0x8c000000; vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val); - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1)); + reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1)); reg_val &= 0xffffff00; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val); + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val); reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11); reg_val &= 0x00ffffff; @@ -1923,9 +1923,9 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f); /* Disable target IRef on PLL */ - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW8(pipe)); + reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe)); reg_val &= 0x00ffffff; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW8(pipe), reg_val); + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), reg_val); /* Disable fast lock */ vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610); @@ -1951,10 +1951,10 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) if (crtc_state->port_clock == 162000 || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe), + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe), 0x009f0003); else - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe), + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe), 0x00d0000f); if (intel_crtc_has_dp_encoder(crtc_state)) { @@ -1981,7 +1981,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) coreclk |= 0x01000000; vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(pipe), coreclk); - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW11(pipe), 0x87871000); + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW19(pipe), 0x87871000); vlv_dpio_put(dev_priv); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8f3c83d2ab8d..747221f8ac72 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -229,21 +229,21 @@ #define _VLV_PLL_DW7_CH1 0x803c #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) -#define _VLV_PLL_DW8_CH0 0x8040 -#define _VLV_PLL_DW8_CH1 0x8060 -#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) +#define _VLV_PLL_DW16_CH0 0x8040 +#define _VLV_PLL_DW16_CH1 0x8060 +#define VLV_PLL_DW16(ch) _PIPE(ch, _VLV_PLL_DW16_CH0, _VLV_PLL_DW16_CH1) -#define _VLV_PLL_DW9_CH0 0x8044 -#define _VLV_PLL_DW9_CH1 0x8064 -#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) +#define _VLV_PLL_DW17_CH0 0x8044 +#define _VLV_PLL_DW17_CH1 0x8064 +#define VLV_PLL_DW17(ch) _PIPE(ch, _VLV_PLL_DW17_CH0, _VLV_PLL_DW17_CH1) -#define _VLV_PLL_DW10_CH0 0x8048 -#define _VLV_PLL_DW10_CH1 0x8068 -#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) +#define _VLV_PLL_DW18_CH0 0x8048 +#define _VLV_PLL_DW18_CH1 0x8068 +#define VLV_PLL_DW18(ch) _PIPE(ch, _VLV_PLL_DW18_CH0, _VLV_PLL_DW18_CH1) -#define _VLV_PLL_DW11_CH0 0x804c -#define _VLV_PLL_DW11_CH1 0x806c -#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) +#define _VLV_PLL_DW19_CH0 0x804c +#define _VLV_PLL_DW19_CH1 0x806c +#define VLV_PLL_DW19(ch) _PIPE(ch, _VLV_PLL_DW19_CH0, _VLV_PLL_DW19_CH1) /* Spec for ref block start counts at DW8 */ #define VLV_REF_DW11 0x80ac From patchwork Mon Apr 22 08:34:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13637905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E729DC10F16 for ; Mon, 22 Apr 2024 08:35:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0D0121128C0; Mon, 22 Apr 2024 08:35:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="m34JZKkq"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6DE571128C3 for ; Mon, 22 Apr 2024 08:35:13 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="24021801" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Apr 2024 01:35:11 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 22 Apr 2024 11:35:10 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 05/14] drm/i915/dpio: Remove pointless variables from vlv/chv DPLL code Date: Mon, 22 Apr 2024 11:34:48 +0300 Message-ID: <20240422083457.23815-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240422083457.23815-1-ville.syrjala@linux.intel.com> References: <20240422083457.23815-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Drop all the local variables for the DPLL dividers for vlv/chv and just consult the state directly. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dpll.c | 62 ++++++++++------------- 1 file changed, 27 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index b95032651da0..01f800b6b30e 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -1899,20 +1899,13 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct dpll *clock = &crtc_state->dpll; enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); enum pipe pipe = crtc->pipe; - u32 mdiv; - u32 bestn, bestm1, bestm2, bestp1, bestp2; - u32 coreclk, reg_val; + u32 mdiv, coreclk, reg_val; vlv_dpio_get(dev_priv); - bestn = crtc_state->dpll.n; - bestm1 = crtc_state->dpll.m1; - bestm2 = crtc_state->dpll.m2; - bestp1 = crtc_state->dpll.p1; - bestp2 = crtc_state->dpll.p2; - /* See eDP HDMI DPIO driver vbios notes doc */ /* PLL B needs special handling */ @@ -1931,10 +1924,12 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610); /* Set idtafcrecal before PLL is enabled */ - mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); - mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); - mdiv |= ((bestn << DPIO_N_SHIFT)); - mdiv |= (1 << DPIO_K_SHIFT); + mdiv = (clock->m1 << DPIO_M1DIV_SHIFT) | + (clock->m2 & DPIO_M2DIV_MASK) | + (clock->p1 << DPIO_P1_SHIFT) | + (clock->p2 << DPIO_P2_SHIFT) | + (clock->n << DPIO_N_SHIFT) | + (1 << DPIO_K_SHIFT); /* * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, @@ -2030,19 +2025,14 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct dpll *clock = &crtc_state->dpll; enum pipe pipe = crtc->pipe; enum dpio_channel port = vlv_pipe_to_channel(pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); - u32 loopfilter, tribuf_calcntr; - u32 bestm2, bestp1, bestp2, bestm2_frac; - u32 dpio_val; - int vco; + u32 dpio_val, loopfilter, tribuf_calcntr; + u32 m2_frac; - bestm2_frac = crtc_state->dpll.m2 & 0x3fffff; - bestm2 = crtc_state->dpll.m2 >> 22; - bestp1 = crtc_state->dpll.p1; - bestp2 = crtc_state->dpll.p2; - vco = crtc_state->dpll.vco; + m2_frac = clock->m2 & 0x3fffff; dpio_val = 0; loopfilter = 0; @@ -2050,27 +2040,29 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) /* p1 and p2 divider */ vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(port), - 5 << DPIO_CHV_S1_DIV_SHIFT | - bestp1 << DPIO_CHV_P1_DIV_SHIFT | - bestp2 << DPIO_CHV_P2_DIV_SHIFT | - 1 << DPIO_CHV_K_DIV_SHIFT); + 5 << DPIO_CHV_S1_DIV_SHIFT | + clock->p1 << DPIO_CHV_P1_DIV_SHIFT | + clock->p2 << DPIO_CHV_P2_DIV_SHIFT | + 1 << DPIO_CHV_K_DIV_SHIFT); /* Feedback post-divider - m2 */ - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port), bestm2); + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port), + clock->m2 >> 22); /* Feedback refclk divider - n and m1 */ vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(port), - DPIO_CHV_M1_DIV_BY_2 | - 1 << DPIO_CHV_N_DIV_SHIFT); + DPIO_CHV_M1_DIV_BY_2 | + 1 << DPIO_CHV_N_DIV_SHIFT); /* M2 fraction division */ - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port), bestm2_frac); + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port), + m2_frac); /* M2 fraction division enable */ dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port)); dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); - if (bestm2_frac) + if (m2_frac) dpio_val |= DPIO_CHV_FRAC_DIV_EN; vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), dpio_val); @@ -2079,22 +2071,22 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); - if (!bestm2_frac) + if (!m2_frac) dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(port), dpio_val); /* Loop filter */ - if (vco == 5400000) { + if (clock->vco == 5400000) { loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); tribuf_calcntr = 0x9; - } else if (vco <= 6200000) { + } else if (clock->vco <= 6200000) { loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); tribuf_calcntr = 0x9; - } else if (vco <= 6480000) { + } else if (clock->vco <= 6480000) { loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); From patchwork Mon Apr 22 08:34:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13637906 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 382AEC4345F for ; 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X-CSE-ConnectionGUID: FFWKexJUTrWSt+CiFi1gKA== X-CSE-MsgGUID: LP6Lbp1vQTqfwfLJ/v74Lg== X-IronPort-AV: E=McAfee;i="6600,9927,11051"; a="9453470" X-IronPort-AV: E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="9453470" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Apr 2024 01:35:16 -0700 X-CSE-ConnectionGUID: RQ4KsFUBSGujD3KBGBA6Rw== X-CSE-MsgGUID: SURcfsd7RfifhUHCqfApqA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="24021806" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Apr 2024 01:35:14 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 22 Apr 2024 11:35:13 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 06/14] drm/i915/dpio: Rename some variables Date: Mon, 22 Apr 2024 11:34:49 +0300 Message-ID: <20240422083457.23815-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240422083457.23815-1-ville.syrjala@linux.intel.com> References: <20240422083457.23815-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Use a constent 'tmp' as the variable name for the register values during rmw when we don't deal with multiple registers in parallel. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dpll.c | 97 +++++++++++------------ 1 file changed, 48 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 01f800b6b30e..0a738b491c40 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -514,23 +514,23 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; - struct dpll clock; - u32 mdiv; int refclk = 100000; + struct dpll clock; + u32 tmp; /* In case of DSI, DPLL will not be used */ if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) return; vlv_dpio_get(dev_priv); - mdiv = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe)); + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe)); vlv_dpio_put(dev_priv); - clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; - clock.m2 = mdiv & DPIO_M2DIV_MASK; - clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; - clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; - clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; + clock.m1 = (tmp >> DPIO_M1DIV_SHIFT) & 7; + clock.m2 = tmp & DPIO_M2DIV_MASK; + clock.n = (tmp >> DPIO_N_SHIFT) & 0xf; + clock.p1 = (tmp >> DPIO_P1_SHIFT) & 7; + clock.p2 = (tmp >> DPIO_P2_SHIFT) & 0x1f; crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock); } @@ -1869,30 +1869,30 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum dpio_phy phy) { - u32 reg_val; + u32 tmp; /* * PLLB opamp always calibrates to max value of 0x3f, force enable it * and set it to a reasonable value instead. */ - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1)); - reg_val &= 0xffffff00; - reg_val |= 0x00000030; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val); + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1)); + tmp &= 0xffffff00; + tmp |= 0x00000030; + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp); - reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11); - reg_val &= 0x00ffffff; - reg_val |= 0x8c000000; - vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val); + tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11); + tmp &= 0x00ffffff; + tmp |= 0x8c000000; + vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp); - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1)); - reg_val &= 0xffffff00; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val); + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1)); + tmp &= 0xffffff00; + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp); - reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11); - reg_val &= 0x00ffffff; - reg_val |= 0xb0000000; - vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val); + tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11); + tmp &= 0x00ffffff; + tmp |= 0xb0000000; + vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp); } static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) @@ -1902,7 +1902,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) const struct dpll *clock = &crtc_state->dpll; enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); enum pipe pipe = crtc->pipe; - u32 mdiv, coreclk, reg_val; + u32 tmp, coreclk; vlv_dpio_get(dev_priv); @@ -1916,15 +1916,15 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f); /* Disable target IRef on PLL */ - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe)); - reg_val &= 0x00ffffff; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), reg_val); + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe)); + tmp &= 0x00ffffff; + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), tmp); /* Disable fast lock */ vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610); /* Set idtafcrecal before PLL is enabled */ - mdiv = (clock->m1 << DPIO_M1DIV_SHIFT) | + tmp = (clock->m1 << DPIO_M1DIV_SHIFT) | (clock->m2 & DPIO_M2DIV_MASK) | (clock->p1 << DPIO_P1_SHIFT) | (clock->p2 << DPIO_P2_SHIFT) | @@ -1936,11 +1936,11 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) * but we don't support that). * Note: don't use the DAC post divider as it seems unstable. */ - mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), mdiv); + tmp |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), tmp); - mdiv |= DPIO_ENABLE_CALIBRATION; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), mdiv); + tmp |= DPIO_ENABLE_CALIBRATION; + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), tmp); /* Set HBR and RBR LPF coefficients */ if (crtc_state->port_clock == 162000 || @@ -2029,11 +2029,10 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) enum pipe pipe = crtc->pipe; enum dpio_channel port = vlv_pipe_to_channel(pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); - u32 dpio_val, loopfilter, tribuf_calcntr; + u32 tmp, loopfilter, tribuf_calcntr; u32 m2_frac; m2_frac = clock->m2 & 0x3fffff; - dpio_val = 0; loopfilter = 0; vlv_dpio_get(dev_priv); @@ -2059,21 +2058,21 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) m2_frac); /* M2 fraction division enable */ - dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port)); - dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); - dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); + tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port)); + tmp &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); + tmp |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); if (m2_frac) - dpio_val |= DPIO_CHV_FRAC_DIV_EN; - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), dpio_val); + tmp |= DPIO_CHV_FRAC_DIV_EN; + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), tmp); /* Program digital lock detect threshold */ - dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(port)); - dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | + tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(port)); + tmp &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); - dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); + tmp |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); if (!m2_frac) - dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(port), dpio_val); + tmp |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(port), tmp); /* Loop filter */ if (clock->vco == 5400000) { @@ -2100,10 +2099,10 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) } vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(port), loopfilter); - dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(port)); - dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; - dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(port), dpio_val); + tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(port)); + tmp &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; + tmp |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(port), tmp); /* AFC Recal */ vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), From patchwork Mon Apr 22 08:34:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13637907 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DFB6AC07E8F for ; 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X-CSE-ConnectionGUID: KHTv7+tqR5ya/U4VphrO1w== X-CSE-MsgGUID: OpJRGZ9+TUG58QRdFZWbqw== X-IronPort-AV: E=McAfee;i="6600,9927,11051"; a="9453473" X-IronPort-AV: E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="9453473" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Apr 2024 01:35:19 -0700 X-CSE-ConnectionGUID: Zl3/cxNwTxCjrgrex9dBjw== X-CSE-MsgGUID: eBu3B4uGR1yoDifkXErNDQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="24021811" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Apr 2024 01:35:17 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 22 Apr 2024 11:35:16 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 07/14] drm/i915/dpio: s/port/ch/ Date: Mon, 22 Apr 2024 11:34:50 +0300 Message-ID: <20240422083457.23815-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240422083457.23815-1-ville.syrjala@linux.intel.com> References: <20240422083457.23815-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Stop calling the DPIO PHY channel "port". Just say "ch", which is already used in a bunch of places. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 44 +++++++-------- drivers/gpu/drm/i915/display/intel_dpll.c | 54 +++++++++---------- 2 files changed, 49 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 6cbee88e608f..e4a04c9b5b19 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -1069,23 +1069,23 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - enum dpio_channel port = vlv_dig_port_to_channel(dig_port); + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); vlv_dpio_get(dev_priv); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), 0x00000000); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(port), demph_reg_value); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(port), + vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), 0x00000000); + vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch), demph_reg_value); + vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch), uniqtranscale_reg_value); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(port), 0x0C782040); + vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(ch), 0x0C782040); if (tx3_demph) - vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(port), tx3_demph); + vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(port), 0x00030000); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(port), preemph_reg_value); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(ch), 0x00030000); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(ch), preemph_reg_value); + vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), DPIO_TX_OCALINIT_EN); vlv_dpio_put(dev_priv); } @@ -1096,25 +1096,25 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - enum dpio_channel port = vlv_dig_port_to_channel(dig_port); + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); /* Program Tx lane resets to default */ vlv_dpio_get(dev_priv); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port), + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch), DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port), + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch), DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | (1<base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - enum dpio_channel port = vlv_dig_port_to_channel(dig_port); + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum pipe pipe = crtc->pipe; enum dpio_phy phy = vlv_pipe_to_phy(pipe); u32 val; @@ -1140,11 +1140,11 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, else val &= ~(1<<21); val |= 0x001000c4; - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(port), val); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(ch), val); /* Program lane clock */ - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(port), 0x00760018); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(port), 0x00400888); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(ch), 0x00760018); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(ch), 0x00400888); vlv_dpio_put(dev_priv); } @@ -1155,11 +1155,11 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder, struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); - enum dpio_channel port = vlv_dig_port_to_channel(dig_port); + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); vlv_dpio_get(dev_priv); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port), 0x00000000); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port), 0x00e00060); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch), 0x00000000); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch), 0x00e00060); vlv_dpio_put(dev_priv); } diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 0a738b491c40..743cc466ee39 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -539,7 +539,7 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - enum dpio_channel port = vlv_pipe_to_channel(crtc->pipe); + enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; struct dpll clock; @@ -551,11 +551,11 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state) return; vlv_dpio_get(dev_priv); - cmn_dw13 = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW13(port)); - pll_dw0 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW0(port)); - pll_dw1 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW1(port)); - pll_dw2 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW2(port)); - pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port)); + cmn_dw13 = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW13(ch)); + pll_dw0 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW0(ch)); + pll_dw1 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW1(ch)); + pll_dw2 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW2(ch)); + pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch)); vlv_dpio_put(dev_priv); clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; @@ -2027,7 +2027,7 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct dpll *clock = &crtc_state->dpll; enum pipe pipe = crtc->pipe; - enum dpio_channel port = vlv_pipe_to_channel(pipe); + enum dpio_channel ch = vlv_pipe_to_channel(pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); u32 tmp, loopfilter, tribuf_calcntr; u32 m2_frac; @@ -2038,41 +2038,41 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) vlv_dpio_get(dev_priv); /* p1 and p2 divider */ - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(port), + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(ch), 5 << DPIO_CHV_S1_DIV_SHIFT | clock->p1 << DPIO_CHV_P1_DIV_SHIFT | clock->p2 << DPIO_CHV_P2_DIV_SHIFT | 1 << DPIO_CHV_K_DIV_SHIFT); /* Feedback post-divider - m2 */ - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port), + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(ch), clock->m2 >> 22); /* Feedback refclk divider - n and m1 */ - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(port), + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(ch), DPIO_CHV_M1_DIV_BY_2 | 1 << DPIO_CHV_N_DIV_SHIFT); /* M2 fraction division */ - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port), + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(ch), m2_frac); /* M2 fraction division enable */ - tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port)); + tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch)); tmp &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); tmp |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); if (m2_frac) tmp |= DPIO_CHV_FRAC_DIV_EN; - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), tmp); + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(ch), tmp); /* Program digital lock detect threshold */ - tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(port)); + tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(ch)); tmp &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); tmp |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); if (!m2_frac) tmp |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(port), tmp); + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(ch), tmp); /* Loop filter */ if (clock->vco == 5400000) { @@ -2097,17 +2097,17 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); tribuf_calcntr = 0; } - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(port), loopfilter); + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(ch), loopfilter); - tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(port)); + tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(ch)); tmp &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; tmp |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(port), tmp); + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(ch), tmp); /* AFC Recal */ - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), - vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port)) | - DPIO_AFC_RECAL); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), + vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch)) | + DPIO_AFC_RECAL); vlv_dpio_put(dev_priv); } @@ -2118,16 +2118,16 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum pipe pipe = crtc->pipe; - enum dpio_channel port = vlv_pipe_to_channel(pipe); + enum dpio_channel ch = vlv_pipe_to_channel(pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); u32 tmp; vlv_dpio_get(dev_priv); /* Enable back the 10bit clock to display controller */ - tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port)); + tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch)); tmp |= DPIO_DCLKP_EN; - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), tmp); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), tmp); vlv_dpio_put(dev_priv); @@ -2246,7 +2246,7 @@ void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) { - enum dpio_channel port = vlv_pipe_to_channel(pipe); + enum dpio_channel ch = vlv_pipe_to_channel(pipe); enum dpio_phy phy = vlv_pipe_to_phy(pipe); u32 val; @@ -2264,9 +2264,9 @@ void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) vlv_dpio_get(dev_priv); /* Disable 10bit clock to display controller */ - val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port)); + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch)); val &= ~DPIO_DCLKP_EN; - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), val); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), val); vlv_dpio_put(dev_priv); } From patchwork Mon Apr 22 08:34:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13637908 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 78ABEC4345F for ; Mon, 22 Apr 2024 08:35:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8F0A71128CF; Mon, 22 Apr 2024 08:35:24 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="9453475" X-IronPort-AV: E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="9453475" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Apr 2024 01:35:21 -0700 X-CSE-ConnectionGUID: 8ff+XtlrSNilVD0+l5615g== X-CSE-MsgGUID: 9IDhPRbYTCOITVH6EJ5V5w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="24021817" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Apr 2024 01:35:19 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 22 Apr 2024 11:35:18 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 08/14] drm/i915/dpio: s/pipe/ch/ Date: Mon, 22 Apr 2024 11:34:51 +0300 Message-ID: <20240422083457.23815-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240422083457.23815-1-ville.syrjala@linux.intel.com> References: <20240422083457.23815-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Stop using 'pipe' directly as the DPIO PHY channel. This does happen to work on VLV since it just has the one PHY with CH0==pipe A and CH1==pipe B. But explicitly converting the thing to the right enum makes the whole thing less confusing. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dpll.c | 49 ++++++++++++----------- 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 743cc466ee39..861f4a735251 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -512,6 +512,7 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; int refclk = 100000; @@ -523,7 +524,7 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state) return; vlv_dpio_get(dev_priv); - tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe)); + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(ch)); vlv_dpio_put(dev_priv); clock.m1 = (tmp >> DPIO_M1DIV_SHIFT) & 7; @@ -1867,7 +1868,7 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) } static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, - enum dpio_phy phy) + enum dpio_phy phy, enum dpio_channel ch) { u32 tmp; @@ -1875,19 +1876,19 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, * PLLB opamp always calibrates to max value of 0x3f, force enable it * and set it to a reasonable value instead. */ - tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1)); + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch)); tmp &= 0xffffff00; tmp |= 0x00000030; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp); + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp); tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11); tmp &= 0x00ffffff; tmp |= 0x8c000000; vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp); - tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1)); + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch)); tmp &= 0xffffff00; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp); + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp); tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11); tmp &= 0x00ffffff; @@ -1900,6 +1901,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct dpll *clock = &crtc_state->dpll; + enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); enum pipe pipe = crtc->pipe; u32 tmp, coreclk; @@ -1910,15 +1912,15 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) /* PLL B needs special handling */ if (pipe == PIPE_B) - vlv_pllb_recal_opamp(dev_priv, phy); + vlv_pllb_recal_opamp(dev_priv, phy, ch); /* Set up Tx target for periodic Rcomp update */ vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f); /* Disable target IRef on PLL */ - tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe)); + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(ch)); tmp &= 0x00ffffff; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), tmp); + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(ch), tmp); /* Disable fast lock */ vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610); @@ -1937,46 +1939,46 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) * Note: don't use the DAC post divider as it seems unstable. */ tmp |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), tmp); + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp); tmp |= DPIO_ENABLE_CALIBRATION; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), tmp); + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp); /* Set HBR and RBR LPF coefficients */ if (crtc_state->port_clock == 162000 || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe), + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch), 0x009f0003); else - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe), + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch), 0x00d0000f); if (intel_crtc_has_dp_encoder(crtc_state)) { /* Use SSC source */ if (pipe == PIPE_A) - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe), + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch), 0x0df40000); else - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe), + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch), 0x0df70000); } else { /* HDMI or VGA */ /* Use bend source */ if (pipe == PIPE_A) - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe), + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch), 0x0df70000); else - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe), + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch), 0x0df40000); } - coreclk = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW7(pipe)); + coreclk = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW7(ch)); coreclk = (coreclk & 0x0000ff00) | 0x01c00000; if (intel_crtc_has_dp_encoder(crtc_state)) coreclk |= 0x01000000; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(pipe), coreclk); + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(ch), coreclk); - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW19(pipe), 0x87871000); + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW19(ch), 0x87871000); vlv_dpio_put(dev_priv); } @@ -2026,8 +2028,7 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct dpll *clock = &crtc_state->dpll; - enum pipe pipe = crtc->pipe; - enum dpio_channel ch = vlv_pipe_to_channel(pipe); + enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); u32 tmp, loopfilter, tribuf_calcntr; u32 m2_frac; @@ -2117,9 +2118,9 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; - enum pipe pipe = crtc->pipe; - enum dpio_channel ch = vlv_pipe_to_channel(pipe); + enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + enum pipe pipe = crtc->pipe; u32 tmp; vlv_dpio_get(dev_priv); From patchwork Mon Apr 22 08:34:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13637910 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 801D4C07E8F for ; Mon, 22 Apr 2024 08:35:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DA6D51128D3; Mon, 22 Apr 2024 08:35:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="9453479" X-IronPort-AV: E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="9453479" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Apr 2024 01:35:24 -0700 X-CSE-ConnectionGUID: YsNeaJPKR6SBNEnYmd7N6w== X-CSE-MsgGUID: mTGZsTNqQAuFbJX33G0TDQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="24021822" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Apr 2024 01:35:22 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 22 Apr 2024 11:35:21 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 09/14] drm/i915/dpio: Derive the phy from the port rather than pipe in encoder hooks Date: Mon, 22 Apr 2024 11:34:52 +0300 Message-ID: <20240422083457.23815-10-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240422083457.23815-1-ville.syrjala@linux.intel.com> References: <20240422083457.23815-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä In the encoder hooks we are dealing primarily with the encoder, so derive the DPIO PHY from the encoder rather than the pipe. Technically this doesn't matter as we can't cross connect pipes<->port across PHY boundaries, but it does conveny the intention more accurately. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 27 ++++++++----------- drivers/gpu/drm/i915/vlv_sideband.c | 1 - 2 files changed, 11 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index e4a04c9b5b19..4fafac534967 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -719,9 +719,8 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); u32 val; int i; @@ -814,9 +813,9 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder, bool reset) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); u32 val; val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW0(ch)); @@ -861,7 +860,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); enum pipe pipe = crtc->pipe; unsigned int lane_mask = intel_dp_unused_lane_mask(crtc_state->lane_count); @@ -941,9 +940,8 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); int data, i, stagger; u32 val; @@ -1030,8 +1028,8 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe; - enum dpio_phy phy = vlv_pipe_to_phy(pipe); u32 val; vlv_dpio_get(dev_priv); @@ -1068,9 +1066,8 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); vlv_dpio_get(dev_priv); @@ -1095,9 +1092,8 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, { struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); /* Program Tx lane resets to default */ vlv_dpio_get(dev_priv); @@ -1127,8 +1123,8 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); enum pipe pipe = crtc->pipe; - enum dpio_phy phy = vlv_pipe_to_phy(pipe); u32 val; vlv_dpio_get(dev_priv); @@ -1154,9 +1150,8 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder, { struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); vlv_dpio_get(dev_priv); vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch), 0x00000000); diff --git a/drivers/gpu/drm/i915/vlv_sideband.c b/drivers/gpu/drm/i915/vlv_sideband.c index ffa195560d0d..68291412f4cb 100644 --- a/drivers/gpu/drm/i915/vlv_sideband.c +++ b/drivers/gpu/drm/i915/vlv_sideband.c @@ -9,7 +9,6 @@ #include "vlv_sideband.h" #include "display/intel_dpio_phy.h" -#include "display/intel_display_types.h" /* * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and From patchwork Mon Apr 22 08:34:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13637909 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C60EAC4345F for ; Mon, 22 Apr 2024 08:35:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4EFD11128B9; Mon, 22 Apr 2024 08:35:28 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="h2eS4T5+"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 636131128D3 for ; Mon, 22 Apr 2024 08:35:27 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="24021826" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Apr 2024 01:35:25 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 22 Apr 2024 11:35:24 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 10/14] drm/i915/dpio: Give VLV DPIO group register a clearer name Date: Mon, 22 Apr 2024 11:34:53 +0300 Message-ID: <20240422083457.23815-11-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240422083457.23815-1-ville.syrjala@linux.intel.com> References: <20240422083457.23815-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Include _GRP in VLV DPOP PHY group access register define names. Makes it more obvious where the accesses will land. Also matches the naming used by BXT already. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 34 +++---- drivers/gpu/drm/i915/i915_reg.h | 90 +++++++++---------- 2 files changed, 62 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 4fafac534967..791902ba729c 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -1071,18 +1071,18 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder, vlv_dpio_get(dev_priv); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), 0x00000000); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch), demph_reg_value); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch), + vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), 0x00000000); + vlv_dpio_write(dev_priv, phy, VLV_TX_DW4_GRP(ch), demph_reg_value); + vlv_dpio_write(dev_priv, phy, VLV_TX_DW2_GRP(ch), uniqtranscale_reg_value); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(ch), 0x0C782040); + vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040); if (tx3_demph) vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(ch), 0x00030000); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(ch), preemph_reg_value); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), DPIO_TX_OCALINIT_EN); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x00030000); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value); + vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN); vlv_dpio_put(dev_priv); } @@ -1098,19 +1098,19 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, /* Program Tx lane resets to default */ vlv_dpio_get(dev_priv); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch), + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch), + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | (1< X-Patchwork-Id: 13637911 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BE00AC4345F for ; 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X-CSE-ConnectionGUID: uAQNdCLZRxKQwHa6Z+/lDA== X-CSE-MsgGUID: +dJPbIXhSKux3UeN4LY51w== X-IronPort-AV: E=McAfee;i="6600,9927,11051"; a="9453489" X-IronPort-AV: E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="9453489" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Apr 2024 01:35:30 -0700 X-CSE-ConnectionGUID: y6oC6Sk2T7Ghnv5DoCnyEA== X-CSE-MsgGUID: sQ0RpPh4QweCNH7pc05drw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="24021829" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Apr 2024 01:35:28 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 22 Apr 2024 11:35:27 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 11/14] drm/i915/dpio: Rename a few CHV DPIO PHY registers Date: Mon, 22 Apr 2024 11:34:54 +0300 Message-ID: <20240422083457.23815-12-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240422083457.23815-1-ville.syrjala@linux.intel.com> References: <20240422083457.23815-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Drop the leading underscore from the CHV PHY common lane register definitons. We use these directly from actual code so the underscore here is misleading as usually it indicates an intermediate define that shouldn't be used directly. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- .../i915/display/intel_display_power_well.c | 8 +++---- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 16 ++++++------- drivers/gpu/drm/i915/i915_reg.h | 23 +++++++++---------- 3 files changed, 23 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index e8a6e53fd551..49114afc9a61 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -1442,9 +1442,9 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, vlv_dpio_write(dev_priv, phy, CHV_CMN_DW28, tmp); if (id == VLV_DISP_PW_DPIO_CMN_BC) { - tmp = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW6_CH1); + tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW6_CH1); tmp |= DPIO_DYNPWRDOWNEN_CH1; - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW6_CH1, tmp); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW6_CH1, tmp); } else { /* * Force the non-existing CL2 off. BXT does this @@ -1520,9 +1520,9 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi return; if (ch == DPIO_CH0) - reg = _CHV_CMN_DW0_CH0; + reg = CHV_CMN_DW0_CH0; else - reg = _CHV_CMN_DW6_CH1; + reg = CHV_CMN_DW6_CH1; vlv_dpio_get(dev_priv); val = vlv_dpio_read(dev_priv, phy, reg); diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 791902ba729c..89a51b420075 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -883,21 +883,21 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, /* program left/right clock distribution */ if (pipe != PIPE_B) { - val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0); + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0); val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); if (ch == DPIO_CH0) val |= CHV_BUFLEFTENA1_FORCE; if (ch == DPIO_CH1) val |= CHV_BUFRIGHTENA1_FORCE; - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val); } else { - val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1); + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1); val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); if (ch == DPIO_CH0) val |= CHV_BUFLEFTENA2_FORCE; if (ch == DPIO_CH1) val |= CHV_BUFRIGHTENA2_FORCE; - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val); } /* program clock channel usage */ @@ -1036,13 +1036,13 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder, /* disable left/right clock distribution */ if (pipe != PIPE_B) { - val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0); + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0); val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val); } else { - val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1); + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1); val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val); } vlv_dpio_put(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3804ef4697d5..b24ce3cff1a0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -459,13 +459,13 @@ #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) -#define _CHV_CMN_DW0_CH0 0x8100 +#define CHV_CMN_DW0_CH0 0x8100 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 #define DPIO_ALLDL_POWERDOWN (1 << 1) #define DPIO_ANYDL_POWERDOWN (1 << 0) -#define _CHV_CMN_DW5_CH0 0x8114 +#define CHV_CMN_DW5_CH0 0x8114 #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) #define CHV_BUFRIGHTENA1_FORCE (3 << 20) @@ -475,18 +475,18 @@ #define CHV_BUFLEFTENA1_FORCE (3 << 22) #define CHV_BUFLEFTENA1_MASK (3 << 22) -#define _CHV_CMN_DW13_CH0 0x8134 -#define _CHV_CMN_DW0_CH1 0x8080 +#define CHV_CMN_DW13_CH0 0x8134 +#define CHV_CMN_DW0_CH1 0x8080 #define DPIO_CHV_S1_DIV_SHIFT 21 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ #define DPIO_CHV_K_DIV_SHIFT 4 #define DPIO_PLL_FREQLOCK (1 << 1) #define DPIO_PLL_LOCK (1 << 0) -#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) +#define CHV_CMN_DW13(ch) _PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1) -#define _CHV_CMN_DW14_CH0 0x8138 -#define _CHV_CMN_DW1_CH1 0x8084 +#define CHV_CMN_DW14_CH0 0x8138 +#define CHV_CMN_DW1_CH1 0x8084 #define DPIO_AFC_RECAL (1 << 14) #define DPIO_DCLKP_EN (1 << 13) #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ @@ -497,16 +497,15 @@ #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ -#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) +#define CHV_CMN_DW14(ch) _PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1) -#define _CHV_CMN_DW19_CH0 0x814c -#define _CHV_CMN_DW6_CH1 0x8098 +#define CHV_CMN_DW19_CH0 0x814c +#define CHV_CMN_DW6_CH1 0x8098 #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ #define CHV_CMN_USEDCLKCHANNEL (1 << 13) - -#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) +#define CHV_CMN_DW19(ch) _PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1) #define CHV_CMN_DW28 0x8170 #define DPIO_CL1POWERDOWNEN (1 << 23) From patchwork Mon Apr 22 08:34:55 2024 Content-Type: text/plain; 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d="scan'208";a="24021835" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Apr 2024 01:35:30 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 22 Apr 2024 11:35:30 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 12/14] drm/i915/dpio: Clean up VLV/CHV DPIO PHY register defines Date: Mon, 22 Apr 2024 11:34:55 +0300 Message-ID: <20240422083457.23815-13-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240422083457.23815-1-ville.syrjala@linux.intel.com> References: <20240422083457.23815-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The DPIO PHY registers follow clear numbering rules. Express those in a few macros to get rid of the hand calculated final offsets. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 271 +++++++----------- 2 files changed, 99 insertions(+), 174 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 89a51b420075..fa665d353df9 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -1078,7 +1078,7 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder, vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040); if (tx3_demph) - vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph); + vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch, 3), tx3_demph); vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x00030000); vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b24ce3cff1a0..6d16f9944eff 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -195,10 +195,22 @@ #define DPIO_SFR_BYPASS (1 << 1) #define DPIO_CMNRST (1 << 0) +#define _VLV_CMN(dw) (0x8100 + (dw) * 4) +#define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4) +#define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */ +#define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4) +#define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */ +#define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + (dw) * 4) +#define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4) +#define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4) +#define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) +#define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4) +#define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4) + /* * Per pipe/PLL DPIO regs */ -#define _VLV_PLL_DW3_CH0 0x800c +#define VLV_PLL_DW3(ch) _VLV_PLL((ch), 3) #define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ #define DPIO_POST_DIV_DAC 0 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ @@ -211,10 +223,8 @@ #define DPIO_ENABLE_CALIBRATION (1 << 11) #define DPIO_M1DIV_SHIFT (8) /* 3 bits */ #define DPIO_M2DIV_MASK 0xff -#define _VLV_PLL_DW3_CH1 0x802c -#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) -#define _VLV_PLL_DW5_CH0 0x8014 +#define VLV_PLL_DW5(ch) _VLV_PLL((ch), 5) #define DPIO_REFSEL_OVERRIDE 27 #define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ #define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ @@ -222,101 +232,60 @@ #define DPIO_PLL_REFCLK_SEL_MASK 3 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ -#define _VLV_PLL_DW5_CH1 0x8034 -#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) -#define _VLV_PLL_DW7_CH0 0x801c -#define _VLV_PLL_DW7_CH1 0x803c -#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) +#define VLV_PLL_DW7(ch) _VLV_PLL((ch), 7) -#define _VLV_PLL_DW16_CH0 0x8040 -#define _VLV_PLL_DW16_CH1 0x8060 -#define VLV_PLL_DW16(ch) _PIPE(ch, _VLV_PLL_DW16_CH0, _VLV_PLL_DW16_CH1) +#define VLV_PLL_DW16(ch) _VLV_PLL((ch), 16) -#define _VLV_PLL_DW17_CH0 0x8044 -#define _VLV_PLL_DW17_CH1 0x8064 -#define VLV_PLL_DW17(ch) _PIPE(ch, _VLV_PLL_DW17_CH0, _VLV_PLL_DW17_CH1) +#define VLV_PLL_DW17(ch) _VLV_PLL((ch), 17) -#define _VLV_PLL_DW18_CH0 0x8048 -#define _VLV_PLL_DW18_CH1 0x8068 -#define VLV_PLL_DW18(ch) _PIPE(ch, _VLV_PLL_DW18_CH0, _VLV_PLL_DW18_CH1) +#define VLV_PLL_DW18(ch) _VLV_PLL((ch), 18) -#define _VLV_PLL_DW19_CH0 0x804c -#define _VLV_PLL_DW19_CH1 0x806c -#define VLV_PLL_DW19(ch) _PIPE(ch, _VLV_PLL_DW19_CH0, _VLV_PLL_DW19_CH1) +#define VLV_PLL_DW19(ch) _VLV_PLL((ch), 19) -/* Spec for ref block start counts at DW8 */ -#define VLV_REF_DW11 0x80ac +#define VLV_REF_DW11 _VLV_REF(11) -#define VLV_CMN_DW0 0x8100 +#define VLV_CMN_DW0 _VLV_CMN(0) /* * Per DDI channel DPIO regs */ - -#define _VLV_PCS_DW0_CH0_GRP 0x8200 -#define _VLV_PCS_DW0_CH1_GRP 0x8400 +#define VLV_PCS_DW0_GRP(ch) _VLV_PCS_GRP((ch), 0) +#define VLV_PCS01_DW0(ch) _VLV_PCS((ch), 0, 0) +#define VLV_PCS23_DW0(ch) _VLV_PCS((ch), 1, 0) #define DPIO_PCS_TX_LANE2_RESET (1 << 16) #define DPIO_PCS_TX_LANE1_RESET (1 << 7) #define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) #define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) -#define VLV_PCS_DW0_GRP(ch) _PORT(ch, _VLV_PCS_DW0_CH0_GRP, _VLV_PCS_DW0_CH1_GRP) -#define _VLV_PCS01_DW0_CH0 0x200 -#define _VLV_PCS23_DW0_CH0 0x400 -#define _VLV_PCS01_DW0_CH1 0x2600 -#define _VLV_PCS23_DW0_CH1 0x2800 -#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) -#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) - -#define _VLV_PCS_DW1_CH0_GRP 0x8204 -#define _VLV_PCS_DW1_CH1_GRP 0x8404 +#define VLV_PCS_DW1_GRP(ch) _VLV_PCS_GRP((ch), 1) +#define VLV_PCS01_DW1(ch) _VLV_PCS((ch), 0, 1) +#define VLV_PCS23_DW1(ch) _VLV_PCS((ch), 1, 1) #define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) #define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) #define DPIO_PCS_CLK_SOFT_RESET (1 << 5) -#define VLV_PCS_DW1_GRP(ch) _PORT(ch, _VLV_PCS_DW1_CH0_GRP, _VLV_PCS_DW1_CH1_GRP) -#define _VLV_PCS01_DW1_CH0 0x204 -#define _VLV_PCS23_DW1_CH0 0x404 -#define _VLV_PCS01_DW1_CH1 0x2604 -#define _VLV_PCS23_DW1_CH1 0x2804 -#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) -#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) - -#define _VLV_PCS_DW8_CH0_GRP 0x8220 -#define _VLV_PCS_DW8_CH1_GRP 0x8420 +#define VLV_PCS_DW8_GRP(ch) _VLV_PCS_GRP((ch), 8) +#define VLV_PCS01_DW8(ch) _VLV_PCS((ch), 0, 8) +#define VLV_PCS23_DW8(ch) _VLV_PCS((ch), 1, 8) #define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) #define CHV_PCS_USEDCLKCHANNEL (1 << 21) -#define VLV_PCS_DW8_GRP(ch) _PORT(ch, _VLV_PCS_DW8_CH0_GRP, _VLV_PCS_DW8_CH1_GRP) -#define _VLV_PCS01_DW8_CH0 0x0220 -#define _VLV_PCS23_DW8_CH0 0x0420 -#define _VLV_PCS01_DW8_CH1 0x2620 -#define _VLV_PCS23_DW8_CH1 0x2820 -#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) -#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) - -#define _VLV_PCS_DW9_CH0_GRP 0x8224 -#define _VLV_PCS_DW9_CH1_GRP 0x8424 +#define VLV_PCS_DW9_GRP(ch) _VLV_PCS_GRP((ch), 9) +#define VLV_PCS01_DW9(ch) _VLV_PCS((ch), 0, 9) +#define VLV_PCS23_DW9(ch) _VLV_PCS((ch), 1, 9) #define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) #define DPIO_PCS_TX2MARGIN_000 (0 << 13) #define DPIO_PCS_TX2MARGIN_101 (1 << 13) #define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) #define DPIO_PCS_TX1MARGIN_000 (0 << 10) #define DPIO_PCS_TX1MARGIN_101 (1 << 10) -#define VLV_PCS_DW9_GRP(ch) _PORT(ch, _VLV_PCS_DW9_CH0_GRP, _VLV_PCS_DW9_CH1_GRP) -#define _VLV_PCS01_DW9_CH0 0x224 -#define _VLV_PCS23_DW9_CH0 0x424 -#define _VLV_PCS01_DW9_CH1 0x2624 -#define _VLV_PCS23_DW9_CH1 0x2824 -#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) -#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) - -#define _CHV_PCS_DW10_CH0_GRP 0x8228 -#define _CHV_PCS_DW10_CH1_GRP 0x8428 +#define VLV_PCS_DW10_GRP(ch) _VLV_PCS_GRP((ch), 10) +#define VLV_PCS01_DW10(ch) _VLV_PCS((ch), 0, 10) +#define VLV_PCS23_DW10(ch) _VLV_PCS((ch), 1, 10) #define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) #define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) #define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) @@ -325,147 +294,104 @@ #define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) #define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) #define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) -#define CHV_PCS_DW10_GRP(ch) _PORT(ch, _CHV_PCS_DW10_CH0_GRP, _CHV_PCS_DW10_CH1_GRP) -#define _VLV_PCS01_DW10_CH0 0x0228 -#define _VLV_PCS23_DW10_CH0 0x0428 -#define _VLV_PCS01_DW10_CH1 0x2628 -#define _VLV_PCS23_DW10_CH1 0x2828 -#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) -#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) - -#define _VLV_PCS_DW11_CH0_GRP 0x822c -#define _VLV_PCS_DW11_CH1_GRP 0x842c +#define VLV_PCS_DW11_GRP(ch) _VLV_PCS_GRP((ch), 11) +#define VLV_PCS01_DW11(ch) _VLV_PCS((ch), 0, 11) +#define VLV_PCS23_DW11(ch) _VLV_PCS((ch), 1, 11) #define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) #define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) #define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) #define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) -#define VLV_PCS_DW11_GRP(ch) _PORT(ch, _VLV_PCS_DW11_CH0_GRP, _VLV_PCS_DW11_CH1_GRP) -#define _VLV_PCS01_DW11_CH0 0x022c -#define _VLV_PCS23_DW11_CH0 0x042c -#define _VLV_PCS01_DW11_CH1 0x262c -#define _VLV_PCS23_DW11_CH1 0x282c -#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) -#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) - -#define _VLV_PCS01_DW12_CH0 0x0230 -#define _VLV_PCS23_DW12_CH0 0x0430 -#define _VLV_PCS01_DW12_CH1 0x2630 -#define _VLV_PCS23_DW12_CH1 0x2830 -#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) -#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) - -#define _VLV_PCS_DW12_CH0_GRP 0x8230 -#define _VLV_PCS_DW12_CH1_GRP 0x8430 +#define VLV_PCS_DW12_GRP(ch) _VLV_PCS_GRP((ch), 12) +#define VLV_PCS01_DW12(ch) _VLV_PCS((ch), 0, 12) +#define VLV_PCS23_DW12(ch) _VLV_PCS((ch), 1, 12) #define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) #define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) #define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) #define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) #define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) -#define VLV_PCS_DW12_GRP(ch) _PORT(ch, _VLV_PCS_DW12_CH0_GRP, _VLV_PCS_DW12_CH1_GRP) -#define _VLV_PCS_DW14_CH0_GRP 0x8238 -#define _VLV_PCS_DW14_CH1_GRP 0x8438 -#define VLV_PCS_DW14_GRP(ch) _PORT(ch, _VLV_PCS_DW14_CH0_GRP, _VLV_PCS_DW14_CH1_GRP) +#define VLV_PCS_DW14_GRP(ch) _VLV_PCS_GRP((ch), 14) +#define VLV_PCS01_DW14(ch) _VLV_PCS((ch), 0, 14) +#define VLV_PCS23_DW14(ch) _VLV_PCS((ch), 1, 14) -#define VLV_PCS_DW17_BCAST 0xc044 +#define VLV_PCS_DW17_BCAST _VLV_PCS_BCAST(17) +#define VLV_PCS_DW17_GRP(ch) _VLV_PCS_GRP((ch), 17) +#define VLV_PCS01_DW17(ch) _VLV_PCS((ch), 0, 17) +#define VLV_PCS23_DW17(ch) _VLV_PCS((ch), 1, 17) -#define _VLV_PCS_DW23_CH0_GRP 0x825c -#define _VLV_PCS_DW23_CH1_GRP 0x845c -#define VLV_PCS_DW23_GRP(ch) _PORT(ch, _VLV_PCS_DW23_CH0_GRP, _VLV_PCS_DW23_CH1_GRP) +#define VLV_PCS_DW23_GRP(ch) _VLV_PCS_GRP((ch), 23) +#define VLV_PCS01_DW23(ch) _VLV_PCS((ch), 0, 23) +#define VLV_PCS23_DW23(ch) _VLV_PCS((ch), 1, 23) -#define _VLV_TX_DW2_CH0_GRP 0x8288 -#define _VLV_TX_DW2_CH1_GRP 0x8488 +#define VLV_TX_DW2_GRP(ch) _VLV_TX_GRP((ch), 2) +#define VLV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) #define DPIO_SWING_MARGIN000_SHIFT 16 #define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 -#define VLV_TX_DW2_GRP(ch) _PORT(ch, _VLV_TX_DW2_CH0_GRP, _VLV_TX_DW2_CH1_GRP) -#define _VLV_TX_DW3_CH0_GRP 0x828c -#define _VLV_TX_DW3_CH1_GRP 0x848c +#define VLV_TX_DW3_GRP(ch) _VLV_TX_GRP((ch), 3) +#define VLV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) /* The following bit for CHV phy */ #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) #define DPIO_SWING_MARGIN101_SHIFT 16 #define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) -#define VLV_TX_DW3_GRP(ch) _PORT(ch, _VLV_TX_DW3_CH0_GRP, _VLV_TX_DW3_CH1_GRP) -#define _VLV_TX_DW4_CH0_GRP 0x8290 -#define _VLV_TX_DW4_CH1_GRP 0x8490 +#define VLV_TX_DW4_GRP(ch) _VLV_TX_GRP((ch), 4) +#define VLV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) #define DPIO_SWING_DEEMPH9P5_SHIFT 24 #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) #define DPIO_SWING_DEEMPH6P0_SHIFT 16 #define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) -#define VLV_TX_DW4_GRP(ch) _PORT(ch, _VLV_TX_DW4_CH0_GRP, _VLV_TX_DW4_CH1_GRP) -#define _VLV_TX3_DW4_CH0 0x690 -#define _VLV_TX3_DW4_CH1 0x2a90 -#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) - -#define _VLV_TX_DW5_CH0_GRP 0x8294 -#define _VLV_TX_DW5_CH1_GRP 0x8494 +#define VLV_TX_DW5_GRP(ch) _VLV_TX_GRP((ch), 5) +#define VLV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), 5) #define DPIO_TX_OCALINIT_EN (1 << 31) -#define VLV_TX_DW5_GRP(ch) _PORT(ch, _VLV_TX_DW5_CH0_GRP, _VLV_TX_DW5_CH1_GRP) -#define _VLV_TX_DW11_CH0_GRP 0x82ac -#define _VLV_TX_DW11_CH1_GRP 0x84ac -#define VLV_TX_DW11_GRP(ch) _PORT(ch, _VLV_TX_DW11_CH0_GRP, _VLV_TX_DW11_CH1_GRP) +#define VLV_TX_DW11_GRP(ch) _VLV_TX_GRP((ch), 11) +#define VLV_TX_DW11(ch, lane) _VLV_TX((ch), (lane), 11) -#define _VLV_TX_DW14_CH0_GRP 0x82b8 -#define _VLV_TX_DW14_CH1_GRP 0x84b8 -#define VLV_TX_DW14_GRP(ch) _PORT(ch, _VLV_TX_DW14_CH0_GRP, _VLV_TX_DW14_CH1_GRP) +#define VLV_TX_DW14_GRP(ch) _VLV_TX_GRP((ch), 14) +#define VLV_TX_DW14(ch, lane) _VLV_TX((ch), (lane), 14) /* CHV dpPhy registers */ -#define _CHV_PLL_DW0_CH0 0x8000 -#define _CHV_PLL_DW0_CH1 0x8180 -#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) +#define CHV_PLL_DW0(ch) _CHV_PLL((ch), 0) -#define _CHV_PLL_DW1_CH0 0x8004 -#define _CHV_PLL_DW1_CH1 0x8184 +#define CHV_PLL_DW1(ch) _CHV_PLL((ch), 1) #define DPIO_CHV_N_DIV_SHIFT 8 #define DPIO_CHV_M1_DIV_BY_2 (0 << 0) -#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) -#define _CHV_PLL_DW2_CH0 0x8008 -#define _CHV_PLL_DW2_CH1 0x8188 -#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) +#define CHV_PLL_DW2(ch) _CHV_PLL((ch), 2) -#define _CHV_PLL_DW3_CH0 0x800c -#define _CHV_PLL_DW3_CH1 0x818c +#define CHV_PLL_DW3(ch) _CHV_PLL((ch), 3) #define DPIO_CHV_FRAC_DIV_EN (1 << 16) #define DPIO_CHV_FIRST_MOD (0 << 8) #define DPIO_CHV_SECOND_MOD (1 << 8) #define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 #define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) -#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) -#define _CHV_PLL_DW6_CH0 0x8018 -#define _CHV_PLL_DW6_CH1 0x8198 +#define CHV_PLL_DW6(ch) _CHV_PLL((ch), 6) #define DPIO_CHV_GAIN_CTRL_SHIFT 16 #define DPIO_CHV_INT_COEFF_SHIFT 8 #define DPIO_CHV_PROP_COEFF_SHIFT 0 -#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) -#define _CHV_PLL_DW8_CH0 0x8020 -#define _CHV_PLL_DW8_CH1 0x81A0 +#define CHV_PLL_DW8(ch) _CHV_PLL((ch), 8) #define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 #define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) -#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) -#define _CHV_PLL_DW9_CH0 0x8024 -#define _CHV_PLL_DW9_CH1 0x81A4 +#define CHV_PLL_DW9(ch) _CHV_PLL((ch), 9) #define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ #define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) #define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ -#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) -#define CHV_CMN_DW0_CH0 0x8100 +#define CHV_CMN_DW0_CH0 _CHV_CMN(0, 0) #define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 #define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 #define DPIO_ALLDL_POWERDOWN (1 << 1) #define DPIO_ANYDL_POWERDOWN (1 << 0) -#define CHV_CMN_DW5_CH0 0x8114 +#define CHV_CMN_DW5_CH0 _CHV_CMN(0, 5) #define CHV_BUFRIGHTENA1_DISABLE (0 << 20) #define CHV_BUFRIGHTENA1_NORMAL (1 << 20) #define CHV_BUFRIGHTENA1_FORCE (3 << 20) @@ -475,18 +401,18 @@ #define CHV_BUFLEFTENA1_FORCE (3 << 22) #define CHV_BUFLEFTENA1_MASK (3 << 22) -#define CHV_CMN_DW13_CH0 0x8134 -#define CHV_CMN_DW0_CH1 0x8080 +#define CHV_CMN_DW13_CH0 _CHV_CMN(0, 13) +#define CHV_CMN_DW0_CH1 _CHV_CMN(1, 0) #define DPIO_CHV_S1_DIV_SHIFT 21 #define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ #define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ #define DPIO_CHV_K_DIV_SHIFT 4 #define DPIO_PLL_FREQLOCK (1 << 1) #define DPIO_PLL_LOCK (1 << 0) -#define CHV_CMN_DW13(ch) _PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1) +#define CHV_CMN_DW13(ch) _PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1) -#define CHV_CMN_DW14_CH0 0x8138 -#define CHV_CMN_DW1_CH1 0x8084 +#define CHV_CMN_DW14_CH0 _CHV_CMN(0, 14) +#define CHV_CMN_DW1_CH1 _CHV_CMN(1, 1) #define DPIO_AFC_RECAL (1 << 14) #define DPIO_DCLKP_EN (1 << 13) #define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ @@ -497,17 +423,17 @@ #define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ #define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ #define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ -#define CHV_CMN_DW14(ch) _PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1) +#define CHV_CMN_DW14(ch) _PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1) -#define CHV_CMN_DW19_CH0 0x814c -#define CHV_CMN_DW6_CH1 0x8098 +#define CHV_CMN_DW19_CH0 _CHV_CMN(0, 19) +#define CHV_CMN_DW6_CH1 _CHV_CMN(1, 6) #define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ #define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ #define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ #define CHV_CMN_USEDCLKCHANNEL (1 << 13) -#define CHV_CMN_DW19(ch) _PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1) +#define CHV_CMN_DW19(ch) _PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1) -#define CHV_CMN_DW28 0x8170 +#define CHV_CMN_DW28 _CHV_CMN(0, 28) #define DPIO_CL1POWERDOWNEN (1 << 23) #define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) #define DPIO_SUS_CLK_CONFIG_ON (0 << 0) @@ -515,27 +441,26 @@ #define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) #define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) -#define CHV_CMN_DW30 0x8178 +#define CHV_CMN_DW30 _CHV_CMN(0, 30) #define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) #define DPIO_LRC_BYPASS (1 << 3) -#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ - (lane) * 0x200 + (offset)) +#define CHV_TX_DW0(ch, lane) _VLV_TX((ch), (lane), 0) +#define CHV_TX_DW1(ch, lane) _VLV_TX((ch), (lane), 1) +#define CHV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) +#define CHV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) +#define CHV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) +#define CHV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), 5) +#define CHV_TX_DW6(ch, lane) _VLV_TX((ch), (lane), 6) +#define CHV_TX_DW7(ch, lane) _VLV_TX((ch), (lane), 7) +#define CHV_TX_DW8(ch, lane) _VLV_TX((ch), (lane), 8) +#define CHV_TX_DW9(ch, lane) _VLV_TX((ch), (lane), 9) +#define CHV_TX_DW10(ch, lane) _VLV_TX((ch), (lane), 10) -#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) -#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) -#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) -#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) -#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) -#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) -#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) -#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) -#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) -#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) -#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) -#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) +#define CHV_TX_DW11(ch, lane) _VLV_TX((ch), (lane), 11) #define DPIO_FRC_LATENCY_SHFIT 8 -#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) + +#define CHV_TX_DW14(ch, lane) _VLV_TX((ch), (lane), 14) #define DPIO_UPAR_SHIFT 30 #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) From patchwork Mon Apr 22 08:34:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13637913 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 756BFC10F16 for ; Mon, 22 Apr 2024 08:35:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B59921128C1; Mon, 22 Apr 2024 08:35:38 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="D/Mj8en2"; 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E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="9453506" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Apr 2024 01:35:35 -0700 X-CSE-ConnectionGUID: Y2kfqrZPSjijh2on/IsiWw== X-CSE-MsgGUID: +L8Paw9cQ8m3sPZqmUsHsA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,220,1708416000"; d="scan'208";a="24021837" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Apr 2024 01:35:33 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 22 Apr 2024 11:35:32 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 13/14] drm/i915/dpio: Clean up the vlv/chv PHY register bits Date: Mon, 22 Apr 2024 11:34:56 +0300 Message-ID: <20240422083457.23815-14-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240422083457.23815-1-ville.syrjala@linux.intel.com> References: <20240422083457.23815-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Use REG_BIT() & co. for the vlv/chv DPIO PHY registers. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- .../i915/display/intel_display_power_well.c | 7 +- drivers/gpu/drm/i915/display/intel_dpio_phy.c | 59 ++-- drivers/gpu/drm/i915/display/intel_dpll.c | 85 +++-- drivers/gpu/drm/i915/i915_reg.h | 294 ++++++++++-------- 4 files changed, 236 insertions(+), 209 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 49114afc9a61..e4ba6efc90e6 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -1553,10 +1553,11 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi } if (ch == DPIO_CH0) - actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; + actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH0 | + DPIO_ALLDL_POWERDOWN_CH0, val); else - actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; - actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; + actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 | + DPIO_ALLDL_POWERDOWN_CH1, val); drm_WARN(&dev_priv->drm, actual != expected, "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index fa665d353df9..11875d18a8fc 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -757,7 +757,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, for (i = 0; i < crtc_state->lane_count; i++) { val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW4(ch, i)); val &= ~DPIO_SWING_DEEMPH9P5_MASK; - val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; + val |= DPIO_SWING_DEEMPH9P5(deemph_reg_value); vlv_dpio_write(dev_priv, phy, CHV_TX_DW4(ch, i), val); } @@ -766,15 +766,15 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW2(ch, i)); val &= ~DPIO_SWING_MARGIN000_MASK; - val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; + val |= DPIO_SWING_MARGIN000(margin_reg_value); /* * Supposedly this value shouldn't matter when unique transition * scale is disabled, but in fact it does matter. Let's just * always program the same value and hope it's OK. */ - val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); - val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; + val &= ~DPIO_UNIQ_TRANS_SCALE_MASK; + val |= DPIO_UNIQ_TRANS_SCALE(0x9a); vlv_dpio_write(dev_priv, phy, CHV_TX_DW2(ch, i), val); } @@ -902,20 +902,20 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, /* program clock channel usage */ val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(ch)); - val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; - if (pipe != PIPE_B) - val &= ~CHV_PCS_USEDCLKCHANNEL; + val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; + if (pipe == PIPE_B) + val |= DPIO_PCS_USEDCLKCHANNEL; else - val |= CHV_PCS_USEDCLKCHANNEL; + val &= ~DPIO_PCS_USEDCLKCHANNEL; vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW8(ch), val); if (crtc_state->lane_count > 2) { val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW8(ch)); - val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; - if (pipe != PIPE_B) - val &= ~CHV_PCS_USEDCLKCHANNEL; + val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; + if (pipe == PIPE_B) + val |= DPIO_PCS_USEDCLKCHANNEL; else - val |= CHV_PCS_USEDCLKCHANNEL; + val &= ~DPIO_PCS_USEDCLKCHANNEL; vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW8(ch), val); } @@ -925,10 +925,10 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, * pick the CL based on the port. */ val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW19(ch)); - if (pipe != PIPE_B) - val &= ~CHV_CMN_USEDCLKCHANNEL; - else + if (pipe == PIPE_B) val |= CHV_CMN_USEDCLKCHANNEL; + else + val &= ~CHV_CMN_USEDCLKCHANNEL; vlv_dpio_write(dev_priv, phy, CHV_CMN_DW19(ch), val); vlv_dpio_put(dev_priv); @@ -962,11 +962,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, for (i = 0; i < crtc_state->lane_count; i++) { /* Set the upar bit */ if (crtc_state->lane_count == 1) - data = 0x0; + data = 0; else - data = (i == 1) ? 0x0 : 0x1; - vlv_dpio_write(dev_priv, phy, CHV_TX_DW14(ch, i), - data << DPIO_UPAR_SHIFT); + data = (i == 1) ? 0 : DPIO_UPAR; + vlv_dpio_write(dev_priv, phy, CHV_TX_DW14(ch, i), data); } /* Data lane stagger programming */ @@ -1099,13 +1098,13 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, vlv_dpio_get(dev_priv); vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), - DPIO_PCS_TX_LANE2_RESET | - DPIO_PCS_TX_LANE1_RESET); + DPIO_PCS_TX_LANE2_RESET | + DPIO_PCS_TX_LANE1_RESET); vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), - DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | - DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | - (1<> DPIO_M1DIV_SHIFT) & 7; - clock.m2 = tmp & DPIO_M2DIV_MASK; - clock.n = (tmp >> DPIO_N_SHIFT) & 0xf; - clock.p1 = (tmp >> DPIO_P1_SHIFT) & 7; - clock.p2 = (tmp >> DPIO_P2_SHIFT) & 0x1f; + clock.m1 = REG_FIELD_GET(DPIO_M1_DIV_MASK, tmp); + clock.m2 = REG_FIELD_GET(DPIO_M2_DIV_MASK, tmp); + clock.n = REG_FIELD_GET(DPIO_N_DIV_MASK, tmp); + clock.p1 = REG_FIELD_GET(DPIO_P1_DIV_MASK, tmp); + clock.p2 = REG_FIELD_GET(DPIO_P2_DIV_MASK, tmp); crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock); } @@ -559,13 +559,13 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state) pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch)); vlv_dpio_put(dev_priv); - clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; - clock.m2 = (pll_dw0 & 0xff) << 22; + clock.m1 = REG_FIELD_GET(DPIO_CHV_M1_DIV_MASK, pll_dw1) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; + clock.m2 = REG_FIELD_GET(DPIO_CHV_M2_DIV_MASK, pll_dw0) << 22; if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) - clock.m2 |= pll_dw2 & 0x3fffff; - clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; - clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; - clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; + clock.m2 |= REG_FIELD_GET(DPIO_CHV_M2_FRAC_DIV_MASK, pll_dw2); + clock.n = REG_FIELD_GET(DPIO_CHV_N_DIV_MASK, pll_dw1); + clock.p1 = REG_FIELD_GET(DPIO_CHV_P1_DIV_MASK, cmn_dw13); + clock.p2 = REG_FIELD_GET(DPIO_CHV_P2_DIV_MASK, cmn_dw13); crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock); } @@ -1926,19 +1926,19 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610); /* Set idtafcrecal before PLL is enabled */ - tmp = (clock->m1 << DPIO_M1DIV_SHIFT) | - (clock->m2 & DPIO_M2DIV_MASK) | - (clock->p1 << DPIO_P1_SHIFT) | - (clock->p2 << DPIO_P2_SHIFT) | - (clock->n << DPIO_N_SHIFT) | - (1 << DPIO_K_SHIFT); + tmp = DPIO_M1_DIV(clock->m1) | + DPIO_M2_DIV(clock->m2) | + DPIO_P1_DIV(clock->p1) | + DPIO_P2_DIV(clock->p2) | + DPIO_N_DIV(clock->n) | + DPIO_K_DIV(1); /* * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, * but we don't support that). * Note: don't use the DAC post divider as it seems unstable. */ - tmp |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); + tmp |= DPIO_S1_DIV(DPIO_S1_DIV_HDMIDP); vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp); tmp |= DPIO_ENABLE_CALIBRATION; @@ -2034,34 +2034,33 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) u32 m2_frac; m2_frac = clock->m2 & 0x3fffff; - loopfilter = 0; vlv_dpio_get(dev_priv); /* p1 and p2 divider */ vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(ch), - 5 << DPIO_CHV_S1_DIV_SHIFT | - clock->p1 << DPIO_CHV_P1_DIV_SHIFT | - clock->p2 << DPIO_CHV_P2_DIV_SHIFT | - 1 << DPIO_CHV_K_DIV_SHIFT); + DPIO_CHV_S1_DIV(5) | + DPIO_CHV_P1_DIV(clock->p1) | + DPIO_CHV_P2_DIV(clock->p2) | + DPIO_CHV_K_DIV(1)); /* Feedback post-divider - m2 */ vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(ch), - clock->m2 >> 22); + DPIO_CHV_M2_DIV(clock->m2 >> 22)); /* Feedback refclk divider - n and m1 */ vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(ch), - DPIO_CHV_M1_DIV_BY_2 | - 1 << DPIO_CHV_N_DIV_SHIFT); + DPIO_CHV_M1_DIV(DPIO_CHV_M1_DIV_BY_2) | + DPIO_CHV_N_DIV(1)); /* M2 fraction division */ vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(ch), - m2_frac); + DPIO_CHV_M2_FRAC_DIV(m2_frac)); /* M2 fraction division enable */ tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch)); tmp &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); - tmp |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); + tmp |= DPIO_CHV_FEEDFWD_GAIN(2); if (m2_frac) tmp |= DPIO_CHV_FRAC_DIV_EN; vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(ch), tmp); @@ -2069,40 +2068,40 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) /* Program digital lock detect threshold */ tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(ch)); tmp &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | - DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); - tmp |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); + DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); + tmp |= DPIO_CHV_INT_LOCK_THRESHOLD(0x5); if (!m2_frac) tmp |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(ch), tmp); /* Loop filter */ if (clock->vco == 5400000) { - loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); - loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); - loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); + loopfilter = DPIO_CHV_PROP_COEFF(0x3) | + DPIO_CHV_INT_COEFF(0x8) | + DPIO_CHV_GAIN_CTRL(0x1); tribuf_calcntr = 0x9; } else if (clock->vco <= 6200000) { - loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); - loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); - loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); + loopfilter = DPIO_CHV_PROP_COEFF(0x5) | + DPIO_CHV_INT_COEFF(0xB) | + DPIO_CHV_GAIN_CTRL(0x3); tribuf_calcntr = 0x9; } else if (clock->vco <= 6480000) { - loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); - loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); - loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); + loopfilter = DPIO_CHV_PROP_COEFF(0x4) | + DPIO_CHV_INT_COEFF(0x9) | + DPIO_CHV_GAIN_CTRL(0x3); tribuf_calcntr = 0x8; } else { /* Not supported. Apply the same limits as in the max case */ - loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); - loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); - loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); + loopfilter = DPIO_CHV_PROP_COEFF(0x4) | + DPIO_CHV_INT_COEFF(0x9) | + DPIO_CHV_GAIN_CTRL(0x3); tribuf_calcntr = 0; } vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(ch), loopfilter); tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(ch)); tmp &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; - tmp |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); + tmp |= DPIO_CHV_TDC_TARGET_CNT(tribuf_calcntr); vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(ch), tmp); /* AFC Recal */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6d16f9944eff..a2313658ecae 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -211,27 +211,33 @@ * Per pipe/PLL DPIO regs */ #define VLV_PLL_DW3(ch) _VLV_PLL((ch), 3) -#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ -#define DPIO_POST_DIV_DAC 0 -#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ -#define DPIO_POST_DIV_LVDS1 2 -#define DPIO_POST_DIV_LVDS2 3 -#define DPIO_K_SHIFT (24) /* 4 bits */ -#define DPIO_P1_SHIFT (21) /* 3 bits */ -#define DPIO_P2_SHIFT (16) /* 5 bits */ -#define DPIO_N_SHIFT (12) /* 4 bits */ -#define DPIO_ENABLE_CALIBRATION (1 << 11) -#define DPIO_M1DIV_SHIFT (8) /* 3 bits */ -#define DPIO_M2DIV_MASK 0xff +#define DPIO_S1_DIV_MASK REG_GENMASK(30, 28) +#define DPIO_S1_DIV(s1) REG_FIELD_PREP(DPIO_S1_DIV_MASK, (s1)) +#define DPIO_S1_DIV_DAC 0 /* 10, DAC 25-225M rate */ +#define DPIO_S1_DIV_HDMIDP 1 /* 5, DAC 225-400M rate */ +#define DPIO_S1_DIV_LVDS1 2 /* 14 */ +#define DPIO_S1_DIV_LVDS2 3 /* 7 */ +#define DPIO_K_DIV_MASK REG_GENMASK(27, 24) +#define DPIO_K_DIV(k) REG_FIELD_PREP(DPIO_K_DIV_MASK, (k)) +#define DPIO_P1_DIV_MASK REG_GENMASK(23, 21) +#define DPIO_P1_DIV(p1) REG_FIELD_PREP(DPIO_P1_DIV_MASK, (p1)) +#define DPIO_P2_DIV_MASK REG_GENMASK(20, 16) +#define DPIO_P2_DIV(p2) REG_FIELD_PREP(DPIO_P2_DIV_MASK, (p2)) +#define DPIO_N_DIV_MASK REG_GENMASK(15, 12) +#define DPIO_N_DIV(n) REG_FIELD_PREP(DPIO_N_DIV_MASK, (n)) +#define DPIO_ENABLE_CALIBRATION REG_BIT(11) +#define DPIO_M1_DIV_MASK REG_GENMASK(10, 8) +#define DPIO_M1_DIV(m1) REG_FIELD_PREP(DPIO_M1_DIV_MASK, (m1)) +#define DPIO_M2_DIV_MASK REG_GENMASK(7, 0) +#define DPIO_M2_DIV(m2) REG_FIELD_PREP(DPIO_M2_DIV_MASK, (m2)) #define VLV_PLL_DW5(ch) _VLV_PLL((ch), 5) -#define DPIO_REFSEL_OVERRIDE 27 -#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ -#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ -#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ -#define DPIO_PLL_REFCLK_SEL_MASK 3 -#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ -#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ +#define DPIO_REFSEL_OVERRIDE REG_BIT(27) +#define DPIO_PLL_MODESEL_MASK REG_GENMASK(26, 24) +#define DPIO_BIAS_CURRENT_CTL_MASK REG_GENMASK(22, 20) /* always 0x7 */ +#define DPIO_PLL_REFCLK_SEL_MASK REG_GENMASK(17, 16) +#define DPIO_DRIVER_CTL_MASK REG_GENMASK(15, 12) /* always set to 0x8 */ +#define DPIO_CLK_BIAS_CTL_MASK REG_GENMASK(11, 8) /* always set to 0x5 */ #define VLV_PLL_DW7(ch) _VLV_PLL((ch), 7) @@ -253,101 +259,110 @@ #define VLV_PCS_DW0_GRP(ch) _VLV_PCS_GRP((ch), 0) #define VLV_PCS01_DW0(ch) _VLV_PCS((ch), 0, 0) #define VLV_PCS23_DW0(ch) _VLV_PCS((ch), 1, 0) -#define DPIO_PCS_TX_LANE2_RESET (1 << 16) -#define DPIO_PCS_TX_LANE1_RESET (1 << 7) -#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) -#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) +#define DPIO_PCS_TX_LANE2_RESET REG_BIT(16) +#define DPIO_PCS_TX_LANE1_RESET REG_BIT(7) +#define DPIO_LEFT_TXFIFO_RST_MASTER2 REG_BIT(4) +#define DPIO_RIGHT_TXFIFO_RST_MASTER2 REG_BIT(3) -#define VLV_PCS_DW1_GRP(ch) _VLV_PCS_GRP((ch), 1) -#define VLV_PCS01_DW1(ch) _VLV_PCS((ch), 0, 1) -#define VLV_PCS23_DW1(ch) _VLV_PCS((ch), 1, 1) -#define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) -#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) -#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) -#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) -#define DPIO_PCS_CLK_SOFT_RESET (1 << 5) +#define VLV_PCS_DW1_GRP(ch) _VLV_PCS_GRP((ch), 1) +#define VLV_PCS01_DW1(ch) _VLV_PCS((ch), 0, 1) +#define VLV_PCS23_DW1(ch) _VLV_PCS((ch), 1, 1) +#define CHV_PCS_REQ_SOFTRESET_EN REG_BIT(23) +#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN REG_BIT(22) +#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN REG_BIT(21) +#define DPIO_PCS_CLK_DATAWIDTH_MASK REG_GENMASK(7, 6) +#define DPIO_PCS_CLK_DATAWIDTH_8_10 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 1) +#define DPIO_PCS_CLK_DATAWIDTH_16_20 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 2) +#define DPIO_PCS_CLK_DATAWIDTH_32_40 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 3) +#define DPIO_PCS_CLK_SOFT_RESET REG_BIT(5) #define VLV_PCS_DW8_GRP(ch) _VLV_PCS_GRP((ch), 8) #define VLV_PCS01_DW8(ch) _VLV_PCS((ch), 0, 8) #define VLV_PCS23_DW8(ch) _VLV_PCS((ch), 1, 8) -#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) -#define CHV_PCS_USEDCLKCHANNEL (1 << 21) +#define DPIO_PCS_USEDCLKCHANNEL REG_BIT(21) +#define DPIO_PCS_USEDCLKCHANNEL_OVRRIDE REG_BIT(20) -#define VLV_PCS_DW9_GRP(ch) _VLV_PCS_GRP((ch), 9) +#define VLV_PCS_DW9_GRP(ch) _VLV_PCS_GRP((ch), 9) #define VLV_PCS01_DW9(ch) _VLV_PCS((ch), 0, 9) #define VLV_PCS23_DW9(ch) _VLV_PCS((ch), 1, 9) -#define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) -#define DPIO_PCS_TX2MARGIN_000 (0 << 13) -#define DPIO_PCS_TX2MARGIN_101 (1 << 13) -#define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) -#define DPIO_PCS_TX1MARGIN_000 (0 << 10) -#define DPIO_PCS_TX1MARGIN_101 (1 << 10) +#define DPIO_PCS_TX2MARGIN_MASK REG_GENMASK(15, 13) +#define DPIO_PCS_TX2MARGIN_000 REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 0) +#define DPIO_PCS_TX2MARGIN_101 REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 1) +#define DPIO_PCS_TX1MARGIN_MASK REG_GENMASK(12, 10) +#define DPIO_PCS_TX1MARGIN_000 REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 0) +#define DPIO_PCS_TX1MARGIN_101 REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 1) -#define VLV_PCS_DW10_GRP(ch) _VLV_PCS_GRP((ch), 10) +#define VLV_PCS_DW10_GRP(ch) _VLV_PCS_GRP((ch), 10) #define VLV_PCS01_DW10(ch) _VLV_PCS((ch), 0, 10) #define VLV_PCS23_DW10(ch) _VLV_PCS((ch), 1, 10) -#define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) -#define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) -#define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) -#define DPIO_PCS_TX2DEEMP_9P5 (0 << 24) -#define DPIO_PCS_TX2DEEMP_6P0 (2 << 24) -#define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) -#define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) -#define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) +#define DPIO_PCS_SWING_CALC_TX1_TX3 REG_BIT(31) +#define DPIO_PCS_SWING_CALC_TX0_TX2 REG_BIT(30) +#define DPIO_PCS_TX2DEEMP_MASK REG_GENMASK(27, 24) +#define DPIO_PCS_TX2DEEMP_9P5 REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 0) +#define DPIO_PCS_TX2DEEMP_6P0 REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 2) +#define DPIO_PCS_TX1DEEMP_MASK REG_GENMASK(19, 16) +#define DPIO_PCS_TX1DEEMP_9P5 REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 0) +#define DPIO_PCS_TX1DEEMP_6P0 REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 2) -#define VLV_PCS_DW11_GRP(ch) _VLV_PCS_GRP((ch), 11) +#define VLV_PCS_DW11_GRP(ch) _VLV_PCS_GRP((ch), 11) #define VLV_PCS01_DW11(ch) _VLV_PCS((ch), 0, 11) #define VLV_PCS23_DW11(ch) _VLV_PCS((ch), 1, 11) -#define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) -#define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) -#define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) -#define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) +#define DPIO_TX2_STAGGER_MASK_MASK REG_GENMASK(28, 24) +#define DPIO_TX2_STAGGER_MASK(x) REG_FIELD_PREP(DPIO_TX2_STAGGER_MASK_MASK, (x)) +#define DPIO_LANEDESKEW_STRAP_OVRD REG_BIT(3) +#define DPIO_LEFT_TXFIFO_RST_MASTER REG_BIT(1) +#define DPIO_RIGHT_TXFIFO_RST_MASTER REG_BIT(0) -#define VLV_PCS_DW12_GRP(ch) _VLV_PCS_GRP((ch), 12) +#define VLV_PCS_DW12_GRP(ch) _VLV_PCS_GRP((ch), 12) #define VLV_PCS01_DW12(ch) _VLV_PCS((ch), 0, 12) #define VLV_PCS23_DW12(ch) _VLV_PCS((ch), 1, 12) -#define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) -#define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) -#define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) -#define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) -#define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) +#define DPIO_TX2_STAGGER_MULT_MASK REG_GENMASK(22, 20) +#define DPIO_TX2_STAGGER_MULT(x) REG_FIELD_PREP(DPIO_TX2_STAGGER_MULT_MASK, (x)) +#define DPIO_TX1_STAGGER_MULT_MASK REG_GENMASK(20, 16) +#define DPIO_TX1_STAGGER_MULT(x) REG_FIELD_PREP(DPIO_TX1_STAGGER_MULT_MASK, (x)) +#define DPIO_TX1_STAGGER_MASK_MASK REG_GENMASK(12, 8) +#define DPIO_TX1_STAGGER_MASK(x) REG_FIELD_PREP(DPIO_TX1_STAGGER_MASK_MASK, (x)) +#define DPIO_LANESTAGGER_STRAP_OVRD REG_BIT(6) +#define DPIO_LANESTAGGER_STRAP_MASK REG_GENMASK(4, 0) +#define DPIO_LANESTAGGER_STRAP(x) REG_FIELD_PREP(DPIO_LANESTAGGER_STRAP_MASK, (x)) -#define VLV_PCS_DW14_GRP(ch) _VLV_PCS_GRP((ch), 14) +#define VLV_PCS_DW14_GRP(ch) _VLV_PCS_GRP((ch), 14) #define VLV_PCS01_DW14(ch) _VLV_PCS((ch), 0, 14) #define VLV_PCS23_DW14(ch) _VLV_PCS((ch), 1, 14) -#define VLV_PCS_DW17_BCAST _VLV_PCS_BCAST(17) -#define VLV_PCS_DW17_GRP(ch) _VLV_PCS_GRP((ch), 17) +#define VLV_PCS_DW17_BCAST _VLV_PCS_BCAST(17) +#define VLV_PCS_DW17_GRP(ch) _VLV_PCS_GRP((ch), 17) #define VLV_PCS01_DW17(ch) _VLV_PCS((ch), 0, 17) #define VLV_PCS23_DW17(ch) _VLV_PCS((ch), 1, 17) -#define VLV_PCS_DW23_GRP(ch) _VLV_PCS_GRP((ch), 23) +#define VLV_PCS_DW23_GRP(ch) _VLV_PCS_GRP((ch), 23) #define VLV_PCS01_DW23(ch) _VLV_PCS((ch), 0, 23) #define VLV_PCS23_DW23(ch) _VLV_PCS((ch), 1, 23) #define VLV_TX_DW2_GRP(ch) _VLV_TX_GRP((ch), 2) #define VLV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) -#define DPIO_SWING_MARGIN000_SHIFT 16 -#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) -#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 +#define DPIO_SWING_MARGIN000_MASK REG_GENMASK(23, 16) +#define DPIO_SWING_MARGIN000(x) REG_FIELD_PREP(DPIO_SWING_MARGIN000_MASK, (x)) +#define DPIO_UNIQ_TRANS_SCALE_MASK REG_GENMASK(15, 8) +#define DPIO_UNIQ_TRANS_SCALE(x) REG_FIELD_PREP(DPIO_UNIQ_TRANS_SCALE_MASK, (x)) #define VLV_TX_DW3_GRP(ch) _VLV_TX_GRP((ch), 3) #define VLV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) /* The following bit for CHV phy */ -#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) -#define DPIO_SWING_MARGIN101_SHIFT 16 -#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) +#define DPIO_TX_UNIQ_TRANS_SCALE_EN REG_BIT(27) +#define DPIO_SWING_MARGIN101_MASK REG_GENMASK(23, 16) +#define DPIO_SWING_MARGIN101(x) REG_FIELD_PREP(DPIO_SWING_MARGIN101_MASK, (x)) #define VLV_TX_DW4_GRP(ch) _VLV_TX_GRP((ch), 4) #define VLV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) -#define DPIO_SWING_DEEMPH9P5_SHIFT 24 -#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) -#define DPIO_SWING_DEEMPH6P0_SHIFT 16 -#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) +#define DPIO_SWING_DEEMPH9P5_MASK REG_GENMASK(31, 24) +#define DPIO_SWING_DEEMPH9P5(x) REG_FIELD_PREP(DPIO_SWING_DEEMPH9P5_MASK, (x)) +#define DPIO_SWING_DEEMPH6P0_MASK REG_GENMASK(23, 16) +#define DPIO_SWING_DEEMPH6P0_SHIFT REG_FIELD_PREP(DPIO_SWING_DEEMPH6P0_MASK, (x)) #define VLV_TX_DW5_GRP(ch) _VLV_TX_GRP((ch), 5) #define VLV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), 5) -#define DPIO_TX_OCALINIT_EN (1 << 31) +#define DPIO_TX_OCALINIT_EN REG_BIT(31) #define VLV_TX_DW11_GRP(ch) _VLV_TX_GRP((ch), 11) #define VLV_TX_DW11(ch, lane) _VLV_TX((ch), (lane), 11) @@ -357,93 +372,107 @@ /* CHV dpPhy registers */ #define CHV_PLL_DW0(ch) _CHV_PLL((ch), 0) +#define DPIO_CHV_M2_DIV_MASK REG_GENMASK(7, 0) +#define DPIO_CHV_M2_DIV(m2) REG_FIELD_PREP(DPIO_CHV_M2_DIV_MASK, (m2)) #define CHV_PLL_DW1(ch) _CHV_PLL((ch), 1) -#define DPIO_CHV_N_DIV_SHIFT 8 -#define DPIO_CHV_M1_DIV_BY_2 (0 << 0) +#define DPIO_CHV_N_DIV_MASK REG_GENMASK(11, 8) +#define DPIO_CHV_N_DIV(n) REG_FIELD_PREP(DPIO_CHV_N_DIV_MASK, (n)) +#define DPIO_CHV_M1_DIV_MASK REG_GENMASK(2, 0) +#define DPIO_CHV_M1_DIV(m1) REG_FIELD_PREP(DPIO_CHV_M1_DIV_MASK, (m1)) +#define DPIO_CHV_M1_DIV_BY_2 0 #define CHV_PLL_DW2(ch) _CHV_PLL((ch), 2) +#define DPIO_CHV_M2_FRAC_DIV_MASK REG_GENMASK(21, 0) +#define DPIO_CHV_M2_FRAC_DIV(m2_frac) REG_FIELD_PREP(DPIO_CHV_M2_FRAC_DIV_MASK, (m2_frac)) #define CHV_PLL_DW3(ch) _CHV_PLL((ch), 3) -#define DPIO_CHV_FRAC_DIV_EN (1 << 16) -#define DPIO_CHV_FIRST_MOD (0 << 8) -#define DPIO_CHV_SECOND_MOD (1 << 8) -#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 -#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) +#define DPIO_CHV_FRAC_DIV_EN REG_BIT(16) +#define DPIO_CHV_SECOND_MOD REG_BIT(8) +#define DPIO_CHV_FEEDFWD_GAIN_MASK REG_GENMASK(3, 0) +#define DPIO_CHV_FEEDFWD_GAIN(x) REG_FIELD_PREP(DPIO_CHV_FEEDFWD_GAIN_MASK, (x)) #define CHV_PLL_DW6(ch) _CHV_PLL((ch), 6) -#define DPIO_CHV_GAIN_CTRL_SHIFT 16 -#define DPIO_CHV_INT_COEFF_SHIFT 8 -#define DPIO_CHV_PROP_COEFF_SHIFT 0 +#define DPIO_CHV_GAIN_CTRL_MASK REG_GENMASK(18, 16) +#define DPIO_CHV_GAIN_CTRL(x) REG_FIELD_PREP(DPIO_CHV_GAIN_CTRL_MASK, (x)) +#define DPIO_CHV_INT_COEFF_MASK REG_GENMASK(12, 8) +#define DPIO_CHV_INT_COEFF(x) REG_FIELD_PREP(DPIO_CHV_INT_COEFF_MASK, (x)) +#define DPIO_CHV_PROP_COEFF_MASK REG_GENMASK(3, 0) +#define DPIO_CHV_PROP_COEFF(x) REG_FIELD_PREP(DPIO_CHV_PROP_COEFF_MASK, (x)) #define CHV_PLL_DW8(ch) _CHV_PLL((ch), 8) -#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 -#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) +#define DPIO_CHV_TDC_TARGET_CNT_MASK REG_GENMASK(9, 0) +#define DPIO_CHV_TDC_TARGET_CNT(x) REG_FIELD_PREP(DPIO_CHV_TDC_TARGET_CNT_MASK, (x)) #define CHV_PLL_DW9(ch) _CHV_PLL((ch), 9) -#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ -#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) -#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ +#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1) +#define DPIO_CHV_INT_LOCK_THRESHOLD(x) REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x)) +#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE REG_BIT(0) /* 1: coarse & 0 : fine */ #define CHV_CMN_DW0_CH0 _CHV_CMN(0, 0) -#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 -#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 -#define DPIO_ALLDL_POWERDOWN (1 << 1) -#define DPIO_ANYDL_POWERDOWN (1 << 0) +#define DPIO_ALLDL_POWERDOWN_CH0 REG_BIT(19) +#define DPIO_ANYDL_POWERDOWN_CH0 REG_BIT(18) +#define DPIO_ALLDL_POWERDOWN BIT(1) +#define DPIO_ANYDL_POWERDOWN BIT(0) #define CHV_CMN_DW5_CH0 _CHV_CMN(0, 5) -#define CHV_BUFRIGHTENA1_DISABLE (0 << 20) -#define CHV_BUFRIGHTENA1_NORMAL (1 << 20) -#define CHV_BUFRIGHTENA1_FORCE (3 << 20) -#define CHV_BUFRIGHTENA1_MASK (3 << 20) -#define CHV_BUFLEFTENA1_DISABLE (0 << 22) -#define CHV_BUFLEFTENA1_NORMAL (1 << 22) -#define CHV_BUFLEFTENA1_FORCE (3 << 22) -#define CHV_BUFLEFTENA1_MASK (3 << 22) +#define CHV_BUFRIGHTENA1_MASK REG_GENMASK(21, 20) +#define CHV_BUFRIGHTENA1_DISABLE REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 0) +#define CHV_BUFRIGHTENA1_NORMAL REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 1) +#define CHV_BUFRIGHTENA1_FORCE REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 3) +#define CHV_BUFLEFTENA1_MASK REG_GENMASK(23, 22) +#define CHV_BUFLEFTENA1_DISABLE REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 0) +#define CHV_BUFLEFTENA1_NORMAL REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 1) +#define CHV_BUFLEFTENA1_FORCE REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 3) #define CHV_CMN_DW13_CH0 _CHV_CMN(0, 13) #define CHV_CMN_DW0_CH1 _CHV_CMN(1, 0) -#define DPIO_CHV_S1_DIV_SHIFT 21 -#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ -#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ -#define DPIO_CHV_K_DIV_SHIFT 4 -#define DPIO_PLL_FREQLOCK (1 << 1) -#define DPIO_PLL_LOCK (1 << 0) +#define DPIO_CHV_S1_DIV_MASK REG_GENMASK(23, 21) +#define DPIO_CHV_S1_DIV(s1) REG_FIELD_PREP(DPIO_CHV_S1_DIV_MASK, (s1)) +#define DPIO_CHV_P1_DIV_MASK REG_GENMASK(15, 13) +#define DPIO_CHV_P1_DIV(p1) REG_FIELD_PREP(DPIO_CHV_P1_DIV_MASK, (p1)) +#define DPIO_CHV_P2_DIV_MASK REG_GENMASK(12, 8) +#define DPIO_CHV_P2_DIV(p2) REG_FIELD_PREP(DPIO_CHV_P2_DIV_MASK, (p2)) +#define DPIO_CHV_K_DIV_MASK REG_GENMASK(7, 4) +#define DPIO_CHV_K_DIV(k) REG_FIELD_PREP(DPIO_CHV_K_DIV_MASK, (k)) +#define DPIO_PLL_FREQLOCK REG_BIT(1) +#define DPIO_PLL_LOCK REG_BIT(0) #define CHV_CMN_DW13(ch) _PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1) #define CHV_CMN_DW14_CH0 _CHV_CMN(0, 14) #define CHV_CMN_DW1_CH1 _CHV_CMN(1, 1) -#define DPIO_AFC_RECAL (1 << 14) -#define DPIO_DCLKP_EN (1 << 13) -#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ -#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ -#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ -#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ -#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ -#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ -#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ -#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ +#define DPIO_AFC_RECAL REG_BIT(14) +#define DPIO_DCLKP_EN REG_BIT(13) +#define CHV_BUFLEFTENA2_MASK REG_GENMASK(18, 17) /* CL2 DW1 only */ +#define CHV_BUFLEFTENA2_DISABLE REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 0) +#define CHV_BUFLEFTENA2_NORMAL REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 1) +#define CHV_BUFLEFTENA2_FORCE REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 3) +#define CHV_BUFRIGHTENA2_MASK REG_GENMASK(20, 19) /* CL2 DW1 only */ +#define CHV_BUFRIGHTENA2_DISABLE REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 0) +#define CHV_BUFRIGHTENA2_NORMAL REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 1) +#define CHV_BUFRIGHTENA2_FORCE REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 3) #define CHV_CMN_DW14(ch) _PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1) #define CHV_CMN_DW19_CH0 _CHV_CMN(0, 19) #define CHV_CMN_DW6_CH1 _CHV_CMN(1, 6) -#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ -#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ -#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ -#define CHV_CMN_USEDCLKCHANNEL (1 << 13) +#define DPIO_ALLDL_POWERDOWN_CH1 REG_BIT(30) /* CL2 DW6 only */ +#define DPIO_ANYDL_POWERDOWN_CH1 REG_BIT(29) /* CL2 DW6 only */ +#define DPIO_DYNPWRDOWNEN_CH1 REG_BIT(28) /* CL2 DW6 only */ +#define CHV_CMN_USEDCLKCHANNEL REG_BIT(13) #define CHV_CMN_DW19(ch) _PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1) #define CHV_CMN_DW28 _CHV_CMN(0, 28) -#define DPIO_CL1POWERDOWNEN (1 << 23) -#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) -#define DPIO_SUS_CLK_CONFIG_ON (0 << 0) -#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) -#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) -#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) +#define DPIO_CL1POWERDOWNEN REG_BIT(23) +#define DPIO_DYNPWRDOWNEN_CH0 REG_BIT(22) +#define DPIO_SUS_CLK_CONFIG_MASK REG_GENMASK(1, 0) +#define DPIO_SUS_CLK_CONFIG_ON REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 0) +#define DPIO_SUS_CLK_CONFIG_CLKREQ REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 1) +#define DPIO_SUS_CLK_CONFIG_GATE REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 2) +#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 3) #define CHV_CMN_DW30 _CHV_CMN(0, 30) -#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) -#define DPIO_LRC_BYPASS (1 << 3) +#define DPIO_CL2_LDOFUSE_PWRENB REG_BIT(6) +#define DPIO_LRC_BYPASS REG_BIT(3) #define CHV_TX_DW0(ch, lane) _VLV_TX((ch), (lane), 0) #define CHV_TX_DW1(ch, lane) _VLV_TX((ch), (lane), 1) @@ -458,10 +487,11 @@ #define CHV_TX_DW10(ch, lane) _VLV_TX((ch), (lane), 10) #define CHV_TX_DW11(ch, lane) _VLV_TX((ch), (lane), 11) -#define DPIO_FRC_LATENCY_SHFIT 8 +#define DPIO_FRC_LATENCY_MASK REG_GENMASK(10, 8) +#define DPIO_FRC_LATENCY(x) REG_FIELD_PREP(DPIO_FRC_LATENCY_MASK, (x)) #define CHV_TX_DW14(ch, lane) _VLV_TX((ch), (lane), 14) -#define DPIO_UPAR_SHIFT 30 +#define DPIO_UPAR REG_BIT(30) #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) #define MIPIO_RST_CTRL (1 << 2) From patchwork Mon Apr 22 08:34:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13637914 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from 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stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 22 Apr 2024 01:35:36 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 22 Apr 2024 11:35:35 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 14/14] drm/i915/dpio: Extract vlv_dpio_phy_regs.h Date: Mon, 22 Apr 2024 11:34:57 +0300 Message-ID: <20240422083457.23815-15-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240422083457.23815-1-ville.syrjala@linux.intel.com> References: <20240422083457.23815-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Pull the VLV/CHV DPIO PHY sideband registers to their own file. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 1 + .../i915/display/intel_display_power_well.c | 1 + drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 + drivers/gpu/drm/i915/display/intel_dpll.c | 1 + .../gpu/drm/i915/display/vlv_dpio_phy_regs.h | 309 ++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 298 ----------------- 6 files changed, 313 insertions(+), 298 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 96ed1490fec7..59f989207c74 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -120,6 +120,7 @@ #include "skl_scaler.h" #include "skl_universal_plane.h" #include "skl_watermark.h" +#include "vlv_dpio_phy_regs.h" #include "vlv_dsi.h" #include "vlv_dsi_pll.h" #include "vlv_dsi_regs.h" diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index e4ba6efc90e6..83f616097a29 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -27,6 +27,7 @@ #include "intel_tc.h" #include "intel_vga.h" #include "skl_watermark.h" +#include "vlv_dpio_phy_regs.h" #include "vlv_sideband.h" #include "vlv_sideband_reg.h" diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 11875d18a8fc..d20e4e9cf7f7 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -30,6 +30,7 @@ #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dpio_phy.h" +#include "vlv_dpio_phy_regs.h" #include "vlv_sideband.h" /** diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index c2ee95993a96..a981f45facb3 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -20,6 +20,7 @@ #include "intel_panel.h" #include "intel_pps.h" #include "intel_snps_phy.h" +#include "vlv_dpio_phy_regs.h" #include "vlv_sideband.h" struct intel_dpll_funcs { diff --git a/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h b/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h new file mode 100644 index 000000000000..477506f0b2cc --- /dev/null +++ b/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h @@ -0,0 +1,309 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2023 Intel Corporation + */ + +#ifndef __VLV_DPIO_PHY_REGS_H__ +#define __VLV_DPIO_PHY_REGS_H__ + +#include "intel_display_reg_defs.h" + +#define _VLV_CMN(dw) (0x8100 + (dw) * 4) +#define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4) +#define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */ +#define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4) +#define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */ +#define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + (dw) * 4) +#define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4) +#define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4) +#define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) +#define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4) +#define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4) + +/* + * Per pipe/PLL DPIO regs + */ +#define VLV_PLL_DW3(ch) _VLV_PLL((ch), 3) +#define DPIO_S1_DIV_MASK REG_GENMASK(30, 28) +#define DPIO_S1_DIV(s1) REG_FIELD_PREP(DPIO_S1_DIV_MASK, (s1)) +#define DPIO_S1_DIV_DAC 0 /* 10, DAC 25-225M rate */ +#define DPIO_S1_DIV_HDMIDP 1 /* 5, DAC 225-400M rate */ +#define DPIO_S1_DIV_LVDS1 2 /* 14 */ +#define DPIO_S1_DIV_LVDS2 3 /* 7 */ +#define DPIO_K_DIV_MASK REG_GENMASK(27, 24) +#define DPIO_K_DIV(k) REG_FIELD_PREP(DPIO_K_DIV_MASK, (k)) +#define DPIO_P1_DIV_MASK REG_GENMASK(23, 21) +#define DPIO_P1_DIV(p1) REG_FIELD_PREP(DPIO_P1_DIV_MASK, (p1)) +#define DPIO_P2_DIV_MASK REG_GENMASK(20, 16) +#define DPIO_P2_DIV(p2) REG_FIELD_PREP(DPIO_P2_DIV_MASK, (p2)) +#define DPIO_N_DIV_MASK REG_GENMASK(15, 12) +#define DPIO_N_DIV(n) REG_FIELD_PREP(DPIO_N_DIV_MASK, (n)) +#define DPIO_ENABLE_CALIBRATION REG_BIT(11) +#define DPIO_M1_DIV_MASK REG_GENMASK(10, 8) +#define DPIO_M1_DIV(m1) REG_FIELD_PREP(DPIO_M1_DIV_MASK, (m1)) +#define DPIO_M2_DIV_MASK REG_GENMASK(7, 0) +#define DPIO_M2_DIV(m2) REG_FIELD_PREP(DPIO_M2_DIV_MASK, (m2)) + +#define VLV_PLL_DW5(ch) _VLV_PLL((ch), 5) +#define DPIO_REFSEL_OVERRIDE REG_BIT(27) +#define DPIO_PLL_MODESEL_MASK REG_GENMASK(26, 24) +#define DPIO_BIAS_CURRENT_CTL_MASK REG_GENMASK(22, 20) /* always 0x7 */ +#define DPIO_PLL_REFCLK_SEL_MASK REG_GENMASK(17, 16) +#define DPIO_DRIVER_CTL_MASK REG_GENMASK(15, 12) /* always set to 0x8 */ +#define DPIO_CLK_BIAS_CTL_MASK REG_GENMASK(11, 8) /* always set to 0x5 */ + +#define VLV_PLL_DW7(ch) _VLV_PLL((ch), 7) + +#define VLV_PLL_DW16(ch) _VLV_PLL((ch), 16) + +#define VLV_PLL_DW17(ch) _VLV_PLL((ch), 17) + +#define VLV_PLL_DW18(ch) _VLV_PLL((ch), 18) + +#define VLV_PLL_DW19(ch) _VLV_PLL((ch), 19) + +#define VLV_REF_DW11 _VLV_REF(11) + +#define VLV_CMN_DW0 _VLV_CMN(0) + +/* + * Per DDI channel DPIO regs + */ +#define VLV_PCS_DW0_GRP(ch) _VLV_PCS_GRP((ch), 0) +#define VLV_PCS01_DW0(ch) _VLV_PCS((ch), 0, 0) +#define VLV_PCS23_DW0(ch) _VLV_PCS((ch), 1, 0) +#define DPIO_PCS_TX_LANE2_RESET REG_BIT(16) +#define DPIO_PCS_TX_LANE1_RESET REG_BIT(7) +#define DPIO_LEFT_TXFIFO_RST_MASTER2 REG_BIT(4) +#define DPIO_RIGHT_TXFIFO_RST_MASTER2 REG_BIT(3) + +#define VLV_PCS_DW1_GRP(ch) _VLV_PCS_GRP((ch), 1) +#define VLV_PCS01_DW1(ch) _VLV_PCS((ch), 0, 1) +#define VLV_PCS23_DW1(ch) _VLV_PCS((ch), 1, 1) +#define CHV_PCS_REQ_SOFTRESET_EN REG_BIT(23) +#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN REG_BIT(22) +#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN REG_BIT(21) +#define DPIO_PCS_CLK_DATAWIDTH_MASK REG_GENMASK(7, 6) +#define DPIO_PCS_CLK_DATAWIDTH_8_10 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 1) +#define DPIO_PCS_CLK_DATAWIDTH_16_20 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 2) +#define DPIO_PCS_CLK_DATAWIDTH_32_40 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 3) +#define DPIO_PCS_CLK_SOFT_RESET REG_BIT(5) + +#define VLV_PCS_DW8_GRP(ch) _VLV_PCS_GRP((ch), 8) +#define VLV_PCS01_DW8(ch) _VLV_PCS((ch), 0, 8) +#define VLV_PCS23_DW8(ch) _VLV_PCS((ch), 1, 8) +#define DPIO_PCS_USEDCLKCHANNEL REG_BIT(21) +#define DPIO_PCS_USEDCLKCHANNEL_OVRRIDE REG_BIT(20) + +#define VLV_PCS_DW9_GRP(ch) _VLV_PCS_GRP((ch), 9) +#define VLV_PCS01_DW9(ch) _VLV_PCS((ch), 0, 9) +#define VLV_PCS23_DW9(ch) _VLV_PCS((ch), 1, 9) +#define DPIO_PCS_TX2MARGIN_MASK REG_GENMASK(15, 13) +#define DPIO_PCS_TX2MARGIN_000 REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 0) +#define DPIO_PCS_TX2MARGIN_101 REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 1) +#define DPIO_PCS_TX1MARGIN_MASK REG_GENMASK(12, 10) +#define DPIO_PCS_TX1MARGIN_000 REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 0) +#define DPIO_PCS_TX1MARGIN_101 REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 1) + +#define VLV_PCS_DW10_GRP(ch) _VLV_PCS_GRP((ch), 10) +#define VLV_PCS01_DW10(ch) _VLV_PCS((ch), 0, 10) +#define VLV_PCS23_DW10(ch) _VLV_PCS((ch), 1, 10) +#define DPIO_PCS_SWING_CALC_TX1_TX3 REG_BIT(31) +#define DPIO_PCS_SWING_CALC_TX0_TX2 REG_BIT(30) +#define DPIO_PCS_TX2DEEMP_MASK REG_GENMASK(27, 24) +#define DPIO_PCS_TX2DEEMP_9P5 REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 0) +#define DPIO_PCS_TX2DEEMP_6P0 REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 2) +#define DPIO_PCS_TX1DEEMP_MASK REG_GENMASK(19, 16) +#define DPIO_PCS_TX1DEEMP_9P5 REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 0) +#define DPIO_PCS_TX1DEEMP_6P0 REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 2) + +#define VLV_PCS_DW11_GRP(ch) _VLV_PCS_GRP((ch), 11) +#define VLV_PCS01_DW11(ch) _VLV_PCS((ch), 0, 11) +#define VLV_PCS23_DW11(ch) _VLV_PCS((ch), 1, 11) +#define DPIO_TX2_STAGGER_MASK_MASK REG_GENMASK(28, 24) +#define DPIO_TX2_STAGGER_MASK(x) REG_FIELD_PREP(DPIO_TX2_STAGGER_MASK_MASK, (x)) +#define DPIO_LANEDESKEW_STRAP_OVRD REG_BIT(3) +#define DPIO_LEFT_TXFIFO_RST_MASTER REG_BIT(1) +#define DPIO_RIGHT_TXFIFO_RST_MASTER REG_BIT(0) + +#define VLV_PCS_DW12_GRP(ch) _VLV_PCS_GRP((ch), 12) +#define VLV_PCS01_DW12(ch) _VLV_PCS((ch), 0, 12) +#define VLV_PCS23_DW12(ch) _VLV_PCS((ch), 1, 12) +#define DPIO_TX2_STAGGER_MULT_MASK REG_GENMASK(22, 20) +#define DPIO_TX2_STAGGER_MULT(x) REG_FIELD_PREP(DPIO_TX2_STAGGER_MULT_MASK, (x)) +#define DPIO_TX1_STAGGER_MULT_MASK REG_GENMASK(20, 16) +#define DPIO_TX1_STAGGER_MULT(x) REG_FIELD_PREP(DPIO_TX1_STAGGER_MULT_MASK, (x)) +#define DPIO_TX1_STAGGER_MASK_MASK REG_GENMASK(12, 8) +#define DPIO_TX1_STAGGER_MASK(x) REG_FIELD_PREP(DPIO_TX1_STAGGER_MASK_MASK, (x)) +#define DPIO_LANESTAGGER_STRAP_OVRD REG_BIT(6) +#define DPIO_LANESTAGGER_STRAP_MASK REG_GENMASK(4, 0) +#define DPIO_LANESTAGGER_STRAP(x) REG_FIELD_PREP(DPIO_LANESTAGGER_STRAP_MASK, (x)) + +#define VLV_PCS_DW14_GRP(ch) _VLV_PCS_GRP((ch), 14) +#define VLV_PCS01_DW14(ch) _VLV_PCS((ch), 0, 14) +#define VLV_PCS23_DW14(ch) _VLV_PCS((ch), 1, 14) + +#define VLV_PCS_DW17_BCAST _VLV_PCS_BCAST(17) +#define VLV_PCS_DW17_GRP(ch) _VLV_PCS_GRP((ch), 17) +#define VLV_PCS01_DW17(ch) _VLV_PCS((ch), 0, 17) +#define VLV_PCS23_DW17(ch) _VLV_PCS((ch), 1, 17) + +#define VLV_PCS_DW23_GRP(ch) _VLV_PCS_GRP((ch), 23) +#define VLV_PCS01_DW23(ch) _VLV_PCS((ch), 0, 23) +#define VLV_PCS23_DW23(ch) _VLV_PCS((ch), 1, 23) + +#define VLV_TX_DW2_GRP(ch) _VLV_TX_GRP((ch), 2) +#define VLV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) +#define DPIO_SWING_MARGIN000_MASK REG_GENMASK(23, 16) +#define DPIO_SWING_MARGIN000(x) REG_FIELD_PREP(DPIO_SWING_MARGIN000_MASK, (x)) +#define DPIO_UNIQ_TRANS_SCALE_MASK REG_GENMASK(15, 8) +#define DPIO_UNIQ_TRANS_SCALE(x) REG_FIELD_PREP(DPIO_UNIQ_TRANS_SCALE_MASK, (x)) + +#define VLV_TX_DW3_GRP(ch) _VLV_TX_GRP((ch), 3) +#define VLV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) +/* The following bit for CHV phy */ +#define DPIO_TX_UNIQ_TRANS_SCALE_EN REG_BIT(27) +#define DPIO_SWING_MARGIN101_MASK REG_GENMASK(23, 16) +#define DPIO_SWING_MARGIN101(x) REG_FIELD_PREP(DPIO_SWING_MARGIN101_MASK, (x)) + +#define VLV_TX_DW4_GRP(ch) _VLV_TX_GRP((ch), 4) +#define VLV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) +#define DPIO_SWING_DEEMPH9P5_MASK REG_GENMASK(31, 24) +#define DPIO_SWING_DEEMPH9P5(x) REG_FIELD_PREP(DPIO_SWING_DEEMPH9P5_MASK, (x)) +#define DPIO_SWING_DEEMPH6P0_MASK REG_GENMASK(23, 16) +#define DPIO_SWING_DEEMPH6P0_SHIFT REG_FIELD_PREP(DPIO_SWING_DEEMPH6P0_MASK, (x)) + +#define VLV_TX_DW5_GRP(ch) _VLV_TX_GRP((ch), 5) +#define VLV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), 5) +#define DPIO_TX_OCALINIT_EN REG_BIT(31) + +#define VLV_TX_DW11_GRP(ch) _VLV_TX_GRP((ch), 11) +#define VLV_TX_DW11(ch, lane) _VLV_TX((ch), (lane), 11) + +#define VLV_TX_DW14_GRP(ch) _VLV_TX_GRP((ch), 14) +#define VLV_TX_DW14(ch, lane) _VLV_TX((ch), (lane), 14) + +/* CHV dpPhy registers */ +#define CHV_PLL_DW0(ch) _CHV_PLL((ch), 0) +#define DPIO_CHV_M2_DIV_MASK REG_GENMASK(7, 0) +#define DPIO_CHV_M2_DIV(m2) REG_FIELD_PREP(DPIO_CHV_M2_DIV_MASK, (m2)) + +#define CHV_PLL_DW1(ch) _CHV_PLL((ch), 1) +#define DPIO_CHV_N_DIV_MASK REG_GENMASK(11, 8) +#define DPIO_CHV_N_DIV(n) REG_FIELD_PREP(DPIO_CHV_N_DIV_MASK, (n)) +#define DPIO_CHV_M1_DIV_MASK REG_GENMASK(2, 0) +#define DPIO_CHV_M1_DIV(m1) REG_FIELD_PREP(DPIO_CHV_M1_DIV_MASK, (m1)) +#define DPIO_CHV_M1_DIV_BY_2 0 + +#define CHV_PLL_DW2(ch) _CHV_PLL((ch), 2) +#define DPIO_CHV_M2_FRAC_DIV_MASK REG_GENMASK(21, 0) +#define DPIO_CHV_M2_FRAC_DIV(m2_frac) REG_FIELD_PREP(DPIO_CHV_M2_FRAC_DIV_MASK, (m2_frac)) + +#define CHV_PLL_DW3(ch) _CHV_PLL((ch), 3) +#define DPIO_CHV_FRAC_DIV_EN REG_BIT(16) +#define DPIO_CHV_SECOND_MOD REG_BIT(8) +#define DPIO_CHV_FEEDFWD_GAIN_MASK REG_GENMASK(3, 0) +#define DPIO_CHV_FEEDFWD_GAIN(x) REG_FIELD_PREP(DPIO_CHV_FEEDFWD_GAIN_MASK, (x)) + +#define CHV_PLL_DW6(ch) _CHV_PLL((ch), 6) +#define DPIO_CHV_GAIN_CTRL_MASK REG_GENMASK(18, 16) +#define DPIO_CHV_GAIN_CTRL(x) REG_FIELD_PREP(DPIO_CHV_GAIN_CTRL_MASK, (x)) +#define DPIO_CHV_INT_COEFF_MASK REG_GENMASK(12, 8) +#define DPIO_CHV_INT_COEFF(x) REG_FIELD_PREP(DPIO_CHV_INT_COEFF_MASK, (x)) +#define DPIO_CHV_PROP_COEFF_MASK REG_GENMASK(3, 0) +#define DPIO_CHV_PROP_COEFF(x) REG_FIELD_PREP(DPIO_CHV_PROP_COEFF_MASK, (x)) + +#define CHV_PLL_DW8(ch) _CHV_PLL((ch), 8) +#define DPIO_CHV_TDC_TARGET_CNT_MASK REG_GENMASK(9, 0) +#define DPIO_CHV_TDC_TARGET_CNT(x) REG_FIELD_PREP(DPIO_CHV_TDC_TARGET_CNT_MASK, (x)) + +#define CHV_PLL_DW9(ch) _CHV_PLL((ch), 9) +#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1) +#define DPIO_CHV_INT_LOCK_THRESHOLD(x) REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x)) +#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE REG_BIT(0) /* 1: coarse & 0 : fine */ + +#define CHV_CMN_DW0_CH0 _CHV_CMN(0, 0) +#define DPIO_ALLDL_POWERDOWN_CH0 REG_BIT(19) +#define DPIO_ANYDL_POWERDOWN_CH0 REG_BIT(18) +#define DPIO_ALLDL_POWERDOWN BIT(1) +#define DPIO_ANYDL_POWERDOWN BIT(0) + +#define CHV_CMN_DW5_CH0 _CHV_CMN(0, 5) +#define CHV_BUFRIGHTENA1_MASK REG_GENMASK(21, 20) +#define CHV_BUFRIGHTENA1_DISABLE REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 0) +#define CHV_BUFRIGHTENA1_NORMAL REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 1) +#define CHV_BUFRIGHTENA1_FORCE REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 3) +#define CHV_BUFLEFTENA1_MASK REG_GENMASK(23, 22) +#define CHV_BUFLEFTENA1_DISABLE REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 0) +#define CHV_BUFLEFTENA1_NORMAL REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 1) +#define CHV_BUFLEFTENA1_FORCE REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 3) + +#define CHV_CMN_DW13_CH0 _CHV_CMN(0, 13) +#define CHV_CMN_DW0_CH1 _CHV_CMN(1, 0) +#define DPIO_CHV_S1_DIV_MASK REG_GENMASK(23, 21) +#define DPIO_CHV_S1_DIV(s1) REG_FIELD_PREP(DPIO_CHV_S1_DIV_MASK, (s1)) +#define DPIO_CHV_P1_DIV_MASK REG_GENMASK(15, 13) +#define DPIO_CHV_P1_DIV(p1) REG_FIELD_PREP(DPIO_CHV_P1_DIV_MASK, (p1)) +#define DPIO_CHV_P2_DIV_MASK REG_GENMASK(12, 8) +#define DPIO_CHV_P2_DIV(p2) REG_FIELD_PREP(DPIO_CHV_P2_DIV_MASK, (p2)) +#define DPIO_CHV_K_DIV_MASK REG_GENMASK(7, 4) +#define DPIO_CHV_K_DIV(k) REG_FIELD_PREP(DPIO_CHV_K_DIV_MASK, (k)) +#define DPIO_PLL_FREQLOCK REG_BIT(1) +#define DPIO_PLL_LOCK REG_BIT(0) +#define CHV_CMN_DW13(ch) _PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1) + +#define CHV_CMN_DW14_CH0 _CHV_CMN(0, 14) +#define CHV_CMN_DW1_CH1 _CHV_CMN(1, 1) +#define DPIO_AFC_RECAL REG_BIT(14) +#define DPIO_DCLKP_EN REG_BIT(13) +#define CHV_BUFLEFTENA2_MASK REG_GENMASK(18, 17) /* CL2 DW1 only */ +#define CHV_BUFLEFTENA2_DISABLE REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 0) +#define CHV_BUFLEFTENA2_NORMAL REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 1) +#define CHV_BUFLEFTENA2_FORCE REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 3) +#define CHV_BUFRIGHTENA2_MASK REG_GENMASK(20, 19) /* CL2 DW1 only */ +#define CHV_BUFRIGHTENA2_DISABLE REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 0) +#define CHV_BUFRIGHTENA2_NORMAL REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 1) +#define CHV_BUFRIGHTENA2_FORCE REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 3) +#define CHV_CMN_DW14(ch) _PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1) + +#define CHV_CMN_DW19_CH0 _CHV_CMN(0, 19) +#define CHV_CMN_DW6_CH1 _CHV_CMN(1, 6) +#define DPIO_ALLDL_POWERDOWN_CH1 REG_BIT(30) /* CL2 DW6 only */ +#define DPIO_ANYDL_POWERDOWN_CH1 REG_BIT(29) /* CL2 DW6 only */ +#define DPIO_DYNPWRDOWNEN_CH1 REG_BIT(28) /* CL2 DW6 only */ +#define CHV_CMN_USEDCLKCHANNEL REG_BIT(13) +#define CHV_CMN_DW19(ch) _PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1) + +#define CHV_CMN_DW28 _CHV_CMN(0, 28) +#define DPIO_CL1POWERDOWNEN REG_BIT(23) +#define DPIO_DYNPWRDOWNEN_CH0 REG_BIT(22) +#define DPIO_SUS_CLK_CONFIG_MASK REG_GENMASK(1, 0) +#define DPIO_SUS_CLK_CONFIG_ON REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 0) +#define DPIO_SUS_CLK_CONFIG_CLKREQ REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 1) +#define DPIO_SUS_CLK_CONFIG_GATE REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 2) +#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 3) + +#define CHV_CMN_DW30 _CHV_CMN(0, 30) +#define DPIO_CL2_LDOFUSE_PWRENB REG_BIT(6) +#define DPIO_LRC_BYPASS REG_BIT(3) + +#define CHV_TX_DW0(ch, lane) _VLV_TX((ch), (lane), 0) +#define CHV_TX_DW1(ch, lane) _VLV_TX((ch), (lane), 1) +#define CHV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) +#define CHV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) +#define CHV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) +#define CHV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), 5) +#define CHV_TX_DW6(ch, lane) _VLV_TX((ch), (lane), 6) +#define CHV_TX_DW7(ch, lane) _VLV_TX((ch), (lane), 7) +#define CHV_TX_DW8(ch, lane) _VLV_TX((ch), (lane), 8) +#define CHV_TX_DW9(ch, lane) _VLV_TX((ch), (lane), 9) +#define CHV_TX_DW10(ch, lane) _VLV_TX((ch), (lane), 10) + +#define CHV_TX_DW11(ch, lane) _VLV_TX((ch), (lane), 11) +#define DPIO_FRC_LATENCY_MASK REG_GENMASK(10, 8) +#define DPIO_FRC_LATENCY(x) REG_FIELD_PREP(DPIO_FRC_LATENCY_MASK, (x)) + +#define CHV_TX_DW14(ch, lane) _VLV_TX((ch), (lane), 14) +#define DPIO_UPAR REG_BIT(30) + +#endif /* __VLV_DPIO_PHY_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a2313658ecae..481ae5529ba2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -195,304 +195,6 @@ #define DPIO_SFR_BYPASS (1 << 1) #define DPIO_CMNRST (1 << 0) -#define _VLV_CMN(dw) (0x8100 + (dw) * 4) -#define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4) -#define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */ -#define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4) -#define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */ -#define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + (dw) * 4) -#define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4) -#define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4) -#define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) -#define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4) -#define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4) - -/* - * Per pipe/PLL DPIO regs - */ -#define VLV_PLL_DW3(ch) _VLV_PLL((ch), 3) -#define DPIO_S1_DIV_MASK REG_GENMASK(30, 28) -#define DPIO_S1_DIV(s1) REG_FIELD_PREP(DPIO_S1_DIV_MASK, (s1)) -#define DPIO_S1_DIV_DAC 0 /* 10, DAC 25-225M rate */ -#define DPIO_S1_DIV_HDMIDP 1 /* 5, DAC 225-400M rate */ -#define DPIO_S1_DIV_LVDS1 2 /* 14 */ -#define DPIO_S1_DIV_LVDS2 3 /* 7 */ -#define DPIO_K_DIV_MASK REG_GENMASK(27, 24) -#define DPIO_K_DIV(k) REG_FIELD_PREP(DPIO_K_DIV_MASK, (k)) -#define DPIO_P1_DIV_MASK REG_GENMASK(23, 21) -#define DPIO_P1_DIV(p1) REG_FIELD_PREP(DPIO_P1_DIV_MASK, (p1)) -#define DPIO_P2_DIV_MASK REG_GENMASK(20, 16) -#define DPIO_P2_DIV(p2) REG_FIELD_PREP(DPIO_P2_DIV_MASK, (p2)) -#define DPIO_N_DIV_MASK REG_GENMASK(15, 12) -#define DPIO_N_DIV(n) REG_FIELD_PREP(DPIO_N_DIV_MASK, (n)) -#define DPIO_ENABLE_CALIBRATION REG_BIT(11) -#define DPIO_M1_DIV_MASK REG_GENMASK(10, 8) -#define DPIO_M1_DIV(m1) REG_FIELD_PREP(DPIO_M1_DIV_MASK, (m1)) -#define DPIO_M2_DIV_MASK REG_GENMASK(7, 0) -#define DPIO_M2_DIV(m2) REG_FIELD_PREP(DPIO_M2_DIV_MASK, (m2)) - -#define VLV_PLL_DW5(ch) _VLV_PLL((ch), 5) -#define DPIO_REFSEL_OVERRIDE REG_BIT(27) -#define DPIO_PLL_MODESEL_MASK REG_GENMASK(26, 24) -#define DPIO_BIAS_CURRENT_CTL_MASK REG_GENMASK(22, 20) /* always 0x7 */ -#define DPIO_PLL_REFCLK_SEL_MASK REG_GENMASK(17, 16) -#define DPIO_DRIVER_CTL_MASK REG_GENMASK(15, 12) /* always set to 0x8 */ -#define DPIO_CLK_BIAS_CTL_MASK REG_GENMASK(11, 8) /* always set to 0x5 */ - -#define VLV_PLL_DW7(ch) _VLV_PLL((ch), 7) - -#define VLV_PLL_DW16(ch) _VLV_PLL((ch), 16) - -#define VLV_PLL_DW17(ch) _VLV_PLL((ch), 17) - -#define VLV_PLL_DW18(ch) _VLV_PLL((ch), 18) - -#define VLV_PLL_DW19(ch) _VLV_PLL((ch), 19) - -#define VLV_REF_DW11 _VLV_REF(11) - -#define VLV_CMN_DW0 _VLV_CMN(0) - -/* - * Per DDI channel DPIO regs - */ -#define VLV_PCS_DW0_GRP(ch) _VLV_PCS_GRP((ch), 0) -#define VLV_PCS01_DW0(ch) _VLV_PCS((ch), 0, 0) -#define VLV_PCS23_DW0(ch) _VLV_PCS((ch), 1, 0) -#define DPIO_PCS_TX_LANE2_RESET REG_BIT(16) -#define DPIO_PCS_TX_LANE1_RESET REG_BIT(7) -#define DPIO_LEFT_TXFIFO_RST_MASTER2 REG_BIT(4) -#define DPIO_RIGHT_TXFIFO_RST_MASTER2 REG_BIT(3) - -#define VLV_PCS_DW1_GRP(ch) _VLV_PCS_GRP((ch), 1) -#define VLV_PCS01_DW1(ch) _VLV_PCS((ch), 0, 1) -#define VLV_PCS23_DW1(ch) _VLV_PCS((ch), 1, 1) -#define CHV_PCS_REQ_SOFTRESET_EN REG_BIT(23) -#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN REG_BIT(22) -#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN REG_BIT(21) -#define DPIO_PCS_CLK_DATAWIDTH_MASK REG_GENMASK(7, 6) -#define DPIO_PCS_CLK_DATAWIDTH_8_10 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 1) -#define DPIO_PCS_CLK_DATAWIDTH_16_20 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 2) -#define DPIO_PCS_CLK_DATAWIDTH_32_40 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 3) -#define DPIO_PCS_CLK_SOFT_RESET REG_BIT(5) - -#define VLV_PCS_DW8_GRP(ch) _VLV_PCS_GRP((ch), 8) -#define VLV_PCS01_DW8(ch) _VLV_PCS((ch), 0, 8) -#define VLV_PCS23_DW8(ch) _VLV_PCS((ch), 1, 8) -#define DPIO_PCS_USEDCLKCHANNEL REG_BIT(21) -#define DPIO_PCS_USEDCLKCHANNEL_OVRRIDE REG_BIT(20) - -#define VLV_PCS_DW9_GRP(ch) _VLV_PCS_GRP((ch), 9) -#define VLV_PCS01_DW9(ch) _VLV_PCS((ch), 0, 9) -#define VLV_PCS23_DW9(ch) _VLV_PCS((ch), 1, 9) -#define DPIO_PCS_TX2MARGIN_MASK REG_GENMASK(15, 13) -#define DPIO_PCS_TX2MARGIN_000 REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 0) -#define DPIO_PCS_TX2MARGIN_101 REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 1) -#define DPIO_PCS_TX1MARGIN_MASK REG_GENMASK(12, 10) -#define DPIO_PCS_TX1MARGIN_000 REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 0) -#define DPIO_PCS_TX1MARGIN_101 REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 1) - -#define VLV_PCS_DW10_GRP(ch) _VLV_PCS_GRP((ch), 10) -#define VLV_PCS01_DW10(ch) _VLV_PCS((ch), 0, 10) -#define VLV_PCS23_DW10(ch) _VLV_PCS((ch), 1, 10) -#define DPIO_PCS_SWING_CALC_TX1_TX3 REG_BIT(31) -#define DPIO_PCS_SWING_CALC_TX0_TX2 REG_BIT(30) -#define DPIO_PCS_TX2DEEMP_MASK REG_GENMASK(27, 24) -#define DPIO_PCS_TX2DEEMP_9P5 REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 0) -#define DPIO_PCS_TX2DEEMP_6P0 REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 2) -#define DPIO_PCS_TX1DEEMP_MASK REG_GENMASK(19, 16) -#define DPIO_PCS_TX1DEEMP_9P5 REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 0) -#define DPIO_PCS_TX1DEEMP_6P0 REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 2) - -#define VLV_PCS_DW11_GRP(ch) _VLV_PCS_GRP((ch), 11) -#define VLV_PCS01_DW11(ch) _VLV_PCS((ch), 0, 11) -#define VLV_PCS23_DW11(ch) _VLV_PCS((ch), 1, 11) -#define DPIO_TX2_STAGGER_MASK_MASK REG_GENMASK(28, 24) -#define DPIO_TX2_STAGGER_MASK(x) REG_FIELD_PREP(DPIO_TX2_STAGGER_MASK_MASK, (x)) -#define DPIO_LANEDESKEW_STRAP_OVRD REG_BIT(3) -#define DPIO_LEFT_TXFIFO_RST_MASTER REG_BIT(1) -#define DPIO_RIGHT_TXFIFO_RST_MASTER REG_BIT(0) - -#define VLV_PCS_DW12_GRP(ch) _VLV_PCS_GRP((ch), 12) -#define VLV_PCS01_DW12(ch) _VLV_PCS((ch), 0, 12) -#define VLV_PCS23_DW12(ch) _VLV_PCS((ch), 1, 12) -#define DPIO_TX2_STAGGER_MULT_MASK REG_GENMASK(22, 20) -#define DPIO_TX2_STAGGER_MULT(x) REG_FIELD_PREP(DPIO_TX2_STAGGER_MULT_MASK, (x)) -#define DPIO_TX1_STAGGER_MULT_MASK REG_GENMASK(20, 16) -#define DPIO_TX1_STAGGER_MULT(x) REG_FIELD_PREP(DPIO_TX1_STAGGER_MULT_MASK, (x)) -#define DPIO_TX1_STAGGER_MASK_MASK REG_GENMASK(12, 8) -#define DPIO_TX1_STAGGER_MASK(x) REG_FIELD_PREP(DPIO_TX1_STAGGER_MASK_MASK, (x)) -#define DPIO_LANESTAGGER_STRAP_OVRD REG_BIT(6) -#define DPIO_LANESTAGGER_STRAP_MASK REG_GENMASK(4, 0) -#define DPIO_LANESTAGGER_STRAP(x) REG_FIELD_PREP(DPIO_LANESTAGGER_STRAP_MASK, (x)) - -#define VLV_PCS_DW14_GRP(ch) _VLV_PCS_GRP((ch), 14) -#define VLV_PCS01_DW14(ch) _VLV_PCS((ch), 0, 14) -#define VLV_PCS23_DW14(ch) _VLV_PCS((ch), 1, 14) - -#define VLV_PCS_DW17_BCAST _VLV_PCS_BCAST(17) -#define VLV_PCS_DW17_GRP(ch) _VLV_PCS_GRP((ch), 17) -#define VLV_PCS01_DW17(ch) _VLV_PCS((ch), 0, 17) -#define VLV_PCS23_DW17(ch) _VLV_PCS((ch), 1, 17) - -#define VLV_PCS_DW23_GRP(ch) _VLV_PCS_GRP((ch), 23) -#define VLV_PCS01_DW23(ch) _VLV_PCS((ch), 0, 23) -#define VLV_PCS23_DW23(ch) _VLV_PCS((ch), 1, 23) - -#define VLV_TX_DW2_GRP(ch) _VLV_TX_GRP((ch), 2) -#define VLV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) -#define DPIO_SWING_MARGIN000_MASK REG_GENMASK(23, 16) -#define DPIO_SWING_MARGIN000(x) REG_FIELD_PREP(DPIO_SWING_MARGIN000_MASK, (x)) -#define DPIO_UNIQ_TRANS_SCALE_MASK REG_GENMASK(15, 8) -#define DPIO_UNIQ_TRANS_SCALE(x) REG_FIELD_PREP(DPIO_UNIQ_TRANS_SCALE_MASK, (x)) - -#define VLV_TX_DW3_GRP(ch) _VLV_TX_GRP((ch), 3) -#define VLV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) -/* The following bit for CHV phy */ -#define DPIO_TX_UNIQ_TRANS_SCALE_EN REG_BIT(27) -#define DPIO_SWING_MARGIN101_MASK REG_GENMASK(23, 16) -#define DPIO_SWING_MARGIN101(x) REG_FIELD_PREP(DPIO_SWING_MARGIN101_MASK, (x)) - -#define VLV_TX_DW4_GRP(ch) _VLV_TX_GRP((ch), 4) -#define VLV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) -#define DPIO_SWING_DEEMPH9P5_MASK REG_GENMASK(31, 24) -#define DPIO_SWING_DEEMPH9P5(x) REG_FIELD_PREP(DPIO_SWING_DEEMPH9P5_MASK, (x)) -#define DPIO_SWING_DEEMPH6P0_MASK REG_GENMASK(23, 16) -#define DPIO_SWING_DEEMPH6P0_SHIFT REG_FIELD_PREP(DPIO_SWING_DEEMPH6P0_MASK, (x)) - -#define VLV_TX_DW5_GRP(ch) _VLV_TX_GRP((ch), 5) -#define VLV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), 5) -#define DPIO_TX_OCALINIT_EN REG_BIT(31) - -#define VLV_TX_DW11_GRP(ch) _VLV_TX_GRP((ch), 11) -#define VLV_TX_DW11(ch, lane) _VLV_TX((ch), (lane), 11) - -#define VLV_TX_DW14_GRP(ch) _VLV_TX_GRP((ch), 14) -#define VLV_TX_DW14(ch, lane) _VLV_TX((ch), (lane), 14) - -/* CHV dpPhy registers */ -#define CHV_PLL_DW0(ch) _CHV_PLL((ch), 0) -#define DPIO_CHV_M2_DIV_MASK REG_GENMASK(7, 0) -#define DPIO_CHV_M2_DIV(m2) REG_FIELD_PREP(DPIO_CHV_M2_DIV_MASK, (m2)) - -#define CHV_PLL_DW1(ch) _CHV_PLL((ch), 1) -#define DPIO_CHV_N_DIV_MASK REG_GENMASK(11, 8) -#define DPIO_CHV_N_DIV(n) REG_FIELD_PREP(DPIO_CHV_N_DIV_MASK, (n)) -#define DPIO_CHV_M1_DIV_MASK REG_GENMASK(2, 0) -#define DPIO_CHV_M1_DIV(m1) REG_FIELD_PREP(DPIO_CHV_M1_DIV_MASK, (m1)) -#define DPIO_CHV_M1_DIV_BY_2 0 - -#define CHV_PLL_DW2(ch) _CHV_PLL((ch), 2) -#define DPIO_CHV_M2_FRAC_DIV_MASK REG_GENMASK(21, 0) -#define DPIO_CHV_M2_FRAC_DIV(m2_frac) REG_FIELD_PREP(DPIO_CHV_M2_FRAC_DIV_MASK, (m2_frac)) - -#define CHV_PLL_DW3(ch) _CHV_PLL((ch), 3) -#define DPIO_CHV_FRAC_DIV_EN REG_BIT(16) -#define DPIO_CHV_SECOND_MOD REG_BIT(8) -#define DPIO_CHV_FEEDFWD_GAIN_MASK REG_GENMASK(3, 0) -#define DPIO_CHV_FEEDFWD_GAIN(x) REG_FIELD_PREP(DPIO_CHV_FEEDFWD_GAIN_MASK, (x)) - -#define CHV_PLL_DW6(ch) _CHV_PLL((ch), 6) -#define DPIO_CHV_GAIN_CTRL_MASK REG_GENMASK(18, 16) -#define DPIO_CHV_GAIN_CTRL(x) REG_FIELD_PREP(DPIO_CHV_GAIN_CTRL_MASK, (x)) -#define DPIO_CHV_INT_COEFF_MASK REG_GENMASK(12, 8) -#define DPIO_CHV_INT_COEFF(x) REG_FIELD_PREP(DPIO_CHV_INT_COEFF_MASK, (x)) -#define DPIO_CHV_PROP_COEFF_MASK REG_GENMASK(3, 0) -#define DPIO_CHV_PROP_COEFF(x) REG_FIELD_PREP(DPIO_CHV_PROP_COEFF_MASK, (x)) - -#define CHV_PLL_DW8(ch) _CHV_PLL((ch), 8) -#define DPIO_CHV_TDC_TARGET_CNT_MASK REG_GENMASK(9, 0) -#define DPIO_CHV_TDC_TARGET_CNT(x) REG_FIELD_PREP(DPIO_CHV_TDC_TARGET_CNT_MASK, (x)) - -#define CHV_PLL_DW9(ch) _CHV_PLL((ch), 9) -#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1) -#define DPIO_CHV_INT_LOCK_THRESHOLD(x) REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x)) -#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE REG_BIT(0) /* 1: coarse & 0 : fine */ - -#define CHV_CMN_DW0_CH0 _CHV_CMN(0, 0) -#define DPIO_ALLDL_POWERDOWN_CH0 REG_BIT(19) -#define DPIO_ANYDL_POWERDOWN_CH0 REG_BIT(18) -#define DPIO_ALLDL_POWERDOWN BIT(1) -#define DPIO_ANYDL_POWERDOWN BIT(0) - -#define CHV_CMN_DW5_CH0 _CHV_CMN(0, 5) -#define CHV_BUFRIGHTENA1_MASK REG_GENMASK(21, 20) -#define CHV_BUFRIGHTENA1_DISABLE REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 0) -#define CHV_BUFRIGHTENA1_NORMAL REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 1) -#define CHV_BUFRIGHTENA1_FORCE REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 3) -#define CHV_BUFLEFTENA1_MASK REG_GENMASK(23, 22) -#define CHV_BUFLEFTENA1_DISABLE REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 0) -#define CHV_BUFLEFTENA1_NORMAL REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 1) -#define CHV_BUFLEFTENA1_FORCE REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 3) - -#define CHV_CMN_DW13_CH0 _CHV_CMN(0, 13) -#define CHV_CMN_DW0_CH1 _CHV_CMN(1, 0) -#define DPIO_CHV_S1_DIV_MASK REG_GENMASK(23, 21) -#define DPIO_CHV_S1_DIV(s1) REG_FIELD_PREP(DPIO_CHV_S1_DIV_MASK, (s1)) -#define DPIO_CHV_P1_DIV_MASK REG_GENMASK(15, 13) -#define DPIO_CHV_P1_DIV(p1) REG_FIELD_PREP(DPIO_CHV_P1_DIV_MASK, (p1)) -#define DPIO_CHV_P2_DIV_MASK REG_GENMASK(12, 8) -#define DPIO_CHV_P2_DIV(p2) REG_FIELD_PREP(DPIO_CHV_P2_DIV_MASK, (p2)) -#define DPIO_CHV_K_DIV_MASK REG_GENMASK(7, 4) -#define DPIO_CHV_K_DIV(k) REG_FIELD_PREP(DPIO_CHV_K_DIV_MASK, (k)) -#define DPIO_PLL_FREQLOCK REG_BIT(1) -#define DPIO_PLL_LOCK REG_BIT(0) -#define CHV_CMN_DW13(ch) _PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1) - -#define CHV_CMN_DW14_CH0 _CHV_CMN(0, 14) -#define CHV_CMN_DW1_CH1 _CHV_CMN(1, 1) -#define DPIO_AFC_RECAL REG_BIT(14) -#define DPIO_DCLKP_EN REG_BIT(13) -#define CHV_BUFLEFTENA2_MASK REG_GENMASK(18, 17) /* CL2 DW1 only */ -#define CHV_BUFLEFTENA2_DISABLE REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 0) -#define CHV_BUFLEFTENA2_NORMAL REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 1) -#define CHV_BUFLEFTENA2_FORCE REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 3) -#define CHV_BUFRIGHTENA2_MASK REG_GENMASK(20, 19) /* CL2 DW1 only */ -#define CHV_BUFRIGHTENA2_DISABLE REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 0) -#define CHV_BUFRIGHTENA2_NORMAL REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 1) -#define CHV_BUFRIGHTENA2_FORCE REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 3) -#define CHV_CMN_DW14(ch) _PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1) - -#define CHV_CMN_DW19_CH0 _CHV_CMN(0, 19) -#define CHV_CMN_DW6_CH1 _CHV_CMN(1, 6) -#define DPIO_ALLDL_POWERDOWN_CH1 REG_BIT(30) /* CL2 DW6 only */ -#define DPIO_ANYDL_POWERDOWN_CH1 REG_BIT(29) /* CL2 DW6 only */ -#define DPIO_DYNPWRDOWNEN_CH1 REG_BIT(28) /* CL2 DW6 only */ -#define CHV_CMN_USEDCLKCHANNEL REG_BIT(13) -#define CHV_CMN_DW19(ch) _PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1) - -#define CHV_CMN_DW28 _CHV_CMN(0, 28) -#define DPIO_CL1POWERDOWNEN REG_BIT(23) -#define DPIO_DYNPWRDOWNEN_CH0 REG_BIT(22) -#define DPIO_SUS_CLK_CONFIG_MASK REG_GENMASK(1, 0) -#define DPIO_SUS_CLK_CONFIG_ON REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 0) -#define DPIO_SUS_CLK_CONFIG_CLKREQ REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 1) -#define DPIO_SUS_CLK_CONFIG_GATE REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 2) -#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 3) - -#define CHV_CMN_DW30 _CHV_CMN(0, 30) -#define DPIO_CL2_LDOFUSE_PWRENB REG_BIT(6) -#define DPIO_LRC_BYPASS REG_BIT(3) - -#define CHV_TX_DW0(ch, lane) _VLV_TX((ch), (lane), 0) -#define CHV_TX_DW1(ch, lane) _VLV_TX((ch), (lane), 1) -#define CHV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) -#define CHV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) -#define CHV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) -#define CHV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), 5) -#define CHV_TX_DW6(ch, lane) _VLV_TX((ch), (lane), 6) -#define CHV_TX_DW7(ch, lane) _VLV_TX((ch), (lane), 7) -#define CHV_TX_DW8(ch, lane) _VLV_TX((ch), (lane), 8) -#define CHV_TX_DW9(ch, lane) _VLV_TX((ch), (lane), 9) -#define CHV_TX_DW10(ch, lane) _VLV_TX((ch), (lane), 10) - -#define CHV_TX_DW11(ch, lane) _VLV_TX((ch), (lane), 11) -#define DPIO_FRC_LATENCY_MASK REG_GENMASK(10, 8) -#define DPIO_FRC_LATENCY(x) REG_FIELD_PREP(DPIO_FRC_LATENCY_MASK, (x)) - -#define CHV_TX_DW14(ch, lane) _VLV_TX((ch), (lane), 14) -#define DPIO_UPAR REG_BIT(30) - #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) #define MIPIO_RST_CTRL (1 << 2)