From patchwork Tue Apr 23 09:06:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13639641 X-Patchwork-Delegate: kw@linux.com Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0883C58105; Tue, 23 Apr 2024 09:08:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713863295; cv=none; b=qSQ1L5wDoh+AkxQAVVvJCi0lYhcKQLyvJuYW0FiToLRtCuZAsfr+eGGw11LFdx+l5GqokwFCHFkwUIsglkM98lZlirHI9oa+Ge8SvXfmqlo5GgSqG2/yi08Q2lo/UmS9ah0Bp1Pmo7koUwLlsE7doEdTcWr/RgkzmmRZaGmZsUM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713863295; c=relaxed/simple; bh=V+31wpy+ViuFYyPXxxni0lbwtREaNbHVwxOi2HByI6I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=bnDWXSp8MIB7ZrxturJYmewokuGqbZTD9+inAuuFSvarR4tzWHf17FLsgnMPoLUiQmfwN4Xvl8Lb4m/O7JHBePwWbaRDWgA0fDoPSdboYrBo0fAsedlbreIezxUwYwDDqvdmMgy67qVhkabTvOIG3+B5YK7Z3UAI20jxx2fB6XY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=b6c/gSBj; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="b6c/gSBj" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 43N7uJnH007871; Tue, 23 Apr 2024 09:08:01 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:date:subject:mime-version:content-type :content-transfer-encoding:message-id:references:in-reply-to:to :cc; s=qcppdkim1; bh=Lge6OIRDCgkl4zCRo6LWVugfANWljw5EKDyEYyAefvo =; b=b6c/gSBjgB5+wF9Bz45oKEm0pdAkkG+zORAurnPefyjkmgeRAcOpSqgXi78 ao3V0r09B5pVEEtB0N0FiIhQ6JR5PUUa2YadXpgrLF6MGRFU9aFAHyZ0U/YXQ7nP 8GPjAFQb1Ec0yvts7O8LK0YBiiNQwSL2oWQnRPDDul5JpqPp1TNkA/jfKMgjbJSs /Jme08hanLOK8MoIljx/DqwuBeJOW4YY5mMKIdhob5g8Yt3Bp/Brm55GIxo9Zwih p8zuG1fM4kLwOObzrFccpgmourgcnyCop4LMgEWvyk47oqTbmX5U+n52VoJylaLN CPtLavKJP+J77VfeMkVMkvE7dBg== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3xp91fg5uh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 23 Apr 2024 09:08:01 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43N980jE030802 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 23 Apr 2024 09:08:00 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 23 Apr 2024 02:07:53 -0700 From: Krishna chaitanya chundru Date: Tue, 23 Apr 2024 14:36:55 +0530 Subject: [PATCH v11 1/6] arm64: dts: qcom: sm8450: Add interconnect path to PCIe node Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240423-opp_support-v11-1-15fdd40b0f95@quicinc.com> References: <20240423-opp_support-v11-0-15fdd40b0f95@quicinc.com> In-Reply-To: <20240423-opp_support-v11-0-15fdd40b0f95@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , , , CC: , , , , , , , , , , X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713863265; l=1661; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=V+31wpy+ViuFYyPXxxni0lbwtREaNbHVwxOi2HByI6I=; b=Rk6K56u92t2kiIqnqFJpkYkzwaq0CnI/ozh1AxLOcRO1bJBTvBHFVww6ljx+8/uR/0xGHDJGo bKbK+UJz69nA7hRs8oXN65WMAYHJ6fQIfPIvor+7m9WiYF3/Niwp1iU X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: r36NtGu1yXqzO4LesjMO_7xMlBM1z-3o X-Proofpoint-ORIG-GUID: r36NtGu1yXqzO4LesjMO_7xMlBM1z-3o X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-23_07,2024-04-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 impostorscore=0 phishscore=0 spamscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 malwarescore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404230024 Add PCIe-MEM & CPU-PCIe interconnect path to the PCIe nodes. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna chaitanya chundru --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index b86be34a912b..615296e13c43 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1807,6 +1807,12 @@ pcie0: pcie@1c00000 { <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", "cpu-pcie"; + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, <&pcie0_phy>, @@ -1930,6 +1936,12 @@ pcie1: pcie@1c08000 { <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", "cpu-pcie"; + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, <&pcie1_phy>, From patchwork Tue Apr 23 09:06:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13639643 X-Patchwork-Delegate: kw@linux.com Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95A7058AA5; Tue, 23 Apr 2024 09:08:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713863314; cv=none; b=QuIGmd84V3Q5+sXDSa+VgRyiSNBgtdMTSrIoq3KFpYB/gAAf8G1rwxDLXHydZs3ZuBYKlSl+SejbPqWvXDRPg1gj67Ui8/UncJcJVXME7ayTJ6k8DLFm5ZqMO6friM+/dA8aUc403WpqYfhchx7Wl8sHRowGsDwk+hikhCWIwhk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713863314; c=relaxed/simple; bh=C2NayGjW+2yDJQATHxooin6cvftBHKUkC3PkjCyzJPo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=eIE9P21GZkm2JndvPV+arRlrVBAxb3VpNOXh61kaGy4yr2FzAzZWlFaF5RTU68bcFA25N+mBxWmcmziX6LJYUswZql9BpUfNXR3igb7AT1c4ww1QZXOYxYctlntsfBwB/eJIJtTagwi9zNBzpstoSDzkpNG1dtsGdN+REREppPM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=YIaUOCQc; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="YIaUOCQc" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 43N888Bn006363; Tue, 23 Apr 2024 09:08:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:date:subject:mime-version:content-type :content-transfer-encoding:message-id:references:in-reply-to:to :cc; s=qcppdkim1; bh=VzCOHrbrCI3iCjamC+SneaLhS4QyR5ImIxB4OKe2PmI =; b=YIaUOCQcIVoBE1AsTodv4Sur3wY+HCmM+v4Ua88EaFkmuFOt65tnDlDQv8E h/YNEL5XmRcZhENUHBR8n+9C3Li/cL5fNEBCAypGcI8kECNbwJRoaylEzmmxK9ob kEsGvJU4DUWqWvvwSyzXa0uqmFM6d/5wtqV43Ww8XfMVPhRKPLkII77T8gOLV8xP 5Un0MG1HzjoCLFDJrG2VIwsb8Na0OHzNuiw1HnbVxr+uLtkvmZGhCpiN362X8FVd McHAw8L0nBqABAMt357IXbrEC9WeDHuF4RntPm5qAb+NJQioS3Ln5uDyPjIuJiAb NLimJSy3yVUV4V+m1NhD/v3Yuqw== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3xp978r4na-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 23 Apr 2024 09:08:07 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43N986Lv000680 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 23 Apr 2024 09:08:06 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 23 Apr 2024 02:08:00 -0700 From: Krishna chaitanya chundru Date: Tue, 23 Apr 2024 14:36:56 +0530 Subject: [PATCH v11 2/6] PCI: qcom: Add ICC bandwidth vote for CPU to PCIe path Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240423-opp_support-v11-2-15fdd40b0f95@quicinc.com> References: <20240423-opp_support-v11-0-15fdd40b0f95@quicinc.com> In-Reply-To: <20240423-opp_support-v11-0-15fdd40b0f95@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , , , CC: , , , , , , , , , , , Bryan O'Donoghue X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713863266; l=4383; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=C2NayGjW+2yDJQATHxooin6cvftBHKUkC3PkjCyzJPo=; b=9MhqXEHEvW8+9r2P3M3HgiDP3jizn/b9lwAk7YEe0KqQRQfGQ/eB2WUBgftCCX2b/Z6M2yGBC EdTa+9tIcBLB+YgMkTSkFd91/hM/yNAM8lb4RBgYHaeKAJz2/NcG9N/ X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: J32x85kOZUxFNFpZiOnUWrlMNLEQB1QL X-Proofpoint-GUID: J32x85kOZUxFNFpZiOnUWrlMNLEQB1QL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-23_07,2024-04-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 spamscore=0 mlxscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404230025 To access the host controller registers of the host controller and the endpoint BAR/config space, the CPU-PCIe ICC (interconnect) path should be voted otherwise it may lead to NoC (Network on chip) timeout. We are surviving because of other driver voting for this path. As there is less access on this path compared to PCIe to mem path add minimum vote i.e 1KBps bandwidth always which is sufficient enough to keep the path active and is recommended by HW team. During S2RAM (Suspend-to-RAM), the DBI access can happen very late (while disabling the boot CPU). So do not disable the CPU-PCIe interconnect path during S2RAM as that may lead to NoC error. Reviewed-by: Bryan O'Donoghue Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 44 ++++++++++++++++++++++++++++++---- 1 file changed, 40 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 14772edcf0d3..465d63b4be1c 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -245,6 +245,7 @@ struct qcom_pcie { struct phy *phy; struct gpio_desc *reset; struct icc_path *icc_mem; + struct icc_path *icc_cpu; const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; bool suspended; @@ -1409,6 +1410,9 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) if (IS_ERR(pcie->icc_mem)) return PTR_ERR(pcie->icc_mem); + pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie"); + if (IS_ERR(pcie->icc_cpu)) + return PTR_ERR(pcie->icc_cpu); /* * Some Qualcomm platforms require interconnect bandwidth constraints * to be set before enabling interconnect clocks. @@ -1418,7 +1422,20 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) */ ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); if (ret) { - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", + dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", + ret); + return ret; + } + + /* + * Since the CPU-PCIe path is only used for activities like register + * access of the host controller and endpoint Config/BAR space access, + * HW team has recommended to use a minimal bandwidth of 1KBps just to + * keep the path active. + */ + ret = icc_set_bw(pcie->icc_cpu, 0, kBps_to_icc(1)); + if (ret) { + dev_err(pci->dev, "Failed to set bandwidth for CPU-PCIe interconnect path: %d\n", ret); return ret; } @@ -1448,7 +1465,7 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie) ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); if (ret) { - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", + dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", ret); } } @@ -1610,7 +1627,7 @@ static int qcom_pcie_suspend_noirq(struct device *dev) */ ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); if (ret) { - dev_err(dev, "Failed to set interconnect bandwidth: %d\n", ret); + dev_err(dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", ret); return ret; } @@ -1634,7 +1651,18 @@ static int qcom_pcie_suspend_noirq(struct device *dev) pcie->suspended = true; } - return 0; + /* + * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. + * Because on some platforms, DBI access can happen very late during the + * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC + * error. + */ + if (pm_suspend_target_state != PM_SUSPEND_MEM) { + ret = icc_disable(pcie->icc_cpu); + if (ret) + dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); + } + return ret; } static int qcom_pcie_resume_noirq(struct device *dev) @@ -1642,6 +1670,14 @@ static int qcom_pcie_resume_noirq(struct device *dev) struct qcom_pcie *pcie = dev_get_drvdata(dev); int ret; + if (pm_suspend_target_state != PM_SUSPEND_MEM) { + ret = icc_enable(pcie->icc_cpu); + if (ret) { + dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); + return ret; + } + } + if (pcie->suspended) { ret = qcom_pcie_host_init(&pcie->pci->pp); if (ret) From patchwork Tue Apr 23 09:06:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13639642 X-Patchwork-Delegate: kw@linux.com Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A0C957333; Tue, 23 Apr 2024 09:08:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713863307; cv=none; b=Sgv9A/Rb1K9U7Z6p3s+pfFpiVZKJlao0WwJxue4yv8NY69hkHlO9VJrsaW6cHPjxGX26zXJn6gZh2L/+lzhM7DWsCGMDeXSJ2qXXohwDpWmB8YXSVdm4kIJbQjH/mC8Hi8rIkW8M8jmD0KVdaTa0XOE1Ntxk01Drryg9DN0zuzI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713863307; c=relaxed/simple; bh=FG21nJMzDgQVBPiWDAMRoSDJCoh5DoD48CK6U3Qv5f8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=ofArj3MbiYuubVeQztAdP4KbnHonMr7B8HKZQOzrWK68e297ajAUxmUPIXCv2CWuGSJh7nBKKiU+bTdiofJ3JhTpiodrM9S4Av9qznmO2LnNszo8nnjZYfcv48T215FtrgbLrK+hCFmsnD/NOo919e+U9itpuMWy3DbpqjYfzUs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=BdIPVgyX; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="BdIPVgyX" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 43N8FdPD009777; Tue, 23 Apr 2024 09:08:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:date:subject:mime-version:content-type :content-transfer-encoding:message-id:references:in-reply-to:to :cc; s=qcppdkim1; bh=ljGBYLQFC3HKRQ9g+LrdPl9BYHhm2n7q5flQqnt1vP8 =; b=BdIPVgyXnOs+BcDdS63bRI16icB5qAtv2f4mE87jZ22lAQ/C2KnbCejcPhT +Q8lf4H7rxKBxVz1ChnMCZ+TJ4gos6szK8L5yY7voVfKJrkyX6pAYHRIa6TCayzB G026nfSwb/yFIGHPJ7Cd0m2ZoU8mee/uhlU6Pi42tYxdJfqg27BF8ApU3bmx8NyS Vdl76p6WzgXbfunRyvpxuCbVLdIQRS5gFWJKe/a+42TV4BIcvLo9Vb+NHxrMA9Y5 LgEBTklN2bY/rVxPSVN7MZADjDljw3JE8at4G7DpCGRtaL7/qiIJs9xfoPVyuR3D Up3cDH66DftK5AilLfU7fux5m5A== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3xp9aa04c7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 23 Apr 2024 09:08:14 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43N98Dsl001926 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 23 Apr 2024 09:08:13 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 23 Apr 2024 02:08:06 -0700 From: Krishna chaitanya chundru Date: Tue, 23 Apr 2024 14:36:57 +0530 Subject: [PATCH v11 3/6] dt-bindings: pci: qcom: Add OPP table Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240423-opp_support-v11-3-15fdd40b0f95@quicinc.com> References: <20240423-opp_support-v11-0-15fdd40b0f95@quicinc.com> In-Reply-To: <20240423-opp_support-v11-0-15fdd40b0f95@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , , , CC: , , , , , , , , , , , Krzysztof Kozlowski X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713863266; l=1082; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=FG21nJMzDgQVBPiWDAMRoSDJCoh5DoD48CK6U3Qv5f8=; b=gKzIIKu1NU2Cx4Ti1z6HPqOt186P9zNlyY8LdyfkL+N/4kLyAsS2LTuQCXN9ORy5hr2PAXHWu P6l1/Yboc95BRwkWG+jS531zXfl0WYWzdWMdLZd+qNqadr8a2q6vO3F X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 17Hwed8_nEFOhj7BAhF34KB1wXSD_2Dy X-Proofpoint-ORIG-GUID: 17Hwed8_nEFOhj7BAhF34KB1wXSD_2Dy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-23_07,2024-04-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 bulkscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 spamscore=0 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404230025 PCIe needs to choose the appropriate performance state of RPMh power domain based on the PCIe gen speed. Adding the Operating Performance Points table allows to adjust power domain performance state and ICC peak bw, depending on the PCIe data rate and link width. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna chaitanya chundru --- Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml index 1496d6993ab4..d8c0afaa4b19 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml @@ -69,6 +69,10 @@ properties: - const: msi6 - const: msi7 + operating-points-v2: true + opp-table: + type: object + resets: maxItems: 1 From patchwork Tue Apr 23 09:06:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13639644 X-Patchwork-Delegate: kw@linux.com Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DBFA58ABC; Tue, 23 Apr 2024 09:08:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713863315; cv=none; b=jf9USosF9PwfOn6Lpvl2sM2fw36QCErs+Q4AGEOAyxTzD/50YsdjNrf95KUddkm/fXn7ocib/AtdYZU9+8E6SH6V4AjlgNDSkN7859ZKcWyYa0sz5a+Shr4RZ76xNM+87fUB+qtvZiLAumzBYpy1FPBXh6RJ6Y6zgPoFKvYx+B0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713863315; c=relaxed/simple; bh=4pRzd9+pDtrMLyrpkNkkMjxwxBU2FfbkTR7Y10bYL9k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=aBOA5hZ9jHTEGCfdDNQxqPGXHgKSK9z8k7QWD+sThkKGmGzixBKQusc75a21BZr6q1g9aVVNLbDFbv1WcQEDAU/dwoMJtNfHswBCfqJo5HzElnC8gqLmexSCD8XMQST3lboBRxO3HzJ3fzFPgPaBZyLDUMAXVK6TVkzeGY79ugQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=CfdG7UEM; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="CfdG7UEM" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 43N5rNrI022152; Tue, 23 Apr 2024 09:08:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:date:subject:mime-version:content-type :content-transfer-encoding:message-id:references:in-reply-to:to :cc; s=qcppdkim1; bh=9n8G1hcjc/AYvUEDDhWjwoL0BEeWTlgUdH6sujP57Z8 =; b=CfdG7UEMkxVPetl0THUZB8jy0yYNJsrzEYrhp3h3M6pKctf1j1TIOEsYi04 HdhaORLZDWMc0U3H+YL29m+zDV+yO+bMUY4ZioYTxNJbQj6MuQmzZfu2vdOKmE9E 3WulHGsgRw0L+tnhq2Qj59kH332zXE8DXu3jqPJGiUi6H2rhYbN6xVn52Q0Pu4Mu eM4PXxFISnxkfpKSK811lG5SBCWt1eyULfPxPgwbG1EvRcWN/WiIHBbWzeH1M0oa oIvx+UzIoc2jLWRRI5pKhlqRKc+aH5tqWCCSx7QFYe2GcZbv6tdWd1oXc10fUnut Fo2c8DkCguCTEX8DC0cU10jOA5w== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3xp6n2gddn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 23 Apr 2024 09:08:21 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43N98JBo031668 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 23 Apr 2024 09:08:19 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 23 Apr 2024 02:08:13 -0700 From: Krishna chaitanya chundru Date: Tue, 23 Apr 2024 14:36:58 +0530 Subject: [PATCH v11 4/6] arm64: dts: qcom: sm8450: Add OPP table support to PCIe Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240423-opp_support-v11-4-15fdd40b0f95@quicinc.com> References: <20240423-opp_support-v11-0-15fdd40b0f95@quicinc.com> In-Reply-To: <20240423-opp_support-v11-0-15fdd40b0f95@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , , , CC: , , , , , , , , , , X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713863266; l=3148; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=4pRzd9+pDtrMLyrpkNkkMjxwxBU2FfbkTR7Y10bYL9k=; b=jKZ+VM9c+rv//+pFQT5JCnA8K0CI1boZu+2HvIdmINwwjuqeAM1s/YZV1ryGGwloO+nbh1FfR zLbqdD+XGLcCb98yRqlMzcqnZh3p5xjzYJ+jTqWherguSV08DghY7j8 X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: iCSXCqnVD4F9I5Lz1YP2c9Df2qGi3Qpv X-Proofpoint-ORIG-GUID: iCSXCqnVD4F9I5Lz1YP2c9Df2qGi3Qpv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-23_07,2024-04-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 priorityscore=1501 adultscore=0 suspectscore=0 mlxlogscore=999 bulkscore=0 phishscore=0 malwarescore=0 mlxscore=0 lowpriorityscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404230025 PCIe host controller driver needs to choose the appropriate performance state of RPMh power domain and interconnect bandwidth based on the PCIe data rate. Hence, add the OPP table support to specify RPMh performance states and interconnect peak bandwidth. It should be noted that the different link configurations may share the same aggregate bandwidth, e.g., a 2.5 GT/s x2 link and a 5.0 GT/s x1 link have the same bandwidth and share the same OPP entry. Signed-off-by: Krishna chaitanya chundru Reviewed-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 77 ++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 615296e13c43..2e047aba220b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1855,7 +1855,35 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; + operating-points-v2 = <&pcie0_opp_table>; + status = "disabled"; + + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + }; + }; pcie0_phy: phy@1c06000 { @@ -1982,7 +2010,56 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; + operating-points-v2 = <&pcie1_opp_table>; + status = "disabled"; + + pcie1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + + /* GEN 4 x2 */ + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + }; + }; + }; pcie1_phy: phy@1c0e000 { From patchwork Tue Apr 23 09:06:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13639645 X-Patchwork-Delegate: kw@linux.com Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B58E59148; Tue, 23 Apr 2024 09:08:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713863320; cv=none; b=FX+MS/fyvWPPJJMQ7YpWgyYZAk5YCNQrZbIXEPq9EjapLM8ky395y9lYGvvmSfZgyBDNAhjGeTNnzWcyFwEKbFOCPvm8ZwKdlefEQR2O8Vzepw9nMQtK45rF0bUFXPkKJKscBR0V7322BxPVYv8ZVoENGqMMimMnIn7OTA2Qttg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713863320; c=relaxed/simple; bh=C8I6H8q1CsCEilGm6xZcUAtD7gbeIhxcNcTyYkuj3Vo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=NVZ2XTb2rNv8T7ri4OWjnz0gkstjBMF3d7kkhxUUWXcLaOQ6IEf5XzDS843bvNzdfO1eSQj7vpbpbzRdcL4cg7tYYQb3j5MSUY15qWmehvjf2v16QKU7ZUnXBNG6dOX7qkC0wOucxLVclB7EBrWmrTbO5UOpzo0k3X72v3ulcXg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=g72p1BZe; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="g72p1BZe" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 43N5pCd2010979; Tue, 23 Apr 2024 09:08:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:date:subject:mime-version:content-type :content-transfer-encoding:message-id:references:in-reply-to:to :cc; s=qcppdkim1; bh=xC+Wq2NeguQc2WvQitBOxzmrCHOw8Xh3tDYQPVO/dHc =; b=g72p1BZe5P3tKN1Khml+OrFOb7W0ra5nNHU15+RDikfZP3kkWomALBB+BO+ burqUUKX0GjWLIalOte6Jl/EFQbQDm1oxiO8/xt3ua1xTJCSaRPkJigzGJYCEuhD 4ktFjtsRcef0WH+aI597oeq7XT+rofB6E/4Noc+a3aK025FPekvCviOwm3J6tLxN nB4o8g6QVpPtUobFIozghX6jF707R3F0XnaNILKJiFh/fJZcYYkKP4qZeDghewWc Dgajj+ZRHOq0mgI0LGM4MSdLWe74/GDNViEnbRLdniRJtpRDfyex9bdp8MIVo8HJ IjHMYtdbegv1tDjUqZKTcRvBMgA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3xnvtn9gx6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 23 Apr 2024 09:08:27 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43N98Qkc001248 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 23 Apr 2024 09:08:26 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 23 Apr 2024 02:08:19 -0700 From: Krishna chaitanya chundru Date: Tue, 23 Apr 2024 14:36:59 +0530 Subject: [PATCH v11 5/6] PCI: Bring the PCIe speed to MBps logic to new pcie_link_speed_to_mbps() Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240423-opp_support-v11-5-15fdd40b0f95@quicinc.com> References: <20240423-opp_support-v11-0-15fdd40b0f95@quicinc.com> In-Reply-To: <20240423-opp_support-v11-0-15fdd40b0f95@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , , , CC: , , , , , , , , , , X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713863266; l=2081; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=C8I6H8q1CsCEilGm6xZcUAtD7gbeIhxcNcTyYkuj3Vo=; b=VEayDnO6GDqE0NBIYhGk0WP8lZMkWeLqGWuSEEjnosEKCLFRoaIJhI7WTMjTgnvCq4zWnzsV/ LnjqnaNCLY5BIu5xDRxuQansWP8rOW55lYHhVfBOeYULHImj6jQ4aFI X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: yyGFdgl5qmoQG1pmHk1q_9UrlV1PWEJm X-Proofpoint-ORIG-GUID: yyGFdgl5qmoQG1pmHk1q_9UrlV1PWEJm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-23_07,2024-04-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 mlxscore=0 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 impostorscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404230025 Bring the switch case in pcie_link_speed_mbps() to new function to the header file so that it can be used in other places like in controller driver. Signed-off-by: Krishna chaitanya chundru Reviewed-by: Manivannan Sadhasivam Acked-by: Bjorn Helgaas --- drivers/pci/pci.c | 19 +------------------ drivers/pci/pci.h | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+), 18 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e5f243dd4288..40487b86a75e 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5922,24 +5922,7 @@ int pcie_link_speed_mbps(struct pci_dev *pdev) if (err) return err; - switch (to_pcie_link_speed(lnksta)) { - case PCIE_SPEED_2_5GT: - return 2500; - case PCIE_SPEED_5_0GT: - return 5000; - case PCIE_SPEED_8_0GT: - return 8000; - case PCIE_SPEED_16_0GT: - return 16000; - case PCIE_SPEED_32_0GT: - return 32000; - case PCIE_SPEED_64_0GT: - return 64000; - default: - break; - } - - return -EINVAL; + return pcie_link_speed_to_mbps(to_pcie_link_speed(lnksta)); } EXPORT_SYMBOL(pcie_link_speed_mbps); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 17fed1846847..4de10087523e 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -290,6 +290,28 @@ void pci_bus_put(struct pci_bus *bus); (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 0) +static inline int pcie_link_speed_to_mbps(enum pci_bus_speed speed) +{ + switch (speed) { + case PCIE_SPEED_2_5GT: + return 2500; + case PCIE_SPEED_5_0GT: + return 5000; + case PCIE_SPEED_8_0GT: + return 8000; + case PCIE_SPEED_16_0GT: + return 16000; + case PCIE_SPEED_32_0GT: + return 32000; + case PCIE_SPEED_64_0GT: + return 64000; + default: + break; + } + + return -EINVAL; +} + const char *pci_speed_string(enum pci_bus_speed speed); enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); From patchwork Tue Apr 23 09:07:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13639646 X-Patchwork-Delegate: kw@linux.com Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FC5F59B56; Tue, 23 Apr 2024 09:08:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713863325; cv=none; b=sxXXob/vCp4OAUTNe+5uWoq7vRz5+mrvB+GPoSIfnXL3iXK6ixkGHl7jGeEJ/GWeptXJNfYCxlEkl51p4uQ1EWKPEtcMhY9H55AacnBzPTyj0vWBhHka/UqOTOgyffiPeA20TFaITmZ4zFt2Xo1gLdUqsjCaf/7YIX8gQeK09GI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713863325; c=relaxed/simple; bh=wwNv0pI2dMCLeSzhSpOy/MncHRyQ8g1i4vlar+nCwXg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=bfy7yciiopXFowdHiGVYlyu0sKyFWV1TuQD23JO+YuLjxfutkMMVQ9nHXvhFTMK/ZhonHTtoK8/FIa2g7iPoRGhXKfcsSgARy9QnNyJRba1tEBwpvyOB1e/kSAbGY1rhjTqUIgVjTZEBOyR/sQaA4gtKacwWkQl59rqn4+sn9oM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ZPTtj8hl; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ZPTtj8hl" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 43N8Ni04017570; Tue, 23 Apr 2024 09:08:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:date:subject:mime-version:content-type :content-transfer-encoding:message-id:references:in-reply-to:to :cc; s=qcppdkim1; bh=DzTEn0h78zzgvHCZTdcWfLx+CrnPL+niHNjH4pJ1fC8 =; b=ZPTtj8hlo1mShx7H6qW+GnkFfsh1RqucS/V3ws1nbYk7J5Jzl/i46ldo7zQ CZ9ZLkfq431/Otzz7FLinadZtpeWY/2H8jWC+23p8ExDY19TmEWl/8sY0AIHIKO2 DNFDXQGZheoIFrFkXExSHcrlWFnVBOm/MTebggkJlMtA5VY9PA4gjmlQoDrpooA6 8TNy7j+/3W516x9U96/qQLxSgD25CahtKGLeiMd3HQ3VNvWroWzqstPfN8v5ajSW LuY+nP6iOwyii8HppuvcoXZYBNOk7C9KBpWumonZv/mHoJ0IrA0B2UMmebtqb14q 4hlrwnExClx95vflaxSnAWs7euA== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3xp6n2gde2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 23 Apr 2024 09:08:33 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43N98W7j031875 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 23 Apr 2024 09:08:32 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 23 Apr 2024 02:08:26 -0700 From: Krishna chaitanya chundru Date: Tue, 23 Apr 2024 14:37:00 +0530 Subject: [PATCH v11 6/6] PCI: qcom: Add OPP support to scale performance Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240423-opp_support-v11-6-15fdd40b0f95@quicinc.com> References: <20240423-opp_support-v11-0-15fdd40b0f95@quicinc.com> In-Reply-To: <20240423-opp_support-v11-0-15fdd40b0f95@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , , , CC: , , , , , , , , , , X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; a=ed25519-sha256; t=1713863266; l=5815; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=wwNv0pI2dMCLeSzhSpOy/MncHRyQ8g1i4vlar+nCwXg=; b=/wkgG3cJms8d4E4TIKUeCCyVI1I4iEO2IGXCw/HJu3+oigMAozJyBNqCMGr25/i6phoETJymI Om1fUSC3ZbQAnnopG6YHryEOtkhZBYrEjmVRTjnfxOlVivKZqhKQ55e X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: B0390ZIcVmepJJsBiIrUPH0Byf6hBex- X-Proofpoint-ORIG-GUID: B0390ZIcVmepJJsBiIrUPH0Byf6hBex- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-23_07,2024-04-22_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 priorityscore=1501 adultscore=0 suspectscore=0 mlxlogscore=999 bulkscore=0 phishscore=0 malwarescore=0 mlxscore=0 lowpriorityscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404230025 QCOM Resource Power Manager-hardened (RPMh) is a hardware block which maintains hardware state of a regulator by performing max aggregation of the requests made by all of the clients. PCIe controller can operate on different RPMh performance state of power domain based on the speed of the link. And this performance state varies from target to target, like some controllers support GEN3 in NOM (Nominal) voltage corner, while some other supports GEN3 in low SVS (static voltage scaling). The SoC can be more power efficient if we scale the performance state based on the aggregate PCIe link bandwidth. Add Operating Performance Points (OPP) support to vote for RPMh state based on the aggregate link bandwidth. OPP can handle ICC bw voting also, so move ICC bw voting through OPP framework if OPP entries are present. As we are moving ICC voting as part of OPP, don't initialize ICC if OPP is supported. Before PCIe link is initialized vote for highest OPP in the OPP table, so that we are voting for maximum voltage corner for the link to come up in maximum supported speed. Signed-off-by: Krishna chaitanya chundru Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 81 ++++++++++++++++++++++++++++------ 1 file changed, 67 insertions(+), 14 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 465d63b4be1c..66bda30305a8 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -1443,15 +1444,13 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) return 0; } -static void qcom_pcie_icc_update(struct qcom_pcie *pcie) +static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) { struct dw_pcie *pci = pcie->pci; - u32 offset, status; + u32 offset, status, freq; + struct dev_pm_opp *opp; int speed, width; - int ret; - - if (!pcie->icc_mem) - return; + int ret, mbps; offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); @@ -1463,10 +1462,26 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie) speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); - ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); - if (ret) { - dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", - ret); + if (pcie->icc_mem) { + ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); + if (ret) { + dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", + ret); + } + } else { + mbps = pcie_link_speed_to_mbps(pcie_link_speed[speed]); + if (mbps < 0) + return; + + freq = mbps * 1000; + opp = dev_pm_opp_find_freq_exact(pci->dev, freq * width, true); + if (!IS_ERR(opp)) { + ret = dev_pm_opp_set_opp(pci->dev, opp); + if (ret) + dev_err(pci->dev, "Failed to set opp for freq (%ld): %d\n", + dev_pm_opp_get_freq(opp), ret); + } + dev_pm_opp_put(opp); } } @@ -1510,7 +1525,9 @@ static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) static int qcom_pcie_probe(struct platform_device *pdev) { const struct qcom_pcie_cfg *pcie_cfg; + unsigned long max_freq = INT_MAX; struct device *dev = &pdev->dev; + struct dev_pm_opp *opp; struct qcom_pcie *pcie; struct dw_pcie_rp *pp; struct resource *res; @@ -1578,9 +1595,42 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } - ret = qcom_pcie_icc_init(pcie); - if (ret) + /* OPP table is optional */ + ret = devm_pm_opp_of_add_table(dev); + if (ret && ret != -ENODEV) { + dev_err_probe(dev, ret, "Failed to add OPP table\n"); goto err_pm_runtime_put; + } + + /* + * Before PCIe link is initialized vote for highest OPP in the OPP table, + * so that we are voting for maximum voltage corner for the link to come up + * in maximum supported speed. At the end of the probe(), OPP will be + * updated using qcom_pcie_icc_opp_update(). + */ + if (!ret) { + opp = dev_pm_opp_find_freq_floor(dev, &max_freq); + if (IS_ERR(opp)) { + dev_err_probe(pci->dev, PTR_ERR(opp), + "Unable to find max freq OPP\n"); + goto err_pm_runtime_put; + } else { + ret = dev_pm_opp_set_opp(dev, opp); + } + + dev_pm_opp_put(opp); + if (ret) { + dev_err_probe(pci->dev, ret, + "Failed to set OPP for freq (%ld): %d\n", + max_freq, ret); + goto err_pm_runtime_put; + } + } else { + /* Skip ICC init if OPP is supported as it is handled by OPP */ + ret = qcom_pcie_icc_init(pcie); + if (ret) + goto err_pm_runtime_put; + } ret = pcie->cfg->ops->get_resources(pcie); if (ret) @@ -1600,7 +1650,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_phy_exit; } - qcom_pcie_icc_update(pcie); + qcom_pcie_icc_opp_update(pcie); if (pcie->mhi) qcom_pcie_init_debugfs(pcie); @@ -1661,6 +1711,9 @@ static int qcom_pcie_suspend_noirq(struct device *dev) ret = icc_disable(pcie->icc_cpu); if (ret) dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); + + if (!pcie->icc_mem) + dev_pm_opp_set_opp(pcie->pci->dev, NULL); } return ret; } @@ -1686,7 +1739,7 @@ static int qcom_pcie_resume_noirq(struct device *dev) pcie->suspended = false; } - qcom_pcie_icc_update(pcie); + qcom_pcie_icc_opp_update(pcie); return 0; }