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Thu, 25 Apr 2024 03:45:31 GMT Received: from hu-bjorande-lv.qualcomm.com (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 24 Apr 2024 20:45:31 -0700 From: Bjorn Andersson Date: Wed, 24 Apr 2024 20:45:31 -0700 Subject: [PATCH] pinctrl: qcom: Fix behavior in abscense of open-drain support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240424-tlmm-open-drain-v1-1-9dd2041f0532@quicinc.com> X-B4-Tracking: v=1; b=H4sIANrRKWYC/x3MQQqAIBBA0avIrBtQmUV0lWhhNtZAqWhEEN09a fkW/z9QuQhXGNQDhS+pkmKD6RT4zcWVUZZmsNqSJkt47seBKXPEpTiJ2M/akDc+OOOgVblwkPs /jtP7fhQTmpRhAAAA To: Bjorn Andersson , Linus Walleij , Brian Norris , Jaiganesh Narayanan CC: Johan Hovold , Doug Anderson , , , , Bjorn Andersson X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714016731; l=2745; i=quic_bjorande@quicinc.com; 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The TLMM block in most Qualcomm platform does not implement such functionality, so this call would be expected to fail. But due to lack of checks for this condition, the zero-initialized od_bit will cause this request to silently corrupt the lowest bit in the config register (which typically is part of the bias configuration) and happily continue on. Fix this by checking if the od_bit value is unspecified and if so fail the request to avoid the unexpected state, and to make sure the software fallback actually kicks in. It is assumed for now that no implementation will come into existence with BIT(0) being the open-drain bit, simply for convenience sake. Fixes: 13355ca35cd1 ("pinctrl: qcom: ipq4019: add open drain support") Signed-off-by: Bjorn Andersson --- drivers/pinctrl/qcom/pinctrl-msm.c | 2 ++ drivers/pinctrl/qcom/pinctrl-msm.h | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) --- base-commit: 5e4f84f18c4ee9b0ccdc19e39b7de41df21699dd change-id: 20240424-tlmm-open-drain-8b014c1cfa1a Best regards, diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index aeaf0d1958f5..329474dc21c0 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -313,6 +313,8 @@ static int msm_config_reg(struct msm_pinctrl *pctrl, *mask |= BIT(g->i2c_pull_bit) >> *bit; break; case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!g->od_bit) + return -EOPNOTSUPP; *bit = g->od_bit; *mask = 1; break; diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 63852ed70295..7b8cd1832112 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -51,7 +51,8 @@ struct pinctrl_pin_desc; * @mux_bit: Offset in @ctl_reg for the pinmux function selection. * @pull_bit: Offset in @ctl_reg for the bias configuration. * @drv_bit: Offset in @ctl_reg for the drive strength configuration. - * @od_bit: Offset in @ctl_reg for controlling open drain. + * @od_bit: Offset in @ctl_reg for controlling open drain. 0 if + * not supported by target. * @oe_bit: Offset in @ctl_reg for controlling output enable. * @in_bit: Offset in @io_reg for the input bit value. * @out_bit: Offset in @io_reg for the output bit value.