From patchwork Fri Apr 26 07:38:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Aiuto X-Patchwork-Id: 13644190 Received: from smtpcmd11116.aruba.it (smtpcmd11116.aruba.it [62.149.156.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEADC13C3D2 for ; Fri, 26 Apr 2024 07:41:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=62.149.156.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714117297; cv=none; b=jMB0Cd6z3MqDos6teRcJCdXUyGPJEhQ7RIfNKD4dcPOR/kv2Y90MryRzBlhVVelAsax6uu94vQjilri8FCJxGUHRcn57k6olo7lixMUGkrP3IiHgPpixvNPYm9LRQxcJhwhmaPAZq80hGwxxIL1E4S/77TAR2U/6M+sDh/srgKk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714117297; c=relaxed/simple; bh=zYKq99FX6bSTj9flwcYNc4uocVSd8mkKIJiOpYzrO5s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VCg0q0wWD20GtQCEv1ja75x6bF1+Bnb4BHhZ64mpWbi0F5UubsPm29uaqMYL14KsyzgteRW4RK4cFdZ7IbfKmX3ATg6EnPy54l9tH4XmlMbt/oHokU8TG72X74mvmJgtUvBn1BZXzKdDwBTY+TOpFYu66C3CCfQlwf6fzfAeQck= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=engicam.com; spf=pass smtp.mailfrom=engicam.com; dkim=pass (2048-bit key) header.d=aruba.it header.i=@aruba.it header.b=XwPh2Rxt; arc=none smtp.client-ip=62.149.156.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=engicam.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=engicam.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=aruba.it header.i=@aruba.it header.b="XwPh2Rxt" Received: from engicam.com ([146.241.21.121]) by Aruba Outgoing Smtp with ESMTPSA id 0GA2s5OJj7AmW0GA3sQ98F; Fri, 26 Apr 2024 09:38:24 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=aruba.it; s=a1; t=1714117104; bh=zYKq99FX6bSTj9flwcYNc4uocVSd8mkKIJiOpYzrO5s=; h=From:To:Subject:Date:MIME-Version; b=XwPh2RxtobdkhytyxoFlx7+wG7w1xaDzwQUi8tbLXjjuA646s9fCR1U+Xt60TJMix S67wcI9kMs6XevjQ8IJztsPWAuPgbIdltScFhb2tLMC2mWLiLEwu68ZFvhMhPPGx5R 1gOfoD/0dlNixcvPyrGF6XlSS5EPpLzgAnYN87jBadf5jNl6TzZppU55DpTh9NVzo9 Nt6foj+74tldvaJzCqprEn0YERafPmZBQOyMEHG62zDOaOlkhocNehvYNJFe5+Hxyj wy4toDQR8oumUScynf6ZF/Q4sVHaQVXpx1ZFEOjTbIh9Ln/jkSFx1thSfjGVadJxB7 TQSZNgN20Cx6w== From: Fabio Aiuto To: Shawn Guo , Sascha Hauer , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabio Aiuto , Matteo Lisi , Mirko Ardinghi , Krzysztof Kozlowsky , Conor Dooley Subject: [PATCH v5 1/3] dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit Date: Fri, 26 Apr 2024 09:38:18 +0200 Message-Id: <20240426073820.6466-2-fabio.aiuto@engicam.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240426073820.6466-1-fabio.aiuto@engicam.com> References: <20240426073820.6466-1-fabio.aiuto@engicam.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CMAE-Envelope: MS4xfD1XcedmZ1mUcGuYT6SmwH4d5NUx70sNmxpClv0ZEsrpcXJwE5/V5XJ65U4m3Wo5CGVMP57dboTrxa4xIqCoFj+iHOPhd6jve9AP9Gn+bLeOnltCTa9e f2GLjaOKvS6cqaY8uDGIo2dZbPur0+pJLAByt7G4Y32eZHPDmG6chNQqk0E4W+bQZneZSbjsVYnv26RLRoe4jJ9xVi7n9HPTCMRSj/qxCnozTXDin/YC8+yY F3Bm6dBLdIxbE0PMLvSWp92i7S7sGpF8N48LRZ6raGXWn9nkJ1vhZzojC9NViHtFeBmqylE9YB/gV8n9sIxroTXCAKG4UUOdLKr2Wp8cR8CPAKSSCnuqW2i3 +vZ89/FPr+0iHBs9IkwSgUvuboSFGHruIsYeL0fK9dug/RIeMbn/ZbxVT7UcrAxfy62YfqmvoNeKXiR9cf5XJ4+I+iTWRC+I4/JMFp2AMnb3X14yjq4s0OQN t5NgCDIZBKDzbrRMvvgu9AgOdd8Ciq+TEkTjaD+CQfQeVLJWLwbqrdMQLrZasQksdetbAGscj/y2HGUl3lnp8DiSCy4Eyx8pIjhHkppEB6/EZJJ/ckitH2f1 X5sdFx+0IwHjujKlIGB83bvVl5r2Fzx/sETBRYIav0DuQb9oyeukS3EGbcp0Uc/yNLf6aan6F4Z2PjRIh5MArkb1 i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam. EDIMM 2.0 Starter Kit is an EDIMM 2.0 Form Factor Capacitive Evaluation Board by Engicam. i.Core MX93 needs to be mounted on top of EDIMM 2.0 Starter Kit to get the full i.Core MX93 EDIMM 2.0 Starter Kit board. Add bindings for this board. Cc: Matteo Lisi Cc: Mirko Ardinghi Reviewed-by: Krzysztof Kozlowsky Acked-by: Conor Dooley Signed-off-by: Fabio Aiuto --- Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 0027201e19f8..b497a01c7418 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1265,6 +1265,13 @@ properties: - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board - const: fsl,imx93 + - description: Engicam i.Core MX93 based Boards + items: + - enum: + - engicam,icore-mx93-edimm2 # i.MX93 Engicam i.Core MX93 EDIMM 2.0 Starter Kit + - const: engicam,icore-mx93 # i.MX93 Engicam i.Core MX93 Som + - const: fsl,imx93 + - description: i.MXRT1050 based Boards items: - enum: From patchwork Fri Apr 26 07:38:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Aiuto X-Patchwork-Id: 13644188 Received: from smtpcmd11116.aruba.it (smtpcmd11116.aruba.it [62.149.156.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEA1922338 for ; Fri, 26 Apr 2024 07:41:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=62.149.156.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714117296; cv=none; b=en6Hc+i8JytCBHqggmn+Adxv4hMJchsQARBzgCdQt3kfidulmtpV8OqwLscU52mc7nwf2CjZwl04MOjufiT5ktOrmfIKqSoX7K693GBhaPublfkn+AM1bfxnDNxnkq6lfWUtEO4l3mMPjedlfjSP/whz8LpPWZy+XeBOi7zOBPo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714117296; c=relaxed/simple; bh=oLpS1ywFi/E4JcK3AJqe04SGtz0Tg8XK4zh42cLNxpE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Sgi3SsDM+gq2drSHpEFvnzP9ROwODuTxBvejslNRxGUXOtJjtIgsAxO+b4Znj51IKUcFdyoE0IKbAxiPVIajR6PwB1P3xpueTLw9dXRnVJZdWT2G8a+iFqp5Ys4Qg85OOWojsdnlE0WmUk478LhqzTpAv/xHMt0qkEaqa0H0160= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=engicam.com; spf=pass smtp.mailfrom=engicam.com; dkim=pass (2048-bit key) header.d=aruba.it header.i=@aruba.it header.b=nfTuFYQK; arc=none smtp.client-ip=62.149.156.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=engicam.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=engicam.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=aruba.it header.i=@aruba.it header.b="nfTuFYQK" Received: from engicam.com ([146.241.21.121]) by Aruba Outgoing Smtp with ESMTPSA id 0GA2s5OJj7AmW0GA4sQ98j; Fri, 26 Apr 2024 09:38:24 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=aruba.it; s=a1; t=1714117104; bh=oLpS1ywFi/E4JcK3AJqe04SGtz0Tg8XK4zh42cLNxpE=; h=From:To:Subject:Date:MIME-Version; b=nfTuFYQKPegRGDQolO2+YJfIORJx+ADc1SoG3c8GdI7dMKa24tM0NIhUiU9o4O2bU DvyDGtXwrih93AYW68Rpxcmc1+lVVv7BIX4X4ii5PvocTj/nSiOxyywBf4QQpwg5Ug HiirvOA2+LQum18HCULy0hR1OeEGsj3it1h387TuIt8cwYKquPh/didR2KayiPqdKd upxlyQpSnkqxECrhA1J3a2QsYjn5wKq/PmcLYFRscfTVB2mbqHNrpWZ6RMn1uUw9dW qYEuXO4e7sABnjzeY1f15FYjqTsiITMQVZeCI/03xRp6eW0WrZDdLWJ5nIGZY07BPp u4rLizqAd+mJA== From: Fabio Aiuto To: Shawn Guo , Sascha Hauer , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabio Aiuto , Matteo Lisi , Mirko Ardinghi , Peng Fan Subject: [PATCH v5 2/3] arm64: dts: imx93: add Engicam i.Core MX93 SoM Date: Fri, 26 Apr 2024 09:38:19 +0200 Message-Id: <20240426073820.6466-3-fabio.aiuto@engicam.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240426073820.6466-1-fabio.aiuto@engicam.com> References: <20240426073820.6466-1-fabio.aiuto@engicam.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CMAE-Envelope: MS4xfD1XcedmZ1mUcGuYT6SmwH4d5NUx70sNmxpClv0ZEsrpcXJwE5/V5XJ65U4m3Wo5CGVMP57dboTrxa4xIqCoFj+iHOPhd6jve9AP9Gn+bLeOnltCTa9e f2GLjaOKvS6cqUOiz7HPzthIjBFVQuWqVc+3lPiulc9QAM8LP7he3+3oDgYfZuZjDmIuEeeTv/vfkPpUVScLWY56BU8jOMY6w3wB7/9sWx8II9cjUV+2swjh KCp8LV1uXGFUp8ThXtNqGds0NhRTyj0jhznxFlz16DOskS9YmD9x2zD9T1EyDCTWGbr3HH1401OsoXPps8v+++C7MbHJP77bW61Cgrq+RC5B8mlCZd9IrMBZ uVWybR2fnsSdwTqMJhdXltqk8rv1HmLVtZi3NPvagnMHbRJ3Rp3BpwEjjtADXHFIucHEypwr9JGp68xIWqJDFCMHTe5IZYkaue7p1HVFz3dAwMCBh2wr9cw3 P8nLIrLhlceayj4kDmWnXt1VdnDXnve0nMguNaoCGw+I/7NTUWOVAWzjITr6mE5ZHwGorw9xzsOAraY/8/fr33DlJoZetntGS/zbzSpCJ3X2TPG/lSKyIJCH FtRAjh/zy2/jX2ooAKQjdpM76+9w2MX3rzXFden2ZDAGxA== i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam. Main features: CPU: NXP i.MX 93 MEMORY: Up to 2GB LPDDR4 NETWORKING: 2x Gb Ethernet USB: USB OTG 2.0, USB HOST 2.0 STORAGE: eMMC starting from 4GB PERIPHERALS: UART, I2C, SPI, CAN, SDIO, GPIO The i.Core MX93 needs to be mounted on top of Engicam baseboards to work. Add devicetree include file. Cc: Matteo Lisi Cc: Mirko Ardinghi Reviewed-by: Peng Fan Signed-off-by: Fabio Aiuto --- .../boot/dts/freescale/imx93-icore-mx93.dtsi | 269 ++++++++++++++++++ 1 file changed, 269 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi b/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi new file mode 100644 index 000000000000..9c97b620ccfc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + * Copyright 2024 Engicam s.r.l. + */ + +/dts-v1/; + +#include "imx93.dtsi" + +/ { + model = "Engicam i.Core MX93 SoM"; + compatible = "engicam,icore-mx93", "fsl,imx93"; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy2: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&gpio2>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + nxp,wdog_b-warm-reset; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 {/*SD Card*/ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + bus-width = <4>; + no-1-8-v; + max-frequency = <25000000>; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x53e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x53e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x53e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x53e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x53e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x53e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x53e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x53e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x53e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x53e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x53e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x53e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x53e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x53e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x170e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x130e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x130e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x130e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x130e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x130e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; +}; From patchwork Fri Apr 26 07:38:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Aiuto X-Patchwork-Id: 13644182 Received: from smtpcmd11116.aruba.it (smtpcmd11116.aruba.it [62.149.156.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9C9C1E884 for ; Fri, 26 Apr 2024 07:39:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=62.149.156.116 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=engicam.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=aruba.it header.i=@aruba.it header.b="lIGd1PW8" Received: from engicam.com ([146.241.21.121]) by Aruba Outgoing Smtp with ESMTPSA id 0GA2s5OJj7AmW0GA4sQ99O; Fri, 26 Apr 2024 09:38:25 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=aruba.it; s=a1; t=1714117105; bh=bnhylyzJQWq0Lj3G8nKnfmrMatUQ5Tgl8eddF/amESY=; h=From:To:Subject:Date:MIME-Version; b=lIGd1PW8Us7K0W14sMNvY3vHnNCzRLbq9sYVKINus02mVkGHKVd7GmcncKJd7Q6pu d3gjpd2NYvL/nMkW1nW+tDPNOyAzsA2XeIOW1N6NRjd71UjhV6RBE+EmzamJ96dd48 xsBPm1nO5H9TPkKXdHAu0LvnpbeNdoVQIwRotnLwnMByeJXJwqoGquxOfaKhrkkbJh 8uqcu9ncJVVUS3yfZP4L15zCS5a6iIa4ELLa24APLQLtzXOHGkvHyLvaBfMfHPgVwS vdMSVzyku1ps69dA0La+o/bg6QawuQczmgYm3VsAZ4X8KV/7ipI7xxo+s4Ar2NfLuq f6pmsb43ADNYg== From: Fabio Aiuto To: Shawn Guo , Sascha Hauer , Krzysztof Kozlowski , Rob Herring , Conor Dooley Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Fabio Aiuto , Michael Nazzareno Trimarchi , Matteo Lisi , Mirko Ardinghi , Peng Fan Subject: [PATCH v5 3/3] arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit Date: Fri, 26 Apr 2024 09:38:20 +0200 Message-Id: <20240426073820.6466-4-fabio.aiuto@engicam.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240426073820.6466-1-fabio.aiuto@engicam.com> References: <20240426073820.6466-1-fabio.aiuto@engicam.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CMAE-Envelope: MS4xfE6sT1BnHKAAg50u46xcOOSREsJ4jETE50uuFKom9m7yBFEDaT/LUiYgvr756yJ+fJIqkFdc/rxAwqTTmaFR9YXnw0alETzhz2RZZSTW6YgU/orhnpZq zwsfwOiEKqUDR6Um5TtSaVFUsmtqtd3nqUR5DWDRM4VmDp41DTNJCovL5HPdxmIs3OGcMmzcEycB77ANQpyqT+BjW8mOI8k0p1H/gvStIPq+LksN0yzBNp4t nMdICu1JP/Pc9JLt2GCti5uYFnOT3qXXTnjw2jswK4FjpQUkWVNHSUgjYWZSzvPz8GEDU4kFDr9nBWbwcNvSMyVVURgW+P/uExZ9M7bie+vHiZbrUzu7Si+B E2GY5OeL9SGVcAlhe5OEJVps0OK/RlCzFOtidvLcX/kgIfDD4yl5oSUrrZAMESg+I1bpTrSfsvOAVCq5Bri+imo8FHBYdUX3+vb72XGe6J0rl1KteNbx/jcS +4QI/dt1RkVHuJPqzHTYwV9AAODvNB4lp4VsXcXt0y9VREXxkGJwcOE+MiIP/igcxJC3AOvkGGU5Pl0QGSHdHXgFHWpJSZVKauEFrqA1nx/VsY0Pkvdbm8CN m7oP02nbs7aKKDkBCocNfbBKn2YMCwV8Stsf+1dXyXG4sMARtsiX2nN5Rx/nqMzxf8jbj//o6EqdF482DvN9zvit i.Core MX93 is a NXP i.MX93 based SoM by Enigcam which needs to be mounted on top of Engicam baseboards. Add support for EDIMM 2.0 Starter Kit hosting i.Core MX93. Starter Kit main features: 2x LVDS interfaces HDMI output Audio out Mic in Micro SD card slot USB 3.0 A port 3x USB 2.0 A port Gb Ethernet 2x CAN bus, 3x UART interfaces SIM card slot M.2 KEY_B slot Cc: Michael Nazzareno Trimarchi Cc: Matteo Lisi Cc: Mirko Ardinghi Reviewed-by: Peng Fan Signed-off-by: Fabio Aiuto Reviewed-by: Michael Trimarchi --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx93-icore-mx93-edimm2.dts | 343 ++++++++++++++++++ 2 files changed, 344 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 045250d0a040..d26c0a458a44 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -226,6 +226,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-icore-mx93-edimm2.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts new file mode 100644 index 000000000000..ff69decb8bd6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts @@ -0,0 +1,343 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 NXP + * Copyright 2024 Engicam s.r.l. + */ + +/dts-v1/; + +#include "imx93-icore-mx93.dtsi" + +/ { + model = "Engicam i.Core MX93 - EDIMM 2 Starterkit"; + compatible = "engicam,icore-mx93-edimm2", "engicam,icore-mx93", + "fsl,imx93"; + + aliases { + rtc1 = &bbnsm_rtc; + }; + + chosen { + stdout-path = &lpuart1; + }; + + bt_reg_on: regulator-btregon { + compatible = "regulator-gpio"; + regulator-name = "BT_REG_ON"; + regulator-min-microvolt = <100000>; + regulator-max-microvolt = <3300000>; + states = <3300000 0x1>, <100000 0x0>; + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + }; + + reg_1v8_sgtl: regulator-1v8-sgtl { + compatible = "regulator-fixed"; + regulator-name = "1v8_sgtl"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3_avdd_sgtl: regulator-3v3-avdd-sgtl { + compatible = "regulator-fixed"; + regulator-name = "3v3_avdd_sgtl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_3v3_sgtl: regulator-3v3-sgtl { + compatible = "regulator-fixed"; + regulator-name = "3v3_sgtl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + + rsc_table: rsc-table@2021f000 { + reg = <0 0x2021f000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4000000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx93-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + /*simple-audio-card,mclk-fs = <1>;*/ + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + clocks = <&clk IMX93_CLK_SAI3_IPG>; + }; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_pwrseq>; + reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + }; +}; + +&cm33 { + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu1 0 1>, + <&mu1 1 1>, + <&mu1 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>; + status = "okay"; +}; + +&lpi2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk IMX93_CLK_SAI3_GATE>; + VDDA-supply = <®_3v3_avdd_sgtl>; + VDDIO-supply = <®_3v3_sgtl>; + VDDD-supply = <®_1v8_sgtl>; + status = "okay"; + }; + + pcf8523: rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart5 { /* RS485 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&lpuart8 { /* RS232 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + status = "okay"; +}; + +&micfil { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <196608000>; + status = "okay"; +}; + +&mu1 { + status = "okay"; +}; + +&mu2 { + status = "okay"; +}; + +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + status = "okay"; +}; + +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&usdhc3 { /* WiFi */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3>; + pinctrl-2 = <&pinctrl_usdhc3>; + mmc-pwrseq = <&usdhc3_pwrseq>; + bus-width = <4>; + no-1-8-v; + non-removable; + max-frequency = <25000000>; + status = "okay"; + + brcmf: bcrmf@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&wdog3 { + status = "okay"; +}; + +&iomuxc { + pinctrl_bluetooth: bluetoothgrp { + fsl,pins = < + MX93_PAD_GPIO_IO19__GPIO2_IO19 0x31e /* BT_REG_ON */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x31e + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_GPIO_IO01__LPUART5_RX 0x31e + MX93_PAD_GPIO_IO00__LPUART5_TX 0x31e + MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e + MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e + >; + }; + + pinctrl_uart8: uart8grp { + fsl,pins = < + MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e + MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x17fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; + + pinctrl_usdhc3_pwrseq: usdhc3pwrseqgrp { + fsl,pins = < + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e /* WL_REG_ON */ + >; + }; +};