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[86.12.82.21]) by smtp.gmail.com with ESMTPSA id b8-20020adfe308000000b003436a3cae6dsm22982701wrj.98.2024.04.26.11.34.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 11:34:15 -0700 (PDT) From: Connor Abbott Date: Fri, 26 Apr 2024 19:33:59 +0100 Subject: [PATCH v2 1/6] arm64: dts: qcom: sm8650: Fix GPU cx_mem size Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240426-a750-raytracing-v2-1-562ac9866d63@gmail.com> References: <20240426-a750-raytracing-v2-0-562ac9866d63@gmail.com> In-Reply-To: <20240426-a750-raytracing-v2-0-562ac9866d63@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jun Nie , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714156453; l=916; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=FgrHStJWxmpAEZMZ2wgWBGQcbCI/vHyX2Dufg6pXZPQ=; b=m7MzYEAOpzrakl0SmAdytTqsZxLHqiZxrkiMz7wap9RAwiDRYGRd8S2J3FJ9jrabgSw/PpAxC LCzkL3UFGbmDAQrltzOWNnlW7GKGkiOmoWj+wSgdFnEa0GoNzcDRMqp X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= This is doubled compared to previous GPUs. We can't access the new SW_FUSE_VALUE register without this. Fixes: db33633b05c0 ("arm64: dts: qcom: sm8650: add GPU nodes") Signed-off-by: Connor Abbott Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 658ad2b41c5a..78b8944eaab2 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2607,7 +2607,7 @@ tcsr: clock-controller@1fc0000 { gpu: gpu@3d00000 { compatible = "qcom,adreno-43051401", "qcom,adreno"; reg = <0x0 0x03d00000 0x0 0x40000>, - <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d9e000 0x0 0x2000>, <0x0 0x03d61000 0x0 0x800>; reg-names = "kgsl_3d0_reg_memory", "cx_mem", From patchwork Fri Apr 26 18:34:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Connor Abbott X-Patchwork-Id: 13645246 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CC28B653; Fri, 26 Apr 2024 18:34:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714156460; cv=none; b=DUsueanbqCcFvfTGX4BgshYG5SF920BnEBzYTrqL10c7ntty6x17lgVYcfjBmbDKD4H/l+iJtgG+UZPM4FICehCIsSQuQLCoZEh0poxFniKsHBBL6Wl6jK37b9LylA/3TObjtOrKhOQg5jU0Ox7xMRHmlFf+RkLwswEEDvmyiYM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714156460; c=relaxed/simple; bh=N/n5sG6Oj7TiRA/tmfItyZc/ajS5lCwpGG8c+dowMcE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SdjkP9U976fvOaLVxzBG+OkQP94vzRCu7U7O5UcFkMAl2+fMT8SJ76C+F9r8TjVjEqMoJPsuDz6aWutMRYk6K0gcfA1EABwq9BEjRTdlRMzcwvzSFBpgT58CGwPrFVEVLmJTPJ68tUWT8T88uwN/dOYDTfUPd4zxozzQKvGxcGo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gGBOPg/w; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gGBOPg/w" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-41ba1ba55e8so5416785e9.1; Fri, 26 Apr 2024 11:34:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1714156457; x=1714761257; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wPGsofIHgWBL1F+g9TnTaPw7aEN5jGWIc3fWppeCwfk=; b=gGBOPg/wk4qwLGBWvlQLmhObtycQ6W5FBq2GG8q+U14r2TsWGn7vBH/usdFDzWGqD+ dZEenK3DQoYrlwuuCCff2io9kaAsXJoLeedskof8uVboj8k8GHx+9W6+tWBOlECKdfCP Hv9nID15vq9CCEcmKOunA6rPVT2N135A93Wh1XhPe6Jzo3datVaVxD5+0aJ85ZD/mUSy 2qZDg6DtG6efVGV/e0BiIEbzkitp4705K0RcUWBXlQVt+ZBanVLRXR8nVhBCkd+Ecb/L rEc5u6QIPIoIa6yZviDFTHaZaW33sXYXg1XRRTCeNxFo8GSl7N0D+8z3aRMTv++jLW33 3pGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714156457; x=1714761257; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wPGsofIHgWBL1F+g9TnTaPw7aEN5jGWIc3fWppeCwfk=; b=UFQcumMoLe01BstbEIVCeu/0uoOfFdNZdW6j/lvJOgWW1i43JynoCOKfFXNPddyl2M n1RIaLl2+eSX7arudPGG4hQm2BsUY2tCcIg66EcGgINp4FKG2B/A+jZ4A0ZJDOuFFtzW On5nzvfo8EgggZqX5xyuoGB9o0n4xbL4qXDOUvPJrH7an7N7Lqs7W4vmYOcauQyEapKS aj6a56rkyWV4gEyOrd2Mz8/+NMGeqZ7SEHeRarEYDSY+hjlNO4JnfunREBBFmzeA5cW6 XrgR5NSx5TgSrKe4slkk7mKGFLeGEqrJfS7PAGLrc+pzIzbkrUuuH9bETrY1iz7BN/tK asDQ== X-Forwarded-Encrypted: i=1; AJvYcCXnfTEdeeGLxmcnT5m5h/6gGHUtu3Cz2nDMUBH0SaMuYDHJmHEF6b66p2ywMZZEjl3U5VMvC5dWoudclwZDISxOojouphIxBuGiXA== X-Gm-Message-State: AOJu0YzZjpO2YRdPDqaB1wPY4hRE2OGnm7n7IMCQCuL8fHJT7gkMpEq2 kEgMCSkks8QJZaV/V6wKVqtpx55UaH+OpQy6wfXQxS5xSI35VwUE X-Google-Smtp-Source: AGHT+IGNEQRnCcWAaBVV+a1LMH8fijRxR5qN8l+QUkTdo2Pldhb4ntfED6KMOYAccZjPbrSxV2rI7w== X-Received: by 2002:adf:a395:0:b0:348:1ee3:48fa with SMTP id l21-20020adfa395000000b003481ee348famr2512595wrb.47.1714156457381; Fri, 26 Apr 2024 11:34:17 -0700 (PDT) Received: from [192.168.0.20] (cpc115152-dals23-2-0-cust532.20-2.cable.virginm.net. [86.12.82.21]) by smtp.gmail.com with ESMTPSA id b8-20020adfe308000000b003436a3cae6dsm22982701wrj.98.2024.04.26.11.34.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 11:34:16 -0700 (PDT) From: Connor Abbott Date: Fri, 26 Apr 2024 19:34:00 +0100 Subject: [PATCH v2 2/6] firmware: qcom_scm: Add gpu_init_regs call Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240426-a750-raytracing-v2-2-562ac9866d63@gmail.com> References: <20240426-a750-raytracing-v2-0-562ac9866d63@gmail.com> In-Reply-To: <20240426-a750-raytracing-v2-0-562ac9866d63@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jun Nie , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714156453; l=2862; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=N/n5sG6Oj7TiRA/tmfItyZc/ajS5lCwpGG8c+dowMcE=; b=gLPELZvLs8tfrH5ezqYstN9qVHFJGVLeX5AmdHQ73mgpmNEylkjAZnQ5jYadP+J34x8mcvY9U AL/1y0h7fhWArvEBu4hMsqFMt4qoiWHliAHXC83G2wiXChjNMtTBRmz X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= This will used by drm/msm. Signed-off-by: Connor Abbott Reviewed-by: Dmitry Baryshkov --- drivers/firmware/qcom/qcom_scm.c | 14 ++++++++++++++ drivers/firmware/qcom/qcom_scm.h | 3 +++ include/linux/firmware/qcom/qcom_scm.h | 23 +++++++++++++++++++++++ 3 files changed, 40 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 06e46267161b..f8623ad0987c 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -1394,6 +1394,20 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, } EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh); +int qcom_scm_gpu_init_regs(u32 gpu_req) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_GPU, + .cmd = QCOM_SCM_SVC_GPU_INIT_REGS, + .arginfo = QCOM_SCM_ARGS(1), + .args[0] = gpu_req, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + return qcom_scm_call(__scm->dev, &desc, NULL); +} +EXPORT_SYMBOL_GPL(qcom_scm_gpu_init_regs); + static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) { struct device_node *tcsr; diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_scm.h index 4532907e8489..484e030bcac9 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -138,6 +138,9 @@ int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_WAITQ_RESUME 0x02 #define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03 +#define QCOM_SCM_SVC_GPU 0x28 +#define QCOM_SCM_SVC_GPU_INIT_REGS 0x01 + /* common error codes */ #define QCOM_SCM_V2_EBUSY -12 #define QCOM_SCM_ENOMEM -5 diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index aaa19f93ac43..2c444c98682e 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -115,6 +115,29 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, int qcom_scm_lmh_profile_change(u32 profile_id); bool qcom_scm_lmh_dcvsh_available(void); +/** + * Request TZ to program set of access controlled registers necessary + * irrespective of any features + */ +#define QCOM_SCM_GPU_ALWAYS_EN_REQ BIT(0) +/** + * Request TZ to program BCL id to access controlled register when BCL is + * enabled + */ +#define QCOM_SCM_GPU_BCL_EN_REQ BIT(1) +/** + * Request TZ to program set of access controlled register for CLX feature + * when enabled + */ +#define QCOM_SCM_GPU_CLX_EN_REQ BIT(2) +/** + * Request TZ to program tsense ids to access controlled registers for reading + * gpu temperature sensors + */ +#define QCOM_SCM_GPU_TSENSE_EN_REQ BIT(3) + +int qcom_scm_gpu_init_regs(u32 gpu_req); + #ifdef CONFIG_QCOM_QSEECOM int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id); From patchwork Fri Apr 26 18:34:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Connor Abbott X-Patchwork-Id: 13645247 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24F9F187F; Fri, 26 Apr 2024 18:34:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714156461; cv=none; b=rUbhAc93Wmpiu8UqSnnUhJITpDeLEbqYYQyUJR9lj9FJNS6N8hfcFa6DD9Z8kv8iBxmmUtaDiajfgMo2i09qip/EzcpKJPpyWziTLGDDT/x4T6Y96XvcD3wG1c/qi19brdxOo1iHqaWjbDghjY25xcmoqN+i/jNniYcHJZ45reY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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[86.12.82.21]) by smtp.gmail.com with ESMTPSA id b8-20020adfe308000000b003436a3cae6dsm22982701wrj.98.2024.04.26.11.34.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 11:34:17 -0700 (PDT) From: Connor Abbott Date: Fri, 26 Apr 2024 19:34:01 +0100 Subject: [PATCH v2 3/6] drm/msm: Update a6xx registers Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240426-a750-raytracing-v2-3-562ac9866d63@gmail.com> References: <20240426-a750-raytracing-v2-0-562ac9866d63@gmail.com> In-Reply-To: <20240426-a750-raytracing-v2-0-562ac9866d63@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jun Nie , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714156453; l=4564; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=gj8ZOZvW+TCIsiJ5iAGXzcf8VySoHr8mvB45qYrrVSk=; b=0IYFtFQIQxezVJf/536lrCVpA8yUE1J60uYyJpCj3CYNOna7xZKzii67fQofklvzlp3UlyX7N 8rMr7hgDSSbBMm6d9PFSu6boJoO5YIRLkODQ2z/bS6Rwh018PNs8BkA X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= Update to mesa commit ff155f46a33 ("freedreno/a7xx: Register updates from kgsl"). Signed-off-by: Connor Abbott Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 28 ++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml index 78524aaab9d4..43fe90c12679 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -1227,6 +1227,7 @@ to upconvert to 32b float internally? + @@ -1503,6 +1504,9 @@ to upconvert to 32b float internally? + + + @@ -2842,7 +2846,11 @@ to upconvert to 32b float internally? - + + RB_SAMPLE_COUNT_ADDR register is used up to (and including) a730. After that + the address is specified through CP_EVENT_WRITE7::WRITE_SAMPLE_COUNT. + + @@ -2950,7 +2958,7 @@ to upconvert to 32b float internally? - + @@ -3306,6 +3314,15 @@ to upconvert to 32b float internally? + + + + + @@ -4293,7 +4310,7 @@ to upconvert to 32b float internally? - + @@ -4965,6 +4982,11 @@ to upconvert to 32b float internally? + + + + + From patchwork Fri Apr 26 18:34:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Connor Abbott X-Patchwork-Id: 13645248 Received: from mail-lj1-f170.google.com (mail-lj1-f170.google.com [209.85.208.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A542DB657; Fri, 26 Apr 2024 18:34:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714156463; cv=none; b=Fw8Gmd8BtUXpn59EHx/UpNqCvXPtKewjQKn1kf1M7S8gvhj5SMYaxptKL+oHzltuWqCvk6X+y6lozY0vrSohZ+jpv852ipJQ6s6VNiVdHFB/JsUOvUYrY+j8K5HZbPE7VH1oaoCB5AqRn5iNpFV0IYYRlD/pzLU/MCElA/qBCkk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714156463; c=relaxed/simple; bh=FB4nUm7s1SV7x38lz19WasOXdX8Zxsy0GVCFLqwM5nQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=I9q6SN7HIaDWr4oZ6YzD+iYiuQ1VL1tKACpqDK5XniToTR8KR/AZgK5okWWUqHs/+i/LwFkWK0zXtfnccyNtPeoiarx6Zvq5I4JE2ynrLuHnMvmrgScSaYlO2RIVhxFAK1ko41EBufftPdJrFWVESjtLpzR0NbdOf6XpoFvzDNU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=RKMv2R3H; arc=none smtp.client-ip=209.85.208.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RKMv2R3H" Received: by mail-lj1-f170.google.com with SMTP id 38308e7fff4ca-2de232989aaso28551591fa.1; Fri, 26 Apr 2024 11:34:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1714156460; x=1714761260; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=MNeWNMU4iC0fR64E8ENW7UV7ElqWg5SI0xQxIgkRybU=; b=RKMv2R3HTIZayV3QRCmBIkP/xe3HTqMawP414jnw/emT+eBQIWRNV0Ttn+xhF87/jr iXyGV35RUK2PugaYEAKqAaBnv09pTlnTekfOzKL6nD1nTOcluGM4eotLawCr2ZarD5TY lonWXrHcAg4YnRftKCfNWUeQDSTzi3firsXZ0W9NuqY12rf+BR7kaxY6B4rzUyl5dvzF NYGqheeiIkGtDwap4ZmRQsF/e7y9o6IWBQvp281WeOvVEgi0SlZUuD4qSHjda4A5q69L ktgZWgZQrPz/caWoxuaFWDIhp/qq+1cMGj4inL2DMD66yCM+uXRzqPcC8gWZZvM0vKdg 0MhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714156460; x=1714761260; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MNeWNMU4iC0fR64E8ENW7UV7ElqWg5SI0xQxIgkRybU=; b=FaffG2XCS5pzBpnJg2EH4LWgcpFFYJpt2RXR4dg4D6/LGuHPUlxjZMeuQKI/mAmG5i DIzwAqQjEVuepQErH8qkyixLymbrVLfnt0TtHVkYdInNo8wGo/H33Dz/sPD38i/DMwIG yEa01Ehm/G6elGoNRo9JxxpII7oCYtwJH1BvljMKAeQHGgnm4hHr7PbCPqZI7LPhuzhu h3mcjJ96OPGbf+q2MWPjVNJp3jbL3LWqU58oeMMsG8Xzfvzo8tLG/ScygBIGGm1zSCRG 2Tzj4ZZGe0wZsAe9+dZ1pwejF4jOGaAAGmjrGf/6DzgBQUUrC3DbEBEvZ4qJkpSb0iVJ bD3g== X-Forwarded-Encrypted: i=1; AJvYcCVyxQfffcJYdMIrXwUMCGg3h3x5dLiSaOX7oW8IVzbhrsBnMDHprGU1uWerXe4fzIB4KAjE8O2+AfuvKoGXokkVpkbng3leUd+57g== X-Gm-Message-State: AOJu0YzeDP9L8mDw1ZVO/ApDqurcdwfjxsPSDwTs3shAvFJ1f6cJrNdu NlwB+aCIqSSJ6fhbc0CkYAp63FbrJcA3a6Xh7srFI0KjEX+4Zj1GTc725A7z X-Google-Smtp-Source: AGHT+IFvv+lFVf7ctbMBgdPnE62NbP8Wy6WaIebn1+xIGY49rrJMfTGwVYmEDlV2mh9m21deiF3ujA== X-Received: by 2002:a2e:9186:0:b0:2de:bae:b306 with SMTP id f6-20020a2e9186000000b002de0baeb306mr2307110ljg.8.1714156459506; Fri, 26 Apr 2024 11:34:19 -0700 (PDT) Received: from [192.168.0.20] (cpc115152-dals23-2-0-cust532.20-2.cable.virginm.net. [86.12.82.21]) by smtp.gmail.com with ESMTPSA id b8-20020adfe308000000b003436a3cae6dsm22982701wrj.98.2024.04.26.11.34.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 11:34:19 -0700 (PDT) From: Connor Abbott Date: Fri, 26 Apr 2024 19:34:02 +0100 Subject: [PATCH v2 4/6] drm/msm/a7xx: Initialize a750 "software fuse" Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240426-a750-raytracing-v2-4-562ac9866d63@gmail.com> References: <20240426-a750-raytracing-v2-0-562ac9866d63@gmail.com> In-Reply-To: <20240426-a750-raytracing-v2-0-562ac9866d63@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jun Nie , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714156454; l=5638; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=FB4nUm7s1SV7x38lz19WasOXdX8Zxsy0GVCFLqwM5nQ=; b=mIzn5aKn9u7Lp70e876ok753DBDaJj3YB4/iiM4G65nYqkftFQ7ez4jqHZL9Eqm7FtQjXy/SI suTWxZSmrOUDlCp31Dg3CvfMpRi+uWUD/Z1fbvt5Ni+BUk8hSukZr7M X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled. Signed-off-by: Connor Abbott Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 88 ++++++++++++++++++++++++++++++++- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 + 2 files changed, 89 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index cf0b1de1c071..4a3b12b20802 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -10,6 +10,7 @@ #include #include +#include #include #include @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu) A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \ - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR) + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \ + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \ A6XX_CP_APRIV_CNTL_RBFETCH | \ @@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu) kthread_queue_work(gpu->worker, &gpu->recover_work); } +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu) +{ + u32 status; + + status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS); + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0); + + dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status); + + /* Ignore FASTBLEND violations, because the HW will silently fall back + * to legacy blending. + */ + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) { + del_timer(&gpu->hangcheck_timer); + + kthread_queue_work(gpu->worker, &gpu->recover_work); + } +} + static irqreturn_t a6xx_irq(struct msm_gpu *gpu) { struct msm_drm_private *priv = gpu->dev->dev_private; @@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu) if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) + a7xx_sw_fuse_violation_irq(gpu); + if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) msm_gpu_retire(gpu); @@ -2525,6 +2550,59 @@ static void a6xx_llc_slices_init(struct platform_device *pdev, a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL); } +static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu) +{ + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + struct msm_gpu *gpu = &adreno_gpu->base; + u32 fuse_val; + int ret = 0; + + if (adreno_is_a750(adreno_gpu)) { + /* Assume that if qcom scm isn't available, that whatever + * replacement allows writing the fuse register ourselves. + * Users of alternative firmware need to make sure this + * register is writeable or indicate that it's not somehow. + * Print a warning because if you mess this up you're about to + * crash horribly. + */ + if (!qcom_scm_is_available()) { + dev_warn_once(gpu->dev->dev, + "SCM is not available, poking fuse register\n"); + a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, + A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | + A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND | + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC); + adreno_gpu->has_ray_tracing = true; + return 0; + } + + ret = qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ | + QCOM_SCM_GPU_TSENSE_EN_REQ); + if (ret) + return ret; + + /* On a750 raytracing may be disabled by the firmware, find out whether + * that's the case. The scm call above sets the fuse register. + */ + fuse_val = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE); + adreno_gpu->has_ray_tracing = + !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING); + } else { + if (adreno_is_a740(adreno_gpu)) { + /* Raytracing is always enabled on a740 */ + adreno_gpu->has_ray_tracing = true; + } + + if (!qcom_scm_is_available()) + return 0; + + ret = qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ); + } + + return ret; +} + + #define GBIF_CLIENT_HALT_MASK BIT(0) #define GBIF_ARB_HALT_MASK BIT(1) #define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) @@ -3094,6 +3172,14 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) return ERR_PTR(ret); } + if (adreno_is_a7xx(adreno_gpu)) { + ret = a7xx_cx_mem_init(a6xx_gpu); + if (ret) { + a6xx_destroy(&(a6xx_gpu->base.base)); + return ERR_PTR(ret); + } + } + if (gpu->aspace) msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, a6xx_fault_handler); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 77526892eb8c..4180f3149dd8 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -182,6 +182,8 @@ struct adreno_gpu { */ const unsigned int *reg_offsets; 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[86.12.82.21]) by smtp.gmail.com with ESMTPSA id b8-20020adfe308000000b003436a3cae6dsm22982701wrj.98.2024.04.26.11.34.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 11:34:20 -0700 (PDT) From: Connor Abbott Date: Fri, 26 Apr 2024 19:34:03 +0100 Subject: [PATCH v2 5/6] drm/msm: Add MSM_PARAM_RAYTRACING uapi Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240426-a750-raytracing-v2-5-562ac9866d63@gmail.com> References: <20240426-a750-raytracing-v2-0-562ac9866d63@gmail.com> In-Reply-To: <20240426-a750-raytracing-v2-0-562ac9866d63@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jun Nie , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714156454; l=1497; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=k8+KP5BvBzaV5ltlemprdbB/MkL5yABOBJv6NDeukv0=; b=ocnALglUtUX8abejfJwQNRHOwjqITr5Nn1ufOtg985+P6uOhXhWYrYVVa7XXRSSj/446N+5pc hY56qhN1krCCrQA2Wzyga9JeuOyIPfs0RlQzreXvegRjcspq/JZSBsr X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= Expose the value of the software fuse to userspace. Signed-off-by: Connor Abbott Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++ include/uapi/drm/msm_drm.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 074fb498706f..99ad651857b2 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -376,6 +376,9 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, case MSM_PARAM_HIGHEST_BANK_BIT: *value = adreno_gpu->ubwc_config.highest_bank_bit; return 0; + case MSM_PARAM_RAYTRACING: + *value = adreno_gpu->has_ray_tracing; + return 0; default: DBG("%s: invalid param: %u", gpu->name, param); return -EINVAL; diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index d8a6b3472760..3fca72f73861 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -87,6 +87,7 @@ struct drm_msm_timespec { #define MSM_PARAM_VA_START 0x0e /* RO: start of valid GPU iova range */ #define MSM_PARAM_VA_SIZE 0x0f /* RO: size of valid GPU iova range (bytes) */ #define MSM_PARAM_HIGHEST_BANK_BIT 0x10 /* RO */ +#define MSM_PARAM_RAYTRACING 0x11 /* RO */ /* For backwards compat. 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[86.12.82.21]) by smtp.gmail.com with ESMTPSA id b8-20020adfe308000000b003436a3cae6dsm22982701wrj.98.2024.04.26.11.34.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Apr 2024 11:34:21 -0700 (PDT) From: Connor Abbott Date: Fri, 26 Apr 2024 19:34:04 +0100 Subject: [PATCH v2 6/6] drm/msm/a7xx: Add missing register writes from downstream Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240426-a750-raytracing-v2-6-562ac9866d63@gmail.com> References: <20240426-a750-raytracing-v2-0-562ac9866d63@gmail.com> In-Reply-To: <20240426-a750-raytracing-v2-0-562ac9866d63@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jun Nie , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714156454; l=1002; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=egrZvhM+VJXYHLqq3OZ5q41AGIhcMaeNPTkRYlBKH78=; b=o9fdkDoS/YkfV/V0z0h6hIhKhzcieS6htACG9eESo5iKjrx59eF5rnL36c8VHWB1sjdqAe8SZ 0bXPLzO+8TPA2QIcjD1TetNUU4Znb1gyCaMCVQ6xIQbko3Za4x7ryPO X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= This isn't known to fix anything yet, but it's a good idea to add it. Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 4a3b12b20802..d88ec857f1cb 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1953,6 +1953,14 @@ static int hw_init(struct msm_gpu *gpu) BIT(6) | BIT(5) | BIT(3) | BIT(2) | BIT(1)); } + if (adreno_is_a750(adreno_gpu)) { + gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); + + gpu_write(gpu, REG_A6XX_TPL1_DBG_ECO_CNTL1, 0xc0700); + } else if (adreno_is_a7xx(adreno_gpu)) { + gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); + } + /* Enable interrupts */ gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, adreno_is_a7xx(adreno_gpu) ? A7XX_INT_MASK : A6XX_INT_MASK);