From patchwork Sun Apr 28 11:40:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dragan Simic X-Patchwork-Id: 13646006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 708A4C4345F for ; Sun, 28 Apr 2024 11:41:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=fns/AK8g7HyLNAmO5IA9cbjj4ZtI1Y8NWEa+Ni0qaXU=; b=Ps/vvyECX+eR0E I+L8SB/ah4eRnBvZ3DqP1o/v+w+VzdrR9QLlCwcm1oE48y00OSMPdME9KXVOFvjBmHVzhEeL2NBHg D7Fo4k/pidaMdIdtilQmSdsM73/fLBx/IrQlpl8JDXpsghbp6nC6TdAXeN52irtKPZT/8h06eY581 u3d0+usjLG1JtqShx/r0gvkdsyxwgo7I5RcffpT/3qnJnf2aETroNsUowlnfBeL5fTBYDEWhwB6oI Q4mO7XcOuSWfgFR46FJja8S6asODpdsCBCW3mexlpACD752u+QP3gJI+4y9yixDWYZzhRtPVdNk9G 7pHxHB1QnFPPQa/QtAoA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s12tx-0000000HS29-0cRE; Sun, 28 Apr 2024 11:41:01 +0000 Received: from mail.manjaro.org ([116.203.91.91]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s12tt-0000000HS0B-3Zrb for linux-arm-kernel@lists.infradead.org; Sun, 28 Apr 2024 11:40:59 +0000 From: Dragan Simic DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=manjaro.org; s=2021; t=1714304444; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=fUUlO8nSkAmh0ieyYyxQ3T6zIAKTL4UZHOPVrkuWOnQ=; b=SlJ1ct7Qbmgs/iRfAlf0K+hPxDYtqovcTVLtZoJUXu7iPQxNtw2vyh4VPwNfkmgoNJ1oby fRbsxecxQpE/TgsXDHSM1/ZCpXlFR0mXnfg1DFRk+kRfQaxjoCrFUDPhTaUU1stRMZ2iVw tK0iearS6rjrwl5oELDxFKl6WAFMO6ryubceAJx5HnKJ7n5YF2L3De4N0Oa/YXzCNofYKv /nPKzUdRm05Ds9+cGNRoj6aLghOw3r+p2D87+Y+5ZC4M8gX8KOvadRGpIVKUxdwnwRxkCX U+Ua4OO3Jx9D6R0Em1JcDP9qcH0DLqJrgBiitjLnXDf2FWaJSzF7dA4FGEBYGw== To: linux-sunxi@lists.linux.dev Cc: wens@csie.org, jernej.skrabec@gmail.com, samuel@sholland.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for A64 Date: Sun, 28 Apr 2024 13:40:35 +0200 Message-Id: <6a772756c2c677dbdaaab4a2c71a358d8e4b27e9.1714304058.git.dsimic@manjaro.org> MIME-Version: 1.0 Authentication-Results: ORIGINATING; auth=pass smtp.auth=dsimic@manjaro.org smtp.mailfrom=dsimic@manjaro.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240428_044058_282152_1FE0DD98 X-CRM114-Status: GOOD ( 10.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add missing cache information to the Allwinner A64 SoC dtsi, to allow the userspace, which includes lscpu(1) that uses the virtual files provided by the kernel under the /sys/devices/system/cpu directory, to display the proper A64 cache information. While there, use a more self-descriptive label for the L2 cache node, which also makes it more consistent with other SoC dtsi files. The cache parameters for the A64 dtsi were obtained and partially derived by hand from the cache size and layout specifications found in the following datasheets and technical reference manuals: - Allwinner A64 datasheet, version 1.1 - ARM Cortex-A53 revision r0p3 TRM, version E For future reference, here's a brief summary of the documentation: - All caches employ the 64-byte cache line length - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction cache and 32 KB of L1 4-way, set-associative data cache - The entire SoC has 512 KB of unified L2 16-way, set-associative cache Signed-off-by: Dragan Simic Reviewed-by: Jernej Skrabec Reviewed-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 37 ++++++++++++++++--- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 57ac18738c99..86074d03afa9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -51,49 +51,76 @@ cpu0: cpu@0 { device_type = "cpu"; reg = <0>; enable-method = "psci"; - next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <1>; enable-method = "psci"; - next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <2>; enable-method = "psci"; - next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <3>; enable-method = "psci"; - next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; - L2: l2-cache { + l2_cache: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; };