From patchwork Mon Apr 29 10:46:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13646616 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3AA88C4345F for ; Mon, 29 Apr 2024 10:47:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=N7DdOYdKKniG+ZkvrRY84UxZm8yG3q5RNE7BLGXWT1k=; b=2MVDAPTe3P7i1T 0df8Mqc8X7UvHfXjUkE6CD42lyKEt0A8OPPWSl+cMyfQjBxz+l8+3E0CZcWAIOLhNiQ7+TrI9gYN9 To/U01F49AFJG5iZHHZONT/fY4LjTnaSWqXnxSwQuGd5C7+TwfkRY9dabEiFibZTfxDzMoPQbL1yB olsMfs1wH6ONsuAyrBHpqQ1IdlRhPIPKjUJCB1s5pkMZS6wncwMUiyZRvH/cLz73XTNoHvIVlMDzQ AJqS9lI9ce6ea3N0c2+4ePz/Bp6EFlplk/eDgHuU4uCghWa57xsl4HNU28hx4nCsjQ7zQftgyAJIT 6sxB/cAdE7KuqkSeILgg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s1OXH-00000002KvK-0rmP; Mon, 29 Apr 2024 10:47:03 +0000 Received: from mgamail.intel.com ([192.198.163.8]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s1OXC-00000002Ktn-2t4L for linux-arm-kernel@lists.infradead.org; Mon, 29 Apr 2024 10:47:00 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714387618; x=1745923618; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R2riUg/Wc1wqrQ5JnljoOoCmOH+vsHTb6i6sFG4RQIs=; b=C7ZLExr1GqJoyBmRJ7DUKauscrsOR3x16lxIaIXNIZjYaeT+reiXmLn4 V+a2TqZuvGtyPXEF2y52hjJttDW0+U8KnRtV+d1VNGFThXS/NnbZ+L456 XXBkj1m5isDzK1VzwAKYo//feIGgKE2yJGhhDLPQeaMsx3W25LVRMDg4J Zd2KqBi1O+IM3O03Rxjg+ewpY5cBBJjiPHA6QUZJFTjGmoZAp9Gg9UArO uhD3y/hPspeFgb1X/lHBNCuiYFptmhgwwZP6++YgQpKJkmthFQuoqjSqT pyDeXzLak8qyLo3XbkxLI21nR4G+TxHYuztYKowqnwyBvqbJoIeg8Bxf8 g==; X-CSE-ConnectionGUID: RYV2La3ATZ+RNRj/Yd6Hhg== X-CSE-MsgGUID: uIA33Z6PQPeZN419gy/E/w== X-IronPort-AV: E=McAfee;i="6600,9927,11057"; a="27558813" X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="27558813" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:46:55 -0700 X-CSE-ConnectionGUID: 8awMQp1vRrWFMQAWhN3V4A== X-CSE-MsgGUID: nM3+DbKYRoC6OTW0EV+TyA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="30896676" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.45]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:46:50 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Russell King , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH 01/10] ARM: orion5x: Rename PCI_CONF_{REG,FUNC}() out of the way Date: Mon, 29 Apr 2024 13:46:24 +0300 Message-Id: <20240429104633.11060-2-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240429_034658_762845_7AF4B78A X-CRM114-Status: GOOD ( 11.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org orion5x defines PCI_CONF_REG() and PCI_CONF_FUNC() that are problematic because PCI core is going to introduce defines with the same names. Add ORION5X prefix to those defines to avoid name conflicts. Note: as this is part of series that replaces the code in question anyway, only bare minimum renaming is done and other similarly named macros are not touched. Signed-off-by: Ilpo Järvinen Reviewed-by: Andrew Lunn Acked-by: Gregory CLEMENT --- arch/arm/mach-orion5x/pci.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index 3313bc5a63ea..77ddab90f448 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -219,8 +219,8 @@ static int __init pcie_setup(struct pci_sys_data *sys) /* * PCI_CONF_ADDR bits */ -#define PCI_CONF_REG(reg) ((reg) & 0xfc) -#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8) +#define ORION5X_PCI_CONF_REG(reg) ((reg) & 0xfc) +#define ORION5X_PCI_CONF_FUNC(func) (((func) & 0x3) << 8) #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) #define PCI_CONF_ADDR_EN (1 << 31) @@ -277,8 +277,8 @@ static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, spin_lock_irqsave(&orion5x_pci_lock, flags); writel(PCI_CONF_BUS(bus) | - PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | - PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); + PCI_CONF_DEV(dev) | ORION5X_PCI_CONF_REG(where) | + ORION5X_PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); *val = readl(PCI_CONF_DATA); @@ -301,8 +301,8 @@ static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, spin_lock_irqsave(&orion5x_pci_lock, flags); writel(PCI_CONF_BUS(bus) | - PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | - PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); + PCI_CONF_DEV(dev) | ORION5X_PCI_CONF_REG(where) | + ORION5X_PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); if (size == 4) { __raw_writel(val, PCI_CONF_DATA); From patchwork Mon Apr 29 10:46:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13646617 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0FDCDC4345F for ; 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a="9966399" X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="9966399" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:13 -0700 X-CSE-ConnectionGUID: stDX6XgTSJuv+E6+WewvQg== X-CSE-MsgGUID: rEQrG+G5SKmYxHUm7cDUyA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="26037436" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.45]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:09 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Russell King , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH 03/10] ARM: orion5x: Pass devfn to orion5x_pci_hw_{rd,wr}_conf() Date: Mon, 29 Apr 2024 13:46:26 +0300 Message-Id: <20240429104633.11060-4-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240429_034717_239468_0A03AD34 X-CRM114-Status: GOOD ( 14.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Pass the usual devfn instead of individual components into orion5x_pci_hw_{rd,wr}_conf() to make the change into pci_conf1_offset() in an upcoming commit easier. Signed-off-by: Ilpo Järvinen Reviewed-by: Andrew Lunn Acked-by: Gregory CLEMENT --- arch/arm/mach-orion5x/pci.c | 45 +++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index 77ddab90f448..6376e1db6386 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -270,15 +270,15 @@ static int orion5x_pci_local_bus_nr(void) return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); } -static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, - u32 where, u32 size, u32 *val) +static int orion5x_pci_hw_rd_conf(int bus, u8 devfn, u32 where, + u32 size, u32 *val) { unsigned long flags; spin_lock_irqsave(&orion5x_pci_lock, flags); writel(PCI_CONF_BUS(bus) | - PCI_CONF_DEV(dev) | ORION5X_PCI_CONF_REG(where) | - ORION5X_PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); + PCI_CONF_DEV(PCI_SLOT(devfn)) | ORION5X_PCI_CONF_REG(where) | + ORION5X_PCI_CONF_FUNC(PCI_FUNC(devfn)) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); *val = readl(PCI_CONF_DATA); @@ -292,8 +292,8 @@ static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func, return PCIBIOS_SUCCESSFUL; } -static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, - u32 where, u32 size, u32 val) +static int orion5x_pci_hw_wr_conf(int bus, u8 devfn, u32 where, + u32 size, u32 val) { unsigned long flags; int ret = PCIBIOS_SUCCESSFUL; @@ -301,8 +301,8 @@ static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func, spin_lock_irqsave(&orion5x_pci_lock, flags); writel(PCI_CONF_BUS(bus) | - PCI_CONF_DEV(dev) | ORION5X_PCI_CONF_REG(where) | - ORION5X_PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); + PCI_CONF_DEV(PCI_SLOT(devfn)) | ORION5X_PCI_CONF_REG(where) | + ORION5X_PCI_CONF_FUNC(PCI_FUNC(devfn)) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); if (size == 4) { __raw_writel(val, PCI_CONF_DATA); @@ -347,8 +347,7 @@ static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, return PCIBIOS_DEVICE_NOT_FOUND; } - return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where, size, val); + return orion5x_pci_hw_rd_conf(bus->number, devfn, where, size, val); } static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, @@ -357,8 +356,7 @@ static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, if (!orion5x_pci_valid_config(bus->number, devfn)) return PCIBIOS_DEVICE_NOT_FOUND; - return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where, size, val); + return orion5x_pci_hw_wr_conf(bus->number, devfn, where, size, val); } static struct pci_ops pci_ops = { @@ -375,12 +373,14 @@ static void __init orion5x_pci_set_bus_nr(int nr) * PCI-X mode */ u32 pcix_status, bus, dev; + u8 devfn; bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS; dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS; - orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status); + devfn = PCI_DEVFN(dev, 0); + orion5x_pci_hw_rd_conf(bus, devfn, PCIX_STAT, 4, &pcix_status); pcix_status &= ~PCIX_STAT_BUS_MASK; pcix_status |= (nr << PCIX_STAT_BUS_OFFS); - orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status); + orion5x_pci_hw_wr_conf(bus, devfn, PCIX_STAT, 4, pcix_status); } else { /* * PCI Conventional mode @@ -393,15 +393,16 @@ static void __init orion5x_pci_set_bus_nr(int nr) static void __init orion5x_pci_master_slave_enable(void) { - int bus_nr, func, reg; + int bus_nr, reg; + u8 devfn; u32 val; bus_nr = orion5x_pci_local_bus_nr(); - func = PCI_CONF_FUNC_STAT_CMD; + devfn = PCI_DEVFN(0, PCI_CONF_FUNC_STAT_CMD); reg = PCI_CONF_REG_STAT_CMD; - orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val); + orion5x_pci_hw_rd_conf(bus_nr, devfn, reg, 4, &val); val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7); + orion5x_pci_hw_wr_conf(bus_nr, devfn, reg, 4, val | 0x7); } static void __init orion5x_setup_pci_wins(void) @@ -424,7 +425,7 @@ static void __init orion5x_setup_pci_wins(void) for (i = 0; i < dram->num_cs; i++) { const struct mbus_dram_window *cs = dram->cs + i; - u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index); + u8 devfn = PCI_DEVFN(0, PCI_CONF_FUNC_BAR_CS(cs->cs_index)); u32 reg; u32 val; @@ -432,15 +433,15 @@ static void __init orion5x_setup_pci_wins(void) * Write DRAM bank base address register. */ reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index); - orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val); + orion5x_pci_hw_rd_conf(bus, devfn, reg, 4, &val); val = (cs->base & 0xfffff000) | (val & 0xfff); - orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val); + orion5x_pci_hw_wr_conf(bus, devfn, reg, 4, val); /* * Write DRAM bank size register. */ reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); - orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); + orion5x_pci_hw_wr_conf(bus, devfn, reg, 4, 0); writel((cs->size - 1) & 0xfffff000, PCI_BAR_SIZE_DDR_CS(cs->cs_index)); writel(cs->base & 0xfffff000, From patchwork Mon Apr 29 10:46:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13646618 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB6F9C4345F for ; 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a="9966407" X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="9966407" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:21 -0700 X-CSE-ConnectionGUID: 4DvHrAC2QZakeUA59jFLEA== X-CSE-MsgGUID: d/YhKH28ScaMZhNP8uPcwQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="26037455" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.45]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:18 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Russell King , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH 04/10] ARM: orion5x: Use generic PCI Conf Type 1 helper Date: Mon, 29 Apr 2024 13:46:27 +0300 Message-Id: <20240429104633.11060-5-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240429_034721_756788_ED1AF4B4 X-CRM114-Status: UNSURE ( 9.76 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert orion5x PCI code to use pci_conf1_ext_addr() from PCI core to calculate PCI Configuration Type 1 address. Signed-off-by: Ilpo Järvinen Acked-by: Gregory CLEMENT --- arch/arm/mach-orion5x/pci.c | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index 6376e1db6386..8b7d67549adf 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -216,15 +216,6 @@ static int __init pcie_setup(struct pci_sys_data *sys) #define PCI_P2P_DEV_OFFS 24 #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS) -/* - * PCI_CONF_ADDR bits - */ -#define ORION5X_PCI_CONF_REG(reg) ((reg) & 0xfc) -#define ORION5X_PCI_CONF_FUNC(func) (((func) & 0x3) << 8) -#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11) -#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16) -#define PCI_CONF_ADDR_EN (1 << 31) - /* * Internal configuration space */ @@ -276,9 +267,7 @@ static int orion5x_pci_hw_rd_conf(int bus, u8 devfn, u32 where, unsigned long flags; spin_lock_irqsave(&orion5x_pci_lock, flags); - writel(PCI_CONF_BUS(bus) | - PCI_CONF_DEV(PCI_SLOT(devfn)) | ORION5X_PCI_CONF_REG(where) | - ORION5X_PCI_CONF_FUNC(PCI_FUNC(devfn)) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); + writel(pci_conf1_addr(bus, devfn, where, true), PCI_CONF_ADDR); *val = readl(PCI_CONF_DATA); @@ -300,9 +289,7 @@ static int orion5x_pci_hw_wr_conf(int bus, u8 devfn, u32 where, spin_lock_irqsave(&orion5x_pci_lock, flags); - writel(PCI_CONF_BUS(bus) | - PCI_CONF_DEV(PCI_SLOT(devfn)) | ORION5X_PCI_CONF_REG(where) | - ORION5X_PCI_CONF_FUNC(PCI_FUNC(devfn)) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR); + writel(pci_conf1_addr(bus, devfn, where, true), PCI_CONF_ADDR); if (size == 4) { __raw_writel(val, PCI_CONF_DATA); From patchwork Mon Apr 29 10:46:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13646619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D655AC4345F for ; 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d="scan'208";a="10201846" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:49 -0700 X-CSE-ConnectionGUID: /nnKB6kaSHeZOlfWFHxV8w== X-CSE-MsgGUID: k64qq1ZHTVWYmwqvHsqZzA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="26589567" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.45]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:47:44 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Lorenzo Pieralisi , Linus Walleij , Sergio Paracuellos , Matthias Brugger , AngeloGioacchino Del Regno , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Cc: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH 07/10] PCI: Replace PCI_CONF1{,_EXT}_ADDRESS() with the new helpers Date: Mon, 29 Apr 2024 13:46:30 +0300 Message-Id: <20240429104633.11060-8-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240429_034750_243586_EBE06F3E X-CRM114-Status: GOOD ( 14.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Replace the old PCI_CONF1{,_EXT}_ADDRESS() helpers used to calculate PCI Configuration Space Type 1 addresses with the new pci_conf1{,_ext}_offset() helpers that are more generic and more widely available. Signed-off-by: Ilpo Järvinen Reviewed-by: Linus Walleij Acked-by: Sergio Paracuellos Tested-by: Sergio Paracuellos --- drivers/pci/controller/pci-ftpci100.c | 6 ++---- drivers/pci/controller/pci-ixp4xx.c | 5 ++--- drivers/pci/controller/pcie-mt7621.c | 7 +++---- drivers/pci/pci.h | 8 -------- 4 files changed, 7 insertions(+), 19 deletions(-) diff --git a/drivers/pci/controller/pci-ftpci100.c b/drivers/pci/controller/pci-ftpci100.c index ffdeed25e961..a8d0217a0b94 100644 --- a/drivers/pci/controller/pci-ftpci100.c +++ b/drivers/pci/controller/pci-ftpci100.c @@ -182,8 +182,7 @@ static int faraday_raw_pci_read_config(struct faraday_pci *p, int bus_number, unsigned int fn, int config, int size, u32 *value) { - writel(PCI_CONF1_ADDRESS(bus_number, PCI_SLOT(fn), - PCI_FUNC(fn), config), + writel(pci_conf1_addr(bus_number, fn, config, true), p->base + FTPCI_CONFIG); *value = readl(p->base + FTPCI_DATA); @@ -214,8 +213,7 @@ static int faraday_raw_pci_write_config(struct faraday_pci *p, int bus_number, { int ret = PCIBIOS_SUCCESSFUL; - writel(PCI_CONF1_ADDRESS(bus_number, PCI_SLOT(fn), - PCI_FUNC(fn), config), + writel(pci_conf1_addr(bus_number, fn, config, true), p->base + FTPCI_CONFIG); switch (size) { diff --git a/drivers/pci/controller/pci-ixp4xx.c b/drivers/pci/controller/pci-ixp4xx.c index ec0125344ca1..fd52f4a3ef31 100644 --- a/drivers/pci/controller/pci-ixp4xx.c +++ b/drivers/pci/controller/pci-ixp4xx.c @@ -192,9 +192,8 @@ static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where) BIT(32 - PCI_SLOT(devfn)); } else { /* type 1 */ - return (PCI_CONF1_ADDRESS(bus_num, PCI_SLOT(devfn), - PCI_FUNC(devfn), where) & - ~PCI_CONF1_ENABLE) | PCI_CONF1_TRANSACTION; + return pci_conf1_addr(bus_num, devfn, where, false) | + PCI_CONF1_TRANSACTION; } } diff --git a/drivers/pci/controller/pcie-mt7621.c b/drivers/pci/controller/pcie-mt7621.c index 79e225edb42a..2b2d9828a910 100644 --- a/drivers/pci/controller/pcie-mt7621.c +++ b/drivers/pci/controller/pcie-mt7621.c @@ -127,8 +127,7 @@ static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { struct mt7621_pcie *pcie = bus->sysdata; - u32 address = PCI_CONF1_EXT_ADDRESS(bus->number, PCI_SLOT(devfn), - PCI_FUNC(devfn), where); + u32 address = pci_conf1_ext_addr(bus->number, devfn, where, true); writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR); @@ -143,7 +142,7 @@ static struct pci_ops mt7621_pcie_ops = { static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) { - u32 address = PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg); + u32 address = pci_conf1_ext_addr(0, PCI_DEVFN(dev, 0), reg, true); pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); return pcie_read(pcie, RALINK_PCI_CONFIG_DATA); @@ -152,7 +151,7 @@ static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) static void write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val) { - u32 address = PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg); + u32 address = pci_conf1_ext_addr(0, PCI_DEVFN(dev, 0), reg, true); pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index cf0530a60105..fdf9624b0b12 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -833,12 +833,4 @@ struct pci_devres { struct pci_devres *find_pci_dr(struct pci_dev *pdev); -#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ - (PCI_CONF1_ENABLE | \ - pci_conf1_addr(bus, PCI_DEVFN(dev, func), reg & ~0x3U)) - -#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ - (PCI_CONF1_ENABLE | \ - pci_conf1_ext_addr(bus, PCI_DEVFN(dev, func), reg & ~0x3U)) - #endif /* DRIVERS_PCI_H */ From patchwork Mon Apr 29 10:46:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13646620 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50C60C4345F for ; Mon, 29 Apr 2024 10:48:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; 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29 Apr 2024 03:48:08 -0700 X-CSE-ConnectionGUID: bOPtYgLLRmirNCTAizYk1Q== X-CSE-MsgGUID: 0IPQ+Z+tQTiB4Q/+A6EYGQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,239,1708416000"; d="scan'208";a="30896807" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.245.247.45]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2024 03:48:04 -0700 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH 09/10] PCI: mvebu: Use generic PCI Conf Type 1 helper Date: Mon, 29 Apr 2024 13:46:32 +0300 Message-Id: <20240429104633.11060-10-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> References: <20240429104633.11060-1-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240429_034808_849470_B5128C0B X-CRM114-Status: GOOD ( 10.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert mvebu to use the pci_conf1_ext_addr() helper from PCI core to calculate PCI Configuration Space address for Type 1 access. Signed-off-by: Ilpo Järvinen Tested-by: Andrew Lunn --- drivers/pci/controller/pci-mvebu.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c index 29fe09c99e7d..1908754ee6fd 100644 --- a/drivers/pci/controller/pci-mvebu.c +++ b/drivers/pci/controller/pci-mvebu.c @@ -45,15 +45,6 @@ #define PCIE_WIN5_BASE_OFF 0x1884 #define PCIE_WIN5_REMAP_OFF 0x188c #define PCIE_CONF_ADDR_OFF 0x18f8 -#define PCIE_CONF_ADDR_EN 0x80000000 -#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc)) -#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16) -#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11) -#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8) -#define PCIE_CONF_ADDR(bus, devfn, where) \ - (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ - PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \ - PCIE_CONF_ADDR_EN) #define PCIE_CONF_DATA_OFF 0x18fc #define PCIE_INT_CAUSE_OFF 0x1900 #define PCIE_INT_UNMASK_OFF 0x1910 @@ -361,7 +352,7 @@ static int mvebu_pcie_child_rd_conf(struct pci_bus *bus, u32 devfn, int where, conf_data = port->base + PCIE_CONF_DATA_OFF; - mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), + mvebu_writel(port, pci_conf1_ext_addr(bus->number, devfn, where, true), PCIE_CONF_ADDR_OFF); switch (size) { @@ -397,7 +388,7 @@ static int mvebu_pcie_child_wr_conf(struct pci_bus *bus, u32 devfn, conf_data = port->base + PCIE_CONF_DATA_OFF; - mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), + mvebu_writel(port, pci_conf1_ext_addr(bus->number, devfn, where, true), PCIE_CONF_ADDR_OFF); switch (size) {