From patchwork Tue Apr 30 01:20:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13647932 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E8BB5C4345F for ; Tue, 30 Apr 2024 01:20:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2lWlRepK4HGCvEqVeX9UzcZGzOxTxvWgI8uefy+nPl4=; b=B9Noxe9UhtRGl+ YyBNDz7su6jvOVVJVjRJ7Dn77BkjOlD+Za/Yr3UI+95FY0I9jxVscqLOQN6S1ZxJ9WeeXaOZl28g+ JXi8n51zFKIxe8J7SNugHXIqA8SH5IIQ2yzgAWmEZVPFmK/HpUotJmK1gWHsm5HkW/h3gFdm3p8xD WnulaDC9ZHeoi1YyhUedhxaxzxrR8wmby5A9s7ejsJIKS4iys8MySb9AV4ion8nQoe70Hrx08ynLs 1pOTnX5pRSG7iluIFZrERsa8yzmf/yZUAhyYq3o+kM1ljQo/rLYrCT20aX3muoqAiDH2tvg0pRNgA po09AqGld0fwNLHmHW+w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s1cAM-00000004f6s-1kXH; Tue, 30 Apr 2024 01:20:18 +0000 Received: from mail-lf1-x136.google.com ([2a00:1450:4864:20::136]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s1cAI-00000004f5a-1Emj for linux-arm-kernel@lists.infradead.org; Tue, 30 Apr 2024 01:20:15 +0000 Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-5196c755e82so6277475e87.0 for ; Mon, 29 Apr 2024 18:20:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714440011; x=1715044811; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=5dsfoDrDqhFi2M0qRhXB0Rpx7fbnSThvVod9k+rsj1w=; b=jqF5o5dEvPd49J3umIKuPu2R19VzwTjMjHMHc0oPrEvcQF9JUPZz+f5O70X+UAc04o sTNLk3HJ5BefjbMOcqAJ7bVy7KAS6jFs8pal63jJuJTGqb2kZLVc/2B68BBqbo+vnNk7 YpKl1i+CesFFhrxjFz4VT/H/buPMRyS+zFJKz+axn7HFo7LFnVLnlo+ZkL/pUmG4FxFH uWepNvtD9k8gVnaNyXiVDdVHtHO9t/acbcsatuabDFUGYd7+YqNyF+Ie43raRDLWmuij 4a2gQEguhBOyb2o0F7F2YPqfOMMvFaXr0n/4VQXUyTHmspOembTt0EohJYLi22jSaFSc Jdgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714440011; x=1715044811; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5dsfoDrDqhFi2M0qRhXB0Rpx7fbnSThvVod9k+rsj1w=; b=o33X2ySiGNmchEYa59S3Iftpu+ZRsHRYJ4sCHkvq9i/5tEKCsHIS8yzWh4Lfq+N0xh c5MM+pvDbt0vSVep82SM4cMLd5Crr6P/+rjheopf1TmPHlXs8mDuUaK2Z1iA+OHckOkk iDCV7/5PQqxqexC7bXyjHnHxjBaJxoBGPKktu0x6jWPq1JICK1HvHe0Em30pE3dghwoY i+cS8a6cK71nkfSJ3EW4dnyc8oqPLrFkdswKft1ssfUDwsL0CctM7gWGxhWx2fz6zguf 1B2o7tTac9oQc8J36909XAQcBRoIx06+w/H8njaAhIDSO/Jm7NyLsARu1KE3ZNTi4Vrj F5vA== X-Gm-Message-State: AOJu0Yx693nrxHigVe4JGSGX0+3GAXm4f36jJ2MrUR5P49+ATi49Qj/o xy2v/HIXiv/Plbvolawe/3lsRzj9Lq50UglBkSrJjnRQEFDyQL3KFlc/3Y2SIPf/8uCk684Tn03 F X-Google-Smtp-Source: AGHT+IE79pdb3H2E5Nq28zFBUGJK9MOIsMcVZQXlavIWFjq+RNrNoGOlCeHKSWbpCQGMq8i/ELvcoA== X-Received: by 2002:ac2:58ca:0:b0:518:e69b:25a2 with SMTP id u10-20020ac258ca000000b00518e69b25a2mr6947187lfo.45.1714440011192; Mon, 29 Apr 2024 18:20:11 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 17-20020ac24851000000b00518a01fdf2asm4322096lfy.144.2024.04.29.18.20.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Apr 2024 18:20:10 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 30 Apr 2024 04:20:08 +0300 Subject: [PATCH RESEND 1/2] ARM: add CLIDR accessor functions MIME-Version: 1.0 Message-Id: <20240430-armv7-cacheinfo-v1-1-e3d1caa40dc5@linaro.org> References: <20240430-armv7-cacheinfo-v1-0-e3d1caa40dc5@linaro.org> In-Reply-To: <20240430-armv7-cacheinfo-v1-0-e3d1caa40dc5@linaro.org> To: Russell King Cc: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1067; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=t8WE1+fA8j81+AJkUCcorxLRWwscCfXSF46thI/6wwA=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmMEdIjLCQZ2SQ2cybmALKMcsD4fzlk7p9Q2Qnf h7P8hLmmG6JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZjBHSAAKCRCLPIo+Aiko 1T0RB/wLwtHcsFKJHNF9r3i5xCA+7YDktL+lV1oTMWZBkAzXladfQXnaEabnTx/+0ZJct/rd/xr D82d2k0Ng/bxq2S+7ygkiCaqhM0Q9Z2CIl//L3Hlp0BGD7DD/8C/O96biCJKW9Br+Th/AL2yZYG cTb/V9HFpJ0N5WFgCGHHMVdZL6jbsxw+mJdoH0dx2gTMNDvla5Mmt8LRmwMoiCKEdHpcw1cadYS OVV+jgwvjrRozZebtOBPIZT1fFswWr/HMZqqUURXNueynlLSzFPKdfyE4u1jtA5mG6ZGt6u+EKy you5CNpc7ZbXiALAgaNnQvVBsy22O8svkz46TosSsyLJxFI7 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240429_182014_431276_72C1476F X-CRM114-Status: GOOD ( 10.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add functions to read the CLIDR, Cache Level ID Register. Signed-off-by: Dmitry Baryshkov --- arch/arm/include/asm/cachetype.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h index e8c30430be33..90203a6d7270 100644 --- a/arch/arm/include/asm/cachetype.h +++ b/arch/arm/include/asm/cachetype.h @@ -81,6 +81,14 @@ static inline unsigned int read_ccsidr(void) asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val)); return val; } + +static inline unsigned int read_clidr(void) +{ + unsigned int val; + + asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (val)); + return val; +} #else /* CONFIG_CPU_V7M */ #include #include "asm/v7m.h" @@ -94,6 +102,11 @@ static inline unsigned int read_ccsidr(void) { return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR); } + +static inline unsigned int read_clidr(void) +{ + return readl(BASEADDR_V7M_SCB + V7M_SCB_CLIDR); +} #endif #endif From patchwork Tue Apr 30 01:20:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13647933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82255C4345F for ; Tue, 30 Apr 2024 01:20:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Y4NQvbb+dyupmIOa663OatpdbfcOKL2fx2704DLT55o=; b=g7Qzq6L6FNnlmQ Id4LJGQ1drFWttJpPhSBmoUE9o4wjG7S7OqbyruAvPBXJHPlcOF2dCZeGTbmqoy6hA+MlywQw5bO7 XLkjQHBmbyJKUHLPSP3AKcPw41H/Holmm6V+R5AWPX6R9edy0YnMe5XgJc03k2NCVdNh90e0rQovz +9JMmd2m5i5NdOqKxTUpFbViNP4Q4GLK9SiiqArsAYbmEvr+UTUGCA26KA1W0wKltQIjvRgEatMP+ pxr9QCE/ZZpuliQnT4+ij/ytpZiXA4GQTJFBfCBLIXIShqMT0pkuQ1Putj7TczFF2P52Mn2P9EYQ5 Filn6LVnpL+C/qmRqeBQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s1cAc-00000004fA9-26hX; Tue, 30 Apr 2024 01:20:34 +0000 Received: from mail-lf1-x129.google.com ([2a00:1450:4864:20::129]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s1cAJ-00000004f5g-0Y89 for linux-arm-kernel@lists.infradead.org; Tue, 30 Apr 2024 01:20:17 +0000 Received: by mail-lf1-x129.google.com with SMTP id 2adb3069b0e04-5171a529224so6508290e87.0 for ; Mon, 29 Apr 2024 18:20:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714440012; x=1715044812; darn=lists.infradead.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=AycSOZZElt80+nGkUPVSHZn5jQIyWVlzHRqHfSaFet8=; b=wMf9mY02mAFuKUlCpf3EaGHTTY8rHaTMcEto19oO62P4mHDLTJurRXc31BhRmQNUFx A1WzTTHVHIf6omfcPijT/zuKA0LxNG7/YKlAkjq8d6gyhLoCYnH187xtVFJ89Z/WfRiW ewh72wFa1eVb/MdcUHhTnDXYyYa011wxfjHb2yL9ogIOGz2/lS3pV15mK+R6DlvW46Gx 5Ur8QmiNE35vZIhFV8DWAMAbW8Z1FXdN8ZOBEzNqM5pCe4B3kTBlw4oNb2s16u7xuea6 0ASc+XQ4FIop4V5Nq529IYueocYzAQfI2+1Cq+bPD/uwjjpR854/MFEydztesPUEQBig jc/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714440012; x=1715044812; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AycSOZZElt80+nGkUPVSHZn5jQIyWVlzHRqHfSaFet8=; b=FwqIkM2DWXT6Ueu+BSawDfjQXbbkTxz8oMbMw8aQXn5GfRcBfQwQpXQJQH99l/xYhq B1dDEWCFoSd9nCsnC546MCgTb+jw8ZEtBhvGJ2GdNM9idHW59K/oObbMr6ZRdW+t/O54 L/kjSxcUctg5x0XKi/7oEe3kA4kE6tixAQNAwdSG/OzRx+NboOC9JsOs/dizte7JXTo9 hWnsVumUemztOGxDF876F5JF6WDeacJHpLqXb62A4OPT5WwFgqGXott0pmj3Vl4ZpXvv xClq2rihfWJUykaFqjhNTS6mgJMJkoQIB9luxlKzrhUNSKsR6lUjhyeIeCYLJj6osoW6 /b2A== X-Gm-Message-State: AOJu0Yz8yHQTMunY1Be1CCH0u8Zu2jFtcePQCKDF1Uh+Ka+hZxAfk0gU 3yOYe6HlzbiTClCs50f7zH4PFJ1XwPj+NyIgqt6FU8s4UDIx4XUnMYX6gCZd5ls= X-Google-Smtp-Source: AGHT+IH9bw0AMe3tVZIP6KbsbA10hOX2fQYYdQMg4pnIA2cGEpgy22EyGZUR34+wH/R4MrrPQYpPTQ== X-Received: by 2002:a19:f012:0:b0:51b:812:3c87 with SMTP id p18-20020a19f012000000b0051b08123c87mr739495lfc.39.1714440012223; Mon, 29 Apr 2024 18:20:12 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 17-20020ac24851000000b00518a01fdf2asm4322096lfy.144.2024.04.29.18.20.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Apr 2024 18:20:11 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 30 Apr 2024 04:20:09 +0300 Subject: [PATCH RESEND 2/2] ARM: implement cacheinfo support MIME-Version: 1.0 Message-Id: <20240430-armv7-cacheinfo-v1-2-e3d1caa40dc5@linaro.org> References: <20240430-armv7-cacheinfo-v1-0-e3d1caa40dc5@linaro.org> In-Reply-To: <20240430-armv7-cacheinfo-v1-0-e3d1caa40dc5@linaro.org> To: Russell King Cc: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6946; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=znYqH4KKX5PqF5T6XnwgCw2bHRlbEzXsyiPDt8vHcKg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmMEdJPa805beDVCb+SR4kkUFPhY4N7PufjDHcl gi8C/JiOauJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZjBHSQAKCRCLPIo+Aiko 1aJ/CACL6dYBYXdPvWD+XfE439szkIN7PDF/VmnfHkkxYAZKavrxW+CnLiXReqpzfJVSP8GYmXa jzDjkaX4aeOWjV5ue++RdidHfok/Tof4cIg29mgQVeJ7NwgoO5+6951oGirSzihPkIxb+iMmX69 RlxxBsYm7oBXXsIk8lYOzyUpDp94mAjyBn7RRbg6fFaJJ3jdhrPG9trSyyUTRnKJtIyZ/gHiddU Yn8v59kDFOiMKtDP3xXlJi7jg++sYvtdvlIf3Kq7s5+I2F5GLlPiZyYpW97uz0xi3XlvFyz83ra 9Xtvmh9Ix5NYTrGscyUO5kF4at2BvaeNLtsqmOYpE3KGih5c X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240429_182015_214580_169BC0A6 X-CRM114-Status: GOOD ( 22.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On ARMv7 / v7m machines read CTR and CLIDR registers to provide information regarding the cache topology. Earlier machines should describe full cache topology in the device tree. Note, this follows the ARM64 cacheinfo support and provides only minimal support required to bootstrap cache info. All useful properties should be decribed in Device Tree. Signed-off-by: Dmitry Baryshkov --- arch/arm/Kconfig | 1 + arch/arm/include/asm/cache.h | 6 ++ arch/arm/kernel/Makefile | 1 + arch/arm/kernel/cacheinfo.c | 164 +++++++++++++++++++++++++++++++++++++++++++ include/linux/cacheinfo.h | 2 +- 5 files changed, 173 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8f47d6762ea4..cb293ddae6bb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -5,6 +5,7 @@ config ARM select ARCH_32BIT_OFF_T select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND select ARCH_HAS_BINFMT_FLAT + select ARCH_HAS_CACHE_LINE_SIZE if OF select ARCH_HAS_CPU_FINALIZE_INIT if MMU select ARCH_HAS_CURRENT_STACK_POINTER select ARCH_HAS_DEBUG_VIRTUAL if MMU diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index e3ea34558ada..ecbc100d22a5 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -26,4 +26,10 @@ #define __read_mostly __section(".data..read_mostly") +#ifndef __ASSEMBLY__ +#ifdef CONFIG_ARCH_HAS_CACHE_LINE_SIZE +int cache_line_size(void); +#endif +#endif + #endif diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 771264d4726a..b39c38ee9fdb 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -40,6 +40,7 @@ obj-y += entry-armv.o endif obj-$(CONFIG_MMU) += bugs.o +obj-$(CONFIG_OF) += cacheinfo.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ISA_DMA_API) += dma.o obj-$(CONFIG_FIQ) += fiq.o fiqasm.o diff --git a/arch/arm/kernel/cacheinfo.c b/arch/arm/kernel/cacheinfo.c new file mode 100644 index 000000000000..878ff4d10139 --- /dev/null +++ b/arch/arm/kernel/cacheinfo.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * ARM cacheinfo support + * + * Copyright (C) 2023 Linaro Ltd. + * Copyright (C) 2015 ARM Ltd. + * All Rights Reserved + */ + +#include +#include +#include + +#include +#include +#include + +/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */ +#define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1)) +#define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level)) +#define CLIDR_CTYPE(clidr, level) \ + (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) + +#define MAX_CACHE_LEVEL 7 /* Max 7 level supported */ + +#define CTR_FORMAT_MASK GENMASK(27, 24) +#define CTR_CWG_MASK GENMASK(27, 24) +#define CTR_DSIZE_LEN_MASK GENMASK(13, 12) +#define CTR_ISIZE_LEN_MASK GENMASK(1, 0) + +/* Also valid for v7m */ +static inline int cache_line_size_cp15(void) +{ + u32 ctr = read_cpuid_cachetype(); + u32 format = FIELD_GET(CTR_FORMAT_MASK, ctr); + + if (format == 4) { + u32 cwg = FIELD_GET(CTR_CWG_MASK, ctr); + + return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; + } else if (WARN_ON_ONCE(format != 0)) { + return ARCH_DMA_MINALIGN; + } + + return 8 << max(FIELD_GET(CTR_ISIZE_LEN_MASK, ctr), + FIELD_GET(CTR_DSIZE_LEN_MASK, ctr)); +} + +int cache_line_size(void) +{ + if (coherency_max_size != 0) + return coherency_max_size; + + /* CP15 is optional / implementation defined before ARMv6 */ + if (cpu_architecture() < CPU_ARCH_ARMv6) + return ARCH_DMA_MINALIGN; + + return cache_line_size_cp15(); +} +EXPORT_SYMBOL_GPL(cache_line_size); + +static inline enum cache_type get_cache_type(int level) +{ + u32 clidr; + + if (level > MAX_CACHE_LEVEL) + return CACHE_TYPE_NOCACHE; + + clidr = read_clidr(); + + return CLIDR_CTYPE(clidr, level); +} + +static void ci_leaf_init(struct cacheinfo *this_leaf, + enum cache_type type, unsigned int level) +{ + this_leaf->level = level; + this_leaf->type = type; +} + +static int detect_cache_level(unsigned int *level_p, unsigned int *leaves_p) +{ + unsigned int ctype, level, leaves; + + /* CLIDR is not present before ARMv7/v7m */ + if (cpu_architecture() < CPU_ARCH_ARMv7) + return -EOPNOTSUPP; + + for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) { + ctype = get_cache_type(level); + if (ctype == CACHE_TYPE_NOCACHE) { + level--; + break; + } + /* Separate instruction and data caches */ + leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1; + } + + *level_p = level; + *leaves_p = leaves; + + return 0; +} + +int early_cache_level(unsigned int cpu) +{ + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); + + return detect_cache_level(&this_cpu_ci->num_levels, &this_cpu_ci->num_leaves); +} + +int init_cache_level(unsigned int cpu) +{ + unsigned int level, leaves; + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); + int fw_level; + int ret; + + ret = detect_cache_level(&level, &leaves); + if (ret) + return ret; + + fw_level = of_find_last_cache_level(cpu); + + if (level < fw_level) { + /* + * some external caches not specified in CLIDR_EL1 + * the information may be available in the device tree + * only unified external caches are considered here + */ + leaves += (fw_level - level); + level = fw_level; + } + + this_cpu_ci->num_levels = level; + this_cpu_ci->num_leaves = leaves; + return 0; +} + +int populate_cache_leaves(unsigned int cpu) +{ + unsigned int level, idx; + enum cache_type type; + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); + struct cacheinfo *this_leaf = this_cpu_ci->info_list; + unsigned int arch = cpu_architecture(); + + /* CLIDR is not present before ARMv7/v7m */ + if (arch < CPU_ARCH_ARMv7) + return -EOPNOTSUPP; + + for (idx = 0, level = 1; level <= this_cpu_ci->num_levels && + idx < this_cpu_ci->num_leaves; idx++, level++) { + type = get_cache_type(level); + if (type == CACHE_TYPE_SEPARATE) { + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); + } else { + ci_leaf_init(this_leaf++, type, level); + } + } + + return 0; +} diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h index d504eb4b49ab..cb1222b8bbc8 100644 --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -132,7 +132,7 @@ static inline int get_cpu_cacheinfo_id(int cpu, int level) return -1; } -#ifdef CONFIG_ARM64 +#if defined(CONFIG_ARM64) || defined(CONFIG_ARM) #define use_arch_cache_info() (true) #else #define use_arch_cache_info() (false)