From patchwork Tue Apr 30 01:38:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nas Chung X-Patchwork-Id: 13647941 Received: from SEVP216CU002.outbound.protection.outlook.com (mail-koreacentralazon11022018.outbound.protection.outlook.com [52.101.154.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F4E41113; Tue, 30 Apr 2024 01:39:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.154.18 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714441156; cv=fail; b=pTznKfy4kzjfycAEujvINHXEaUrvc9Q0LCFyqMXTcLcpYnuGNXcicv56DTX22EpxtfwZOldNLI5MSEtckZv3hbJM7zA5nkRFS9PN0w95iNMDg86rpbwEaMRUrpM30x5QIY/hhiGzv8qxekjvEaWgGrye8X3OrKiFUYqtkWBHOAQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714441156; c=relaxed/simple; bh=lrEi0r97o8Y/xoHGwh+4ip2R0DIFHkyP/JQtkN8aDZQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=oNCy0vqPvi5ttKTHjt5tVefuMphKROSdegV6W32K909MAvrSuqlX1G+qEjsGfO1xdEwcgOkLRHXZSbr/8C7RZJtCOBdbDoFgWbdy0ZjVKH5XkWTT7/rtPen9R9Z4UxehoOIdAUvEZ8nozvzyvqetqxRwun/cGsykO5xCX8O/Qe8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chipsnmedia.com; spf=pass smtp.mailfrom=chipsnmedia.com; dkim=pass (1024-bit key) header.d=chipsnmedia.com header.i=@chipsnmedia.com header.b=hHw44X+4; arc=fail smtp.client-ip=52.101.154.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chipsnmedia.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chipsnmedia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chipsnmedia.com header.i=@chipsnmedia.com header.b="hHw44X+4" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=DX18LGSuCc1P2/kW9q65V7iqpqGEJK2x7m7uG6YFyReUJoBIkqvRTYN6iNzM82y/ZtXRqUg8GhVe9Ok1HK8HJV6NGwINC3ulwoBAIbVYgHBUf5T4v3fbxPLJ0UBdm1ZZ4sForZOgQ0pmdv5Sbi/tNqPFnixFUU9UrVrOYBrtBAa5xuB7VSziDI1luzyTbFMhEexEvGGFZRWSZeLGa75i/13TK7qsSacfCq9fyJ0yEUXchoDlAWhVQT0cyG1ZcmDEJ08LHluvyjQHQ+pgH2kiHoFnv+SGcOy4PXQx6xB7xrWhGiPpLaQnFCtPC1lVibx0abwx3gC5JC0xAmXlRJznUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vACLLSZhrmTQO90kzFV39ILswOgXNXFuEX/8TwheFwc=; b=HfTkeQ+FN05/jUgp8h05HGaojmVkpim542nNuF/4CAp/uKukhe3mRIBjoCztqEW8wvw4N2jBrQKy50S2ldjsRWgqDMzcT3bU6v2IiVf6K6cV5Y+U8z0Xr3kWA7mthiqwI/8WhmzvnYIkCsou6QsJ7Kl6rxCALUm/9dIlI2GzzU2XgHnT2zIeM8c8/9p/CWKvw33lZBhwLlUcpsvp8DU+dxSr/teGVclC3kNB7fjg2Ew3wkhxaeQoLwJKWKOHa9htyx6DdxHtEIeDaDVchIbHX0j5Mw1CopZGkcrgUB9Gks4s3Zk/Kt/V+JfrkgWzOxQApqJe0bCxWn08IOoek5IbDA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=chipsnmedia.com; dmarc=pass action=none header.from=chipsnmedia.com; dkim=pass header.d=chipsnmedia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chipsnmedia.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vACLLSZhrmTQO90kzFV39ILswOgXNXFuEX/8TwheFwc=; b=hHw44X+4RhrzfsNCQqGw+UwZBkuB/ho+1WCznhyzYZTrpiGm7Sk4F1TZFkWrHxJpAN7wP5qVv+fXi4Ep+7lp59CV0Ib4zA7QNONijMmN3L1TuVMwatF7pN2y15b/20lF2/QqyzbdcsnD3X2/OSVWVblfnd93r83kCgqXcR+/9Hk= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=chipsnmedia.com; Received: from SL2P216MB1246.KORP216.PROD.OUTLOOK.COM (2603:1096:101:a::9) by SL2P216MB2195.KORP216.PROD.OUTLOOK.COM (2603:1096:101:150::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.36; Tue, 30 Apr 2024 01:39:10 +0000 Received: from SL2P216MB1246.KORP216.PROD.OUTLOOK.COM ([fe80::5b8:35f1:821f:4f57]) by SL2P216MB1246.KORP216.PROD.OUTLOOK.COM ([fe80::5b8:35f1:821f:4f57%2]) with mapi id 15.20.7519.035; Tue, 30 Apr 2024 01:39:10 +0000 From: Nas Chung To: mchehab@kernel.org, nicolas@ndufresne.ca, sebastian.fricke@collabora.com Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, hverkuil@xs4all.nl, nas.chung@chipsnmedia.com, lafley.kim@chipsnmedia.com, b-brnich@ti.com, jackson.lee@chipnsmedia.com, "Jackson.lee" Subject: [PATCH v3 1/4] media: chips-media: wave5: Support SPS/PPS generation for each IDR Date: Tue, 30 Apr 2024 10:38:57 +0900 Message-Id: <20240430013900.187-2-nas.chung@chipsnmedia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240430013900.187-1-nas.chung@chipsnmedia.com> References: <20240430013900.187-1-nas.chung@chipsnmedia.com> X-ClientProxiedBy: SL2P216CA0211.KORP216.PROD.OUTLOOK.COM (2603:1096:101:19::19) To SL2P216MB1246.KORP216.PROD.OUTLOOK.COM (2603:1096:101:a::9) Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SL2P216MB1246:EE_|SL2P216MB2195:EE_ X-MS-Office365-Filtering-Correlation-Id: ade7885d-d6f2-4338-9178-08dc68b654ef X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|52116005|376005|366007|38350700005; X-Microsoft-Antispam-Message-Info: xQ02mcOYx9F2P5ujU+ZG79tXgF3v3XKSHbVmkiNpD79eIPUChcalxDTOqADo5P9nSeCAZD1ZlfpPqPIkrgKOid0N91cJTm0ED6Hh88IPmyy3yBwvxOow+cmmZc19T1MEXm7DMTAFeikXi14uGmNtk7DXwZTi2fQGrnBQV6sZoL+MsVU7rTqYMEfBClFIG8IIqMgSv0LzWKxlT0MlIaTu0IlqoPW2cFsflQAfYLub7xgp0/FqVot+Et75HxhWuNmLp4WWp/uNHnoUvE/dE6L7hvKINHVrb5rJoOrU73ZM+OIMFCX//D/YRjnuOScUn51K9Sn7cHCT+jo14260Tc0/1CpfXrXAFmDqbpNSMOlXorUe+FRwrGBr4kO1b7a+mS0OxOTpbIv7d1sHDzJkCcE97uetDKmVxH00O1rQlGh/yFbx9H/tV2FPbeXH4xAI8+wLL6xoNsV19Fa4MZtMK0QGqa9vPK+iAK5ZIcxhXA1jIpQCtsHESYB138806NyTQUlcCDtgOzJeK/ruDpyxi2VCR1eW3majeKgQQwzDv6sA+Yvlx/jETGbMaCV9Ajr8nVQMnmfL5Uzqd2yatrF7f3dIxpaKkhERpTXkabXGXor01F6K3S2MCCqDQdSyiOv36EPfXviZroyYhzS1q8aTfOUcpirDvgnMnURPqUlrorvTKXFmTJh9IQXHo6wAII3CENAOVF+I64SWdH02wGY6Hokw+R9aAT12wGztQhjvbTt3ZWEgi78OSUGvN9p+sQ3c8rlUiMerYhsDnrtiTanUrOhZuSYpIWP05vMb3raaxQ9zPDazUoUdzdfb6OLTXLJvn359X3O7FPPMmVvaeStt7oThmmAbulaYKqD3hV2J3EuvsxbsezUmjTG4Zh7DXyW3CkV2XRpU4ul6QXA335q+3CUbmifEWj/PBwBjXQiN4PKULnqyCwmD96d5evFZn/rS1zm8F4Q2b2ENFBbbPOSGy/wkcphkYx5x6IMWuaafhxK5DY18V0sNhhsplbHSs7pl6Vf7C88wHNbhoe+SwI8+4IUtFfXaDtbT+tRqZcKPTed2u6VbxA42YvjFNh2yC4Piq56u3T3AZHCA0T2qG/i9wLBWeqYRBR03Qv8itWoShVOgm6HCJArUFQRff4YOmhNZQb4S1CJJN9CpqIaWAnbARC6CFT54titmgBADsZ6+hE5FATXzBypA4kfs8YNjGbXmbIZs30T0POr+tX8Ki9ZfNnXxlaVV6gvuD9bVEYfslDGjkWukkUj/j8QLBIfbQcTWVzIX2ovI9UxAp+dBV6Ru+f3SUG7Zbv19HFoMRz95vgoDzQWHcMkitcNPeMOUM1rRt+oAbg5AfNH0EeI1dzHM2DC7TQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SL2P216MB1246.KORP216.PROD.OUTLOOK.COM;PTR:;CAT:NONE;SFS:(13230031)(1800799015)(52116005)(376005)(366007)(38350700005);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: iok2cVKdBhK8QsU1++joBvr19Pnr6n+/R9+SOMFHTF3sw6eIORboQQIQ9f3JK34K6q3KgJ/+6V9Et2hOOwjr+7Ada5jvc/x4+O9W7YA0przXcsc/KyOo4jxevEt3/0RpNxOkUc2KNgQcfUCHNIQf1Jo6JSQbLamLmo/GqoRAlRUxC8kE6KgDOGu0mKaTiDcd9X0Ol0WtXDYLE0riGy4t38g4eHZf064bQqe86o51peJdxEzw02uLmJS+PWjTTkqDPtU0+SMe0CpWyerQtLcM8b4FwsDy5CTTyWE4YM/qWrPi6hSC462tdOqgHwuwW3kWl835kvpwqSCJTZy/A99pvn2i6IEloAGs+V7xUPdSPHaprAAaN2XAO7fKvxyzj32UC8ZG5Wx5ZKK0xApDBPNcrWCOiEOqmDNdZSibGuu5gN/H3Atg/gr48p5JjrbrFM2tzLmVRDH9EXEN5Jr7USWrCC+9VOgdTdnMISqEp9d+dLK8Oj8ZaobG0dF5bVwppM7uwPzwEd5lidVzifpKvyaJ3Dck/Og3ZClY+0ywcus4TZ20vA8lYPqklSU3ecIe2LrPFNFVsalN7w0rQUHUBxXM855MpkKCXVhqxzCEbP0hpNrT5weGRmSg0oJhGTrIHZeWOxCFqxx5QpwNYus2CgyDA/YTGiUxeKfow4aqoc7SZRTlxQscmyCbKlhax1iZlS83uOihWY4u7eyueWXGUrLjjT4CoJFEig/wxeA+KKRl2EqYako9ftNU4JKGAaGoggCOj/RQeserXcTP18acxpvtPhOXlxJeWZ6G/o04IJqcwhIMfHIBAF6aFOJJFavDBe4RRsEC7Guq/V2euhk3QexQA4Rf1TTvbtg6yi/y6HEmeavuW4DOYTg+Ja7t8kydoX9xdHQwj4KwBImR/ojBLGzjqXLIS+SM9njEzkXKAI/k0+RPxAqc7wR777dTZcoapBEb8Ikwk6TnIvFUhKtA9KVBu2mkwB4MJ3TSuJMznVxYFYm4gTQG2L71VoiVaRtnQhOFzM81MsAWYCVv5eQgnd4P3VXHTcYiK1p77LbEtAACm41r3rEOSCBv1YCl53FsfgE4xaLm8r41DMFGvKge/r+Qynh2bP7Mdz5ut4omBFWTmpNgoH7gxsoaZON751Tpw+m34BNEzkZZX7uZ7PJfg8CgUSgIxbF+V9ZG1KB5UnJVxl17u7UN6ZdgTJ4AoDu5Xg64qsGL7ZDu2zJT6HtTTXaGVJOJNg01Q6K6dgePcpe7hsd2rAW4qX17GS40TiCylg9ZwbIdOu6pn14ZqK+kqFJzbSvLwWNOY4Q+Jpxc2MgFdoiLkt4bj/BGoJMs5QhjUX4Bzgu3pIaYQMwsO2yLAPTG7XM6upyUaTtprBJTnfZfJAOXDFISj0N+6oIEJzAdTCff0gSOhJG3Pii8T1Hie7EEgd2ZAqjbzl0VDVDGtVI5d3S4MsrDWVMsnLJ3z7UsEqI9R0G/cy6qjbSB3L+TdIJuCJlRP6OtSAqCrOX29/2T1ahZbsPrNr9Qaic5Zebkm29+FAlj7sl4GfXHZe3qU/mUI7dJ9WXxMr9pOHzcYSVRvV2vLzZDvskCPDrUSJb8XJsaV1fHqrCtZWGUUvbeQIrhsw== X-OriginatorOrg: chipsnmedia.com X-MS-Exchange-CrossTenant-Network-Message-Id: ade7885d-d6f2-4338-9178-08dc68b654ef X-MS-Exchange-CrossTenant-AuthSource: SL2P216MB1246.KORP216.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2024 01:39:09.9531 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4d70c8e9-142b-4389-b7f2-fa8a3c68c467 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: slShTY3Qkt0MTk6lFdd9BsIJL48p4MlLuvDVIwXqCbUAOzsUqLdW8EzntozaULnpA96JoyUagIjSei+SpGewu09RtKN+GuOhMkSEjR50Gqk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SL2P216MB2195 From: "Jackson.lee" Provide a control to toggle (0 = off / 1 = on), whether the SPS and PPS are generated for every IDR. Signed-off-by: Jackson.lee Signed-off-by: Nas Chung Reviewed-by: Nicolas Dufresne --- .../platform/chips-media/wave5/wave5-hw.c | 19 +++++++++++++++---- .../chips-media/wave5/wave5-vpu-enc.c | 7 +++++++ .../platform/chips-media/wave5/wave5-vpuapi.h | 1 + 3 files changed, 23 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c index 2d82791f575e..fff6e66b66e4 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-hw.c +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c @@ -23,6 +23,15 @@ #define FEATURE_AVC_ENCODER BIT(1) #define FEATURE_HEVC_ENCODER BIT(0) +#define ENC_AVC_INTRA_IDR_PARAM_MASK 0x7ff +#define ENC_AVC_INTRA_PERIOD_SHIFT 6 +#define ENC_AVC_IDR_PERIOD_SHIFT 17 +#define ENC_AVC_FORCED_IDR_HEADER_SHIFT 28 + +#define ENC_HEVC_INTRA_QP_SHIFT 3 +#define ENC_HEVC_FORCED_IDR_HEADER_SHIFT 9 +#define ENC_HEVC_INTRA_PERIOD_SHIFT 16 + /* Decoder support fields */ #define FEATURE_AVC_DECODER BIT(3) #define FEATURE_HEVC_DECODER BIT(2) @@ -1601,12 +1610,14 @@ int wave5_vpu_enc_init_seq(struct vpu_instance *inst) if (inst->std == W_AVC_ENC) vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->intra_qp | - ((p_param->intra_period & 0x7ff) << 6) | - ((p_param->avc_idr_period & 0x7ff) << 17)); + ((p_param->intra_period & ENC_AVC_INTRA_IDR_PARAM_MASK) << ENC_AVC_INTRA_PERIOD_SHIFT) | + ((p_param->avc_idr_period & ENC_AVC_INTRA_IDR_PARAM_MASK) << ENC_AVC_IDR_PERIOD_SHIFT) | + (p_param->forced_idr_header_enable << ENC_AVC_FORCED_IDR_HEADER_SHIFT)); else if (inst->std == W_HEVC_ENC) vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, - p_param->decoding_refresh_type | (p_param->intra_qp << 3) | - (p_param->intra_period << 16)); + p_param->decoding_refresh_type | (p_param->intra_qp << ENC_HEVC_INTRA_QP_SHIFT) | + (p_param->forced_idr_header_enable << ENC_HEVC_FORCED_IDR_HEADER_SHIFT) | + (p_param->intra_period << ENC_HEVC_INTRA_PERIOD_SHIFT)); reg_val = (p_param->rdo_skip << 2) | (p_param->lambda_scaling_enable << 3) | diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c index a45a2f699000..a23908011a39 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c @@ -1061,6 +1061,9 @@ static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE: inst->enc_param.entropy_coding_mode = ctrl->val; break; + case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: + inst->enc_param.forced_idr_header_enable = ctrl->val; + break; case V4L2_CID_MIN_BUFFERS_FOR_OUTPUT: break; default: @@ -1219,6 +1222,7 @@ static void wave5_set_enc_openparam(struct enc_open_param *open_param, else open_param->wave_param.intra_refresh_arg = num_ctu_row; } + open_param->wave_param.forced_idr_header_enable = input.forced_idr_header_enable; } static int initialize_sequence(struct vpu_instance *inst) @@ -1701,6 +1705,9 @@ static int wave5_vpu_open_enc(struct file *filp) 0, 1, 1, 0); v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 1); + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR, + 0, 1, 1, 0); if (v4l2_ctrl_hdl->error) { ret = -ENODEV; diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h index edc50450ddb8..554c40b2e002 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h @@ -566,6 +566,7 @@ struct enc_wave_param { u32 lambda_scaling_enable: 1; /* enable lambda scaling using custom GOP */ u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */ u32 mb_level_rc_enable: 1; /* enable MB-level rate control */ + u32 forced_idr_header_enable: 1; /* enable header encoding before IDR frame */ }; struct enc_open_param { From patchwork Tue Apr 30 01:38:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nas Chung X-Patchwork-Id: 13647944 Received: from SEVP216CU002.outbound.protection.outlook.com (mail-koreacentralazon11022018.outbound.protection.outlook.com [52.101.154.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D342BE65; Tue, 30 Apr 2024 01:39:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.154.18 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714441160; cv=fail; b=PxppntSfK+qmxR0OaED7EkaqZWKyoYalJPuIjabkNkF5tulP6pXwbqzJ2H4eK09kE7TUkAlZi1jExxc7RPyBb9y0dcZVW6ZrrXBIuDl/Jg1gbROfgZylvD9R7sTkA9tbxKgzoF4Cux1M1PEwPoGIXHLTceXJ3/13h7fONTPEaRU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714441160; c=relaxed/simple; bh=xZjC5Ab4JmVwWF4Uog4CgivMX3blp6oRo08rwmQXU6Q=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=kGjKc4twyVyiv/eukwqR4GjE3bCxF0lMF2i17ZxnvNexm198/K/4joajylY3JofF8ea+KKMLvzS6I7VwSul5IioTz6J86uexjdoGM3lau3xXhUXZW+ZUpSK5U532/wtHwNug0BBLJZ0NJsPD3yw+2yfO8UDz1vzDampE9lg0xTQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chipsnmedia.com; spf=pass smtp.mailfrom=chipsnmedia.com; dkim=pass (1024-bit key) header.d=chipsnmedia.com header.i=@chipsnmedia.com header.b=A2SGq7AA; arc=fail smtp.client-ip=52.101.154.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chipsnmedia.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chipsnmedia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chipsnmedia.com header.i=@chipsnmedia.com header.b="A2SGq7AA" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ZVIVCDb8+sz51do2PxMHAcEFZ6+sAb23ZMIbIQQKROGBKLj8CM8KAFLvcCfSI5B7Fhm4OqNGgG/KmXg/B2QydzeGljU+Bs867HhErf97bKLp2GcZzZfC0ZKB3Fsvtgam81rA+mCZVSCEUVzQLlEvO7OPFSLYKX5jm5cgSiO+0SRQ0hUn6odyWdWQ+lbXBhqC47dUUacHQQogoQ9CayKzQt02EarxEpIqWgWEXKpb5E03xUZwWKJkhnGfNX6mvMeohSuQbY8gROWy6Me8UaDwh+XW1reWuvLrpWr8LujYnH4a9K7P3vJ2QcOKzh1m/zUzNmmgWsmYZkaL4oD/LGGU0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=TcO/zvPBzs7ZGOQScq+lMlN0ZObPQX4lYy5u7RowwwM=; b=lfyIc4WPVV8xDMLGzb/EVRowjzcA7T2WRHM71UFFwbKy3cVLT6nuCLAhVKfruFJVVnrXZK6B8jD7VE2T++ddBd4p5skOwURKMkO1ctLCrhDk//A/MNY0qJ0LCtjdJ0PupLFenxRxMno0pN/W28Cdhiw24YgWqbnZn0cdU+w+13e+WUymGeHMhbJaRg+kANl+aim3WB/miKSIH8jw20kf2Chb1nReI5nJSAOiJOBwUttHe1jG+8hmBf+BPpVcIgq0kKVeQ7XIemyvMxuH7YaRD6dxEJ76BVIrvLwYJCQ0ZXCG4RV0sDIpu/ag+/GO2oraiu9pSmuGj2A7/z/vs1aJyg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=chipsnmedia.com; dmarc=pass action=none header.from=chipsnmedia.com; dkim=pass header.d=chipsnmedia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chipsnmedia.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TcO/zvPBzs7ZGOQScq+lMlN0ZObPQX4lYy5u7RowwwM=; b=A2SGq7AA9CxqHUjf6gmaBfK1pHueTI8xQN1iZJtjZ20TRupRrAnDYLZDfWUV2vZBh6Mpitqh6XwrUqdVmXk3QovqsdaxI81iROtpogCZsn7lMSKtXqy61iX/n5mCXxeckrOX/9SiQLCKJsY7ahdrpCdeTzIjQTF+K5BHnCP91x0= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=chipsnmedia.com; Received: from SL2P216MB1246.KORP216.PROD.OUTLOOK.COM (2603:1096:101:a::9) by SL2P216MB2195.KORP216.PROD.OUTLOOK.COM (2603:1096:101:150::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.36; Tue, 30 Apr 2024 01:39:10 +0000 Received: from SL2P216MB1246.KORP216.PROD.OUTLOOK.COM ([fe80::5b8:35f1:821f:4f57]) by SL2P216MB1246.KORP216.PROD.OUTLOOK.COM ([fe80::5b8:35f1:821f:4f57%2]) with mapi id 15.20.7519.035; Tue, 30 Apr 2024 01:39:10 +0000 From: Nas Chung To: mchehab@kernel.org, nicolas@ndufresne.ca, sebastian.fricke@collabora.com Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, hverkuil@xs4all.nl, nas.chung@chipsnmedia.com, lafley.kim@chipsnmedia.com, b-brnich@ti.com, jackson.lee@chipnsmedia.com, "Jackson.lee" Subject: [PATCH v3 2/4] media: chips-media: wave5: Support runtime suspend/resume Date: Tue, 30 Apr 2024 10:38:58 +0900 Message-Id: <20240430013900.187-3-nas.chung@chipsnmedia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240430013900.187-1-nas.chung@chipsnmedia.com> References: <20240430013900.187-1-nas.chung@chipsnmedia.com> X-ClientProxiedBy: SL2P216CA0211.KORP216.PROD.OUTLOOK.COM (2603:1096:101:19::19) To SL2P216MB1246.KORP216.PROD.OUTLOOK.COM (2603:1096:101:a::9) Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SL2P216MB1246:EE_|SL2P216MB2195:EE_ X-MS-Office365-Filtering-Correlation-Id: 7f1e57e3-cffa-47a5-9296-08dc68b6552f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|52116005|376005|366007|38350700005; X-Microsoft-Antispam-Message-Info: bG2NKC2cEMykwWWqg29rtdWOFT9OkyQaXC5V/LyLDGHy8V1rTYjAmqzWTy34Z02U0hsv2GaUT8YGCmWxZUwg2Z8Kb5NAK9HJ9bCbr9VP7lhx/IO7+2Lmrg6NFbfV7zt6lry8zKnvCcXBcebfE+lRLBHxzuURrjrJiHHXN2lr/182P+BzziIFbt2TZWWP5smg1oo6Ls+0bm4A2wSakp8LUw0bnUOuPmi0mxlDSnkGDBXKG7w1JVqML4dBwzSuIOwiNvBfe8Rh9lKP0LPNq3QxObMDIUne9liP0cc+XuoXaepMEzxKxpUqeUHins7bYAeo6sq7yNbqSDHcWMSiouWa5nnkk6mJ4TORKO3b77LqztodqKEkeBHfKhU19YP3DnuFad+kyrz71aoIzroJCPB0y2kgxS/5Sv73HuqOusfEjrH1etioWQo9yTuSzsLgnW7nT0kSab+yFXx3IwUpFHloyw+wnnZLpwuaL0msINsZsDCDFKldLT0slrLyUiyP+FFBUm+gwr1hgdA+4znl855hSufpewnjTE2EeHQ9rh4xxLBKzgTDfQK0z2z6j7GVCgViIgIjSYtG/8R1HY1HWuzTO+jUGXIyWQkNwDMY7iT+QMpSK/7Ga1Ji7CSDZqFrNAeKg3Soq8XA1+wSBwTIgG3aI3pi3cfL2E4FcOrONZE/hzjSHlNuHqcdQn0DymRJa5qwtjtulCvC/hXdWJUVRMDpFprAxdiq+w19h61qEOXUdf3BuYptXrB8EJbOwsM7siE1x7nbMGnbA+lyZP0XJiZxIv+04NnwSPP2tV0X7y7b1+5+io9H5G4SmZnIKSLKCg1a0IxK67qfDsLuYlJDjkpBavhqRBTar+5NNh0WsqPQ7Jv1MpGuXRjtWeFEvLoQPx2lvZ9im2HQlWN/Enq99BW+pXJwFytvtg1lDcqRAnEz7YmsLsRkSEZGE0tk8OkFHIjwU1qV8UbN2WmSROQv9OFPaCccbshUKAGW7yKjMaEKa+jAqbE21oXFDvkBjhjOdoRu34yI7ETxdFgjDYU9vIVllwRO3MyUN80wBvzzruxWy/tKLzjq2awwkACZfnr8moTkE/A3vx8s7kZW2FT+6OEfsNtCKxsNI0Y5gSBpxenEEM/Ky2orV6UrGhoSvmYqg4jsA6bhn2uGsv3SxVVQsa+Nl7m3KH+rO6sLpShgUrvesP/MKcISgXDrKtIKfdV1hmuKdNnQbpCCaLC6GdT4AW5lajwvJ42yMMlIp/q4YPMmzHj0B6gL+W0FgwL9tDjLBK2NwFAVbIj6sA7k9CiZna5wZjrKvGFxyi4Vq9hJQJ2ec4eY503iiP8pWNXYLZr3ia+jEtM5Dx9mqWP0Q1O/3wM9kQ== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SL2P216MB1246.KORP216.PROD.OUTLOOK.COM;PTR:;CAT:NONE;SFS:(13230031)(1800799015)(52116005)(376005)(366007)(38350700005);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GaNeQwMZFfXS+Jq+uJDW/nDcSpuO6dNgo8WfsYDs6grRPjFo74A2w882DGgcnR61J8gTmOfRR5U00nPYCvDOjIeN/eCFDuCouOdFCs9Rf1pqD6zh3otHYoF7oIURlajwjjSaGjwST/qdAKfG/TIoOKHE+nGn4y6TccL3LlozgKHkJqfurbYJKiBFjkPs6IyunUO6vx7Hpfstg3+i8xXfkfGFkOWGDm8H52ssuW8QXNQYbn/lsspCQPpVvLXIKjGct+n4loDNFcTlwjMA6DI17MZC47TM5aRur/CwO5WDrTtIk/DP9ut87istPb9REGBbmqyfYzEGPi+lWdQ6AwNSTDx8mTSljzT/yQtZxKWGrf/JjxTQs89JGZH8ks2eyFlptUxLqCDdGRJY6xK8s7D9NP4xM3Q+4S5clHRh/zHuGVGYCO0i7UqA3Wae/w2n2BAI3I4YOaw1+uvDdE3ZgyjBQPTvRohR+tOHeCH2YQVqhlXLJ3fwUwndNQISA71YEqoIqfhCRpo9R+1ULSA/q2U4fQYqNqEehyjzoGZ5EYRmp/RK9vPi5E2vnZ1cE4wbZYTqPIYBrBchMCmEe99UkQXLkeBAdfHkBCZf26Yo/lhXh1WhDZQX+/MRkJ6E4/RxuHbMX4ObJR5HtosSw1HX1c9yR6A4eMwePx9rBgUFTitjb7uuf/QBNoSPu9ILgf5Dmyly/8h07/5C/F6BE+K/eB4ovGUWXL9SjnIyYkvWnMur4FuPeJjw7lMA27TiZruJgVrL7PkDJzsUhWsts75PBCNZHGCyRvl/hQ6lx9XtKaZjTUVGqkPD5T0VBYV+pHMWkiOcd6BdlQ2JrA9DiH91O7v3hLINa4rvNAONovfQKO9wGdT+WQGiUeCk4aD22PMKk30eLQUiObkzUpZocPO7rYMF5IWxeguRh4qllwVc+H0VzXvp8mXhfOde/Qyqm+xBGsO/VVReKFVeHwoLROzflrGypnzaHbDc/c1n25u9YOfekoZV29/HpdXv/p4g2DbQgtMutCS70EXexOQ2fmaYVSv1if87odYBu/U1u6YEcsObORb6obqrPJ3sXgqdStXbwzi6FmYAEo6eplmjxn7aRGQw+U+SiGzyuMCQYA8cdrIIVD1nCKfjZ3Dog/ckiGGxM3DW1OTiwNLpC3qCEnVYcyd5nKIMTLu6ScAEjycOBGxZ6ozY1ykvVdj0Cw2fCr2/QhpDZif9QvVIFS60J/UDrM2b6Du0SozlDY2aya0/7ZzbjpOr1s9Q8CnCxw3MjcLEIkS/ViG8rIMBmYHKYRl+/TKmsJAdxT9S0fjBXLCQaxjFEBUaZ97aD1gkBMdFy4p+NzpQPPYW2HJTnBIWL1iMCDbGA/UPJKBaW5HvH6oua3Bzsh+cJOPOmoLK+lw9CSTtlotgTP6LBTu19w7QAhilTwUAGj9PsD+hhU0LD8YVRKVCamBXz6oYBoswbHeRV+mMZd9/QmKZTFye9YTzAsgMFPQCAYiSflSZv4s49y3VvhWanp2bUhTnWQwCdLBrjxHaqjYs+dpoCsP7yFnsCvfUr88hqG0u1mB2EIgR/iYh8HGRLyfkdfl/mkv4BDUw9sRP+qG2+jz7q9j2KJpn9RXcMolOGA== X-OriginatorOrg: chipsnmedia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7f1e57e3-cffa-47a5-9296-08dc68b6552f X-MS-Exchange-CrossTenant-AuthSource: SL2P216MB1246.KORP216.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2024 01:39:10.3222 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4d70c8e9-142b-4389-b7f2-fa8a3c68c467 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6vkprfPFO6326DNqCtb3Yy/EZzzuCefqMxIvdvKk6aaPXEpKeAs8mzUB0t0aY97uoVsGJtsVXtm82WPQlPfM5RuhLgYTpiblhsWMmlu2Q6U= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SL2P216MB2195 From: "Jackson.lee" Add support for runtime suspend/resume in the encoder and decoder. This is achieved by saving the VPU state and powering it off while the VPU idle. Signed-off-by: Jackson.lee Signed-off-by: Nas Chung Reviewed-by: Nicolas Dufresne --- .../platform/chips-media/wave5/wave5-hw.c | 4 +- .../chips-media/wave5/wave5-vpu-dec.c | 16 ++++++- .../chips-media/wave5/wave5-vpu-enc.c | 15 +++++++ .../platform/chips-media/wave5/wave5-vpu.c | 43 +++++++++++++++++++ .../platform/chips-media/wave5/wave5-vpuapi.c | 14 ++++-- .../media/platform/chips-media/wave5/wave5.h | 3 ++ 6 files changed, 88 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c index fff6e66b66e4..791b1f0e3199 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-hw.c +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c @@ -1084,8 +1084,8 @@ int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size) return setup_wave5_properties(dev); } -static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uint16_t *code, - size_t size) +int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uint16_t *code, + size_t size) { u32 reg_val; struct vpu_buf *common_vb; diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c index c8624c681fa6..861a0664047c 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c @@ -5,6 +5,7 @@ * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ +#include #include "wave5-helper.h" #define VPU_DEC_DEV_NAME "C&M Wave5 VPU decoder" @@ -518,6 +519,8 @@ static void wave5_vpu_dec_finish_decode(struct vpu_instance *inst) if (q_status.report_queue_count == 0 && (q_status.instance_queue_count == 0 || dec_info.sequence_changed)) { dev_dbg(inst->dev->dev, "%s: finishing job.\n", __func__); + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); } } @@ -1382,6 +1385,7 @@ static int wave5_vpu_dec_start_streaming(struct vb2_queue *q, unsigned int count int ret = 0; dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); + pm_runtime_resume_and_get(inst->dev->dev); v4l2_m2m_update_start_streaming_state(m2m_ctx, q); @@ -1425,13 +1429,15 @@ static int wave5_vpu_dec_start_streaming(struct vb2_queue *q, unsigned int count } } } - + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); return ret; free_bitstream_vbuf: wave5_vdi_free_dma_memory(inst->dev, &inst->bitstream_vbuf); return_buffers: wave5_return_bufs(q, VB2_BUF_STATE_QUEUED); + pm_runtime_put_autosuspend(inst->dev->dev); return ret; } @@ -1517,6 +1523,7 @@ static void wave5_vpu_dec_stop_streaming(struct vb2_queue *q) bool check_cmd = TRUE; dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); + pm_runtime_resume_and_get(inst->dev->dev); while (check_cmd) { struct queue_status_info q_status; @@ -1540,6 +1547,9 @@ static void wave5_vpu_dec_stop_streaming(struct vb2_queue *q) streamoff_output(q); else streamoff_capture(q); + + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); } static const struct vb2_ops wave5_vpu_dec_vb2_ops = { @@ -1626,7 +1636,7 @@ static void wave5_vpu_dec_device_run(void *priv) int ret = 0; dev_dbg(inst->dev->dev, "%s: Fill the ring buffer with new bitstream data", __func__); - + pm_runtime_resume_and_get(inst->dev->dev); ret = fill_ringbuffer(inst); if (ret) { dev_warn(inst->dev->dev, "Filling ring buffer failed\n"); @@ -1709,6 +1719,8 @@ static void wave5_vpu_dec_device_run(void *priv) finish_job_and_return: dev_dbg(inst->dev->dev, "%s: leave and finish job", __func__); + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); } diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c index a23908011a39..703fd8d1c7da 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c @@ -5,6 +5,7 @@ * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ +#include #include "wave5-helper.h" #define VPU_ENC_DEV_NAME "C&M Wave5 VPU encoder" @@ -1310,6 +1311,7 @@ static int wave5_vpu_enc_start_streaming(struct vb2_queue *q, unsigned int count struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; int ret = 0; + pm_runtime_resume_and_get(inst->dev->dev); v4l2_m2m_update_start_streaming_state(m2m_ctx, q); if (inst->state == VPU_INST_STATE_NONE && q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { @@ -1364,9 +1366,13 @@ static int wave5_vpu_enc_start_streaming(struct vb2_queue *q, unsigned int count if (ret) goto return_buffers; + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); return 0; return_buffers: wave5_return_bufs(q, VB2_BUF_STATE_QUEUED); + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); return ret; } @@ -1408,6 +1414,7 @@ static void wave5_vpu_enc_stop_streaming(struct vb2_queue *q) */ dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); + pm_runtime_resume_and_get(inst->dev->dev); if (wave5_vpu_both_queues_are_streaming(inst)) switch_state(inst, VPU_INST_STATE_STOP); @@ -1432,6 +1439,9 @@ static void wave5_vpu_enc_stop_streaming(struct vb2_queue *q) streamoff_output(inst, q); else streamoff_capture(inst, q); + + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); } static const struct vb2_ops wave5_vpu_enc_vb2_ops = { @@ -1478,6 +1488,7 @@ static void wave5_vpu_enc_device_run(void *priv) u32 fail_res = 0; int ret = 0; + pm_runtime_resume_and_get(inst->dev->dev); switch (inst->state) { case VPU_INST_STATE_PIC_RUN: ret = start_encode(inst, &fail_res); @@ -1491,6 +1502,8 @@ static void wave5_vpu_enc_device_run(void *priv) break; } dev_dbg(inst->dev->dev, "%s: leave with active job", __func__); + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); return; default: WARN(1, "Execution of a job in state %s is invalid.\n", @@ -1498,6 +1511,8 @@ static void wave5_vpu_enc_device_run(void *priv) break; } dev_dbg(inst->dev->dev, "%s: leave and finish job", __func__); + pm_runtime_mark_last_busy(inst->dev->dev); + pm_runtime_put_autosuspend(inst->dev->dev); v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); } diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.c b/drivers/media/platform/chips-media/wave5/wave5-vpu.c index 68a519ac412d..325e311cdedc 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "wave5-vpu.h" #include "wave5-regdefine.h" #include "wave5-vpuconfig.h" @@ -145,6 +146,38 @@ static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name, return 0; } +static int wave5_pm_suspend(struct device *dev) +{ + struct vpu_device *vpu = dev_get_drvdata(dev); + + if (pm_runtime_suspended(dev)) + return 0; + + wave5_vpu_sleep_wake(dev, true, NULL, 0); + clk_bulk_disable_unprepare(vpu->num_clks, vpu->clks); + + return 0; +} + +static int wave5_pm_resume(struct device *dev) +{ + struct vpu_device *vpu = dev_get_drvdata(dev); + int ret = 0; + + wave5_vpu_sleep_wake(dev, false, NULL, 0); + ret = clk_bulk_prepare_enable(vpu->num_clks, vpu->clks); + if (ret) { + dev_err(dev, "Enabling clocks, fail: %d\n", ret); + return ret; + } + + return ret; +} + +static const struct dev_pm_ops wave5_pm_ops = { + SET_RUNTIME_PM_OPS(wave5_pm_suspend, wave5_pm_resume, NULL) +}; + static int wave5_vpu_probe(struct platform_device *pdev) { int ret; @@ -268,6 +301,12 @@ static int wave5_vpu_probe(struct platform_device *pdev) (match_data->flags & WAVE5_IS_DEC) ? "'DECODE'" : ""); dev_info(&pdev->dev, "Product Code: 0x%x\n", dev->product_code); dev_info(&pdev->dev, "Firmware Revision: %u\n", fw_revision); + + pm_runtime_set_autosuspend_delay(&pdev->dev, 5000); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_enable(&pdev->dev); + wave5_vpu_sleep_wake(&pdev->dev, true, NULL, 0); + return 0; err_enc_unreg: @@ -295,6 +334,9 @@ static void wave5_vpu_remove(struct platform_device *pdev) hrtimer_cancel(&dev->hrtimer); } + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); + mutex_destroy(&dev->dev_lock); mutex_destroy(&dev->hw_lock); clk_bulk_disable_unprepare(dev->num_clks, dev->clks); @@ -320,6 +362,7 @@ static struct platform_driver wave5_vpu_driver = { .driver = { .name = VPU_PLATFORM_DEVICE_NAME, .of_match_table = of_match_ptr(wave5_dt_ids), + .pm = &wave5_pm_ops, }, .probe = wave5_vpu_probe, .remove_new = wave5_vpu_remove, diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c index 1a3efb638dde..b0911fef232f 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c @@ -6,6 +6,8 @@ */ #include +#include +#include #include "wave5-vpuapi.h" #include "wave5-regdefine.h" #include "wave5.h" @@ -200,9 +202,13 @@ int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res) if (!inst->codec_info) return -EINVAL; + pm_runtime_resume_and_get(inst->dev->dev); + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); - if (ret) + if (ret) { + pm_runtime_put_sync(inst->dev->dev); return ret; + } do { ret = wave5_vpu_dec_finish_seq(inst, fail_res); @@ -234,7 +240,7 @@ int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res) unlock_and_return: mutex_unlock(&vpu_dev->hw_lock); - + pm_runtime_put_sync(inst->dev->dev); return ret; } @@ -702,6 +708,8 @@ int wave5_vpu_enc_close(struct vpu_instance *inst, u32 *fail_res) if (!inst->codec_info) return -EINVAL; + pm_runtime_resume_and_get(inst->dev->dev); + ret = mutex_lock_interruptible(&vpu_dev->hw_lock); if (ret) return ret; @@ -733,9 +741,9 @@ int wave5_vpu_enc_close(struct vpu_instance *inst, u32 *fail_res) } wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_task); - mutex_unlock(&vpu_dev->hw_lock); + pm_runtime_put_sync(inst->dev->dev); return 0; } diff --git a/drivers/media/platform/chips-media/wave5/wave5.h b/drivers/media/platform/chips-media/wave5/wave5.h index 063028eccd3b..6125eff938a8 100644 --- a/drivers/media/platform/chips-media/wave5/wave5.h +++ b/drivers/media/platform/chips-media/wave5/wave5.h @@ -56,6 +56,9 @@ int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision); int wave5_vpu_init(struct device *dev, u8 *fw, size_t size); +int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uint16_t *code, + size_t size); + int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode); int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, struct dec_open_param *param); From patchwork Tue Apr 30 01:38:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nas Chung X-Patchwork-Id: 13647945 Received: from SEVP216CU002.outbound.protection.outlook.com (mail-koreacentralazon11022018.outbound.protection.outlook.com [52.101.154.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 809B1DF6B; Tue, 30 Apr 2024 01:39:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.154.18 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714441163; cv=fail; b=IV7Ee7yrhhX34NZNJ29lsgo0bXGc7wBI86XHLaVgSKnu7KAytuRfr6fWbFHZArHsmWPBx8m62BoAYkfGl2vhfIiZ2hnqR5x650s0U+1TfPxtpP6F65URZx2qL550tMvXWl+pIuIXQaa6xGxM53zQGUxb/0O18vMgDoMsa4GcjZI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714441163; c=relaxed/simple; bh=fWMfOKl0WaENi/wH3IETIAGpgBhq3z+Q0r3lFOIfvT0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=KH2zWvAayoniOANYr5LQ/Ab0YdezaV7GITszyZ6swggkhjeKyx2omFFGQqo4Bhv0qqp1AXghFnSKDfVPN6ieDAGtV3soL9RcXjku7c79s5mmtc/xIyTGes8Yt9PrwWLqxVgZhcp1n/fwp0NYqKOyiwpkT2ox9KiUwVUcrysfxIQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chipsnmedia.com; spf=pass smtp.mailfrom=chipsnmedia.com; dkim=pass (1024-bit key) header.d=chipsnmedia.com header.i=@chipsnmedia.com header.b=PCy0MIHF; arc=fail smtp.client-ip=52.101.154.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chipsnmedia.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chipsnmedia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chipsnmedia.com header.i=@chipsnmedia.com header.b="PCy0MIHF" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=V1iaLd43KAy/lIapi6tIWxYyh25t9qEeJaHVVgTPJ4QAa71O/sH0ii89wyIAiVru23xEmuXbPEhwMdYpGUne+r2l/aMTbEm5OiHWM3qyFLFa55syIXVRBKSKAowa0CXhuDluIwOcXT+DcYa/kAXBJRrlLwFn1yQXhqksk6V2j7kWJPkfYKi4gj8PHQ9hZxzUGuYo6LJ2xp8vC9jC+HJN/LADDIVhLcJGxkdceY9ocaLPDBlu359bkA0jvSRN1RxUpdMebwmJI3dmnjG9kzkBggSxTPCc2I6wGD/U0D8DhrXCcZ8hLmb0xai1EFZm544oaZ4mGCgypnTwuswfUuxmfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=HMpRAJuDXeAL/jDdaHyv14CvGuT1qCcCjG8+V8gEFFs=; b=BJoplyZrwsPcFGble+/c49tLccl7KoQ8SkdB1fKLEo0IqW+S2ORXAPZV7+t7Zscn5HQwNBNFpJqtZUnMZPe4zyxRGqrki70Y9ArCpXqtSEZLfqMcLsF46Horg2/S+zUMmqf295lntoyIq9ppKnJaiK0oEbTuwkInqw23mbKDbXPM7t5/C8s3+wvMJ7EEZCI8Na2IGXAAHSdRQBXQMY6zlTxqMIkk7MtXlWmNRxalktOqEAiMP6ZziAaZHYKdxNwNpL5GWQx45hsSfUEC/+m+urw/BCjkHiPO49ZDLVnmOpmAWIo4jIdu1Aq4rjmtw6Je7lLK9/wSNU8aDoH8/IUXWQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=chipsnmedia.com; dmarc=pass action=none header.from=chipsnmedia.com; dkim=pass header.d=chipsnmedia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chipsnmedia.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HMpRAJuDXeAL/jDdaHyv14CvGuT1qCcCjG8+V8gEFFs=; b=PCy0MIHFGv+9wqbm2Ly41IcAQ1B5PvDdtc9PXMCLwyTj383OYdgs5GRkorgVIxaCu+Yd0scOnXgdtMXN1y7IidiP4oiVdQsB8g3we5ZFlytVvKLlRiFvOuBmKOTUz7e9QaIJgyXVF3X+oHWymIrVcaPRIbGzdlxJqct0ggs3tb4= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=chipsnmedia.com; Received: from SL2P216MB1246.KORP216.PROD.OUTLOOK.COM (2603:1096:101:a::9) by SL2P216MB2195.KORP216.PROD.OUTLOOK.COM (2603:1096:101:150::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.36; Tue, 30 Apr 2024 01:39:10 +0000 Received: from SL2P216MB1246.KORP216.PROD.OUTLOOK.COM ([fe80::5b8:35f1:821f:4f57]) by SL2P216MB1246.KORP216.PROD.OUTLOOK.COM ([fe80::5b8:35f1:821f:4f57%2]) with mapi id 15.20.7519.035; Tue, 30 Apr 2024 01:39:10 +0000 From: Nas Chung To: mchehab@kernel.org, nicolas@ndufresne.ca, sebastian.fricke@collabora.com Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, hverkuil@xs4all.nl, nas.chung@chipsnmedia.com, lafley.kim@chipsnmedia.com, b-brnich@ti.com, jackson.lee@chipnsmedia.com, "Jackson.lee" Subject: [PATCH v3 3/4] media: chips-media: wave5: Use helpers to calculate bytesperline and sizeimage. Date: Tue, 30 Apr 2024 10:38:59 +0900 Message-Id: <20240430013900.187-4-nas.chung@chipsnmedia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240430013900.187-1-nas.chung@chipsnmedia.com> References: <20240430013900.187-1-nas.chung@chipsnmedia.com> X-ClientProxiedBy: SL2P216CA0211.KORP216.PROD.OUTLOOK.COM (2603:1096:101:19::19) To SL2P216MB1246.KORP216.PROD.OUTLOOK.COM (2603:1096:101:a::9) Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SL2P216MB1246:EE_|SL2P216MB2195:EE_ X-MS-Office365-Filtering-Correlation-Id: 35202a82-af80-471a-c944-08dc68b65563 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|52116005|376005|366007|38350700005; X-Microsoft-Antispam-Message-Info: uSPIZTSwx/PDEopb5jxBLuSf9vpmeD9Hv6oiNIPvGhJXWSdxcWHIgLYXVuqbmH3/5XQpB+doPWG2b7+jGnzsGsG5SJ+7/GRjNXBoNBy0/syW+2CnbC0LQ7iqNqBEMEq9mjCuZMPEI1mRIk0mFETBDFnzOz5GDJOVnIxQpgfCgA7lYpoF4CSbDoofI8JjuSmS7ZiproUi/tWI2baOMNgEY0XNIFHIVVULSFTtF2NYbB6YxY2bKvvikMHiAKzFmXWA891LRc35pgk8V9/NyBr072hp37hsKgCLFxL0xWFcwQd4NO6+2vW3/rd1iHxOPDK5dwOnNV0gAjztMCLQkAUZK9L5w9O2x1PkNdxZsRF/YDPQpJnamxHU7nranHOsLG+o3NszM7E6OKuAicQQkDJEgxGmNCvoym1aZSUptmDC8Lxfe7QSkkY5S+j+kxhIQewsemqshxniKhoqne9vVZFsiOGkSfXPOxPyMNdEr3/estkNWV3GI05o6ROYl008QX5qOkJmgmT8KofrXS/eYDUiDwC4qz7aArDxJP9PR0nSs5JwVFaxLYv3mauUOPzz2oSLXrv1C0xRZCMpTDmqWoYtW5up4RxKegOfFJYRb7CElrWekhfekuj+AnXUtCLkp8rV8rZpjn7B7MLXfw/NSysottkvGLBkEbrea2LLi34Zxab0clHSDApV+lunBdaPDTm38eo4XIyMk4n1hOEJZ82odbFDBNdVwZocpgeiwJ6OHjcBZN8I6d+xsJ3be48Cjca99byXsLsVQ+5FWiXJwHcsLGD2MfmjqMf5hil1BNMZpmRleXQ9s7FLEO6wUTs5CRVeUA5/yWjnfkyydOWA3QpzTNS00UkIhZP5Kz8x1zIP8qrz9mwFz4YtdaLkrVumtcu3cpO/TcTc80TUlsaKRCJJS/DX3yTstLG4P1mj0I2eFvtlsYhXx0Db26wBfbh50mZ9HV+Vkf7Av697pUlksuw9sQ4o5CsfdMLz1MtI3259x+4JZgGtq4MDsx2mHl8uaXjL5ueoWwPmC5EMbZp0Yzbh6Pjf1uFr+kGFe+/fFqdSJYzBzD2n8s9mZXK8Lf/aSixbF3uU7G0WvP3jxUGEoz0f8mRpOT0c4RQvqnc1e2NVTWJgQofh0g/fkLO66imcGYBFHTChKDd0N9HUkz0+rVvMgbJECLL30Cyr86TMKMoNVNhYCpHGpD6GSQU2V9mxq7Yf6fAANLOed7al1Jx2tFAzLJJ0pWPQwRIEJYaTC8z/hAT8t9a/7I26e12vQocM/hZCG7MYSPYZB/LcrU0VnjdES6o/ro4oVirhXwJ1s8KyICFfQ4rI1YSz4zDYD3xg3IlBJpt3BXAPq5TxXxXSZ0uFnA== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SL2P216MB1246.KORP216.PROD.OUTLOOK.COM;PTR:;CAT:NONE;SFS:(13230031)(1800799015)(52116005)(376005)(366007)(38350700005);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: M5O2GamFEUL0f6utfNTCOLAwGWPOBn3k5piX43msr6ZukIlJ45aUXBUCUj52MJ/0mdmAh1wVqimeqQFx8rtXodUsCJTQbvIBNxC3JuB/TDLyRvx0X1HhzyZK8Xum7BWT1YZB9b3cHniwqKTZW4Hoi8a7SBWhu+MevLz7yvfzuNQNM3uLRFcA14xGM90CHI3fnfWipCKpANd4peWjMm/Gr2UZRjyFI1rNVFQVZp35lrVjRI7GWLuIGzYOlE0OpYICuoD2CLOR0Zy8/QvHb2b5EXmmlqSCWkHDuMiJtpXioylXgdrmM96lc1NccoIZigJPe9mIV/UfOAEdLPZuB21N0Vr+jxkIqtlp62OTCPVYNrg9UOYGec+n0k0VOxmtckqlKchy0ksWHjxqDsHuLjTqYJW0i552CSQkn97nBLsOrZfKnlhd3zUVI7lEJK9jVZ7dZA5Ryo/bdYBTJNG/dFTC2spX60C01I48ewgHMGx0TeHiS/e7ZeTvw7b0JodB8B2SZyZqm+a4mW/HlTx+g0G5ZSzY4/oO3J8c5XrnqHr6yLjaeQIaILLz2rKYTiQWS+QYFUlSZQUioDmJayJQrdZmOjszFXzjAj74I2T8iGBcmJl4Y+QRuaskQfwvTWk3u2ZGfhIuWdOz0EQPEtr4b0lPFtoWRozcs8IsyBJ7UwEEXwA+927qzhBA56mOLPLvTwmqJAUnV6V3kBfYpSTJYTndp4dmEtpMvzq9soFnRz+VOTIwnfBTVsf41s2Lr/mFIAhxUCQOEDuFMtXbVZlFxHUA8w4TkTUEG/i4jNpyFk5MgHtpgKTnS9rLTdBJuLdce80ZryeSr17c0ej5s9VrOsLjuOsh7OUfJb4+/r1sKCg15kttRZE92pRbBHpiTKcqw8XvdW8vvgHYaZdedtqRKvyq55J7DHgrG+s3uQQOkNva89eC5OjTgPdKsdSTEFEVrLyCrIGIrk3cXzY6UbMnPYc71O6MITnCrtS9oyhrjoaHQWVRo2TriaEAolZ46ZwWEqfR+saYsu3uZyJG/NpxLDAaljePG1duGctjcbPO6opvSRhGnwcVPmHoRer/xGkdw2EUhCmQTcONMjEusRKlMgwEaM2uNof6t+4UwVgeQ+ax1wqqN9F0zOrRi2Ww7TfUWA0irtUIbupt0BYI2jsyEdy+31rSdn+gDHvQeHFYA0DZ4qh22uUVta+a0xiWtEWIDYnzaU1dP+Q/g+tqCkrkQePMk1zg9e3Ztuz2kkgixfhEuW3TfEx07IXXI9Dixw0+Z0oQmzxhuwBjycWN9NOe/6UL/sNM1nuO6DKEiE/wGyVPdJdDOLQ5k1YWuQtzJ8Zx1UxXTQ/hE+cRJvIDM8GKDFq+xqvs5Ne3AIS7E1BSgtuVYNNWmPR3iM0mrWVq+yDNF/8Dg805F/rNTQFNM5c1YAhn81TxqzbkSN8PASSpjNeDYX5zDcgxi6KFUeGyKlUOB51B5k728WXXQXA42HbvQYkaI53+WaGtdSugK0hZc41CeQb0F1jDppEhOwNeDKyq2EuI9L8sKAVVd0WKqaKRcZwS/OMCgP1+ylp7J4OCbVAuppZT515otcghmaw6Q2Gke/dPWYctmHPptANWgnQN1GVcqg== X-OriginatorOrg: chipsnmedia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 35202a82-af80-471a-c944-08dc68b65563 X-MS-Exchange-CrossTenant-AuthSource: SL2P216MB1246.KORP216.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2024 01:39:10.7382 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4d70c8e9-142b-4389-b7f2-fa8a3c68c467 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: HO2eVBMea5gLZ89mWPyLZ+GsDtacm7YaS8Lsm+ltTMOSUKAz5/N/XKGJ+dytLxzAOqY6/29FCi4CpAcXSqFbeYaVujaZZpvDL9fSkgFWvA8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SL2P216MB2195 From: "Jackson.lee" Use v4l2-common helper functions to calculate bytesperline and sizeimage, instead of calculating in a wave5 driver directly. In case of raw(YUV) v4l2_pix_format, the wave5 driver updates v4l2_pix_format_mplane struct through v4l2_fill_pixfmt_mp() function. Encoder and Decoder need same bytesperline and sizeimage values for same v4l2_pix_format. So, a wave5_update_pix_fmt is refactored to support both together. Signed-off-by: Jackson.lee Signed-off-by: Nas Chung Reviewed-by: Nicolas Dufresne --- .../platform/chips-media/wave5/wave5-helper.c | 24 ++ .../platform/chips-media/wave5/wave5-helper.h | 5 + .../chips-media/wave5/wave5-vpu-dec.c | 298 ++++++------------ .../chips-media/wave5/wave5-vpu-enc.c | 197 +++++------- .../platform/chips-media/wave5/wave5-vpu.h | 5 +- .../chips-media/wave5/wave5-vpuconfig.h | 27 +- 6 files changed, 238 insertions(+), 318 deletions(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-helper.c b/drivers/media/platform/chips-media/wave5/wave5-helper.c index 7e0f34bfa5be..b20ab69cd341 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-helper.c +++ b/drivers/media/platform/chips-media/wave5/wave5-helper.c @@ -7,6 +7,8 @@ #include "wave5-helper.h" +#define DEFAULT_BS_SIZE(width, height) ((width) * (height) / 8 * 3) + const char *state_to_str(enum vpu_instance_state state) { switch (state) { @@ -224,3 +226,25 @@ void wave5_return_bufs(struct vb2_queue *q, u32 state) v4l2_m2m_buf_done(vbuf, state); } } + +void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, + int pix_fmt_type, + unsigned int width, + unsigned int height, + const struct v4l2_frmsize_stepwise *frmsize) +{ + v4l2_apply_frmsize_constraints(&width, &height, frmsize); + + if (pix_fmt_type == VPU_FMT_TYPE_CODEC) { + pix_mp->width = width; + pix_mp->height = height; + pix_mp->num_planes = 1; + pix_mp->plane_fmt[0].bytesperline = 0; + pix_mp->plane_fmt[0].sizeimage = max(DEFAULT_BS_SIZE(width, height), + pix_mp->plane_fmt[0].sizeimage); + } else { + v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, width, height); + } + pix_mp->flags = 0; + pix_mp->field = V4L2_FIELD_NONE; +} diff --git a/drivers/media/platform/chips-media/wave5/wave5-helper.h b/drivers/media/platform/chips-media/wave5/wave5-helper.h index 6cee1c14d3ce..9937fce553fc 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-helper.h +++ b/drivers/media/platform/chips-media/wave5/wave5-helper.h @@ -28,4 +28,9 @@ const struct vpu_format *wave5_find_vpu_fmt_by_idx(unsigned int idx, const struct vpu_format fmt_list[MAX_FMTS]); enum wave_std wave5_to_vpu_std(unsigned int v4l2_pix_fmt, enum vpu_instance_type type); void wave5_return_bufs(struct vb2_queue *q, u32 state); +void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, + int pix_fmt_type, + unsigned int width, + unsigned int height, + const struct v4l2_frmsize_stepwise *frmsize); #endif diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c index 861a0664047c..b20cec5d8fdd 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c @@ -11,111 +11,96 @@ #define VPU_DEC_DEV_NAME "C&M Wave5 VPU decoder" #define VPU_DEC_DRV_NAME "wave5-dec" -#define DEFAULT_SRC_SIZE(width, height) ({ \ - (width) * (height) / 8 * 3; \ -}) +static const struct v4l2_frmsize_stepwise dec_frmsize[FMT_TYPES][MAX_FMTS] = { + [VPU_FMT_TYPE_CODEC] = { + { + .min_width = W5_MIN_DEC_PIC_8_WIDTH, + .max_width = W5_MAX_DEC_PIC_WIDTH, + .step_width = W5_DEC_CODEC_STEP_WIDTH, + .min_height = W5_MIN_DEC_PIC_8_HEIGHT, + .max_height = W5_MAX_DEC_PIC_HEIGHT, + .step_height = W5_DEC_CODEC_STEP_HEIGHT, + }, + { + .min_width = W5_MIN_DEC_PIC_32_WIDTH, + .max_width = W5_MAX_DEC_PIC_WIDTH, + .step_width = W5_DEC_CODEC_STEP_WIDTH, + .min_height = W5_MIN_DEC_PIC_32_HEIGHT, + .max_height = W5_MAX_DEC_PIC_HEIGHT, + .step_height = W5_DEC_CODEC_STEP_HEIGHT, + } + }, + [VPU_FMT_TYPE_RAW] = { + { + .min_width = W5_MIN_DEC_PIC_8_WIDTH, + .max_width = W5_MAX_DEC_PIC_WIDTH, + .step_width = W5_DEC_RAW_STEP_WIDTH, + .min_height = W5_MIN_DEC_PIC_8_HEIGHT, + .max_height = W5_MAX_DEC_PIC_HEIGHT, + .step_height = W5_DEC_RAW_STEP_HEIGHT, + } + }, +}; static const struct vpu_format dec_fmt_list[FMT_TYPES][MAX_FMTS] = { [VPU_FMT_TYPE_CODEC] = { { .v4l2_pix_fmt = V4L2_PIX_FMT_HEVC, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_frmsize[VPU_FMT_TYPE_CODEC][0], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_H264, - .max_width = 8192, - .min_width = 32, - .max_height = 4320, - .min_height = 32, + .v4l2_frmsize = &dec_frmsize[VPU_FMT_TYPE_CODEC][1], }, }, [VPU_FMT_TYPE_RAW] = { { .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_frmsize[VPU_FMT_TYPE_RAW][0], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV12, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_frmsize[VPU_FMT_TYPE_RAW][0], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV21, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_frmsize[VPU_FMT_TYPE_RAW][0], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_YUV422P, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_frmsize[VPU_FMT_TYPE_RAW][0], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV16, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_frmsize[VPU_FMT_TYPE_RAW][0], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV61, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_frmsize[VPU_FMT_TYPE_RAW][0], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420M, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_frmsize[VPU_FMT_TYPE_RAW][0], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV12M, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_frmsize[VPU_FMT_TYPE_RAW][0], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV21M, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_frmsize[VPU_FMT_TYPE_RAW][0], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_YUV422M, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_frmsize[VPU_FMT_TYPE_RAW][0], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV16M, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_frmsize[VPU_FMT_TYPE_RAW][0], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV61M, - .max_width = 8192, - .min_width = 8, - .max_height = 4320, - .min_height = 8, + .v4l2_frmsize = &dec_frmsize[VPU_FMT_TYPE_RAW][0], }, } }; @@ -234,74 +219,6 @@ static void wave5_handle_src_buffer(struct vpu_instance *inst, dma_addr_t rd_ptr inst->remaining_consumed_bytes = consumed_bytes; } -static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned int width, - unsigned int height) -{ - switch (pix_mp->pixelformat) { - case V4L2_PIX_FMT_YUV420: - case V4L2_PIX_FMT_NV12: - case V4L2_PIX_FMT_NV21: - pix_mp->width = round_up(width, 32); - pix_mp->height = round_up(height, 16); - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = width * height * 3 / 2; - break; - case V4L2_PIX_FMT_YUV422P: - case V4L2_PIX_FMT_NV16: - case V4L2_PIX_FMT_NV61: - pix_mp->width = round_up(width, 32); - pix_mp->height = round_up(height, 16); - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = width * height * 2; - break; - case V4L2_PIX_FMT_YUV420M: - pix_mp->width = round_up(width, 32); - pix_mp->height = round_up(height, 16); - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = width * height; - pix_mp->plane_fmt[1].bytesperline = round_up(width, 32) / 2; - pix_mp->plane_fmt[1].sizeimage = width * height / 4; - pix_mp->plane_fmt[2].bytesperline = round_up(width, 32) / 2; - pix_mp->plane_fmt[2].sizeimage = width * height / 4; - break; - case V4L2_PIX_FMT_NV12M: - case V4L2_PIX_FMT_NV21M: - pix_mp->width = round_up(width, 32); - pix_mp->height = round_up(height, 16); - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = width * height; - pix_mp->plane_fmt[1].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[1].sizeimage = width * height / 2; - break; - case V4L2_PIX_FMT_YUV422M: - pix_mp->width = round_up(width, 32); - pix_mp->height = round_up(height, 16); - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = width * height; - pix_mp->plane_fmt[1].bytesperline = round_up(width, 32) / 2; - pix_mp->plane_fmt[1].sizeimage = width * height / 2; - pix_mp->plane_fmt[2].bytesperline = round_up(width, 32) / 2; - pix_mp->plane_fmt[2].sizeimage = width * height / 2; - break; - case V4L2_PIX_FMT_NV16M: - case V4L2_PIX_FMT_NV61M: - pix_mp->width = round_up(width, 32); - pix_mp->height = round_up(height, 16); - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = width * height; - pix_mp->plane_fmt[1].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[1].sizeimage = width * height; - break; - default: - pix_mp->width = width; - pix_mp->height = height; - pix_mp->plane_fmt[0].bytesperline = 0; - pix_mp->plane_fmt[0].sizeimage = max(DEFAULT_SRC_SIZE(width, height), - pix_mp->plane_fmt[0].sizeimage); - break; - } -} - static int start_decode(struct vpu_instance *inst, u32 *fail_res) { struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; @@ -389,6 +306,8 @@ static int handle_dynamic_resolution_change(struct vpu_instance *inst) } if (p_dec_info->initial_info_obtained) { + const struct vpu_format *vpu_fmt; + inst->conf_win.left = initial_info->pic_crop_rect.left; inst->conf_win.top = initial_info->pic_crop_rect.top; inst->conf_win.width = initial_info->pic_width - @@ -396,10 +315,25 @@ static int handle_dynamic_resolution_change(struct vpu_instance *inst) inst->conf_win.height = initial_info->pic_height - initial_info->pic_crop_rect.top - initial_info->pic_crop_rect.bottom; - wave5_update_pix_fmt(&inst->src_fmt, initial_info->pic_width, - initial_info->pic_height); - wave5_update_pix_fmt(&inst->dst_fmt, initial_info->pic_width, - initial_info->pic_height); + vpu_fmt = wave5_find_vpu_fmt(inst->src_fmt.pixelformat, dec_fmt_list[VPU_FMT_TYPE_CODEC]); + if (!vpu_fmt) + return -EINVAL; + + wave5_update_pix_fmt(&inst->src_fmt, + VPU_FMT_TYPE_CODEC, + initial_info->pic_width, + initial_info->pic_height, + vpu_fmt->v4l2_frmsize); + + vpu_fmt = wave5_find_vpu_fmt(inst->dst_fmt.pixelformat, dec_fmt_list[VPU_FMT_TYPE_RAW]); + if (!vpu_fmt) + return -EINVAL; + + wave5_update_pix_fmt(&inst->dst_fmt, + VPU_FMT_TYPE_RAW, + initial_info->pic_width, + initial_info->pic_height, + vpu_fmt->v4l2_frmsize); } v4l2_event_queue_fh(fh, &vpu_event_src_ch); @@ -548,12 +482,7 @@ static int wave5_vpu_dec_enum_framesizes(struct file *f, void *fh, struct v4l2_f } fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; - fsize->stepwise.min_width = vpu_fmt->min_width; - fsize->stepwise.max_width = vpu_fmt->max_width; - fsize->stepwise.step_width = 1; - fsize->stepwise.min_height = vpu_fmt->min_height; - fsize->stepwise.max_height = vpu_fmt->max_height; - fsize->stepwise.step_height = 1; + fsize->stepwise = *vpu_fmt->v4l2_frmsize; return 0; } @@ -589,14 +518,10 @@ static int wave5_vpu_dec_try_fmt_cap(struct file *file, void *fh, struct v4l2_fo width = inst->dst_fmt.width; height = inst->dst_fmt.height; f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; - f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; } else { - const struct v4l2_format_info *info = v4l2_format_info(vpu_fmt->v4l2_pix_fmt); - - width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); - height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); + width = f->fmt.pix_mp.width; + height = f->fmt.pix_mp.height; f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; - f->fmt.pix_mp.num_planes = info->mem_planes; } if (p_dec_info->initial_info_obtained) { @@ -604,9 +529,10 @@ static int wave5_vpu_dec_try_fmt_cap(struct file *file, void *fh, struct v4l2_fo height = inst->dst_fmt.height; } - wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); - f->fmt.pix_mp.flags = 0; - f->fmt.pix_mp.field = V4L2_FIELD_NONE; + wave5_update_pix_fmt(&f->fmt.pix_mp, VPU_FMT_TYPE_RAW, + width, + height, + vpu_fmt->v4l2_frmsize); f->fmt.pix_mp.colorspace = inst->colorspace; f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; f->fmt.pix_mp.quantization = inst->quantization; @@ -719,6 +645,7 @@ static int wave5_vpu_dec_try_fmt_out(struct file *file, void *fh, struct v4l2_fo { struct vpu_instance *inst = wave5_to_vpu_inst(fh); const struct vpu_format *vpu_fmt; + int width, height; dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u colorspace: %u field: %u\n", @@ -727,20 +654,19 @@ static int wave5_vpu_dec_try_fmt_out(struct file *file, void *fh, struct v4l2_fo vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, dec_fmt_list[VPU_FMT_TYPE_CODEC]); if (!vpu_fmt) { + width = inst->src_fmt.width; + height = inst->src_fmt.height; f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; - f->fmt.pix_mp.num_planes = inst->src_fmt.num_planes; - wave5_update_pix_fmt(&f->fmt.pix_mp, inst->src_fmt.width, inst->src_fmt.height); } else { - int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); - int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); - + width = f->fmt.pix_mp.width; + height = f->fmt.pix_mp.height; f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; - f->fmt.pix_mp.num_planes = 1; - wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); } - f->fmt.pix_mp.flags = 0; - f->fmt.pix_mp.field = V4L2_FIELD_NONE; + wave5_update_pix_fmt(&f->fmt.pix_mp, VPU_FMT_TYPE_CODEC, + width, + height, + vpu_fmt->v4l2_frmsize); return 0; } @@ -748,6 +674,7 @@ static int wave5_vpu_dec_try_fmt_out(struct file *file, void *fh, struct v4l2_fo static int wave5_vpu_dec_s_fmt_out(struct file *file, void *fh, struct v4l2_format *f) { struct vpu_instance *inst = wave5_to_vpu_inst(fh); + const struct vpu_format *vpu_fmt; int i, ret; dev_dbg(inst->dev->dev, @@ -782,7 +709,14 @@ static int wave5_vpu_dec_s_fmt_out(struct file *file, void *fh, struct v4l2_form inst->quantization = f->fmt.pix_mp.quantization; inst->xfer_func = f->fmt.pix_mp.xfer_func; - wave5_update_pix_fmt(&inst->dst_fmt, f->fmt.pix_mp.width, f->fmt.pix_mp.height); + vpu_fmt = wave5_find_vpu_fmt(inst->dst_fmt.pixelformat, dec_fmt_list[VPU_FMT_TYPE_RAW]); + if (!vpu_fmt) + return -EINVAL; + + wave5_update_pix_fmt(&inst->dst_fmt, VPU_FMT_TYPE_RAW, + f->fmt.pix_mp.width, + f->fmt.pix_mp.height, + vpu_fmt->v4l2_frmsize); return 0; } @@ -1005,6 +939,7 @@ static int wave5_vpu_dec_queue_setup(struct vb2_queue *q, unsigned int *num_buff struct vpu_instance *inst = vb2_get_drv_priv(q); struct v4l2_pix_format_mplane inst_format = (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->dst_fmt; + unsigned int i; dev_dbg(inst->dev->dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__, *num_buffers, *num_planes, q->type); @@ -1018,31 +953,9 @@ static int wave5_vpu_dec_queue_setup(struct vb2_queue *q, unsigned int *num_buff if (*num_buffers < inst->fbc_buf_count) *num_buffers = inst->fbc_buf_count; - if (*num_planes == 1) { - if (inst->output_format == FORMAT_422) - sizes[0] = inst_format.width * inst_format.height * 2; - else - sizes[0] = inst_format.width * inst_format.height * 3 / 2; - dev_dbg(inst->dev->dev, "%s: size[0]: %u\n", __func__, sizes[0]); - } else if (*num_planes == 2) { - sizes[0] = inst_format.width * inst_format.height; - if (inst->output_format == FORMAT_422) - sizes[1] = inst_format.width * inst_format.height; - else - sizes[1] = inst_format.width * inst_format.height / 2; - dev_dbg(inst->dev->dev, "%s: size[0]: %u | size[1]: %u\n", - __func__, sizes[0], sizes[1]); - } else if (*num_planes == 3) { - sizes[0] = inst_format.width * inst_format.height; - if (inst->output_format == FORMAT_422) { - sizes[1] = inst_format.width * inst_format.height / 2; - sizes[2] = inst_format.width * inst_format.height / 2; - } else { - sizes[1] = inst_format.width * inst_format.height / 4; - sizes[2] = inst_format.width * inst_format.height / 4; - } - dev_dbg(inst->dev->dev, "%s: size[0]: %u | size[1]: %u | size[2]: %u\n", - __func__, sizes[0], sizes[1], sizes[2]); + for (i = 0; i < *num_planes; i++) { + sizes[i] = inst_format.plane_fmt[i].sizeimage; + dev_dbg(inst->dev->dev, "%s: size[%u]: %u\n", __func__, i, sizes[i]); } } @@ -1564,20 +1477,17 @@ static const struct vb2_ops wave5_vpu_dec_vb2_ops = { static void wave5_set_default_format(struct v4l2_pix_format_mplane *src_fmt, struct v4l2_pix_format_mplane *dst_fmt) { - unsigned int dst_pix_fmt = dec_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt; - const struct v4l2_format_info *dst_fmt_info = v4l2_format_info(dst_pix_fmt); - src_fmt->pixelformat = dec_fmt_list[VPU_FMT_TYPE_CODEC][0].v4l2_pix_fmt; - src_fmt->field = V4L2_FIELD_NONE; - src_fmt->flags = 0; - src_fmt->num_planes = 1; - wave5_update_pix_fmt(src_fmt, 720, 480); - - dst_fmt->pixelformat = dst_pix_fmt; - dst_fmt->field = V4L2_FIELD_NONE; - dst_fmt->flags = 0; - dst_fmt->num_planes = dst_fmt_info->mem_planes; - wave5_update_pix_fmt(dst_fmt, 736, 480); + wave5_update_pix_fmt(src_fmt, VPU_FMT_TYPE_CODEC, + W5_DEF_DEC_PIC_WIDTH, + W5_DEF_DEC_PIC_HEIGHT, + &dec_frmsize[VPU_FMT_TYPE_CODEC][0]); + + dst_fmt->pixelformat = dec_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt; + wave5_update_pix_fmt(dst_fmt, VPU_FMT_TYPE_RAW, + W5_DEF_DEC_PIC_WIDTH, + W5_DEF_DEC_PIC_HEIGHT, + &dec_frmsize[VPU_FMT_TYPE_RAW][0]); } static int wave5_vpu_dec_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c index 703fd8d1c7da..75d230df45f6 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c @@ -11,65 +11,60 @@ #define VPU_ENC_DEV_NAME "C&M Wave5 VPU encoder" #define VPU_ENC_DRV_NAME "wave5-enc" +static const struct v4l2_frmsize_stepwise enc_frmsize[FMT_TYPES] = { + [VPU_FMT_TYPE_CODEC] = { + .min_width = W5_MIN_ENC_PIC_WIDTH, + .max_width = W5_MAX_ENC_PIC_WIDTH, + .step_width = W5_ENC_CODEC_STEP_WIDTH, + .min_height = W5_MIN_ENC_PIC_HEIGHT, + .max_height = W5_MAX_ENC_PIC_HEIGHT, + .step_height = W5_ENC_CODEC_STEP_HEIGHT, + }, + [VPU_FMT_TYPE_RAW] = { + .min_width = W5_MIN_ENC_PIC_WIDTH, + .max_width = W5_MAX_ENC_PIC_WIDTH, + .step_width = W5_ENC_RAW_STEP_WIDTH, + .min_height = W5_MIN_ENC_PIC_HEIGHT, + .max_height = W5_MAX_ENC_PIC_HEIGHT, + .step_height = W5_ENC_RAW_STEP_HEIGHT, + }, +}; + static const struct vpu_format enc_fmt_list[FMT_TYPES][MAX_FMTS] = { [VPU_FMT_TYPE_CODEC] = { { .v4l2_pix_fmt = V4L2_PIX_FMT_HEVC, - .max_width = W5_MAX_ENC_PIC_WIDTH, - .min_width = W5_MIN_ENC_PIC_WIDTH, - .max_height = W5_MAX_ENC_PIC_HEIGHT, - .min_height = W5_MIN_ENC_PIC_HEIGHT, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_CODEC], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_H264, - .max_width = W5_MAX_ENC_PIC_WIDTH, - .min_width = W5_MIN_ENC_PIC_WIDTH, - .max_height = W5_MAX_ENC_PIC_HEIGHT, - .min_height = W5_MIN_ENC_PIC_HEIGHT, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_CODEC], }, }, [VPU_FMT_TYPE_RAW] = { { .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420, - .max_width = W5_MAX_ENC_PIC_WIDTH, - .min_width = W5_MIN_ENC_PIC_WIDTH, - .max_height = W5_MAX_ENC_PIC_HEIGHT, - .min_height = W5_MIN_ENC_PIC_HEIGHT, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV12, - .max_width = W5_MAX_ENC_PIC_WIDTH, - .min_width = W5_MIN_ENC_PIC_WIDTH, - .max_height = W5_MAX_ENC_PIC_HEIGHT, - .min_height = W5_MIN_ENC_PIC_HEIGHT, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV21, - .max_width = W5_MAX_ENC_PIC_WIDTH, - .min_width = W5_MIN_ENC_PIC_WIDTH, - .max_height = W5_MAX_ENC_PIC_HEIGHT, - .min_height = W5_MIN_ENC_PIC_HEIGHT, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_YUV420M, - .max_width = W5_MAX_ENC_PIC_WIDTH, - .min_width = W5_MIN_ENC_PIC_WIDTH, - .max_height = W5_MAX_ENC_PIC_HEIGHT, - .min_height = W5_MIN_ENC_PIC_HEIGHT, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV12M, - .max_width = W5_MAX_ENC_PIC_WIDTH, - .min_width = W5_MIN_ENC_PIC_WIDTH, - .max_height = W5_MAX_ENC_PIC_HEIGHT, - .min_height = W5_MIN_ENC_PIC_HEIGHT, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], }, { .v4l2_pix_fmt = V4L2_PIX_FMT_NV21M, - .max_width = W5_MAX_ENC_PIC_WIDTH, - .min_width = W5_MIN_ENC_PIC_WIDTH, - .max_height = W5_MAX_ENC_PIC_HEIGHT, - .min_height = W5_MIN_ENC_PIC_HEIGHT, + .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], }, } }; @@ -106,46 +101,6 @@ static int switch_state(struct vpu_instance *inst, enum vpu_instance_state state return -EINVAL; } -static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned int width, - unsigned int height) -{ - switch (pix_mp->pixelformat) { - case V4L2_PIX_FMT_YUV420: - case V4L2_PIX_FMT_NV12: - case V4L2_PIX_FMT_NV21: - pix_mp->width = width; - pix_mp->height = height; - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height * 3 / 2; - break; - case V4L2_PIX_FMT_YUV420M: - pix_mp->width = width; - pix_mp->height = height; - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height; - pix_mp->plane_fmt[1].bytesperline = round_up(width, 32) / 2; - pix_mp->plane_fmt[1].sizeimage = round_up(width, 32) * height / 4; - pix_mp->plane_fmt[2].bytesperline = round_up(width, 32) / 2; - pix_mp->plane_fmt[2].sizeimage = round_up(width, 32) * height / 4; - break; - case V4L2_PIX_FMT_NV12M: - case V4L2_PIX_FMT_NV21M: - pix_mp->width = width; - pix_mp->height = height; - pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[0].sizeimage = round_up(width, 32) * height; - pix_mp->plane_fmt[1].bytesperline = round_up(width, 32); - pix_mp->plane_fmt[1].sizeimage = round_up(width, 32) * height / 2; - break; - default: - pix_mp->width = width; - pix_mp->height = height; - pix_mp->plane_fmt[0].bytesperline = 0; - pix_mp->plane_fmt[0].sizeimage = width * height / 8 * 3; - break; - } -} - static int start_encode(struct vpu_instance *inst, u32 *fail_res) { struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; @@ -360,13 +315,8 @@ static int wave5_vpu_enc_enum_framesizes(struct file *f, void *fh, struct v4l2_f return -EINVAL; } - fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; - fsize->stepwise.min_width = vpu_fmt->min_width; - fsize->stepwise.max_width = vpu_fmt->max_width; - fsize->stepwise.step_width = 1; - fsize->stepwise.min_height = vpu_fmt->min_height; - fsize->stepwise.max_height = vpu_fmt->max_height; - fsize->stepwise.step_height = 1; + fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; + fsize->stepwise = enc_frmsize[VPU_FMT_TYPE_CODEC]; return 0; } @@ -392,6 +342,7 @@ static int wave5_vpu_enc_try_fmt_cap(struct file *file, void *fh, struct v4l2_fo { struct vpu_instance *inst = wave5_to_vpu_inst(fh); const struct vpu_format *vpu_fmt; + int width, height; dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, @@ -399,20 +350,19 @@ static int wave5_vpu_enc_try_fmt_cap(struct file *file, void *fh, struct v4l2_fo vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_CODEC]); if (!vpu_fmt) { + width = inst->dst_fmt.width; + height = inst->dst_fmt.height; f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; - f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; - wave5_update_pix_fmt(&f->fmt.pix_mp, inst->dst_fmt.width, inst->dst_fmt.height); } else { - int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); - int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); - + width = f->fmt.pix_mp.width; + height = f->fmt.pix_mp.height; f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; - f->fmt.pix_mp.num_planes = 1; - wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); } - f->fmt.pix_mp.flags = 0; - f->fmt.pix_mp.field = V4L2_FIELD_NONE; + wave5_update_pix_fmt(&f->fmt.pix_mp, VPU_FMT_TYPE_CODEC, + width, + height, + vpu_fmt->v4l2_frmsize); f->fmt.pix_mp.colorspace = inst->colorspace; f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; f->fmt.pix_mp.quantization = inst->quantization; @@ -500,6 +450,7 @@ static int wave5_vpu_enc_try_fmt_out(struct file *file, void *fh, struct v4l2_fo { struct vpu_instance *inst = wave5_to_vpu_inst(fh); const struct vpu_format *vpu_fmt; + int width, height; dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, @@ -507,21 +458,19 @@ static int wave5_vpu_enc_try_fmt_out(struct file *file, void *fh, struct v4l2_fo vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_RAW]); if (!vpu_fmt) { + width = inst->src_fmt.width; + height = inst->src_fmt.height; f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; - f->fmt.pix_mp.num_planes = inst->src_fmt.num_planes; - wave5_update_pix_fmt(&f->fmt.pix_mp, inst->src_fmt.width, inst->src_fmt.height); } else { - int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); - int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); - const struct v4l2_format_info *info = v4l2_format_info(vpu_fmt->v4l2_pix_fmt); - + width = f->fmt.pix_mp.width; + height = f->fmt.pix_mp.height; f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; - f->fmt.pix_mp.num_planes = info->mem_planes; - wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); } - f->fmt.pix_mp.flags = 0; - f->fmt.pix_mp.field = V4L2_FIELD_NONE; + wave5_update_pix_fmt(&f->fmt.pix_mp, VPU_FMT_TYPE_RAW, + width, + height, + vpu_fmt->v4l2_frmsize); return 0; } @@ -529,6 +478,7 @@ static int wave5_vpu_enc_try_fmt_out(struct file *file, void *fh, struct v4l2_fo static int wave5_vpu_enc_s_fmt_out(struct file *file, void *fh, struct v4l2_format *f) { struct vpu_instance *inst = wave5_to_vpu_inst(fh); + const struct vpu_format *vpu_fmt; int i, ret; dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u num_planes: %u field: %u\n", @@ -568,7 +518,16 @@ static int wave5_vpu_enc_s_fmt_out(struct file *file, void *fh, struct v4l2_form inst->quantization = f->fmt.pix_mp.quantization; inst->xfer_func = f->fmt.pix_mp.xfer_func; - wave5_update_pix_fmt(&inst->dst_fmt, f->fmt.pix_mp.width, f->fmt.pix_mp.height); + vpu_fmt = wave5_find_vpu_fmt(inst->dst_fmt.pixelformat, enc_fmt_list[VPU_FMT_TYPE_CODEC]); + if (!vpu_fmt) + return -EINVAL; + + wave5_update_pix_fmt(&inst->dst_fmt, VPU_FMT_TYPE_CODEC, + f->fmt.pix_mp.width, + f->fmt.pix_mp.height, + vpu_fmt->v4l2_frmsize); + inst->conf_win.width = inst->dst_fmt.width; + inst->conf_win.height = inst->dst_fmt.height; return 0; } @@ -584,12 +543,17 @@ static int wave5_vpu_enc_g_selection(struct file *file, void *fh, struct v4l2_se switch (s->target) { case V4L2_SEL_TGT_CROP_DEFAULT: case V4L2_SEL_TGT_CROP_BOUNDS: - case V4L2_SEL_TGT_CROP: s->r.left = 0; s->r.top = 0; s->r.width = inst->dst_fmt.width; s->r.height = inst->dst_fmt.height; break; + case V4L2_SEL_TGT_CROP: + s->r.left = 0; + s->r.top = 0; + s->r.width = inst->conf_win.width; + s->r.height = inst->conf_win.height; + break; default: return -EINVAL; } @@ -612,8 +576,10 @@ static int wave5_vpu_enc_s_selection(struct file *file, void *fh, struct v4l2_se s->r.left = 0; s->r.top = 0; - s->r.width = inst->src_fmt.width; - s->r.height = inst->src_fmt.height; + s->r.width = min(s->r.width, inst->dst_fmt.width); + s->r.height = min(s->r.height, inst->dst_fmt.height); + + inst->conf_win = s->r; return 0; } @@ -1151,8 +1117,8 @@ static void wave5_set_enc_openparam(struct enc_open_param *open_param, open_param->wave_param.lambda_scaling_enable = 1; open_param->line_buf_int_en = true; - open_param->pic_width = inst->dst_fmt.width; - open_param->pic_height = inst->dst_fmt.height; + open_param->pic_width = inst->conf_win.width; + open_param->pic_height = inst->conf_win.height; open_param->frame_rate_info = inst->frame_rate; open_param->rc_enable = inst->rc_enable; if (inst->rc_enable) { @@ -1456,20 +1422,17 @@ static const struct vb2_ops wave5_vpu_enc_vb2_ops = { static void wave5_set_default_format(struct v4l2_pix_format_mplane *src_fmt, struct v4l2_pix_format_mplane *dst_fmt) { - unsigned int src_pix_fmt = enc_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt; - const struct v4l2_format_info *src_fmt_info = v4l2_format_info(src_pix_fmt); - - src_fmt->pixelformat = src_pix_fmt; - src_fmt->field = V4L2_FIELD_NONE; - src_fmt->flags = 0; - src_fmt->num_planes = src_fmt_info->mem_planes; - wave5_update_pix_fmt(src_fmt, 416, 240); + src_fmt->pixelformat = enc_fmt_list[VPU_FMT_TYPE_RAW][0].v4l2_pix_fmt; + wave5_update_pix_fmt(src_fmt, VPU_FMT_TYPE_RAW, + W5_DEF_ENC_PIC_WIDTH, + W5_DEF_ENC_PIC_HEIGHT, + &enc_frmsize[VPU_FMT_TYPE_RAW]); dst_fmt->pixelformat = enc_fmt_list[VPU_FMT_TYPE_CODEC][0].v4l2_pix_fmt; - dst_fmt->field = V4L2_FIELD_NONE; - dst_fmt->flags = 0; - dst_fmt->num_planes = 1; - wave5_update_pix_fmt(dst_fmt, 416, 240); + wave5_update_pix_fmt(dst_fmt, VPU_FMT_TYPE_CODEC, + W5_DEF_ENC_PIC_WIDTH, + W5_DEF_ENC_PIC_HEIGHT, + &enc_frmsize[VPU_FMT_TYPE_CODEC]); } static int wave5_vpu_enc_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) @@ -1733,6 +1696,8 @@ static int wave5_vpu_open_enc(struct file *filp) v4l2_ctrl_handler_setup(v4l2_ctrl_hdl); wave5_set_default_format(&inst->src_fmt, &inst->dst_fmt); + inst->conf_win.width = inst->dst_fmt.width; + inst->conf_win.height = inst->dst_fmt.height; inst->colorspace = V4L2_COLORSPACE_REC709; inst->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; inst->quantization = V4L2_QUANTIZATION_DEFAULT; diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.h b/drivers/media/platform/chips-media/wave5/wave5-vpu.h index 32b7fd3730b5..3847332551fc 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.h @@ -38,10 +38,7 @@ enum vpu_fmt_type { struct vpu_format { unsigned int v4l2_pix_fmt; - unsigned int max_width; - unsigned int min_width; - unsigned int max_height; - unsigned int min_height; + const struct v4l2_frmsize_stepwise *v4l2_frmsize; }; static inline struct vpu_instance *wave5_to_vpu_inst(struct v4l2_fh *vfh) diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h b/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h index d9751eedb0f9..8e11d93ca38f 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h @@ -30,10 +30,29 @@ #define MAX_NUM_INSTANCE 32 -#define W5_MIN_ENC_PIC_WIDTH 256 -#define W5_MIN_ENC_PIC_HEIGHT 128 -#define W5_MAX_ENC_PIC_WIDTH 8192 -#define W5_MAX_ENC_PIC_HEIGHT 8192 +#define W5_DEF_DEC_PIC_WIDTH 720U +#define W5_DEF_DEC_PIC_HEIGHT 480U +#define W5_MIN_DEC_PIC_8_WIDTH 8U +#define W5_MIN_DEC_PIC_8_HEIGHT 8U +#define W5_MIN_DEC_PIC_32_WIDTH 32U +#define W5_MIN_DEC_PIC_32_HEIGHT 32U +#define W5_MAX_DEC_PIC_WIDTH 8192U +#define W5_MAX_DEC_PIC_HEIGHT 4320U +#define W5_DEC_CODEC_STEP_WIDTH 1U +#define W5_DEC_CODEC_STEP_HEIGHT 1U +#define W5_DEC_RAW_STEP_WIDTH 32U +#define W5_DEC_RAW_STEP_HEIGHT 16U + +#define W5_DEF_ENC_PIC_WIDTH 416U +#define W5_DEF_ENC_PIC_HEIGHT 240U +#define W5_MIN_ENC_PIC_WIDTH 256U +#define W5_MIN_ENC_PIC_HEIGHT 128U +#define W5_MAX_ENC_PIC_WIDTH 8192U +#define W5_MAX_ENC_PIC_HEIGHT 8192U +#define W5_ENC_CODEC_STEP_WIDTH 8U +#define W5_ENC_CODEC_STEP_HEIGHT 8U +#define W5_ENC_RAW_STEP_WIDTH 32U +#define W5_ENC_RAW_STEP_HEIGHT 16U // application specific configuration #define VPU_ENC_TIMEOUT 60000 From patchwork Tue Apr 30 01:39:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nas Chung X-Patchwork-Id: 13647942 Received: from SEVP216CU002.outbound.protection.outlook.com (mail-koreacentralazon11022018.outbound.protection.outlook.com [52.101.154.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0482C17F5; Tue, 30 Apr 2024 01:39:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.154.18 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714441156; cv=fail; b=N3KCBfeN9vu3itziQ4nyKV4akU30g+nehX495TRI1DJFgu9027O46YzDv9591j0+XrmNk0Vm2vxs5yZJ4OY0skrbCVmlSMlcKMUk+U4i6sua9veXxBd6L+Ubeomgz8porZRu4C2HLBqOBclsDkK4fhQH04JJoIjcwdjRJkSsul4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714441156; c=relaxed/simple; bh=LRZ7WFXbHhzipeQ4f4GxVYXrahpPa1ffp4oaRK4ViNo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=IVw7Xi/pAgZoflGTJiio+XYQYiEbxcpdtyXsaOeoYyTdrujRqU4AEliu7lCuGFMYKnp+a+9rhVOtMbcedjMBsuWhZu86nXITSRer+SpInt7Q/nceLeP1Ik3zYThXpR/QCA+scteWMMx/5piUtFPGEJTMqXKiTK46ZWUo5gZDiJ4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chipsnmedia.com; spf=pass smtp.mailfrom=chipsnmedia.com; dkim=pass (1024-bit key) header.d=chipsnmedia.com header.i=@chipsnmedia.com header.b=jMQdILad; arc=fail smtp.client-ip=52.101.154.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=chipsnmedia.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chipsnmedia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=chipsnmedia.com header.i=@chipsnmedia.com header.b="jMQdILad" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=IAFqCCQc8KWQv62a25TRgoxGXC8Y7hiFllzk6TayMxHtpbo1k8cr/Be075sh7tfNoYTav6jXakQVMLpb2uWyRBu8cjmc5410rynvtunsBOSgrx7h4ISKRm+t+ImOXYaGS3hlafwgMED8+MpoI/L+PxHeG9xTjJISK2L0QTVkYsWUMgIC34IGtSiTEZ4DUaeTr+3j4BK1akx0A6Hk3l8HAiIY830Vfs0SHFP2ik34hcs9d/sDe0syp4P2Bl2GXsYdm8LWzw5e1/zBaUSKsozD3w1Gj1fJD/JkDiA3d6AZr4rguAOTui9qi+rw5uIU/iJZqWPoT2LhiO9hZj40LJN1lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=HZmiTKU+GeUSjmX5LtpCmEnBh4mdQBL3M1DfjwaYLIA=; b=hZxPwT7v3l/2xSfAC/+kEejR8SDnOzpLGjmAvWkrkZpTU6+AUydjHEpPp96Eo1iiHk1iRVw6fuiOAdYzpGiZkMoEVwMVZTtKQtIAlxbHyFMNcJxf5o8Lf1pVG8Qthuh1MiNqV1bzP7atsSG07oJ8URFpBE2s1is5A4wUpvGVA2jlDI3Ph7PuQfW7sBUqgH5xWChFJUQfbgQcfUNzEyCicVbo+4n0ed5R6nDKaAEnx6A2sT7ja2PF8yJYojeYMBIVKNZ5JPOSSuUEYysj5L5S5RK2Hyw/I98ymb/+57TmGTIbFGpytTdqbAgG9hdMQ1hN38PaKFPvh+WD37Z8zXM4mA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=chipsnmedia.com; dmarc=pass action=none header.from=chipsnmedia.com; dkim=pass header.d=chipsnmedia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chipsnmedia.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HZmiTKU+GeUSjmX5LtpCmEnBh4mdQBL3M1DfjwaYLIA=; b=jMQdILadD/ENoVehWGL4C8y2A2lyian7Uj+XSUU2EXAFcNzfwFVLmQFOx6FXaB2bg14NkLO2r2NvXEFNW9rr5ml/oFxW4c3NBjjTSNXG1AUCARUKW25lkOUs3LSwofUnRhxhS5N+H1cH4dxZgeW7xbzsxyP7CPBrUBwBT4qT0Lg= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=chipsnmedia.com; Received: from SL2P216MB1246.KORP216.PROD.OUTLOOK.COM (2603:1096:101:a::9) by PU4P216MB1324.KORP216.PROD.OUTLOOK.COM (2603:1096:301:a8::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7519.36; Tue, 30 Apr 2024 01:39:11 +0000 Received: from SL2P216MB1246.KORP216.PROD.OUTLOOK.COM ([fe80::5b8:35f1:821f:4f57]) by SL2P216MB1246.KORP216.PROD.OUTLOOK.COM ([fe80::5b8:35f1:821f:4f57%2]) with mapi id 15.20.7519.035; Tue, 30 Apr 2024 01:39:11 +0000 From: Nas Chung To: mchehab@kernel.org, nicolas@ndufresne.ca, sebastian.fricke@collabora.com Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, hverkuil@xs4all.nl, nas.chung@chipsnmedia.com, lafley.kim@chipsnmedia.com, b-brnich@ti.com, jackson.lee@chipnsmedia.com, "Jackson.lee" Subject: [PATCH v3 4/4] media: chips-media: wave5: Support YUV422 raw pixel-formats on the encoder. Date: Tue, 30 Apr 2024 10:39:00 +0900 Message-Id: <20240430013900.187-5-nas.chung@chipsnmedia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240430013900.187-1-nas.chung@chipsnmedia.com> References: <20240430013900.187-1-nas.chung@chipsnmedia.com> X-ClientProxiedBy: SL2P216CA0211.KORP216.PROD.OUTLOOK.COM (2603:1096:101:19::19) To SL2P216MB1246.KORP216.PROD.OUTLOOK.COM (2603:1096:101:a::9) Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SL2P216MB1246:EE_|PU4P216MB1324:EE_ X-MS-Office365-Filtering-Correlation-Id: b39bdff6-ed38-4a8b-7be6-08dc68b6559b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|52116005|376005|366007|38350700005; X-Microsoft-Antispam-Message-Info: rGpZp02/u6iXNL9/Mc6jUVPKam4xZ1WEBmAROEvgUl8Y1Rf/j2snMcEmvWhwJDuR4tbxMuYA6lo71yFmsN9or36yIbKcKgcL+JK8axALTKZKboKrxa0WVv6Ln2LIBtwwWsO2QoLs1RR3WJwW3UVITl4lS80jkkV9K1Xn3WWz7BXax3FYajy2tb+qSBDB9Y/BVv5Ia975ETo5exA2k9uPQ3Tz4HZ9fOo+YGCa2twesfRKgJOhv2DPJuxgEyG/dInQ3BBmCIh4ih1jAY22CC8CfbW7f9tAqQfUkaL5lccU8CNcMcii3aq+QMt3D59C9w5RLEwE1juA+s/y63gM0ztDUBYUasm1rpVJ//OjsjkDQMR0CQHppoyDek4umv2ZjJ0PsKu5rDfK4QiRoJLkgvVmyGev7Sp2TS82cxM1YJegYqqmR/dS4ObfWVmWPDWzdcNzYkHhCUQmENGUHZNbsAqAeUab40pI610I5I6aIBWukNDpWcc8YrkSZ2BHPWTkBc//o0NBADwFmG2vrXwBwXFyuQtdAuzH8LtfErxgS+olJHFE6Ow6J6eKemar87FWKC7hzVu+iT2/wKDdSvJaN2ma6KevSM1NaFmB9OMCggBI4cjE7++4kl/du+2Lu7IcDM5MU9WP7LiIvcIEgWn53LYItzwWAIYMDG7XJDcCuS9CLd5EfMRUChCc9z8fAiTIZ+QPPwZ9ykZE2iurtT3JlOxiDYMfR8K5FsvrvVZWEPVGOMPJB9ylczd9UFxwMXI1w0HhtewfxhIp9apa/fe1OfcFS2l/V87Oo3TE1EFcEsFoV+DkBbRENxFOTTgVKhtvLy9a+eXVEQR0xBq4j1sVvXcbr8EP4JA/39zKUIr8Sw2uYMxC4w4f23P544XZTguVVSHU8AWFwNzDEPjsmEQgJ6E0MCqHO3qYKnKP7GEGj22IOVOe0W0+gGWdgb+fVlblAjLOw0NXCWEX6WVWoiPvXEGZwz2JaCJJC765bJsBGidWSmkHzQxu0G7SyHEN9HVEAgcHQClhloGqrhf0BLmNr5qT5+XpIurIhvNN46MDtvz0BfekXMPnKok0OqymI7P4nYvwbES3wxejclcNjoWWZrcWWd3qFJWTlvX9eR1VsyYG++AwFRtbcE2/Bb8hPCg9iSKUSUH0vkh2dn0kTYQUPJEX0LAb/fmz2KPhioYlEH5Ilml+yD0dCSe62HlFIQBB/A4P1d6ekv21JN+4JkKEd0dbvqkAgI3R8GTukKv6ugTCdU4wvems5+n+FtOF/9q68ZjHzsVfS2uewE7g2QvxAor3SmUaoTQoUhxC5NidGPYF7/QARZYtK3GmKkBPfCy1Y1qtA2xny9ASc9Tr6I/VIPmIsw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SL2P216MB1246.KORP216.PROD.OUTLOOK.COM;PTR:;CAT:NONE;SFS:(13230031)(1800799015)(52116005)(376005)(366007)(38350700005);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: blG7TrdS6lD1kcatld35V7fEtt5gIzvvy7YmM167Cpc9wR3gA1y9tW3fFdRPhSLc1GFLdG47W/18IpipYzXBL8hAqMJUxiseHkJhYaqy4GmqN2WoZMgZ3TC+xvzwJCFPeGG/ezfabPNcm2b0j7nzsodnpNVRafF+U5Bf7l/U9KOOQrRzqdaX+EuMOz45Cs26+qMdyFMRFGSsGWWxaMILQV14+bT5BLEwXreyV1UTZFEYYkCIZBc2NU0iqabYPkp5rGYdELW3DNh3Ya0vFVZU4Q9EPsTGywe90udo44eIyWwoGgY/dCklYDuOLU03GVQ9VZZo+1asyKna0JKkLVulnJaSqyaldZZKU1VXr4R0yphpcJM/6IbaC2bcKcFJjRQ+ogHl/fLQY4LSmwPk7OhRK7Uls6gb0fSmdVRrRWsJsk6/0vASrYRV3z433o82EGmhdwnacDTeyfHe4KyKtKAUe0X3X233YAnKVFaajERjIchKrYuff+keNiBJXbTU+Cy+RDYXRNup07j+jxH6UfFhLj5ODg9dGgDxmBagMbtAOCm4ncdzXhgPjm6eZBcIXPMzwkMaJ9YZyhgB5dF06p4kF2McXZ2yAJ1jx63XSUn7oz0POgud0oOCUg6syAeHSn+8HNymmzOZyGFrp9s1nCwSx5fTZBdOUpd6PM2R5NOMTOCbzluUHuME1qrzgzPwgr/k09atwYDGaV8vq+3FXMXnOo8CWiKGQD+IBr+usnANsLmSYCshd2fVBKBlt41MiRxgjKKWz1IWj00kxOH+UE9WwmVX4TZfOU77NtFrxoQk4SIf4tLhAfdEVJTpUhm5Svog4tuU/gk8QnX9c3o/TBB8l7e8qBWaMF58+f5feJct96COYrSdqUug9ApNHR6lgU8ggFZpjq6F2meljBau2CQ0u2OXU+qVAzXBGH3OJwhRszhZFi3aBFz33oYzY7Oxnn/L3UjAlgfBjiBYAQI3paeBoBWwTqcrEzDM1iQ8Vns0xx3ysyVSvxiJEviZFCJmEFMnyIau3X+/RtzXipMBgzPLWfxD1VkKILmU0b6uO0EhLj1tYVelLrlUxs/8zfFP1bO9lyPN93nRLNA6evWnj6RsGM3wVJGnrqAniuKVQKCW8ds0zLfpXPv9LVX33R5QUnbInbny6/lsGzIcbMwWtWXFLZSOD1Whr+mxKh8Q7PoDUpr01s028z/2kvSITljosKni4Oadklew9lOEVRMv6A2kq/yyBa1z1XgCnroBoWMgywHIvwxuSdc5E/8EpMYMUwCcJxSk/JzIP8y6sF2B5tSsH+lprEvAoNpFdW0kL/20y6ZPsZVgpoGJ/cKcTcjDxbqUxYtoxccwhxp1VwFrjoiODMbnOoJ56tkhBL8uiP5EP4ivJGHwbLuI2RJJ5ICUYx2VL7wkI8IVTiqzY7wQo1WCzloghR1H0MD2SRA92yh6Sb9lI+WdaHBVb9ECXWwylg5yu9/HGmT4a0cgyEM4qylCfuGdpDCYizBVlS9Ug22qcMRVcNr33y3h4Za7XwqLGh5sXXGrAbGS0w/cQDA1X7cuGjv0Dl2m5P9FW//bOCsZNtSeth5y7xKt1cuHTrPVNdlcbg3KIyjc6frV89gmJEZvIw== X-OriginatorOrg: chipsnmedia.com X-MS-Exchange-CrossTenant-Network-Message-Id: b39bdff6-ed38-4a8b-7be6-08dc68b6559b X-MS-Exchange-CrossTenant-AuthSource: SL2P216MB1246.KORP216.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2024 01:39:11.1101 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4d70c8e9-142b-4389-b7f2-fa8a3c68c467 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: gQFBL71WBWljVz/IkDdFLdsxsix/xJr+Tn0cIvrwNwBSTl5UG44d8vn/sdmswrGcADdmHzqyml65u65j67UFmp50n42Qah8ZRK4/YJPwudg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PU4P216MB1324 From: "Jackson.lee" Add support for the YUV422P, NV16, NV61, YUV422M, NV16M, NV61M raw pixel-formats to the Wave5 encoder. All these formats have a chroma subsampling ratio of 4:2:2 and therefore require a new image size calculation as the driver previously only handled a ratio of 4:2:0. Signed-off-by: Jackson.lee Signed-off-by: Nas Chung --- .../chips-media/wave5/wave5-vpu-enc.c | 59 +++++++++++++++++-- 1 file changed, 54 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c index 75d230df45f6..0d6bec4e28d1 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c @@ -66,6 +66,24 @@ static const struct vpu_format enc_fmt_list[FMT_TYPES][MAX_FMTS] = { .v4l2_pix_fmt = V4L2_PIX_FMT_NV21M, .v4l2_frmsize = &enc_frmsize[VPU_FMT_TYPE_RAW], }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_YUV422P, + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_NV16, + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_NV61, + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_YUV422M, + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_NV16M, + }, + { + .v4l2_pix_fmt = V4L2_PIX_FMT_NV61M, + }, } }; @@ -109,13 +127,30 @@ static int start_encode(struct vpu_instance *inst, u32 *fail_res) struct vb2_v4l2_buffer *dst_buf; struct frame_buffer frame_buf; struct enc_param pic_param; - u32 stride = ALIGN(inst->dst_fmt.width, 32); - u32 luma_size = (stride * inst->dst_fmt.height); - u32 chroma_size = ((stride / 2) * (inst->dst_fmt.height / 2)); + u32 stride = inst->src_fmt.plane_fmt[0].bytesperline; + u32 luma_size = (stride * inst->src_fmt.height); + u32 chroma_size = 0; memset(&pic_param, 0, sizeof(struct enc_param)); memset(&frame_buf, 0, sizeof(struct frame_buffer)); + if (inst->src_fmt.pixelformat == V4L2_PIX_FMT_YUV420 || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_YUV420M) + chroma_size = luma_size / 4; + else if (inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV12 || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV21 || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV12M || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV21M) + chroma_size = luma_size / 2; + else if (inst->src_fmt.pixelformat == V4L2_PIX_FMT_YUV422P || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_YUV422M) + chroma_size = luma_size / 2; + else if (inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV16 || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV61 || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV16M || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV61M) + chroma_size = luma_size; + dst_buf = v4l2_m2m_next_dst_buf(m2m_ctx); if (!dst_buf) { dev_dbg(inst->dev->dev, "%s: No destination buffer found\n", __func__); @@ -501,11 +536,15 @@ static int wave5_vpu_enc_s_fmt_out(struct file *file, void *fh, struct v4l2_form } if (inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV12 || - inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV12M) { + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV12M || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV16 || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV16M) { inst->cbcr_interleave = true; inst->nv21 = false; } else if (inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV21 || - inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV21M) { + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV21M || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV61 || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV61M) { inst->cbcr_interleave = true; inst->nv21 = true; } else { @@ -1102,6 +1141,16 @@ static void wave5_set_enc_openparam(struct enc_open_param *open_param, u32 num_ctu_row = ALIGN(inst->dst_fmt.height, 64) / 64; u32 num_mb_row = ALIGN(inst->dst_fmt.height, 16) / 16; + if (inst->src_fmt.pixelformat == V4L2_PIX_FMT_YUV422P || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV16 || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV61 || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_YUV422M || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV16M || + inst->src_fmt.pixelformat == V4L2_PIX_FMT_NV61M) + open_param->src_format = FORMAT_422; + else + open_param->src_format = FORMAT_420; + open_param->wave_param.gop_preset_idx = PRESET_IDX_IPP_SINGLE; open_param->wave_param.hvs_qp_scale = 2; open_param->wave_param.hvs_max_delta_qp = 10;