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[86.12.82.21]) by smtp.gmail.com with ESMTPSA id p8-20020a5d48c8000000b0034af40b2efdsm23595951wrs.108.2024.04.30.03.44.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 03:44:12 -0700 (PDT) From: Connor Abbott Date: Tue, 30 Apr 2024 11:43:15 +0100 Subject: [PATCH v3 1/6] arm64: dts: qcom: sm8650: Fix GPU cx_mem size Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240430-a750-raytracing-v3-1-7f57c5ac082d@gmail.com> References: <20240430-a750-raytracing-v3-0-7f57c5ac082d@gmail.com> In-Reply-To: <20240430-a750-raytracing-v3-0-7f57c5ac082d@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jun Nie , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714473850; l=1032; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=HdWAhjQ4Ivj20LLc1l3rIJf0eWqfBf5t1jj2qSpI0Qs=; b=uqOrau62L/MfHeD5TX92TkT+xOevf/c/Yi4elm/DQW1IHtSszoYJpU80NmvEDFBiFwqgvpNzT ru8WS1Ozt+MD8t4lnszsEdOAc8twvwEJ260RmG9Jd4qSSb/yCy/K/ah X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= This is doubled compared to previous GPUs. We can't access the new SW_FUSE_VALUE register without this. Fixes: db33633b05c0 ("arm64: dts: qcom: sm8650: add GPU nodes") Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Connor Abbott Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 658ad2b41c5a..78b8944eaab2 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2607,7 +2607,7 @@ tcsr: clock-controller@1fc0000 { gpu: gpu@3d00000 { compatible = "qcom,adreno-43051401", "qcom,adreno"; reg = <0x0 0x03d00000 0x0 0x40000>, - <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d9e000 0x0 0x2000>, <0x0 0x03d61000 0x0 0x800>; reg-names = "kgsl_3d0_reg_memory", "cx_mem", From patchwork Tue Apr 30 10:43:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Connor Abbott X-Patchwork-Id: 13648745 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABBB912D1F6; Tue, 30 Apr 2024 10:44:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714473857; cv=none; b=YQmh2IvAVSadQAmI9qy+hl7bH1tU54dcFUBC64SfkfLQ1PSkxo/87ciQJPMyPOyuFeg3dSPrsyojOuvfTBv0K89y8ylGrCdoEx966aiZ6fqfeKGQaFu2y/ekEPzMc9aRKwmzjJ1ktmwBNmd0Uwa98sIZEDl0dB+Kz+RWlmY/wjA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714473857; c=relaxed/simple; bh=TKn/26YnezLy20U/najOcBKpivRdMFdNQbNQd8UXKNg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=W8ar65lqoe9HfxfPE8WBrZIk2hPMBX8Ik1EEM6ZaUch+zRfuxqHI+0oUBzcqEzuMV1+fKDXpajsbyQvI7q4sDk45C5/7RLRbIFX/qJ9IFu6PxjNQsemAToxNjLmlhq0k+RYWq1wEiD7wDf1DEpWt6PsumwEyvRalbKcmZaQ+w6s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=JrN59H0Z; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JrN59H0Z" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-343c891bca5so4174893f8f.2; Tue, 30 Apr 2024 03:44:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1714473854; x=1715078654; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qmr8dTXmjB4R2TIC3iha2y597f6KErUdWQLGHd0Q118=; b=JrN59H0Z09rSyeNZw11YcPu4dh5xptbrIvJ0NDP/pplxAlqfdOrZF65KM+jndQi38f i641A6FXRVV6D9+2Qzjb0o4+SAOtEQC11JuRAMkokSG/Z0ZicB4qFEcXa8lY1sSAmd01 6AcUJoB/MejLK3AiYG/PvKpgQjtYm98wY70/xD6vShqY8WtE04JsuhC6wE1wDVW5w5of 7PYR326fJvd2Tk32+J4rLuE6gW3Dx3ErSjLo7yZyyajmKPqSlUuRyOy2qRMYq4ZAxiCk gwYymECyYOSbr/5o2TgGh+k2WnUCgUUoz23RDV03skoggW3sAIh+wMdrGHtME0fs9GvT SqsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714473854; x=1715078654; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qmr8dTXmjB4R2TIC3iha2y597f6KErUdWQLGHd0Q118=; b=llymP/Kmw99jzKgQfuiP9R8OnSlanbdqj1NVxsV5b99RcdqNeQ0ZW+nUtofKx6H1wM BUbMxMzVBxzyQXnqstHxL2RMNQud/Ys1rkAE9LSrQHfX9J+AGvwAcwceSu5WYIk5Aw95 p7xiOXT0e1Zi8FnOX3jzfrB8URnzDVix91KKeYGAYaLaUr2pGlthv3PvAHcWhRWiT2Yg 14zowfFPLw/8v9XNr8O3U2VTyUNNRIxOGiznD6Mkl2SBlUnFTtRf3UZoh3weXWZECIQv Ah1ZDSeSr1FBxhZjVGdl38DXh6hzzct2zDPhonWUJjHeL5K4B+xUfjvfSX/mHXTB+ZSG eTyg== X-Forwarded-Encrypted: i=1; AJvYcCU2v8a5+WVe1Rf0A9KwV0Wl4IWer+P+/JFJTceD7CMqJk40PoIVHNgTdzEf0VRAyFugMibi7UHdnbdXd+gdG88ssoSuzN9NDBwMXw== X-Gm-Message-State: AOJu0Yyp7Lh+33yqgA4f/AGRvv5z8qblErZbkaWALqYSjEMaVvC6nzmY c+pWjhW5PHYp9GHN+pFKyTzjMyxHKqyKYKxwXENUkhN5eBwfadYm X-Google-Smtp-Source: AGHT+IEUFFGWrUGe08CoaGquY4VjJG9mPVI5jXUW4owBwPoZnD3wgvmo/zcbryoI/p0af2SnsBFKHA== X-Received: by 2002:adf:f3ce:0:b0:34c:5e02:7875 with SMTP id g14-20020adff3ce000000b0034c5e027875mr10581370wrp.7.1714473853973; Tue, 30 Apr 2024 03:44:13 -0700 (PDT) Received: from [192.168.0.20] (cpc115152-dals23-2-0-cust532.20-2.cable.virginm.net. [86.12.82.21]) by smtp.gmail.com with ESMTPSA id p8-20020a5d48c8000000b0034af40b2efdsm23595951wrs.108.2024.04.30.03.44.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 03:44:13 -0700 (PDT) From: Connor Abbott Date: Tue, 30 Apr 2024 11:43:16 +0100 Subject: [PATCH v3 2/6] firmware: qcom_scm: Add gpu_init_regs call Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240430-a750-raytracing-v3-2-7f57c5ac082d@gmail.com> References: <20240430-a750-raytracing-v3-0-7f57c5ac082d@gmail.com> In-Reply-To: <20240430-a750-raytracing-v3-0-7f57c5ac082d@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jun Nie , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714473850; l=3010; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=TKn/26YnezLy20U/najOcBKpivRdMFdNQbNQd8UXKNg=; b=nPXAL5pTBU3gEo3QipQ3oHu24CwT1kTMGwXQ2e1evASNv9IS9+ltjYA0BdCb76JBdN8yEVw7I brgVzcZN8QFATIQo6+2IgaBmyMiijI59GWahL+u1IZxT2C359DGv9QZ X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= This will used by drm/msm to initialize GPU registers that Qualcomm's firmware doesn't make writeable to the kernel. Reviewed-by: Dmitry Baryshkov Signed-off-by: Connor Abbott Reviewed-by: Konrad Dybcio Acked-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm.c | 14 ++++++++++++++ drivers/firmware/qcom/qcom_scm.h | 3 +++ include/linux/firmware/qcom/qcom_scm.h | 23 +++++++++++++++++++++++ 3 files changed, 40 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 06e46267161b..f8623ad0987c 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -1394,6 +1394,20 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, } EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh); +int qcom_scm_gpu_init_regs(u32 gpu_req) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_GPU, + .cmd = QCOM_SCM_SVC_GPU_INIT_REGS, + .arginfo = QCOM_SCM_ARGS(1), + .args[0] = gpu_req, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + return qcom_scm_call(__scm->dev, &desc, NULL); +} +EXPORT_SYMBOL_GPL(qcom_scm_gpu_init_regs); + static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) { struct device_node *tcsr; diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_scm.h index 4532907e8489..484e030bcac9 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -138,6 +138,9 @@ int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_WAITQ_RESUME 0x02 #define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03 +#define QCOM_SCM_SVC_GPU 0x28 +#define QCOM_SCM_SVC_GPU_INIT_REGS 0x01 + /* common error codes */ #define QCOM_SCM_V2_EBUSY -12 #define QCOM_SCM_ENOMEM -5 diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index aaa19f93ac43..a221a643dc12 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -115,6 +115,29 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, int qcom_scm_lmh_profile_change(u32 profile_id); bool qcom_scm_lmh_dcvsh_available(void); +/* + * Request TZ to program set of access controlled registers necessary + * irrespective of any features + */ +#define QCOM_SCM_GPU_ALWAYS_EN_REQ BIT(0) +/* + * Request TZ to program BCL id to access controlled register when BCL is + * enabled + */ +#define QCOM_SCM_GPU_BCL_EN_REQ BIT(1) +/* + * Request TZ to program set of access controlled register for CLX feature + * when enabled + */ +#define QCOM_SCM_GPU_CLX_EN_REQ BIT(2) +/* + * Request TZ to program tsense ids to access controlled registers for reading + * gpu temperature sensors + */ +#define QCOM_SCM_GPU_TSENSE_EN_REQ BIT(3) + +int qcom_scm_gpu_init_regs(u32 gpu_req); + #ifdef CONFIG_QCOM_QSEECOM int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id); From patchwork Tue Apr 30 10:43:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Connor Abbott X-Patchwork-Id: 13648746 Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 461D212C7E3; Tue, 30 Apr 2024 10:44:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714473859; cv=none; b=mx4/JRaWl916ei2A6BKy3Ymx5d5fKl9PrQl5fiq7X3lprFt94rFR+qX36gaDC33BVHWLxhZwgM0RJRtXCMvmQM9OIGmlVM6WAOJRlh+VH+9nDWfV6nWquarkFNf0B0wknyRtmZ3dBB66VVeg2obISWkXXwqYiw06pFaelgIog/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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[86.12.82.21]) by smtp.gmail.com with ESMTPSA id p8-20020a5d48c8000000b0034af40b2efdsm23595951wrs.108.2024.04.30.03.44.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 03:44:14 -0700 (PDT) From: Connor Abbott Date: Tue, 30 Apr 2024 11:43:17 +0100 Subject: [PATCH v3 3/6] drm/msm: Update a6xx registers Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240430-a750-raytracing-v3-3-7f57c5ac082d@gmail.com> References: <20240430-a750-raytracing-v3-0-7f57c5ac082d@gmail.com> In-Reply-To: <20240430-a750-raytracing-v3-0-7f57c5ac082d@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jun Nie , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714473850; l=4625; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=c+88p0lQCwZBgjudS09WX2xUrrowQXi3V2QQ7pRe9KE=; b=eB1tOZ9YUFlMBVXS2hBViZlVbaW1iwBz+gRI2uiBFiMv2WxAR/dFFF8fIfY6VOgRs8WvvImwr kxGtqYMKS4EDXuggoE39jDmRNwKmDRc8gCRvQAZXrF28Q4Arph5zoPz X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= Update to mesa commit ff155f46a33 ("freedreno/a7xx: Register updates from kgsl"). Reviewed-by: Dmitry Baryshkov Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 28 ++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml index 78524aaab9d4..43fe90c12679 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -1227,6 +1227,7 @@ to upconvert to 32b float internally? + @@ -1503,6 +1504,9 @@ to upconvert to 32b float internally? + + + @@ -2842,7 +2846,11 @@ to upconvert to 32b float internally? - + + RB_SAMPLE_COUNT_ADDR register is used up to (and including) a730. After that + the address is specified through CP_EVENT_WRITE7::WRITE_SAMPLE_COUNT. + + @@ -2950,7 +2958,7 @@ to upconvert to 32b float internally? - + @@ -3306,6 +3314,15 @@ to upconvert to 32b float internally? + + + + + @@ -4293,7 +4310,7 @@ to upconvert to 32b float internally? - + @@ -4965,6 +4982,11 @@ to upconvert to 32b float internally? + + + + + From patchwork Tue Apr 30 10:43:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Connor Abbott X-Patchwork-Id: 13648747 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 032D612D1F6; Tue, 30 Apr 2024 10:44:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714473860; cv=none; b=KHcnogfTygXRaUeytCOwLz7Pj/nABYFbEZnzDNx0mo1/MEY0uiQsNx8o9gYVD5MkBt/k9fPJ8VRf1CxpWEeIg23C3y06101P7y3gpbxQ4OI3tPXbOgfMljeLlNgRu/BMURHpSLcg55CFkTB/RqJ65PiLUXTL/nNdKEB2CJdSUqc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714473860; c=relaxed/simple; bh=xF43mVMcs8MO8ap+Pvdie9rN2riFcwBreI/fz5B9u2E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rXyvGT/qU9Kq966O6GL8R2/yTcOpVHC6SShNCVKaiye8ForQ0aAco8tblvJo0vGPAO2/zsOd9w3Ap+y8t2tht0r6LrCIswDYWbGgFfiinRGSh8ehfszOiERsmse7DoCjWqSDuL9Tz2vEtX3Qcj80Ki9XxdUQsxvTDr6TXL46jFs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Zoc5pWHJ; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Zoc5pWHJ" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-41b4ff362a8so50762625e9.0; Tue, 30 Apr 2024 03:44:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1714473856; x=1715078656; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=swuWmjFhwBOQQWEST6sVjksYDm7049vHTM6meYi4ink=; b=Zoc5pWHJTmTDu6wGvwkgO81wJJUFa+Ucoz6PXu9nfSihpLGvwONP6/nVlSbXMNjj7v uc0b1OYmy0WLSkgcmMVyuYsTs73rpxxx9ctofYNI9lwf8jZ6AilA7fkv/FHHXNjl4tid ZdmRI1VupUrKI6zpicinqx6GDq+YF6StTPss4u7dB2zdOfXewHCBLAtIEZ0XFifzbiCw RVVf4TIsptOclyUNsdHxi85vIUPwaK06lNg7n3w3jIGZrMx8wQ/PJsgbr0Iyp8EHw2Up P1nlmnKacKe6Toheam/2fppDaqpGf8kZYrHQNFO/OwjUpV4kg7+85+PqwfRRWV14e8lN 6SqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714473856; x=1715078656; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=swuWmjFhwBOQQWEST6sVjksYDm7049vHTM6meYi4ink=; b=R4oEDcOkST9XorTvqr4aEpNwpISPTyXjbL4VU0d+QV1wHH/gQErOI/NkAMGMYUEcl8 1Fbdtdk1usMXpONN4zwkipzeILpsNbG5+S4H4xmZuD2O+xAUolppFugAvrqyeozx9ItN Qh6jclmZcqVAZQHtvtCD9U+lCbooZHULDS80/x6HFJyCMWHDpqVOgyn9/JB0YYZ1RluL sOMp/oJ7DCVw/IjswV/YIdkW+lATQ10SFWa95VDFHvFl53X98V4E/QW42+QdaMvzRk0/ wq73q0/Vfs8kddad9ldYrDIbWETHCwJPV6EMYtBnHE3yQcUwgGMaUgbW7tnqQLQvpuHW 7tWg== X-Forwarded-Encrypted: i=1; AJvYcCXgnJR0x7QL12Gu4NRaXgNRGuwqodsWJ2vFglpiYt7VoEKrH/n4ZJ+ghIKdkrSyFGYfoLEPc+Dds0BE+9OYhD9k5VeD88GmsBJXiQ== X-Gm-Message-State: AOJu0Yx21eVBPcUmJSQH61wcGhAeMa93boHSKlCSqGi2FJsy4sGFm6Ha FRsikSDKZWSaLXcVffTRTjbbgVms227OHpyle4Hn5V5tQu8TqeZl X-Google-Smtp-Source: AGHT+IFi6+edvCSxnzf227DMOGNourKZAJBz19Un/ND/aUahCcDGagndZMi5CpKzrvoQAAm0Jy+d0w== X-Received: by 2002:a05:600c:1910:b0:41a:e5f5:99f8 with SMTP id j16-20020a05600c191000b0041ae5f599f8mr14083300wmq.18.1714473856345; Tue, 30 Apr 2024 03:44:16 -0700 (PDT) Received: from [192.168.0.20] (cpc115152-dals23-2-0-cust532.20-2.cable.virginm.net. [86.12.82.21]) by smtp.gmail.com with ESMTPSA id p8-20020a5d48c8000000b0034af40b2efdsm23595951wrs.108.2024.04.30.03.44.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 03:44:15 -0700 (PDT) From: Connor Abbott Date: Tue, 30 Apr 2024 11:43:18 +0100 Subject: [PATCH v3 4/6] drm/msm/a7xx: Initialize a750 "software fuse" Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240430-a750-raytracing-v3-4-7f57c5ac082d@gmail.com> References: <20240430-a750-raytracing-v3-0-7f57c5ac082d@gmail.com> In-Reply-To: <20240430-a750-raytracing-v3-0-7f57c5ac082d@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jun Nie , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714473850; l=5711; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=xF43mVMcs8MO8ap+Pvdie9rN2riFcwBreI/fz5B9u2E=; b=ml+XbxWc/FevhKhPUQSK8jdB1mGNA2fFpD01wXiUnSIYZHZ6sq7FvLSvSG36tiMBS7cdJCShB YemrvM2Rp7ICLQjBrk5Y1QiuSBFR7nkmwrRoukFJUbucVTkkbyCNgUu X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled. Reviewed-by: Dmitry Baryshkov Signed-off-by: Connor Abbott Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 91 ++++++++++++++++++++++++++++++++- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 + 2 files changed, 92 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index cf0b1de1c071..52b080206090 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -10,6 +10,7 @@ #include #include +#include #include #include @@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu) A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \ - A6XX_RBBM_INT_0_MASK_TSBWRITEERROR) + A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \ + A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \ A6XX_CP_APRIV_CNTL_RBFETCH | \ @@ -2356,6 +2358,27 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu) kthread_queue_work(gpu->worker, &gpu->recover_work); } +static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu) +{ + u32 status; + + status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS); + gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0); + + dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status); + + /* + * Ignore FASTBLEND violations, because the HW will silently fall back + * to legacy blending. + */ + if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) { + del_timer(&gpu->hangcheck_timer); + + kthread_queue_work(gpu->worker, &gpu->recover_work); + } +} + static irqreturn_t a6xx_irq(struct msm_gpu *gpu) { struct msm_drm_private *priv = gpu->dev->dev_private; @@ -2384,6 +2407,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu) if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); + if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION) + a7xx_sw_fuse_violation_irq(gpu); + if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) msm_gpu_retire(gpu); @@ -2525,6 +2551,61 @@ static void a6xx_llc_slices_init(struct platform_device *pdev, a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL); } +static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu) +{ + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + struct msm_gpu *gpu = &adreno_gpu->base; + u32 fuse_val; + int ret; + + if (adreno_is_a750(adreno_gpu)) { + /* + * Assume that if qcom scm isn't available, that whatever + * replacement allows writing the fuse register ourselves. + * Users of alternative firmware need to make sure this + * register is writeable or indicate that it's not somehow. + * Print a warning because if you mess this up you're about to + * crash horribly. + */ + if (!qcom_scm_is_available()) { + dev_warn_once(gpu->dev->dev, + "SCM is not available, poking fuse register\n"); + a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, + A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | + A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND | + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC); + adreno_gpu->has_ray_tracing = true; + return 0; + } + + ret = qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ | + QCOM_SCM_GPU_TSENSE_EN_REQ); + if (ret) + return ret; + + /* + * On a750 raytracing may be disabled by the firmware, find out + * whether that's the case. The scm call above sets the fuse + * register. + */ + fuse_val = a6xx_llc_read(a6xx_gpu, + REG_A7XX_CX_MISC_SW_FUSE_VALUE); + adreno_gpu->has_ray_tracing = + !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING); + } else { + if (adreno_is_a740(adreno_gpu)) { + /* Raytracing is always enabled on a740 */ + adreno_gpu->has_ray_tracing = true; + } + + if (qcom_scm_is_available()) + return qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ); + } + + return 0; +} + + #define GBIF_CLIENT_HALT_MASK BIT(0) #define GBIF_ARB_HALT_MASK BIT(1) #define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) @@ -3094,6 +3175,14 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) return ERR_PTR(ret); } + if (adreno_is_a7xx(adreno_gpu)) { + ret = a7xx_cx_mem_init(a6xx_gpu); + if (ret) { + a6xx_destroy(&(a6xx_gpu->base.base)); + return ERR_PTR(ret); + } + } + if (gpu->aspace) msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, a6xx_fault_handler); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 77526892eb8c..4180f3149dd8 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -182,6 +182,8 @@ struct adreno_gpu { */ const unsigned int *reg_offsets; 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[86.12.82.21]) by smtp.gmail.com with ESMTPSA id p8-20020a5d48c8000000b0034af40b2efdsm23595951wrs.108.2024.04.30.03.44.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 03:44:17 -0700 (PDT) From: Connor Abbott Date: Tue, 30 Apr 2024 11:43:19 +0100 Subject: [PATCH v3 5/6] drm/msm: Add MSM_PARAM_RAYTRACING uapi Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240430-a750-raytracing-v3-5-7f57c5ac082d@gmail.com> References: <20240430-a750-raytracing-v3-0-7f57c5ac082d@gmail.com> In-Reply-To: <20240430-a750-raytracing-v3-0-7f57c5ac082d@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jun Nie , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714473850; l=1613; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=FHi4AR63j8pWNcngvHBYBnb8PtEsuBHPoSnbfH71DYk=; b=dffNInQzX2nF4l+Id/KBjq+vNO6/wAHoumSVYQ+CoEIPikRgfVSFtXNjP0PNNzanPj5Rm5j3l Rltt35ZByNqCd5FO/32dB1Pmor0w+LWvxrwSKhQTonth3iUR1ecvoxJ X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= Expose the value of the software fuse to userspace. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Connor Abbott --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++ include/uapi/drm/msm_drm.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 074fb498706f..99ad651857b2 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -376,6 +376,9 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, case MSM_PARAM_HIGHEST_BANK_BIT: *value = adreno_gpu->ubwc_config.highest_bank_bit; return 0; + case MSM_PARAM_RAYTRACING: + *value = adreno_gpu->has_ray_tracing; + return 0; default: DBG("%s: invalid param: %u", gpu->name, param); return -EINVAL; diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index d8a6b3472760..3fca72f73861 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -87,6 +87,7 @@ struct drm_msm_timespec { #define MSM_PARAM_VA_START 0x0e /* RO: start of valid GPU iova range */ #define MSM_PARAM_VA_SIZE 0x0f /* RO: size of valid GPU iova range (bytes) */ #define MSM_PARAM_HIGHEST_BANK_BIT 0x10 /* RO */ +#define MSM_PARAM_RAYTRACING 0x11 /* RO */ /* For backwards compat. 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[86.12.82.21]) by smtp.gmail.com with ESMTPSA id p8-20020a5d48c8000000b0034af40b2efdsm23595951wrs.108.2024.04.30.03.44.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 03:44:18 -0700 (PDT) From: Connor Abbott Date: Tue, 30 Apr 2024 11:43:20 +0100 Subject: [PATCH v3 6/6] drm/msm/a7xx: Add missing register writes from downstream Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240430-a750-raytracing-v3-6-7f57c5ac082d@gmail.com> References: <20240430-a750-raytracing-v3-0-7f57c5ac082d@gmail.com> In-Reply-To: <20240430-a750-raytracing-v3-0-7f57c5ac082d@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jun Nie , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, freedreno@lists.freedesktop.org, Connor Abbott X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1714473850; l=1178; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=jmofaJ3QWKGh4FuQgnidJQUjJ4vAccqiIwWwk4VBoUk=; b=ujp5kRgQelCyVGrPXqO7Kl6H4xLU3dtkkFWc1xAKk6SPvxdAcmD/lCjWErIW2i2gG1Q8n+eOT XvDBjRqaVWmBj97gf7s7X4XErXC6is+dMOqDznpv0NP0SF0YmjR4s+R X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= This isn't known to fix anything yet, but it's a good idea to add it. Signed-off-by: Connor Abbott Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 52b080206090..24a4ed9bfea9 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1953,6 +1953,17 @@ static int hw_init(struct msm_gpu *gpu) BIT(6) | BIT(5) | BIT(3) | BIT(2) | BIT(1)); } + if (adreno_is_a750(adreno_gpu)) { + /* Disable ubwc merged UFC request feature */ + gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(19), BIT(19)); + + /* Enable TP flaghint and other performance settings */ + gpu_write(gpu, REG_A6XX_TPL1_DBG_ECO_CNTL1, 0xc0700); + } else if (adreno_is_a7xx(adreno_gpu)) { + /* Disable non-ubwc read reqs from passing write reqs */ + gpu_rmw(gpu, REG_A6XX_RB_CMP_DBG_ECO_CNTL, BIT(11), BIT(11)); + } + /* Enable interrupts */ gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, adreno_is_a7xx(adreno_gpu) ? A7XX_INT_MASK : A6XX_INT_MASK);