From patchwork Tue Apr 30 17:28:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649721 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EB56CC19F4F for ; Tue, 30 Apr 2024 17:30:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A50E3112D79; Tue, 30 Apr 2024 17:30:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="SAcNFm8s"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id D34C8112D76; Tue, 30 Apr 2024 17:30:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714498219; x=1746034219; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5HzJm4GT4INborqvKvQvE+N+FeItI1VA49CQYkUMHck=; b=SAcNFm8s8nxuFOKy5JK4YmU/gwVya23SuEs+jMt+GQ0kaeGITcx1H+OG fX91fwyFgqb0aOiZrsuTNdP+Mv1J9K7OKycVMianQDiw3P5d5+7gcQ2vu tZzQWgnwtVSESk9TLfj3dJtH8Eu6Nn0XuM01HHpKc+njuBU+0NDSLqmmD U3DmQgOA6VaqyB1f818UN6NEEyHkJYoeO+KGvrs6ePOry/Y5MEDSWU9Hf VYJab+nfGPDI9Z1MTv3GiFpL9a5spMv6SrEtI/G+E+xtJhOCOwXAAh1U0 iBC/kCQzwzC7FPekOL41uLuu0e64pcAYz4V1mdqo5xgkmFdGqeewYHTGg A==; X-CSE-ConnectionGUID: S5oeyzj1Q7Oje9KPf/eDmw== X-CSE-MsgGUID: zcZTfWNeRfqUIRXN5duasw== X-IronPort-AV: E=McAfee;i="6600,9927,11060"; a="27741983" X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="27741983" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:18 -0700 X-CSE-ConnectionGUID: pOdfV7DvR/KTfqrQL8Q5aw== X-CSE-MsgGUID: oFYb2qbqR067lkSmhRq6+w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617813" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:19 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Clint Taylor , Jani Nikula , Balasubramani Vivekanandan , Matt Roper , Radhakrishna Sripada Subject: [PATCH v3 01/19] drm/i915/bmg: Lane reversal requires writes to both context lanes Date: Tue, 30 Apr 2024 10:28:32 -0700 Message-Id: <20240430172850.1881525-2-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Clint Taylor Write both CX0 Lanes for Context Toggle for all except TC pin assignment D. v2: Update title(RK) Bspec: 64539 CC: Jani Nikula Signed-off-by: Clint Taylor Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 8e3b13884bb8..9930fa7313e4 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2337,7 +2337,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, { const struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; bool dp = false; - int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0; + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); u32 clock = crtc_state->port_clock; bool cntx; int i; @@ -2402,19 +2402,19 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, } /* 4. Program custom width to match the link protocol */ - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_WIDTH, + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH, PHY_C20_CUSTOM_WIDTH_MASK, PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(clock, dp)), MB_WRITE_COMMITTED); /* 5. For DP or 6. For HDMI */ if (dp) { - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, BIT(6) | PHY_C20_CUSTOM_SERDES_MASK, BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(clock)), MB_WRITE_COMMITTED); } else { - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, BIT(7) | PHY_C20_CUSTOM_SERDES_MASK, is_hdmi_frl(clock) ? BIT(7) : 0, MB_WRITE_COMMITTED); @@ -2428,7 +2428,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, * 7. Write Vendor specific registers to toggle context setting to load * the updated programming toggle context bit */ - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED); } From patchwork Tue Apr 30 17:28:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649723 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 02D7CC4345F for ; Tue, 30 Apr 2024 17:30:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F39C112D7C; Tue, 30 Apr 2024 17:30:22 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="QBOvh2Or"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 075D4112D77; Tue, 30 Apr 2024 17:30:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714498220; x=1746034220; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4tsmupxqeO8Z6MFrSKag5+FVL7bcRwU48HtTLaw3XpI=; b=QBOvh2OrU9hwxJ7xf2lGjnD5BFXcsltWtmznrXz97dDE/BNxurqoYLyz JelLUBayfZ5WOsb7Y71CP2dCVT0elHahWbzPda7c0hrwZEc9ukxZR9M/z fMgn1wiaMkxe3OqkKjllsJz8FezQw8++KVWX/Z7PQBiQ4xB8us6rBzuIM f8qPGuNU/JcXjsAjBto//mAE61J4wPiVF6oUitDQOBCtQ2pwTQh+RNXWI w8jk+4MoT8p/I3BLU0PC8LnmmocIs6INaxCWvFPa9LiYkxWI7ZPYGOtE+ wh2ebh/0xqLz3UUjL6K30MRpym1fFA6naQkaXQAVmlHKYIGhnOeMOQaj0 Q==; X-CSE-ConnectionGUID: PpMEblgdRQK3peUA7TY0nQ== X-CSE-MsgGUID: XCKwxffGQF6/RsQU8ZhkTA== X-IronPort-AV: E=McAfee;i="6600,9927,11060"; a="27741984" X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="27741984" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:19 -0700 X-CSE-ConnectionGUID: jgu950ZVQ12+61/YJxaOxg== X-CSE-MsgGUID: mlgP1bJLSG2IL7snCB56jg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617816" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:19 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Balasubramani Vivekanandan , Matt Roper , Radhakrishna Sripada Subject: [PATCH v3 02/19] drm/i915/bmg: Define IS_BATTLEMAGE macro Date: Tue, 30 Apr 2024 10:28:33 -0700 Message-Id: <20240430172850.1881525-3-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Balasubramani Vivekanandan Display code uses IS_BATTLEMAGE macro but the platform support doesn't exist in i915. So fake IS_BATTLEMAGE macro defined to enable building i915 code. We should make sure the macro parameter is used in the always-false expression so that we don't run into "unused variable" warnings from i915 builds if the IS_BATTLEMAGE() check is the only place the i915 pointer gets used in a function. While we're at it, also update the IS_LUNARLAKE macro to include the parameter in the false expression for consistency. Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/i915_drv.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ee0d7d5f135d..481ddce038b2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -535,7 +535,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) -#define IS_LUNARLAKE(i915) 0 +/* + * Display code shared by i915 and Xe relies on macros like IS_LUNARLAKE, + * so we need to define these even on platforms that the i915 base driver + * doesn't support. Ensure the parameter is used in the definition to + * avoid 'unused variable' warnings when compiling the shared display code + * for i915. + */ +#define IS_LUNARLAKE(i915) (0 && i915) +#define IS_BATTLEMAGE(i915) (0 && i915) #define IS_DG2_G10(i915) \ IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) From patchwork Tue Apr 30 17:28:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649719 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65FF0C10F16 for ; Tue, 30 Apr 2024 17:30:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DB45C112D78; Tue, 30 Apr 2024 17:30:20 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Rm2smwRU"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0A00C112D78; Tue, 30 Apr 2024 17:30:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714498220; x=1746034220; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=M/Augv4QApN+dSPQmN9/1exhM7/SjAqWXkbZ26nRHnU=; b=Rm2smwRUVrBL2QkTcBGK4RsnDZcbYjQm9JzAGKbYwhGXVO9XO8Ho5PuE bZd7KVUaryqSfxMx5SfwuHYF1JDVVxyvwrJteh9n87urr5Rgk3eEDnjsk ftrfVEvTu6Hi5DtWqrUXO/eiQNGHTqBnyQDOd2q/v0RBqXPW+tkseGOuQ PN8uSFCkvQhF1gUSDZnS8Yl2eb77fjaOvjscorBhf7I6nE+5uZ1nbgnfD 9GHPBCi9v3XlfZ+JcFaJ4zEaLnIfNd7AXE7bo/2M4IWGBgE4vGaY9JTr3 4DDn6CWAZdLLLQ9m2bVgarn4pIzxTrEeqq11uYTk7PIaRL3uD5EZM24wJ g==; X-CSE-ConnectionGUID: wMSUROPMR7aDsDP/bnuyOg== X-CSE-MsgGUID: pRjyjOtqRc+u5QV4yBlixQ== X-IronPort-AV: E=McAfee;i="6600,9927,11060"; a="27741987" X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="27741987" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:19 -0700 X-CSE-ConnectionGUID: 4W2D6InDRQ6tUgs7O5n6Gw== X-CSE-MsgGUID: P3pOHltnRd6bGDun28MIDA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617819" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:19 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Clint Taylor , Lucas De Marchi , Balasubramani Vivekanandan , Matt Roper , Radhakrishna Sripada Subject: [PATCH v3 03/19] drm/i915/xe2hpd: Initial cdclk table Date: Tue, 30 Apr 2024 10:28:34 -0700 Message-Id: <20240430172850.1881525-4-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Clint Taylor Add Xe2_HPD specific CDCLK table and use MTL Funcs. Bspec: 65243 CC: Lucas De Marchi Signed-off-by: Clint Taylor Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 7a833b5f2de2..b78154c82a71 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1443,6 +1443,14 @@ static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = { {} }; +/* + * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771 + */ +static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, + {} +}; + static const int cdclk_squash_len = 16; static int cdclk_squash_divider(u16 waveform) @@ -3778,6 +3786,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) if (DISPLAY_VER(dev_priv) >= 20) { dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; dev_priv->display.cdclk.table = xe2lpd_cdclk_table; + } else if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1)) { + dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; + dev_priv->display.cdclk.table = xe2hpd_cdclk_table; } else if (DISPLAY_VER(dev_priv) >= 14) { dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; dev_priv->display.cdclk.table = mtl_cdclk_table; From patchwork Tue Apr 30 17:28:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649720 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3BFD4C4345F for ; Tue, 30 Apr 2024 17:30:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 52000112D73; Tue, 30 Apr 2024 17:30:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ilp7PBAf"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2FCCC112D73; Tue, 30 Apr 2024 17:30:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714498220; x=1746034220; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=omm6ZvRnGPcvkeKmE2v3Y/SH1p3kTyXwWZgil+QRFBI=; b=ilp7PBAfz5eTRvoDLFWFHx7unrirhnQJYUPUQH9y/J/JVOTqWGzfSXme Xxfzz2J+vfNXhSzwqOzUn4sONWGOxMqK13IBOXRSYLF0tPYEJAI4SB7Xj t95NSV4ByMHGK9e6WfwvmTbpL1VFKbd0VfyWMRmn7Y8TC2yxJtptHKewl 0mP7iuwi1M8Jf9CQZ1tN6ysSCM0IKRcTXpNQTAWyGx7YKE7adlMQN6VaT wRxRnuN1m5ndjiQ4P26Vmeu5SB+RA0g9/pAhUJsDsjNR8XXWCDU2GDNGf pjzl2+6DVricMd2pAgDJA5GWc/9hLvjw2dLQWtdCiyiGzpenArBHP8/9W A==; X-CSE-ConnectionGUID: L2ijmq32SgulQc0DVXfiYA== X-CSE-MsgGUID: yohyRKc6Rc+R+IiYOoOvgA== X-IronPort-AV: E=McAfee;i="6600,9927,11060"; a="27741988" X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="27741988" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:19 -0700 X-CSE-ConnectionGUID: xqR32Z/qTIGiSw6Rp2pQoA== X-CSE-MsgGUID: 3z5Ktu0aR9ymmXGfgnT+dQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617822" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:19 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Radhakrishna Sripada , Balasubramani Vivekanandan , Matt Roper Subject: [PATCH v3 04/19] drm/i915/bmg: Extend DG2 tc check to future Date: Tue, 30 Apr 2024 10:28:35 -0700 Message-Id: <20240430172850.1881525-5-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Discrete cards use the Port numbers TC1-4 for the offsets. The regular flow for type-c subsystem port initialization can be skipped. This check is present in DG2. Extend this to future discrete products. Signed-off-by: Radhakrishna Sripada Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_display.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index f45e5f02096d..00e583fc2a8c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1893,11 +1893,10 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) { /* - * DG2's "TC1", although TC-capable output, doesn't share the same flow - * as other platforms on the display engine side and rather rely on the - * SNPS PHY, that is programmed separately + * Discrete GPU phy's are not attached to FIA's to support TC + * subsystem Legacy or non-legacy, and only support native DP/HDMI */ - if (IS_DG2(dev_priv)) + if (IS_DGFX(dev_priv)) return false; if (DISPLAY_VER(dev_priv) >= 13) From patchwork Tue Apr 30 17:28:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649726 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 55053C19F4F for ; Tue, 30 Apr 2024 17:30:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B38C1112D7A; Tue, 30 Apr 2024 17:30:32 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="GsVE1Zzw"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 307BD112D76; Tue, 30 Apr 2024 17:30:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714498220; x=1746034220; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=POQTqjeQD7S7iWBbsEGY9PQk3TV+hseVmIuycsP0rgM=; b=GsVE1Zzwk2u6VE0UsWZ21FS35hldED+KaFGHju5WDKen6G+nud/1XSrj SJJyJCbfqtgJVqRfGrlI6hg0j2ziQ4dDSCcC4gPiws9jLiSpZjwcW33SI pMLA/ES946f7ZEAXoZcm6NTYZzUpUikgurNDAvtRQMuPhnTp/EUoNSJ7b yC1XzoTETBrBlGoQGLA/tykn2vwdqTxXstYcr9ZKNxdaLiWA6+Qa/+kkS nbhiCRIeIa8keLc8EH7v50k51Rz7Ox6+sgCEoWDdXcZfnD9HljcTgm+vW 34SviyX1QLoP98FzbBuz2sCsdWTk1t7vNREdfQngJjZcfRIUpl5iMAYWW g==; X-CSE-ConnectionGUID: AQq+JtjXRkuouD022L8GWg== X-CSE-MsgGUID: 71caOPSaQhWiVZcmb14E3Q== X-IronPort-AV: E=McAfee;i="6600,9927,11060"; a="27741989" X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="27741989" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:19 -0700 X-CSE-ConnectionGUID: jF5epQUDTDG3rw6PxDheSw== X-CSE-MsgGUID: G/A/oEWbQ7StHy8w0/YvcQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617825" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:19 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= , Balasubramani Vivekanandan , Matt Roper , Radhakrishna Sripada Subject: [PATCH v3 05/19] drm/i915/xe2hpd: Properly disable power in port A Date: Tue, 30 Apr 2024 10:28:36 -0700 Message-Id: <20240430172850.1881525-6-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: José Roberto de Souza Xe2_HPD has a different value to power down port A. BSpec: 65450 Signed-off-by: José Roberto de Souza Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 9930fa7313e4..2fee024d642b 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2900,17 +2900,28 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder, intel_cx0pll_enable(encoder, crtc_state); } +static u8 cx0_power_control_disable_val(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + if (intel_encoder_is_c10phy(encoder)) + return CX0_P2PG_STATE_DISABLE; + + if (IS_BATTLEMAGE(i915) && encoder->port == PORT_A) + return CX0_P2PG_STATE_DISABLE; + + return CX0_P4PG_STATE_DISABLE; +} + static void intel_cx0pll_disable(struct intel_encoder *encoder) { struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_encoder_to_phy(encoder); - bool is_c10 = intel_encoder_is_c10phy(encoder); intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder); /* 1. Change owned PHY lane power to Disable state. */ intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, - is_c10 ? CX0_P2PG_STATE_DISABLE : - CX0_P4PG_STATE_DISABLE); + cx0_power_control_disable_val(encoder)); /* * 2. Follow the Display Voltage Frequency Switching Sequence Before From patchwork Tue Apr 30 17:28:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18187C10F16 for ; Tue, 30 Apr 2024 17:30:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 80561112D76; Tue, 30 Apr 2024 17:30:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="B3ycus8g"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 57FA9112D77; Tue, 30 Apr 2024 17:30:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714498220; x=1746034220; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SlyanrKjN/IS34vD0SpgwAXEeY5eVn3/daJY0YWKMkg=; b=B3ycus8g2FhpTuYQbsm/swk/bjjErPUvPmxRGM4NOb8zJotBpVOrAsxW VbxEJeP3IoKLHlmwQ/doFZf/Jei9bDQPyg7kZfm/HARCXDTTnYJyp2Vy3 wgQQoStkA44+kzoTMYcubv5xUuvkvHw0m82VZ7QuQpGZ7MUs0S3nWmq3b nsSi/UGCiH34avJcwgxHFPGwkrYqvDyYPToP/fJowjSlRlGWc/nWk9H5z buFZD5ElfhIxa1bLb0woGmnJg4+fCdgpsC9m5yCgux+bSqmik1Yyz+82e 0e2qEP417Y8/hzzL47cU+Lq40gTwUjsCt2UkVHUMxH1rDq67jZ7SL98yz w==; X-CSE-ConnectionGUID: 7DjdwDPhQHmvbgewV3KgnQ== X-CSE-MsgGUID: kAaBoaHoQDuON69MO9pQow== X-IronPort-AV: E=McAfee;i="6600,9927,11060"; a="27741990" X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="27741990" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:19 -0700 X-CSE-ConnectionGUID: GGujrcd3ReeFM0GQx9Qw7g== X-CSE-MsgGUID: 55epljsHQCSFKTFLPSEPVA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617828" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:20 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Balasubramani Vivekanandan , Clint Taylor , Gustavo Sousa , Jani Nikula , Lucas De Marchi , Radhakrishna Sripada Subject: [PATCH v3 06/19] drm/i915/xe2hpd: Add new C20 PHY SRAM address Date: Tue, 30 Apr 2024 10:28:37 -0700 Message-Id: <20240430172850.1881525-7-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Balasubramani Vivekanandan Xe2_HPD has different offsets for C20 PHY SRAM configuration context location. Use the display version to select the right address. Note that Xe2_LPD uses the same C20 SRAM offsets used by Xe_LPDP (i.e. MTL's display). According to the BSpec, currently, only Xe2_HPD has different offsets, so make sure it is the only display using them in the driver. v2: * Redesigned how the right offsets are selected for different display IP versions. v3: Fix white space error(RK) Bspec: 67610 Cc: Clint Taylor Cc: Gustavo Sousa Cc: Jani Nikula Signed-off-by: Balasubramani Vivekanandan Signed-off-by: Lucas De Marchi Signed-off-by: Radhakrishna Sripada Reviewed-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 65 ++++++++++++------- .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 48 +++++++++++--- 2 files changed, 81 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 2fee024d642b..866b943311f1 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2161,6 +2161,7 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, bool cntx; intel_wakeref_t wakeref; int i; + struct drm_i915_private *i915 = to_i915(encoder->base.dev); wakeref = intel_cx0_phy_transaction_begin(encoder); @@ -2170,42 +2171,50 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, /* Read Tx configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { if (cntx) - pll_state->tx[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_B_TX_CNTX_CFG(i)); + pll_state->tx[i] = intel_c20_sram_read(encoder, + INTEL_CX0_LANE0, + PHY_C20_B_TX_CNTX_CFG(i915, i)); else - pll_state->tx[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_A_TX_CNTX_CFG(i)); + pll_state->tx[i] = intel_c20_sram_read(encoder, + INTEL_CX0_LANE0, + PHY_C20_A_TX_CNTX_CFG(i915, i)); } /* Read common configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { if (cntx) - pll_state->cmn[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_B_CMN_CNTX_CFG(i)); + pll_state->cmn[i] = intel_c20_sram_read(encoder, + INTEL_CX0_LANE0, + PHY_C20_B_CMN_CNTX_CFG(i915, i)); else - pll_state->cmn[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_A_CMN_CNTX_CFG(i)); + pll_state->cmn[i] = intel_c20_sram_read(encoder, + INTEL_CX0_LANE0, + PHY_C20_A_CMN_CNTX_CFG(i915, i)); } if (intel_c20phy_use_mpllb(pll_state)) { /* MPLLB configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { if (cntx) - pll_state->mpllb[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_B_MPLLB_CNTX_CFG(i)); + pll_state->mpllb[i] = intel_c20_sram_read(encoder, + INTEL_CX0_LANE0, + PHY_C20_B_MPLLB_CNTX_CFG(i915, i)); else - pll_state->mpllb[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_A_MPLLB_CNTX_CFG(i)); + pll_state->mpllb[i] = intel_c20_sram_read(encoder, + INTEL_CX0_LANE0, + PHY_C20_A_MPLLB_CNTX_CFG(i915, i)); } } else { /* MPLLA configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { if (cntx) - pll_state->mplla[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_B_MPLLA_CNTX_CFG(i)); + pll_state->mplla[i] = intel_c20_sram_read(encoder, + INTEL_CX0_LANE0, + PHY_C20_B_MPLLA_CNTX_CFG(i915, i)); else - pll_state->mplla[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_A_MPLLA_CNTX_CFG(i)); + pll_state->mplla[i] = intel_c20_sram_read(encoder, + INTEL_CX0_LANE0, + PHY_C20_A_MPLLA_CNTX_CFG(i915, i)); } } @@ -2363,17 +2372,25 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, /* 3.1 Tx configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { if (cntx) - intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]); + intel_c20_sram_write(encoder, INTEL_CX0_LANE0, + PHY_C20_A_TX_CNTX_CFG(i915, i), + pll_state->tx[i]); else - intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]); + intel_c20_sram_write(encoder, INTEL_CX0_LANE0, + PHY_C20_B_TX_CNTX_CFG(i915, i), + pll_state->tx[i]); } /* 3.2 common configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { if (cntx) - intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]); + intel_c20_sram_write(encoder, INTEL_CX0_LANE0, + PHY_C20_A_CMN_CNTX_CFG(i915, i), + pll_state->cmn[i]); else - intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]); + intel_c20_sram_write(encoder, INTEL_CX0_LANE0, + PHY_C20_B_CMN_CNTX_CFG(i915, i), + pll_state->cmn[i]); } /* 3.3 mpllb or mplla configuration */ @@ -2381,22 +2398,22 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { if (cntx) intel_c20_sram_write(encoder, INTEL_CX0_LANE0, - PHY_C20_A_MPLLB_CNTX_CFG(i), + PHY_C20_A_MPLLB_CNTX_CFG(i915, i), pll_state->mpllb[i]); else intel_c20_sram_write(encoder, INTEL_CX0_LANE0, - PHY_C20_B_MPLLB_CNTX_CFG(i), + PHY_C20_B_MPLLB_CNTX_CFG(i915, i), pll_state->mpllb[i]); } } else { for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { if (cntx) intel_c20_sram_write(encoder, INTEL_CX0_LANE0, - PHY_C20_A_MPLLA_CNTX_CFG(i), + PHY_C20_A_MPLLA_CNTX_CFG(i915, i), pll_state->mplla[i]); else intel_c20_sram_write(encoder, INTEL_CX0_LANE0, - PHY_C20_B_MPLLA_CNTX_CFG(i), + PHY_C20_B_MPLLA_CNTX_CFG(i915, i), pll_state->mplla[i]); } } diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index bdd0c8c4ef97..ab3ae110b68f 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -254,18 +254,50 @@ #define PHY_C20_VDR_CUSTOM_WIDTH 0xD02 #define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0) #define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val) -#define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx)) -#define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx)) + +#define _MTL_C20_A_TX_CNTX_CFG 0xCF2E +#define _MTL_C20_B_TX_CNTX_CFG 0xCF2A +#define _MTL_C20_A_CMN_CNTX_CFG 0xCDAA +#define _MTL_C20_B_CMN_CNTX_CFG 0xCDA5 +#define _MTL_C20_A_MPLLA_CFG 0xCCF0 +#define _MTL_C20_B_MPLLA_CFG 0xCCE5 +#define _MTL_C20_A_MPLLB_CFG 0xCB5A +#define _MTL_C20_B_MPLLB_CFG 0xCB4E + +#define _XE2HPD_C20_A_TX_CNTX_CFG 0xCF5E +#define _XE2HPD_C20_B_TX_CNTX_CFG 0xCF5A +#define _XE2HPD_C20_A_CMN_CNTX_CFG 0xCE8E +#define _XE2HPD_C20_B_CMN_CNTX_CFG 0xCE89 +#define _XE2HPD_C20_A_MPLLA_CFG 0xCE58 +#define _XE2HPD_C20_B_MPLLA_CFG 0xCE4D +#define _XE2HPD_C20_A_MPLLB_CFG 0xCCC2 +#define _XE2HPD_C20_B_MPLLB_CFG 0xCCB6 + +#define _IS_XE2HPD_C20(i915) (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) + +#define PHY_C20_A_TX_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_TX_CNTX_CFG : _MTL_C20_A_TX_CNTX_CFG) - (idx)) +#define PHY_C20_B_TX_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_TX_CNTX_CFG : _MTL_C20_B_TX_CNTX_CFG) - (idx)) #define C20_PHY_TX_RATE REG_GENMASK(2, 0) -#define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx)) -#define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx)) -#define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx)) -#define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx)) + +#define PHY_C20_A_CMN_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_CMN_CNTX_CFG : _MTL_C20_A_CMN_CNTX_CFG) - (idx)) +#define PHY_C20_B_CMN_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_CMN_CNTX_CFG : _MTL_C20_B_CMN_CNTX_CFG) - (idx)) +#define PHY_C20_A_MPLLA_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_MPLLA_CFG : _MTL_C20_A_MPLLA_CFG) - (idx)) +#define PHY_C20_B_MPLLA_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_MPLLA_CFG : _MTL_C20_B_MPLLA_CFG) - (idx)) #define C20_MPLLA_FRACEN REG_BIT(14) #define C20_FB_CLK_DIV4_EN REG_BIT(13) #define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8) -#define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx)) -#define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx)) + +#define PHY_C20_A_MPLLB_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_MPLLB_CFG : _MTL_C20_A_MPLLB_CFG) - (idx)) +#define PHY_C20_B_MPLLB_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_MPLLB_CFG : _MTL_C20_B_MPLLB_CFG) - (idx)) + #define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13) #define C20_MPLLB_FRACEN REG_BIT(13) #define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10) From patchwork Tue Apr 30 17:28:38 2024 Content-Type: text/plain; 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d="scan'208";a="26617831" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:20 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Balasubramani Vivekanandan , Clint Taylor , Matt Roper , Radhakrishna Sripada Subject: [PATCH v3 07/19] drm/i915/xe2hpd: Add support for eDP PLL configuration Date: Tue, 30 Apr 2024 10:28:38 -0700 Message-Id: <20240430172850.1881525-8-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Balasubramani Vivekanandan Tables for eDP PHY PLL configuration for different link rates added for Xe2_HPD. Previous platforms were using C10 PHY for eDP port whereas Xe2_HPD has C20 PHY. v2: Updated with a more appropriate Bspec number. Bspec: 74165 CC: Clint Taylor Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 147 ++++++++++++++++++- 1 file changed, 146 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 866b943311f1..d16aab31349f 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -945,6 +945,148 @@ static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = { NULL, }; +/* + * eDP link rates with 38.4 MHz reference clock. + */ + +static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = { + .clock = 216000, + .tx = { 0xbe88, + 0x4800, + 0x0000, + }, + .cmn = { 0x0500, + 0x0005, + 0x0000, + 0x0000, + }, + .mpllb = { 0x50e1, + 0x2120, + 0x8e18, + 0xbfc1, + 0x9000, + 0x78f6, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + }, +}; + +static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = { + .clock = 243000, + .tx = { 0xbe88, + 0x4800, + 0x0000, + }, + .cmn = { 0x0500, + 0x0005, + 0x0000, + 0x0000, + }, + .mpllb = { 0x50fd, + 0x2120, + 0x8f18, + 0xbfc1, + 0xa200, + 0x8814, + 0x2000, + 0x0001, + 0x1000, + 0x0000, + 0x0000, + }, +}; + +static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = { + .clock = 324000, + .tx = { 0xbe88, + 0x4800, + 0x0000, + }, + .cmn = { 0x0500, + 0x0005, + 0x0000, + 0x0000, + }, + .mpllb = { 0x30a8, + 0x2110, + 0xcd9a, + 0xbfc1, + 0x6c00, + 0x5ab8, + 0x2000, + 0x0001, + 0x6000, + 0x0000, + 0x0000, + }, +}; + +static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = { + .clock = 432000, + .tx = { 0xbe88, + 0x4800, + 0x0000, + }, + .cmn = { 0x0500, + 0x0005, + 0x0000, + 0x0000, + }, + .mpllb = { 0x30e1, + 0x2110, + 0x8e18, + 0xbfc1, + 0x9000, + 0x78f6, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + }, +}; + +static const struct intel_c20pll_state xe2hpd_c20_edp_r675 = { + .clock = 675000, + .tx = { 0xbe88, + 0x4800, + 0x0000, + }, + .cmn = { 0x0500, + 0x0005, + 0x0000, + 0x0000, + }, + .mpllb = { 0x10af, + 0x2108, + 0xce1a, + 0xbfc1, + 0x7080, + 0x5e80, + 0x2000, + 0x0001, + 0x6400, + 0x0000, + 0x0000, + }, +}; + +static const struct intel_c20pll_state * const xe2hpd_c20_edp_tables[] = { + &mtl_c20_dp_rbr, + &xe2hpd_c20_edp_r216, + &xe2hpd_c20_edp_r243, + &mtl_c20_dp_hbr1, + &xe2hpd_c20_edp_r324, + &xe2hpd_c20_edp_r432, + &mtl_c20_dp_hbr2, + &xe2hpd_c20_edp_r675, + &mtl_c20_dp_hbr3, + NULL, +}; + /* * HDMI link rates with 38.4 MHz reference clock. */ @@ -2062,7 +2204,10 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) { if (intel_crtc_has_dp_encoder(crtc_state)) - return mtl_c20_dp_tables; + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) + return xe2hpd_c20_edp_tables; + else + return mtl_c20_dp_tables; else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) return mtl_c20_hdmi_tables; From patchwork Tue Apr 30 17:28:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649731 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8DF3BC25B10 for ; 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X-CSE-ConnectionGUID: yy3WfzIWSmyudCyYHsfTig== X-CSE-MsgGUID: g4F2s5+sTAaZvZbN8e2M0g== X-IronPort-AV: E=McAfee;i="6600,9927,11060"; a="27741992" X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="27741992" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:20 -0700 X-CSE-ConnectionGUID: 8Tnww/KWTg2lTZfU7a89NA== X-CSE-MsgGUID: op0a3JcLQwKnytMRAVsZaA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617834" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:20 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Ravi Kumar Vodapalli , Balasubramani Vivekanandan , Matt Roper , Radhakrishna Sripada Subject: [PATCH v3 08/19] drm/i915/xe2hpd: update pll values in sync with Bspec Date: Tue, 30 Apr 2024 10:28:39 -0700 Message-Id: <20240430172850.1881525-9-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ravi Kumar Vodapalli DP/eDP and HDMI pll values are updated for Xe2_HPD platform v2: Removed the unsupported mtl_c20_dp_uhbr20 from xehpd_c20_dp_tables Bspec: 74165 Signed-off-by: Ravi Kumar Vodapalli Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 46 +++++++++++++++++++- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index d16aab31349f..368daf43382a 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -1087,6 +1087,41 @@ static const struct intel_c20pll_state * const xe2hpd_c20_edp_tables[] = { NULL, }; +static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = { + .clock = 1350000, /* 13.5 Gbps */ + .tx = { 0xbea0, /* tx cfg0 */ + 0x4800, /* tx cfg1 */ + 0x0000, /* tx cfg2 */ + }, + .cmn = {0x0500, /* cmn cfg0*/ + 0x0005, /* cmn cfg1 */ + 0x0000, /* cmn cfg2 */ + 0x0000, /* cmn cfg3 */ + }, + .mpllb = { 0x015f, /* mpllb cfg0 */ + 0x2205, /* mpllb cfg1 */ + 0x1b17, /* mpllb cfg2 */ + 0xffc1, /* mpllb cfg3 */ + 0xbd00, /* mpllb cfg4 */ + 0x9ec3, /* mpllb cfg5 */ + 0x2000, /* mpllb cfg6 */ + 0x0001, /* mpllb cfg7 */ + 0x4800, /* mpllb cfg8 */ + 0x0000, /* mpllb cfg9 */ + 0x0000, /* mpllb cfg10 */ + }, +}; + +static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = { + &mtl_c20_dp_rbr, + &mtl_c20_dp_hbr1, + &mtl_c20_dp_hbr2, + &mtl_c20_dp_hbr3, + &mtl_c20_dp_uhbr10, + &xe2hpd_c20_dp_uhbr13_5, + NULL, +}; + /* * HDMI link rates with 38.4 MHz reference clock. */ @@ -2203,13 +2238,20 @@ static const struct intel_c20pll_state * const * intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) { - if (intel_crtc_has_dp_encoder(crtc_state)) + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + if (intel_crtc_has_dp_encoder(crtc_state)) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) return xe2hpd_c20_edp_tables; + + if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) + return xe2hpd_c20_dp_tables; else return mtl_c20_dp_tables; - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + + } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { return mtl_c20_hdmi_tables; + } MISSING_CASE(encoder->type); return NULL; From patchwork Tue Apr 30 17:28:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649729 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46D33C4345F for ; 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X-CSE-ConnectionGUID: Jmucidl0S8CRKcHIRu8Lnw== X-CSE-MsgGUID: 6KkoOp22RVCTZAePuxiUfw== X-IronPort-AV: E=McAfee;i="6600,9927,11060"; a="27741993" X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="27741993" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:20 -0700 X-CSE-ConnectionGUID: zYR5JrwzRpe5PFIIhejlig== X-CSE-MsgGUID: 4QNlNeAKTVGZo8UPyDL7JA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617837" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:20 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Lucas De Marchi , Matt Roper , Balasubramani Vivekanandan , Radhakrishna Sripada Subject: [PATCH v3 09/19] drm/i915/xe2hpd: Add display info Date: Tue, 30 Apr 2024 10:28:40 -0700 Message-Id: <20240430172850.1881525-10-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Lucas De Marchi Add initial display info for xe2hpd. It is similar to xelpdp, but with no PORT_B. v2: Inherit from XE_LPDP_FEATURES instead of XE_LPD_FEATURES Bspec: 67066 CC: Matt Roper Signed-off-by: Lucas De Marchi Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_display_device.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 120e209ee74a..56a2e17d7d9e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -771,6 +771,12 @@ static const struct intel_display_device_info xe2_lpd_display = { BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D), }; +static const struct intel_display_device_info xe2_hpd_display = { + XE_LPDP_FEATURES, + .__runtime_defaults.port_mask = BIT(PORT_A) | + BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), +}; + __diag_pop(); /* @@ -852,6 +858,7 @@ static const struct { const struct intel_display_device_info *display; } gmdid_display_map[] = { { 14, 0, &xe_lpdp_display }, + { 14, 1, &xe2_hpd_display }, { 20, 0, &xe2_lpd_display }, }; From patchwork Tue Apr 30 17:28:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649724 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3F93C19F4F for ; Tue, 30 Apr 2024 17:30:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D69C5112D77; Tue, 30 Apr 2024 17:30:22 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ith01XyG"; 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d="scan'208";a="27741995" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:20 -0700 X-CSE-ConnectionGUID: YNvq/15fTOWPxrNrJglleQ== X-CSE-MsgGUID: oy34lVeuS9GX7K0sytMZlg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617840" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:20 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Anusha Srivatsa , Balasubramani Vivekanandan , Matt Roper , Radhakrishna Sripada Subject: [PATCH v3 10/19] drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planes Date: Tue, 30 Apr 2024 10:28:41 -0700 Message-Id: <20240430172850.1881525-11-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anusha Srivatsa Add step 9 from initialize display sequence. v2: Commit subject improved Bpsec: 49189 Signed-off-by: Anusha Srivatsa Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 03dc7edcc443..a860d88a65da 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1688,6 +1688,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, if (IS_DG2(dev_priv)) intel_snps_phy_wait_for_calibration(dev_priv); + /* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */ + if (DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 1)) + intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); + if (resume) intel_dmc_load_program(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index beed2b97d4b2..962c1b307bde 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3792,6 +3792,7 @@ #define CHICKEN_MISC_2 _MMIO(0x42084) #define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */ +#define BMG_DARB_HALF_BLK_END_BURST REG_BIT(27) #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) #define GLK_CL2_PWR_DOWN REG_BIT(12) From patchwork Tue Apr 30 17:28:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649732 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A2E04C4345F for ; Tue, 30 Apr 2024 17:30:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0CDC4112D7F; Tue, 30 Apr 2024 17:30:43 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="RC6S2uYK"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id EF83C112D73; Tue, 30 Apr 2024 17:30:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714498221; x=1746034221; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=T5ClS7VLsbLjMGyZQI1wehlRMuYavXYLDONl9hlEgdo=; b=RC6S2uYK5yjVfCsiCMdKO5NSknLHEmOACD3hqaASTz6YiUzTkkBEJSzQ CdeYfsKpzab7PEGfgSz1/pJHyQVzGVV1vsT2l7QZaUPfO9mF/I0Wo6EV5 xJ/aI8wGV9MuaLoW1HXO7BlUu3ZzUOR0BbvW+3NYXYTj3/VvqhOxYKq+5 Qyv1QZmZMja6+xFjwMOyS5wC99Q+gQFLJ3t5+QM9raWCI4NrrxNlrR26d 9DnBCtaiwCYVfBm7yAqD4sXxRXSHI5OaIOl/+YilyjtyxPu5WCxib42a7 anbfGn0AKZUZtNEI6NN9/YJSJvaOuo+cQuimGNSlqTqWoLXg/2swKPr1V g==; X-CSE-ConnectionGUID: mHAvjTD7R7mqlsDaUsuyLg== X-CSE-MsgGUID: mHzPfdWrSoiJbR4VAhqrTQ== X-IronPort-AV: E=McAfee;i="6600,9927,11060"; a="27741996" X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="27741996" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:20 -0700 X-CSE-ConnectionGUID: eNOOmZ65T86DInrkUidF5A== X-CSE-MsgGUID: 3pMonEWqTfKV4rTP1vqz4w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617843" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:20 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Matt Roper , Jani Nikula , Balasubramani Vivekanandan , Radhakrishna Sripada Subject: [PATCH v3 11/19] drm/i915/xe2hpd: Add max memory bandwidth algorithm Date: Tue, 30 Apr 2024 10:28:42 -0700 Message-Id: <20240430172850.1881525-12-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper Unlike DG2, Xe2_HPD does support multiple GV points with different maximum memory bandwidths, but uses a much simpler algorithm than igpu platforms use. Bspec: 64631 CC: Jani Nikula Signed-off-by: Matt Roper Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_bw.c | 65 ++++++++++++++++++++++++- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/soc/intel_dram.c | 4 ++ drivers/gpu/drm/xe/xe_device_types.h | 1 + 4 files changed, 69 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 972ea887e232..47036d4abb33 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -22,6 +22,8 @@ struct intel_qgv_point { u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd; }; +#define DEPROGBWPCLIMIT 60 + struct intel_psf_gv_point { u8 clk; /* clock in multiples of 16.6666 MHz */ }; @@ -241,6 +243,9 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, qi->channel_width = 16; qi->deinterleave = 4; break; + case INTEL_DRAM_GDDR: + qi->channel_width = 32; + break; default: MISSING_CASE(dram_info->type); return -EINVAL; @@ -387,6 +392,12 @@ static const struct intel_sa_info mtl_sa_info = { .derating = 10, }; +static const struct intel_sa_info xe2_hpd_sa_info = { + .derating = 30, + .deprogbwlimit = 53, + /* Other values not used by simplified algorithm */ +}; + static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa) { struct intel_qgv_info qi = {}; @@ -493,7 +504,7 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel dclk_max = icl_sagv_max_dclk(&qi); peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max; - maxdebw = min(sa->deprogbwlimit * 1000, peakbw * 6 / 10); /* 60% */ + maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100); ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels); /* @@ -598,6 +609,54 @@ static void dg2_get_bw_info(struct drm_i915_private *i915) i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED; } +static int xe2_hpd_get_bw_info(struct drm_i915_private *i915, + const struct intel_sa_info *sa) +{ + struct intel_qgv_info qi = {}; + int num_channels = i915->dram_info.num_channels; + int peakbw, maxdebw; + int ret, i; + + ret = icl_get_qgv_points(i915, &qi, true); + if (ret) { + drm_dbg_kms(&i915->drm, + "Failed to get memory subsystem information, ignoring bandwidth limits"); + return ret; + } + + peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi); + maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10); + + for (i = 0; i < qi.num_points; i++) { + const struct intel_qgv_point *point = &qi.points[i]; + int bw = num_channels * (qi.channel_width / 8) * point->dclk; + + i915->display.bw.max[0].deratedbw[i] = + min(maxdebw, (100 - sa->derating) * bw / 100); + i915->display.bw.max[0].peakbw[i] = bw; + + drm_dbg_kms(&i915->drm, "QGV %d: deratedbw=%u peakbw: %u\n", + i, i915->display.bw.max[0].deratedbw[i], + i915->display.bw.max[0].peakbw[i]); + } + + /* Bandwidth does not depend on # of planes; set all groups the same */ + i915->display.bw.max[0].num_planes = 1; + i915->display.bw.max[0].num_qgv_points = qi.num_points; + for (i = 1; i < ARRAY_SIZE(i915->display.bw.max); i++) + memcpy(&i915->display.bw.max[i], &i915->display.bw.max[0], + sizeof(i915->display.bw.max[0])); + + /* + * Xe2_HPD should always have exactly two QGV points representing + * battery and plugged-in operation. + */ + drm_WARN_ON(&i915->drm, qi.num_points != 2); + i915->display.sagv.status = I915_SAGV_ENABLED; + + return 0; +} + static unsigned int icl_max_bw_index(struct drm_i915_private *dev_priv, int num_planes, int qgv_point) { @@ -684,7 +743,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv) if (!HAS_DISPLAY(dev_priv)) return; - if (DISPLAY_VER(dev_priv) >= 14) + if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1) && IS_DGFX(dev_priv)) + xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_sa_info); + else if (DISPLAY_VER(dev_priv) >= 14) tgl_get_bw_info(dev_priv, &mtl_sa_info); else if (IS_DG2(dev_priv)) dg2_get_bw_info(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 481ddce038b2..d1d21d433766 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -305,6 +305,7 @@ struct drm_i915_private { INTEL_DRAM_LPDDR4, INTEL_DRAM_DDR5, INTEL_DRAM_LPDDR5, + INTEL_DRAM_GDDR, } type; u8 num_qgv_points; u8 num_psf_gv_points; diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index e3287f1de774..18a879e98f03 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -640,6 +640,10 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915) case 5: dram_info->type = INTEL_DRAM_LPDDR3; break; + case 8: + drm_WARN_ON(&i915->drm, !IS_DGFX(i915)); + dram_info->type = INTEL_DRAM_GDDR; + break; default: MISSING_CASE(val); return -EINVAL; diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index 0f68c55ea405..842e897a04c7 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -492,6 +492,7 @@ struct xe_device { INTEL_DRAM_LPDDR4, INTEL_DRAM_DDR5, INTEL_DRAM_LPDDR5, + INTEL_DRAM_GDDR, } type; u8 num_qgv_points; u8 num_psf_gv_points; From patchwork Tue Apr 30 17:28:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59B00C4345F for ; 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X-CSE-ConnectionGUID: 8TgRc9cZSKqXgy6lef2nlA== X-CSE-MsgGUID: o2rseOQvQiCHFBzFsFDhfg== X-IronPort-AV: E=McAfee;i="6600,9927,11060"; a="27741997" X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="27741997" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:20 -0700 X-CSE-ConnectionGUID: Em/J19goQfe+q1T/u0LKrQ== X-CSE-MsgGUID: wpOZQ974ScuRl2pzVjSL2g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617846" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:21 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= , Matt Roper , Balasubramani Vivekanandan , Radhakrishna Sripada Subject: [PATCH v3 12/19] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits Date: Tue, 30 Apr 2024 10:28:43 -0700 Message-Id: <20240430172850.1881525-13-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: José Roberto de Souza No display IP beyond Xe_LPD+ has "BW credits" bits in MBUS_DBOX_CTL register. Restrict the programming only to Xe_LPD+. BSpec: 49213 CC: Matt Roper Signed-off-by: José Roberto de Souza Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/skl_watermark.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 7c6187b4479f..be9a4712c54e 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3604,7 +3604,7 @@ static void intel_mbus_dbox_update(struct intel_atomic_state *state) for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) { u32 pipe_val = val; - if (DISPLAY_VER(i915) >= 14) { + if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) { if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe, new_dbuf_state->active_pipes)) pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL; From patchwork Tue Apr 30 17:28:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E373BC10F16 for ; Tue, 30 Apr 2024 17:31:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 17516112D94; Tue, 30 Apr 2024 17:31:19 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="U9+lvb9G"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 36285112D79; Tue, 30 Apr 2024 17:30:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714498221; x=1746034221; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FewVEvq68BJuspVFQjRmefNzDxO+/zqhnTctQSSajmQ=; b=U9+lvb9GNceUZ9JlFjdbDQx0OqX/pCgKUMugik2Npvy/a77+VP9FISQ2 fST3U9z+HZ41jFCGGsQUvwZUBesEJVXG5hroq67ypJB4Jg/vP0FpPMDLN dHe9bYYY/+WVpJsrWEOaX2Q/Kl6TPYxCAk4En5KidN9keHEdMZ113FoJ1 dTGDQhjZ286i4uG/p3JJBcHo2Z6WU9B7KTGWLq3lwUPS7vIeGA4OD5Av+ 62yOg1moiy2u/rkxM5oeqm6ojY9vcMyy9t/dp4yyIdzS1uJ1vUFOsqYkY XLosIzbdrZ0Bog0hsRFXyjyav/kD+C24NfkISe6UOwzycraF4CbwfFWLY w==; X-CSE-ConnectionGUID: ZKmCPoSFSnOs3KXIQQezkg== X-CSE-MsgGUID: RNqisU/rTCKM15DSzoYwmQ== X-IronPort-AV: E=McAfee;i="6600,9927,11060"; a="27741998" X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="27741998" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:21 -0700 X-CSE-ConnectionGUID: hVVRvC3ER/aJGFeibqVVHQ== X-CSE-MsgGUID: 5ApwjS0WQzKGgb94WUPg0g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617849" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:21 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Matt Roper , Balasubramani Vivekanandan , Dnyaneshwar Bhadane , Radhakrishna Sripada Subject: [PATCH v3 13/19] drm/i915/bmg: BMG should re-use MTL's south display logic Date: Tue, 30 Apr 2024 10:28:44 -0700 Message-Id: <20240430172850.1881525-14-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Roper Battlemage's south display is the same as Meteor Lake's, including the need to invert the HPD pins, which Lunar Lake does not need. Signed-off-by: Matt Roper Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Dnyaneshwar Bhadane Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/soc/intel_pch.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c index 3cad6dac06b0..542eea50093c 100644 --- a/drivers/gpu/drm/i915/soc/intel_pch.c +++ b/drivers/gpu/drm/i915/soc/intel_pch.c @@ -218,10 +218,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv) if (DISPLAY_VER(dev_priv) >= 20) { dev_priv->pch_type = PCH_LNL; return; - } else if (IS_METEORLAKE(dev_priv)) { + } else if (IS_BATTLEMAGE(dev_priv) || IS_METEORLAKE(dev_priv)) { /* * Both north display and south display are on the SoC die. - * The real PCH is uninvolved in display. + * The real PCH (if it even exists) is uninvolved in display. */ dev_priv->pch_type = PCH_MTL; return; From patchwork Tue Apr 30 17:28:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649738 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C385DC25B10 for ; Tue, 30 Apr 2024 17:31:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0CA3C112D92; Tue, 30 Apr 2024 17:31:20 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="EiHYZJ87"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8EFE3112D77; Tue, 30 Apr 2024 17:30:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714498221; x=1746034221; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=L23EFbpp/8lafdT3ysklOzFGp7/DGXe33oG5UadcWO4=; b=EiHYZJ87JhUMkNdStWbrF8nrjyiRMpr1bxvFjz/R6F9eObY2gquvW0yc G9W3mgNE13d8E66xSuKFy2cz7r5UzvoFY8xTYDAwb99UBcJDYggIzZ6e6 YzXcMBZFdxtuKmOXTuILubx2KhRO0mZznEk06OtpJOA9QUG2EebqcqT+Z Ev0U+q7J28Hm/8R2RAxoRS3JvZWs9axs8YFdhMxOCUMe/l5w4P+D2aP2X 5+pt4oBGQXinz1n46SDdbrB3lqwkBdBYJ+CQ6pfcrzYqvwSkBylEe/DcC ypU+aT/XcKVnWgVzASSAmqZkXEFpppuadnlv8jsw3WmyFqvaCAGTRblFm Q==; X-CSE-ConnectionGUID: 1guZNPdNSsaj1Q2TodX44w== X-CSE-MsgGUID: T63+/U1pRhGchM/iox3RyA== X-IronPort-AV: E=McAfee;i="6600,9927,11060"; a="27742000" X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="27742000" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:21 -0700 X-CSE-ConnectionGUID: mTbd3I6SQU6fbMHrPSgrMQ== X-CSE-MsgGUID: Z9cQrJNLQoqbhi4h5MZMWA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617852" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:21 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Ankit Nautiyal , Balasubramani Vivekanandan , Matt Roper , Radhakrishna Sripada Subject: [PATCH v3 14/19] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping" Date: Tue, 30 Apr 2024 10:28:45 -0700 Message-Id: <20240430172850.1881525-15-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ankit Nautiyal This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f. For BMG it seems that the VBT to DDI mapping does not follow DG1, and DG2, but follows ADLP mapping given in Bspec:20124. Signed-off-by: Ankit Nautiyal Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_bios.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 661842a3c2e6..cf770c866d13 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -2231,15 +2231,14 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) const u8 *ddc_pin_map; int i, n_entries; - if (IS_DGFX(i915)) - return vbt_pin; - if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) { ddc_pin_map = adlp_ddc_pin_map; n_entries = ARRAY_SIZE(adlp_ddc_pin_map); } else if (IS_ALDERLAKE_S(i915)) { ddc_pin_map = adls_ddc_pin_map; n_entries = ARRAY_SIZE(adls_ddc_pin_map); + } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { + return vbt_pin; } else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) { ddc_pin_map = rkl_pch_tgp_ddc_pin_map; n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); From patchwork Tue Apr 30 17:28:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39C67C4345F for ; Tue, 30 Apr 2024 17:31:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 99AE7112D83; Tue, 30 Apr 2024 17:31:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ACLsh1lg"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id BD3EA112D7A; Tue, 30 Apr 2024 17:30:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714498221; x=1746034221; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=r1sklwSj48CNNRxPiIAqoKjo7MaVp0gz+dElCYGXxnE=; b=ACLsh1lg6A8Y66Ugu802rUgvkJ9AniTeyro4fbN+kN3geMemuPWLOQIV i4mn9tf2XE5aPgrILk7+kBxz7XnnNVL863MI3dK82DYWN/mFxx7nF3ogY 2sYp2Kf+l8yAn+BecvG3nFcmbLKkxzscc/w8kLsbDt8dx3JjybKZqFy7N GXKuh6/afy74UciKS5D4+eXxTanbqwa4s6eLaguh803STVVsXic6Qs5Gn rgO45bOku0rDnaqdUegZ/rx35u1AE0/dJoTvgNYRWRhgEK7ztFi+swI1F PrkLozC313i0Zv/k1Isw9pkKUoCFkrL3/eCIZ7FDFZEu5Fe1GAcLA6ujC g==; X-CSE-ConnectionGUID: Xjw3MIWBTc6cDo4QVHLTQg== X-CSE-MsgGUID: U5oNP7nWQ+WgnP7wFo70qg== X-IronPort-AV: E=McAfee;i="6600,9927,11060"; a="27742002" X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="27742002" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:21 -0700 X-CSE-ConnectionGUID: LTOuyirKQuSRxxSAmksKWw== X-CSE-MsgGUID: KlZswUupTte14HxdqkgJMQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617855" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:21 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Balasubramani Vivekanandan , Shekhar Chauhan , Radhakrishna Sripada Subject: [PATCH v3 15/19] drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5 Date: Tue, 30 Apr 2024 10:28:46 -0700 Message-Id: <20240430172850.1881525-16-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Balasubramani Vivekanandan Max supported speed by xe2hpd is UHBR13.5. Limit the max DP source rate to it. Bspec: 67066 Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Shekhar Chauhan Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index e05e25cd4a94..486361eb0070 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -477,6 +477,9 @@ static int mtl_max_source_rate(struct intel_dp *intel_dp) if (intel_encoder_is_c10phy(encoder)) return 810000; + if (DISPLAY_VER_FULL(to_i915(encoder->base.dev)) == IP_VER(14, 1)) + return 1350000; + return 2000000; } From patchwork Tue Apr 30 17:28:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649727 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50E68C25B10 for ; Tue, 30 Apr 2024 17:30:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 27011112D7B; Tue, 30 Apr 2024 17:30:33 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mPEv53l9"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id F0E54112D77; Tue, 30 Apr 2024 17:30:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714498222; x=1746034222; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=shPQJaO9/KURCj0ZVJLjXTFD7lHOMtV483tA46Qv7rM=; b=mPEv53l9LMWrYzD26deQlQBqqFILNL5fk9CsIKyCcCR0aWT+ARrYDQXq gUA4igiO2EvW6lZLo07YQ51oOrOzsW2XntMmCn1DN1bzVZMcUUij0evlp L3nRA8SUHUz7mZSN+AxcIDvHEpRsAn84nC3WeXfbUSmoXwm+vQyYN3W1R g0Rs8GQxwkM1KmqSjkWXNe1wTTzqRjtPwKTdsMSLBoDeY98XgeqYIFwhJ 2pkRmGCsxOlzALwlkdKOCbtL64MnPk7eB9kL3XDs3N43Nb6ikSd3BPEug FOXysp4xTIspRa4mFffeAlARfRw0Hrg4ZIdtA2h2NbaBnNaVeQRAbQREi w==; X-CSE-ConnectionGUID: CzeJO0+gQAuRRptRWTw00Q== X-CSE-MsgGUID: 7rqG98AnQCyAyGfuqP9wug== X-IronPort-AV: E=McAfee;i="6600,9927,11060"; a="27742003" X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="27742003" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:21 -0700 X-CSE-ConnectionGUID: MjQV/H/mQCuyKQpU5mpr0A== X-CSE-MsgGUID: 8W7VwWg0TRiZmCf77dSsug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617859" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:21 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Matthew Auld , Balasubramani Vivekanandan , Nirmoy Das , Radhakrishna Sripada Subject: [PATCH v3 16/19] drm/xe/gt_print: add xe_gt_err_once() Date: Tue, 30 Apr 2024 10:28:47 -0700 Message-Id: <20240430172850.1881525-17-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matthew Auld Needed in an upcoming patch, where we want GT level print, but only which to trigger once to avoid flooding dmesg. Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Nirmoy Das Signed-off-by: Radhakrishna Sripada Acked-by: Lucas De Marchi --- drivers/gpu/drm/xe/xe_gt_printk.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h index c2b004d3f48e..d6228baaff1e 100644 --- a/drivers/gpu/drm/xe/xe_gt_printk.h +++ b/drivers/gpu/drm/xe/xe_gt_printk.h @@ -13,6 +13,9 @@ #define xe_gt_printk(_gt, _level, _fmt, ...) \ drm_##_level(>_to_xe(_gt)->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__) +#define xe_gt_err_once(_gt, _fmt, ...) \ + xe_gt_printk((_gt), err_once, _fmt, ##__VA_ARGS__) + #define xe_gt_err(_gt, _fmt, ...) \ xe_gt_printk((_gt), err, _fmt, ##__VA_ARGS__) From patchwork Tue Apr 30 17:28:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649735 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31735C10F16 for ; Tue, 30 Apr 2024 17:31:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5372F112D90; Tue, 30 Apr 2024 17:31:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="F4FstbIf"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 22FFD112D7D; Tue, 30 Apr 2024 17:30:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714498222; x=1746034222; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9xYhLgg1rFIkfkuVL2s5K84bbt2YwGwVG9jv59E62ug=; b=F4FstbIfTPr2LOeO6KKXAw/c29SPyaF3yVCSoKSGQ4v1CWP/GsAaIf8u r+SenwpPf77Hd9SeU9wh7IJPHzMgLxS5vhtODmoS7ruGYT0F9X3RR5q+9 vjOeICuuXj3Xl7k8p9XvXEKLFngXyRAOjWRfOmD3pSoui/eGgs6GE0n8K 9ZYwsTktOduSjN/8l2LjnYGUrgfg6Vh0v4Bd2cqwUxoNlqYPlBHP/6qis FK2csH74FNbWZS1mySZmshzrphfSD4Zfkn47iUiU376scBpfYfEcLgpKe W5l2abnT/fUqp09+dn5lAVxn1hJXaflyDYGxselynwypUTUVV0kYIpj3Y g==; X-CSE-ConnectionGUID: 6KetHMXvSKaVc8EFzEw4QQ== X-CSE-MsgGUID: 7NQYJdU6RpmKa51MTMgEjg== X-IronPort-AV: E=McAfee;i="6600,9927,11060"; a="27742004" X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="27742004" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:21 -0700 X-CSE-ConnectionGUID: nWBpdZ/XQL6nUx03VFvnbA== X-CSE-MsgGUID: Q3OI64O5RwSQau0y6k2GPQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617862" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:22 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Nirmoy Das , Matthew Auld , Balasubramani Vivekanandan , Matt Roper , Radhakrishna Sripada Subject: [PATCH v3 17/19] drm/xe/device: implement transient flush Date: Tue, 30 Apr 2024 10:28:48 -0700 Message-Id: <20240430172850.1881525-18-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Nirmoy Das Display surfaces can be tagged as transient by mapping it using one of the various L3:XD PAT index modes on Xe2. The expectation is that KMD needs to request transient data flush at the start of flip sequence to ensure all transient data in L3 cache is flushed to memory. Add a routine for this which we can then call from the display code. v2: rebase(RK) Signed-off-by: Nirmoy Das Co-developed-by: Matthew Auld Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada Acked-by: Lucas De Marchi --- drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 ++ drivers/gpu/drm/xe/xe_device.c | 49 ++++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_device.h | 1 + 3 files changed, 53 insertions(+) diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 83847f2da72a..b4f1a3264e8c 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -334,6 +334,9 @@ #define XE2LPM_L3SQCREG5 XE_REG_MCR(0xb658) +#define XE2_TDF_CTRL XE_REG(0xb418) +#define TRANSIENT_FLUSH_REQUEST REG_BIT(0) + #define XEHP_MERT_MOD_CTRL XE_REG_MCR(0xcf28) #define RENDER_MOD_CTRL XE_REG_MCR(0xcf2c) #define COMP_MOD_CTRL XE_REG_MCR(0xcf30) diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index b61f8356e23e..05c28314b748 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -719,6 +719,55 @@ void xe_device_wmb(struct xe_device *xe) xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33, 0); } +/** + * xe_device_td_flush() - Flush transient L3 cache entries + * @xe: The device + * + * Display engine has direct access to memory and is never coherent with L3/L4 + * caches (or CPU caches), however KMD is responsible for specifically flushing + * transient L3 GPU cache entries prior to the flip sequence to ensure scanout + * can happen from such a surface without seeing corruption. + * + * Display surfaces can be tagged as transient by mapping it using one of the + * various L3:XD PAT index modes on Xe2. + * + * Note: On non-discrete xe2 platforms, like LNL, the entire L3 cache is flushed + * at the end of each submission via PIPE_CONTROL for compute/render, since SA + * Media is not coherent with L3 and we want to support render-vs-media + * usescases. For other engines like copy/blt the HW internally forces uncached + * behaviour, hence why we can skip the TDF on such platforms. + */ +void xe_device_td_flush(struct xe_device *xe) +{ + struct xe_gt *gt; + u8 id; + + if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20) + return; + + for_each_gt(gt, xe, id) { + if (xe_gt_is_media_type(gt)) + continue; + + if (xe_force_wake_get(gt_to_fw(gt), XE_FW_GT)) + return; + + xe_mmio_write32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST); + /* + * FIXME: We can likely do better here with our choice of + * timeout. Currently we just assume the worst case, i.e. 150us, + * which is believed to be sufficient to cover the worst case + * scenario on current platforms if all cache entries are + * transient and need to be flushed.. + */ + if (xe_mmio_wait32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0, + 150, NULL, false)) + xe_gt_err_once(gt, "TD flush timeout\n"); + + xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); + } +} + u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size) { return xe_device_has_flat_ccs(xe) ? diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h index 82317580f4bf..f2a78b6a9bff 100644 --- a/drivers/gpu/drm/xe/xe_device.h +++ b/drivers/gpu/drm/xe/xe_device.h @@ -173,5 +173,6 @@ static inline bool xe_device_wedged(struct xe_device *xe) } void xe_device_declare_wedged(struct xe_device *xe); +void xe_device_td_flush(struct xe_device *xe); #endif From patchwork Tue Apr 30 17:28:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649728 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1A148C10F16 for ; Tue, 30 Apr 2024 17:30:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 27FA5112D7E; Tue, 30 Apr 2024 17:30:33 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="P5bGVykX"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 49401112D7A; Tue, 30 Apr 2024 17:30:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714498222; x=1746034222; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R8psRS3fEG7Y5lNMSQmgHZo5obRWnDjG/QTKOvl/++o=; b=P5bGVykXdeBmVP7RYR+eEgiydYSQPXJFQtKLY4xvIKnXJSMfr7dMbq5v uv6Zbxn3E+ee6aA0tvICoFRtu4tDpDIyjbO5F6Y+P3CDo4qYQVwDoHeVA U0BRILK9W4g2lkXVFfwMDQHpDW1M4VHkc1S70ALg0zyA1fCE8rIDDdZJf YgGkRqTIaBBRVHYcpGbT77P9INbXw2FmlpupkXfdK+otM0EUQVLbvKs2c MTEodlkk0Wsn4L7gcjfI723vVnS+3ZfrPQ29anah/8hQ2G6WpbsADoctn 6d8k7Sb3pW7kgi51npC53sgJuMMFXTlZgmVLzkseqs+LoX+MPoISiF56J g==; X-CSE-ConnectionGUID: dWIeD2HhTwOG0VlPSkLMmQ== X-CSE-MsgGUID: r7u2DyYwSEiIu/vIbPPnag== X-IronPort-AV: E=McAfee;i="6600,9927,11060"; a="27742005" X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="27742005" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:22 -0700 X-CSE-ConnectionGUID: pxFnYOMhRY2QpJOrzjzNNw== X-CSE-MsgGUID: GKhMz+A/SAGHvnLDHvNHBw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617865" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:22 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Matthew Auld , Balasubramani Vivekanandan , Nirmoy Das , Matt Roper , Radhakrishna Sripada Subject: [PATCH v3 18/19] drm/i915/display: perform transient flush Date: Tue, 30 Apr 2024 10:28:49 -0700 Message-Id: <20240430172850.1881525-19-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matthew Auld Perform manual transient cache flush prior to flip and at the end of frontbuffer_flush. This is needed to ensure display engine doesn't see garbage if the surface is L3:XD dirty. Testcase: igt@xe-pat@display-vs-wb-transient Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan Acked-by: Nirmoy Das Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ .../gpu/drm/i915/display/intel_frontbuffer.c | 2 ++ drivers/gpu/drm/i915/display/intel_tdf.h | 25 +++++++++++++++++++ drivers/gpu/drm/xe/Makefile | 3 ++- drivers/gpu/drm/xe/display/xe_tdf.c | 13 ++++++++++ 5 files changed, 45 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/display/intel_tdf.h create mode 100644 drivers/gpu/drm/xe/display/xe_tdf.c diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 00e583fc2a8c..294539b4ca99 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -109,6 +109,7 @@ #include "intel_sdvo.h" #include "intel_snps_phy.h" #include "intel_tc.h" +#include "intel_tdf.h" #include "intel_tv.h" #include "intel_vblank.h" #include "intel_vdsc.h" @@ -7225,6 +7226,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_atomic_commit_fence_wait(state); + intel_td_flush(dev_priv); + drm_atomic_helper_wait_for_dependencies(&state->base); drm_dp_mst_atomic_wait_for_dependencies(&state->base); intel_atomic_global_state_wait_for_dependencies(state); diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c index 2ea37c0414a9..4923c340a0b6 100644 --- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c +++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c @@ -65,6 +65,7 @@ #include "intel_fbc.h" #include "intel_frontbuffer.h" #include "intel_psr.h" +#include "intel_tdf.h" /** * frontbuffer_flush - flush frontbuffer @@ -93,6 +94,7 @@ static void frontbuffer_flush(struct drm_i915_private *i915, trace_intel_frontbuffer_flush(i915, frontbuffer_bits, origin); might_sleep(); + intel_td_flush(i915); intel_drrs_flush(i915, frontbuffer_bits); intel_psr_flush(i915, frontbuffer_bits, origin); intel_fbc_flush(i915, frontbuffer_bits, origin); diff --git a/drivers/gpu/drm/i915/display/intel_tdf.h b/drivers/gpu/drm/i915/display/intel_tdf.h new file mode 100644 index 000000000000..353cde21f6c2 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_tdf.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_TDF_H__ +#define __INTEL_TDF_H__ + +/* + * TDF (Transient-Data-Flush) is needed for Xe2+ where special L3:XD caching can + * be enabled through various PAT index modes. Idea is to use this caching mode + * when for example rendering onto the display surface, with the promise that + * KMD will ensure transient cache entries are always flushed by the time we do + * the display flip, since display engine is never coherent with CPU/GPU caches. + */ + +struct drm_i915_private; + +#ifdef I915 +static inline void intel_td_flush(struct drm_i915_private *i915) {} +#else +void intel_td_flush(struct drm_i915_private *i915); +#endif + +#endif diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index a67977edff5b..b620389761d5 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -206,7 +206,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ display/xe_dsb_buffer.o \ display/xe_fb_pin.o \ display/xe_hdcp_gsc.o \ - display/xe_plane_initial.o + display/xe_plane_initial.o \ + display/xe_tdf.o # SOC code shared with i915 xe-$(CONFIG_DRM_XE_DISPLAY) += \ diff --git a/drivers/gpu/drm/xe/display/xe_tdf.c b/drivers/gpu/drm/xe/display/xe_tdf.c new file mode 100644 index 000000000000..2c0d4e144e09 --- /dev/null +++ b/drivers/gpu/drm/xe/display/xe_tdf.c @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2024 Intel Corporation + */ + +#include "xe_device.h" +#include "intel_display_types.h" +#include "intel_tdf.h" + +void intel_td_flush(struct drm_i915_private *i915) +{ + xe_device_td_flush(i915); +} From patchwork Tue Apr 30 17:28:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13649734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D386EC19F4F for ; Tue, 30 Apr 2024 17:31:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1939F112D8F; Tue, 30 Apr 2024 17:31:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="HI9PnTH4"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6FD33112D77; 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30 Apr 2024 10:30:22 -0700 X-CSE-ConnectionGUID: UufrL4CNQu+D0sJKpFx0aw== X-CSE-MsgGUID: 7ufgrPE9QE6Y5mOwxuTx2g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,242,1708416000"; d="scan'208";a="26617868" Received: from invictus.jf.intel.com ([10.165.21.201]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2024 10:30:22 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, Balasubramani Vivekanandan , Shekhar Chauhan , Radhakrishna Sripada Subject: [PATCH v3 19/19] drm/xe/bmg: Enable the display support Date: Tue, 30 Apr 2024 10:28:50 -0700 Message-Id: <20240430172850.1881525-20-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> References: <20240430172850.1881525-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Balasubramani Vivekanandan Enable the display support for Battlemage Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Shekhar Chauhan Signed-off-by: Radhakrishna Sripada Acked-by: Lucas De Marchi --- drivers/gpu/drm/xe/xe_pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index a0cf5dd803c2..b01b1d30976a 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -342,6 +342,7 @@ static const struct xe_device_desc lnl_desc = { static const struct xe_device_desc bmg_desc __maybe_unused = { DGFX_FEATURES, PLATFORM(XE_BATTLEMAGE), + .has_display = true, .require_force_probe = true, };