From patchwork Thu May 2 09:12:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13651475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F72BC4345F for ; Thu, 2 May 2024 09:13:04 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.715683.1117488 (Exim 4.92) (envelope-from ) id 1s2SUp-00081C-PL; Thu, 02 May 2024 09:12:55 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 715683.1117488; Thu, 02 May 2024 09:12:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s2SUp-000815-MT; Thu, 02 May 2024 09:12:55 +0000 Received: by outflank-mailman (input) for mailman id 715683; Thu, 02 May 2024 09:12:54 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s2SUo-00080h-69 for xen-devel@lists.xenproject.org; Thu, 02 May 2024 09:12:54 +0000 Received: from pb-smtp2.pobox.com (pb-smtp2.pobox.com [64.147.108.71]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 2708c599-0864-11ef-909b-e314d9c70b13; Thu, 02 May 2024 11:12:53 +0200 (CEST) Received: from pb-smtp2.pobox.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 0E9731AFEE; Thu, 2 May 2024 05:12:51 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp2.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 066281AFED; Thu, 2 May 2024 05:12:51 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp2.pobox.com (Postfix) with ESMTPSA id 528781AFEC; Thu, 2 May 2024 05:12:50 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2708c599-0864-11ef-909b-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=n8lh5sI7kgYWqWm0ZWfIf98vp I8aDBlCayXCBhx7N2Q=; b=EnSbZrzqTTb8JKUMDhjijLQ0pnaq3vOJhuoLXgBTv /TIE3764Q+jQo2weoCZp0wLZIGnN80l7PsnNIL790o77y+IZL05JOoVd6g6H2AZW 3c0ohGF70/UqqdGTsYYle96nyf8b5AC1Q0LpwE4ZyVuwi5UpbVA4wKVbkFXMFj+w ik= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Jan Beulich , Stefano Stabellini , Andrew Cooper Subject: [XEN PATCH v2 1/5] x86/vpmu: separate amd/intel vPMU code Date: Thu, 2 May 2024 12:12:43 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 26447D24-0864-11EF-B2B6-25B3960A682E-90055647!pb-smtp2.pobox.com Build AMD vPMU when CONFIG_AMD is on, and Intel vPMU when CONFIG_INTEL is on respectively, allowing for a plaftorm-specific build. No functional change intended. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini CC: Andrew Cooper CC: Jan Beulich Acked-by: Jan Beulich --- changes in v2: - drop static inline stubs, use #idef/#endif in vpmu_init)() changes in v1: - switch to CONFIG_{AMD,INTEL} instead of CONFIG_{SVM,VMX} --- xen/arch/x86/cpu/Makefile | 4 +++- xen/arch/x86/cpu/vpmu.c | 6 ++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile index 35561fe51d..eafce5f204 100644 --- a/xen/arch/x86/cpu/Makefile +++ b/xen/arch/x86/cpu/Makefile @@ -10,4 +10,6 @@ obj-y += intel.o obj-y += intel_cacheinfo.o obj-y += mwait-idle.o obj-y += shanghai.o -obj-y += vpmu.o vpmu_amd.o vpmu_intel.o +obj-y += vpmu.o +obj-$(CONFIG_AMD) += vpmu_amd.o +obj-$(CONFIG_INTEL) += vpmu_intel.o diff --git a/xen/arch/x86/cpu/vpmu.c b/xen/arch/x86/cpu/vpmu.c index b2e9881e06..3db90b7839 100644 --- a/xen/arch/x86/cpu/vpmu.c +++ b/xen/arch/x86/cpu/vpmu.c @@ -827,6 +827,7 @@ static int __init cf_check vpmu_init(void) switch ( vendor ) { +#ifdef CONFIG_AMD case X86_VENDOR_AMD: ops = amd_vpmu_init(); break; @@ -834,11 +835,12 @@ static int __init cf_check vpmu_init(void) case X86_VENDOR_HYGON: ops = hygon_vpmu_init(); break; - +#endif +#ifdef CONFIG_INTEL case X86_VENDOR_INTEL: ops = core2_vpmu_init(); break; - +#endif default: printk(XENLOG_WARNING "VPMU: Unknown CPU vendor: %d. " "Turning VPMU off.\n", vendor); From patchwork Thu May 2 09:14:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13651476 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3B066C4345F for ; Thu, 2 May 2024 09:15:13 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.715687.1117499 (Exim 4.92) (envelope-from ) id 1s2SWo-00016y-4w; Thu, 02 May 2024 09:14:58 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 715687.1117499; Thu, 02 May 2024 09:14:58 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s2SWo-00016r-1W; Thu, 02 May 2024 09:14:58 +0000 Received: by outflank-mailman (input) for mailman id 715687; Thu, 02 May 2024 09:14:56 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s2SWm-00013q-Mw for xen-devel@lists.xenproject.org; Thu, 02 May 2024 09:14:56 +0000 Received: from pb-smtp2.pobox.com (pb-smtp2.pobox.com [64.147.108.71]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 7056ff40-0864-11ef-909b-e314d9c70b13; Thu, 02 May 2024 11:14:55 +0200 (CEST) Received: from pb-smtp2.pobox.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 604951B003; Thu, 2 May 2024 05:14:54 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp2.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 57B601B002; Thu, 2 May 2024 05:14:54 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp2.pobox.com (Postfix) with ESMTPSA id 8AEF71B001; Thu, 2 May 2024 05:14:53 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7056ff40-0864-11ef-909b-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=NanAAy5pF1VN7K+y0zyRcYv8A H8YMR9HJ30IOBBsrB0=; b=pHpgY9rsF3YTATkTEsVfovwnFOTxdLwOkPj7kHf6c NuqCUsnAscGxu+gdTwOaUh1boWQkzCCDbVsrd9ktM7Z6+WwDPn11uyca1JM1m7XX jeHqFzq1FTgZrJSeH2RnOxhDbQyW5Pj0DaGg+J1UF1BnRwKRHSUnmbLZFLNjRZK0 Sc= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Jan Beulich , Stefano Stabellini Subject: [XEN PATCH v2 2/5] x86/intel: move vmce_has_lmce() routine to header Date: Thu, 2 May 2024 12:14:51 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 6FB88086-0864-11EF-A735-25B3960A682E-90055647!pb-smtp2.pobox.com Moving this function out of mce_intel.c would make it possible to disable build of Intel MCE code later on, because the function gets called from common x86 code. Add internal check for CONFIG_INTEL option, as MCG_LMCE_P bit is currently specific to Intel CPUs only. Also replace boilerplate code that checks for MCG_LMCE_P flag with vmce_has_lmce(), which might contribute to readability a bit. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini CC: Jan Beulich --- changes in v2: - move vmce_has_lmce() to cpu/mcheck/mce.h - move IS_ENABLED(CONFIG_INTEL) check inside vmce_has_lmce() - changed description --- xen/arch/x86/cpu/mcheck/mce.h | 5 +++++ xen/arch/x86/cpu/mcheck/mce_intel.c | 4 ---- xen/arch/x86/cpu/mcheck/vmce.c | 5 ++--- xen/arch/x86/include/asm/mce.h | 1 - xen/arch/x86/msr.c | 2 ++ 5 files changed, 9 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h index 4806405f96..d6d56aa232 100644 --- a/xen/arch/x86/cpu/mcheck/mce.h +++ b/xen/arch/x86/cpu/mcheck/mce.h @@ -170,6 +170,11 @@ static inline int mce_bank_msr(const struct vcpu *v, uint32_t msr) return 0; } +static inline bool vmce_has_lmce(const struct vcpu *v) +{ + return IS_ENABLED(CONFIG_INTEL) && v->arch.vmce.mcg_cap & MCG_LMCE_P; +} + struct mce_callbacks { void (*handler)(const struct cpu_user_regs *regs); bool (*check_addr)(uint64_t status, uint64_t misc, int addr_type); diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c index 3f5199b531..af43281cc6 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -1050,7 +1050,3 @@ int vmce_intel_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) return 1; } -bool vmce_has_lmce(const struct vcpu *v) -{ - return v->arch.vmce.mcg_cap & MCG_LMCE_P; -} diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index 353d4f19b2..94d1f021e1 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -199,7 +199,7 @@ int vmce_rdmsr(uint32_t msr, uint64_t *val) * bits are always set in guest MSR_IA32_FEATURE_CONTROL by Xen, so it * does not need to check them here. */ - if ( cur->arch.vmce.mcg_cap & MCG_LMCE_P ) + if ( vmce_has_lmce(cur) ) { *val = cur->arch.vmce.mcg_ext_ctl; mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_EXT_CTL %#"PRIx64"\n", @@ -324,8 +324,7 @@ int vmce_wrmsr(uint32_t msr, uint64_t val) break; case MSR_IA32_MCG_EXT_CTL: - if ( (cur->arch.vmce.mcg_cap & MCG_LMCE_P) && - !(val & ~MCG_EXT_CTL_LMCE_EN) ) + if ( vmce_has_lmce(cur) && !(val & ~MCG_EXT_CTL_LMCE_EN) ) cur->arch.vmce.mcg_ext_ctl = val; else ret = -1; diff --git a/xen/arch/x86/include/asm/mce.h b/xen/arch/x86/include/asm/mce.h index 6ce56b5b85..2ec47a71ae 100644 --- a/xen/arch/x86/include/asm/mce.h +++ b/xen/arch/x86/include/asm/mce.h @@ -41,7 +41,6 @@ extern void vmce_init_vcpu(struct vcpu *v); extern int vmce_restore_vcpu(struct vcpu *v, const struct hvm_vmce_vcpu *ctxt); extern int vmce_wrmsr(uint32_t msr, uint64_t val); extern int vmce_rdmsr(uint32_t msr, uint64_t *val); -extern bool vmce_has_lmce(const struct vcpu *v); extern int vmce_enable_mca_cap(struct domain *d, uint64_t cap); DECLARE_PER_CPU(unsigned int, nr_mce_banks); diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 9babd441f9..b0ec96f021 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -24,6 +24,8 @@ #include +#include "cpu/mcheck/mce.h" + DEFINE_PER_CPU(uint32_t, tsc_aux); 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Thu, 2 May 2024 05:16:56 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: b9ddb56c-0864-11ef-909b-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=lgp28eofjwhEroQqYCklB0e/t P+m22xf9XqOUZKnIoA=; b=iV5Q5v2lZrzH5K4MyUiyAT/abCGCVRTRvk2x/PVvu OeJz58/s4lt7FOHZFK5DXc/413Bm//7t8DKEEcLQyl6fwt/Ncoi3fIhHk3upbG6g PCL5hDPRI4LmNuISx8YI46eGeQ7YFZFEEMIbSDv0GYtDjIYs4azWUIIvghhHEgxc gE= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Jan Beulich , Stefano Stabellini Subject: [XEN PATCH v2 3/5] x86/MCE: guard access to Intel/AMD-specific MCA MSRs Date: Thu, 2 May 2024 12:16:54 +0300 Message-Id: <725b477a688ad17e5fa2a8bac78f4905170523c8.1714640459.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: B914D3A6-0864-11EF-B9EA-25B3960A682E-90055647!pb-smtp2.pobox.com Add build-time checks for newly introduced INTEL/AMD config options when calling vmce_{intel/amd}_{rdmsr/wrmsr}() routines. This way a platform-specific code can be omitted in vmce code, if this platform is disabled in config. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini CC: Jan Beulich Acked-by: Jan Beulich --- changes in v2: - use #ifdef/#endif in switch instead of IS_ENABLED - fallback to returning default 0 if vendor not recognized --- xen/arch/x86/cpu/mcheck/vmce.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index 94d1f021e1..373a8e2452 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -138,17 +138,19 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) default: switch ( boot_cpu_data.x86_vendor ) { +#ifdef CONFIG_INTEL case X86_VENDOR_CENTAUR: case X86_VENDOR_SHANGHAI: case X86_VENDOR_INTEL: ret = vmce_intel_rdmsr(v, msr, val); break; - +#endif +#ifdef CONFIG_AMD case X86_VENDOR_AMD: case X86_VENDOR_HYGON: ret = vmce_amd_rdmsr(v, msr, val); break; - +#endif default: ret = 0; break; @@ -271,15 +273,17 @@ static int bank_mce_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) default: switch ( boot_cpu_data.x86_vendor ) { +#ifdef CONFIG_INTEL case X86_VENDOR_INTEL: ret = vmce_intel_wrmsr(v, msr, val); break; - +#endif +#ifdef CONFIG_AMD case X86_VENDOR_AMD: case X86_VENDOR_HYGON: ret = vmce_amd_wrmsr(v, msr, val); break; - +#endif default: ret = 0; break; From patchwork Thu May 2 09:18:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13651479 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20A0CC4345F for ; Thu, 2 May 2024 09:19:18 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.715698.1117518 (Exim 4.92) (envelope-from ) id 1s2San-0002Hs-Qe; Thu, 02 May 2024 09:19:05 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 715698.1117518; Thu, 02 May 2024 09:19:05 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s2San-0002Hl-O1; Thu, 02 May 2024 09:19:05 +0000 Received: by outflank-mailman (input) for mailman id 715698; Thu, 02 May 2024 09:19:04 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s2Sam-0002Hf-Pv for xen-devel@lists.xenproject.org; Thu, 02 May 2024 09:19:04 +0000 Received: from pb-smtp2.pobox.com (pb-smtp2.pobox.com [64.147.108.71]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 038b4ee0-0865-11ef-b4bb-af5377834399; Thu, 02 May 2024 11:19:02 +0200 (CEST) Received: from pb-smtp2.pobox.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 862961B026; Thu, 2 May 2024 05:19:01 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp2.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 5473D1B025; Thu, 2 May 2024 05:19:01 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp2.pobox.com (Postfix) with ESMTPSA id C77E21B023; Thu, 2 May 2024 05:18:59 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 038b4ee0-0865-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=wfkSN8qgSwdu2/Uw/g3XHdw7o vhuKayF/PQY78NPsFw=; b=kSAmzF3NmmTz+1KvaAiBPC15BgbZ0kwibq9PTkHib brWg1t3SXhWxinar4awFs2ilaSdgZFIw0qCC9nnGEpPyvPY7NgtsFR4PLCmaG/f8 egobJMbfq20EyxHin8hjsGs/L26RhO4ellJa1c2hZ0ivZ2HmGetuXM9eMUd6ZWef YA= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Jan Beulich , Stefano Stabellini Subject: [XEN PATCH v2 4/5] x86/MCE: guard {intel/amd}_mcheck_init() calls Date: Thu, 2 May 2024 12:18:57 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 027E4D10-0865-11EF-ADD8-25B3960A682E-90055647!pb-smtp2.pobox.com Guard calls to CPU-specific mcheck init routines in common MCE code using new INTEL/AMD config options. The purpose is not to build platform-specific mcheck code and calls to it, if this platform is disabled in config. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini CC: Jan Beulich Acked-by: Jan Beulich --- changes in v2: - use #ifdef/#endif in switch instead of IS_ENABLED --- xen/arch/x86/cpu/mcheck/mce.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index d179e6b068..fb943addae 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -760,11 +760,13 @@ void mcheck_init(struct cpuinfo_x86 *c, bool bsp) switch ( c->x86_vendor ) { +#ifdef CONFIG_AMD case X86_VENDOR_AMD: case X86_VENDOR_HYGON: inited = amd_mcheck_init(c, bsp); break; - +#endif +#ifdef CONFIG_INTEL case X86_VENDOR_INTEL: switch ( c->x86 ) { @@ -774,7 +776,7 @@ void mcheck_init(struct cpuinfo_x86 *c, bool bsp) break; } break; - +#endif default: break; } From patchwork Thu May 2 09:21:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13651486 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D09C1C4345F for ; Thu, 2 May 2024 09:21:15 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.715708.1117539 (Exim 4.92) (envelope-from ) id 1s2Scm-0004Fk-I2; Thu, 02 May 2024 09:21:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 715708.1117539; Thu, 02 May 2024 09:21:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s2Scm-0004Fd-FB; Thu, 02 May 2024 09:21:08 +0000 Received: by outflank-mailman (input) for mailman id 715708; Thu, 02 May 2024 09:21:07 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s2Scl-00043A-6p for xen-devel@lists.xenproject.org; Thu, 02 May 2024 09:21:07 +0000 Received: from pb-smtp1.pobox.com (pb-smtp1.pobox.com [64.147.108.70]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 4cc15598-0865-11ef-909b-e314d9c70b13; Thu, 02 May 2024 11:21:06 +0200 (CEST) Received: from pb-smtp1.pobox.com (unknown [127.0.0.1]) by pb-smtp1.pobox.com (Postfix) with ESMTP id D9BDB1EF76; Thu, 2 May 2024 05:21:03 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp1.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp1.pobox.com (Postfix) with ESMTP id BA55A1EF74; Thu, 2 May 2024 05:21:03 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp1.pobox.com (Postfix) with ESMTPSA id CEBDA1EF73; Thu, 2 May 2024 05:21:02 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4cc15598-0865-11ef-909b-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=qhW4J/cTFeEpCYrlIcXjhJRer OeqjMFOR0GWdMpf6D0=; b=WSRxL6Ii5P734QIsNDFDUTACl7oppmt6R0wKYAJXf guqIFaD7Gc5rTIBoqWsfHT69cwkwk5zH+L09BcErNVfFDaxd623nrY5oWfaqIHWP Nh2mN+MFqeEkNTRgsj/P4RoWUbgJEieU12TdcNlnaTB7mDecEaxhLgUfVhUPNI++ LI= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Jan Beulich , Stefano Stabellini Subject: [XEN PATCH v2 5/5] x86/MCE: optional build of AMD/Intel MCE code Date: Thu, 2 May 2024 12:21:00 +0300 Message-Id: <47d32ecff7b915bd23b6d13b76cedf4b39db71a2.1714640459.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 4BD369E6-0865-11EF-B450-78DCEB2EC81B-90055647!pb-smtp1.pobox.com Separate Intel/AMD-specific MCE code using CONFIG_{INTEL,AMD} config options. Now we can avoid build of mcheck code if support for specific platform is intentionally disabled by configuration. Add default return value to init_nonfatal_mce_checker() routine -- in case of a build with both AMD and INTEL options are off (e.g. randconfig). Also global Intel-specific variables lmce_support & cmci_support have to be redefined if !INTEL, as they get checked in common code. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini CC: Jan Beulich --- changes in v2: - fallback to original ordering in Makefile - redefine lmce_support & cmci_support global vars to false when !INTEL - changed patch description --- xen/arch/x86/cpu/mcheck/Makefile | 8 ++++---- xen/arch/x86/cpu/mcheck/mce.h | 8 ++++++++ xen/arch/x86/cpu/mcheck/non-fatal.c | 6 ++++++ 3 files changed, 18 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/Makefile b/xen/arch/x86/cpu/mcheck/Makefile index f927f10b4d..e6cb4dd503 100644 --- a/xen/arch/x86/cpu/mcheck/Makefile +++ b/xen/arch/x86/cpu/mcheck/Makefile @@ -1,12 +1,12 @@ -obj-y += amd_nonfatal.o -obj-y += mce_amd.o +obj-$(CONFIG_AMD) += amd_nonfatal.o +obj-$(CONFIG_AMD) += mce_amd.o obj-y += mcaction.o obj-y += barrier.o -obj-y += intel-nonfatal.o +obj-$(CONFIG_INTEL) += intel-nonfatal.o obj-y += mctelem.o obj-y += mce.o obj-y += mce-apei.o -obj-y += mce_intel.o +obj-$(CONFIG_INTEL) += mce_intel.o obj-y += non-fatal.o obj-y += util.o obj-y += vmce.o diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h index d6d56aa232..7fbf1fa2ae 100644 --- a/xen/arch/x86/cpu/mcheck/mce.h +++ b/xen/arch/x86/cpu/mcheck/mce.h @@ -40,7 +40,11 @@ enum mcheck_type { }; extern uint8_t cmci_apic_vector; +#ifdef CONFIG_INTEL extern bool lmce_support; +#else +#define lmce_support (false) +#endif /* Init functions */ enum mcheck_type amd_mcheck_init(const struct cpuinfo_x86 *c, bool bsp); @@ -120,7 +124,11 @@ DECLARE_PER_CPU(struct mca_banks *, poll_bankmask); DECLARE_PER_CPU(struct mca_banks *, no_cmci_banks); DECLARE_PER_CPU(struct mca_banks *, mce_clear_banks); +#ifdef CONFIG_INTEL extern bool cmci_support; +#else +#define cmci_support (false) +#endif extern bool is_mc_panic; extern bool mce_broadcast; extern void mcheck_mca_clearbanks(struct mca_banks *bankmask); diff --git a/xen/arch/x86/cpu/mcheck/non-fatal.c b/xen/arch/x86/cpu/mcheck/non-fatal.c index 33cacd15c2..2d91a3b1e0 100644 --- a/xen/arch/x86/cpu/mcheck/non-fatal.c +++ b/xen/arch/x86/cpu/mcheck/non-fatal.c @@ -24,14 +24,20 @@ static int __init cf_check init_nonfatal_mce_checker(void) * Check for non-fatal errors every MCE_RATE s */ switch (c->x86_vendor) { +#ifdef CONFIG_AMD case X86_VENDOR_AMD: case X86_VENDOR_HYGON: /* Assume we are on K8 or newer AMD or Hygon CPU here */ amd_nonfatal_mcheck_init(c); break; +#endif +#ifdef CONFIG_INTEL case X86_VENDOR_INTEL: intel_nonfatal_mcheck_init(c); break; +#endif + default: + return -ENODEV; } printk(KERN_INFO "mcheck_poll: Machine check polling timer started.\n"); return 0;