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[93.34.90.105]) by smtp.googlemail.com with ESMTPSA id k8-20020a05600c1c8800b00418a6d62ad0sm9537339wms.34.2024.05.03.06.55.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 May 2024 06:55:09 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , =?utf-8?q?=C3=81lvaro_Fern=C3=A1n?= =?utf-8?q?dez_Rojas?= , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Daniel_?= =?utf-8?q?Gonz=C3=A1lez_Cabanelas?= Subject: [PATCH 1/6] mips: bmips: BCM6358: make sure CBR is correctly set Date: Fri, 3 May 2024 15:54:01 +0200 Message-ID: <20240503135455.966-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240503135455.966-1-ansuelsmth@gmail.com> References: <20240503135455.966-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 It was discovered that some device have CBR address set to 0 causing kernel panic when arch_sync_dma_for_cpu_all is called. This was notice in situation where the system is booted from TP1 and BMIPS_GET_CBR() returns 0 instead of a valid address and !!(read_c0_brcm_cmt_local() & (1 << 31)); not failing. The current check whether RAC flush should be disabled or not are not enough hence lets check if CBR is a valid address or not. Fixes: ab327f8acdf8 ("mips: bmips: BCM6358: disable RAC flush for TP1") Signed-off-by: Christian Marangi --- arch/mips/bmips/setup.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index ec180ab92eaa..66a8ba19c287 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -110,7 +110,8 @@ static void bcm6358_quirks(void) * RAC flush causes kernel panics on BCM6358 when booting from TP1 * because the bootloader is not initializing it properly. */ - bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)); + bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) || + !!BMIPS_GET_CBR(); } static void bcm6368_quirks(void) From patchwork Fri May 3 13:54:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13652906 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C494154431; Fri, 3 May 2024 13:55:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714744514; cv=none; b=KkOdhqcEP1ojVaeZx6HWU1wcj8Cz4Abm6JBs5X6Qu2wZMcee7WIGrVdXXtf7R4cX8ROD3zR99ZCjpsSdocNOeEi+nbi1j8qFPJgeMgXFEqvTGD0haonQeZVFwafGd5UhnrcMGlxaS/goXaSc2CH88jfJmdrdJCtJKo6v86+OM4k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714744514; c=relaxed/simple; bh=gv9YiYQt7k9cDctcD5dXzh486s2xgjA9UvSaHqBG8PY=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=e4CcKtX9REATKNmrn3vbJMOTz5kQpVf77SMQM33Z5BmprlAKd6wGW1uwwzQ/vHkqbHk+Z/GSqLYrQ6lKSvpZQ/IAr8Lmqaj/fTfom2UeiCrVdXkGvZ13bLEkjhnDZDLZsB1m265MiBBnB8YlWqWqZgwkEPHg2Z/7DpSBFZJL2Zg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Aj/i/dyw; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Aj/i/dyw" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-41ba1ba55e8so54526245e9.1; Fri, 03 May 2024 06:55:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1714744511; x=1715349311; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=by5Uyw2XfpPL/yXNDPc72M9QG4hAMA1joBwF3oJ0xO0=; b=Aj/i/dyw/mv0l+4aT7RaVm+0VyQap/gdRZ1L9VmcsLZmIDcdizXjRUUO9+OpD/3zRG vEH05MvKyglzx239rdtI3kj1bzmKMI8flBMuD6lLAbu++XDy7iYFS7UOQrAe4JEdokOr hzCMMY7Z38sAWFhm3jUCBzqqYj3pF+jbyJdUIeX7SlrE0yXycgYEWimqF4OOG5h0MuaO LgZwaRfteNGEhsJKFyNamxrLqCXXRI96sYRDIGX3fkft6vexNKaGdHAkF24oJlKlyqqD uHUJ6/8GQSpg/MUKXmdnDYQuSIPznd2Lu77TqeWc4S3EJWm6LFhTwApCTzFdmqKlHvBG NSTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714744511; x=1715349311; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=by5Uyw2XfpPL/yXNDPc72M9QG4hAMA1joBwF3oJ0xO0=; b=pqqgc/wQnKK1h23kuI/rIMFNHswzZ1BnPWmMHZsC64Z/ClOWjR/wYyiUijs6HRaOXp W1dp9y/r++PQGkMTka88mIq3ReEqrJ0Jz+cfYlM5wd8NUuufzXBg6020X74V6z19m7FS qHQSa+AianSJlx6P+Bt8ZasdjlJg/zejbmyEWCfIRK9f3CLT2SdwP0yUOJuStq3ebIpP XuqI56t2gwc6C0Nk4l7/cBBETvv4dK+t9a9sW5r01axTgZ3vvqVMyMLidmXfS5NG2M/p VZdfjeMl4xOWhd+d/kwuIl8VIg5ORot1Cz+nnUqGTFtA1/7h5G/cftdcIeDDkQcTWfgU qe7A== X-Forwarded-Encrypted: i=1; AJvYcCVeqW5tNDrl7A/9dETUBny5Pp7OyiTr0dwnO6DRJJtb2AgzqtqpGh1lWNaZd+EYOAUpTUvOxoBHOjHU08t4cikiXEeJckMi0dAUp+xezxUA3CTlahjQbdjH+QezE5hCFR0h38y5Z1JnpM2Og761Jw2M0hrhL9GSbDiD0vIfT4eG5YAhyog= X-Gm-Message-State: AOJu0Yx5simKQnFhdk+cfjwLT9vvwEzKqYipov8PC1wJ97mN9lZLljSD l0nkqzwnkPw32QJ8BWyn2O0CE0ULtq+k5DvHFVxTVHfQE++Z8cnI X-Google-Smtp-Source: AGHT+IGjibfDRe2YVGdviu5c/vGoLu9PN2h+92uqjbHwf5Lyz7t41zveMJtrv4ObDQj4iBQkIqbjVw== X-Received: by 2002:a05:600c:3551:b0:41b:e406:5ae6 with SMTP id i17-20020a05600c355100b0041be4065ae6mr2246869wmq.9.1714744510615; Fri, 03 May 2024 06:55:10 -0700 (PDT) Received: from localhost.localdomain (93-34-90-105.ip49.fastwebnet.it. [93.34.90.105]) by smtp.googlemail.com with ESMTPSA id k8-20020a05600c1c8800b00418a6d62ad0sm9537339wms.34.2024.05.03.06.55.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 May 2024 06:55:10 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , =?utf-8?q?=C3=81lvaro_Fern=C3=A1n?= =?utf-8?q?dez_Rojas?= , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Daniel_?= =?utf-8?q?Gonz=C3=A1lez_Cabanelas?= Subject: [PATCH 2/6] mips: bmips: rework and cache CBR addr handling Date: Fri, 3 May 2024 15:54:02 +0200 Message-ID: <20240503135455.966-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240503135455.966-1-ansuelsmth@gmail.com> References: <20240503135455.966-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Rework the handling of the CBR address and cache it. This address doesn't chance and can be cache instead of calling the register every time. This is in preparation of permitting to tweak the CBR address in DT with broken SoC or bootloader. Signed-off-by: Christian Marangi --- arch/mips/bmips/dma.c | 7 +++---- arch/mips/bmips/setup.c | 6 +++++- arch/mips/include/asm/bmips.h | 1 + arch/mips/kernel/smp-bmips.c | 31 ++++++++++++++----------------- 4 files changed, 23 insertions(+), 22 deletions(-) diff --git a/arch/mips/bmips/dma.c b/arch/mips/bmips/dma.c index 3779e7855bd7..799cc3e12fc3 100644 --- a/arch/mips/bmips/dma.c +++ b/arch/mips/bmips/dma.c @@ -9,7 +9,6 @@ bool bmips_rac_flush_disable; void arch_sync_dma_for_cpu_all(void) { - void __iomem *cbr = BMIPS_GET_CBR(); u32 cfg; if (boot_cpu_type() != CPU_BMIPS3300 && @@ -21,7 +20,7 @@ void arch_sync_dma_for_cpu_all(void) return; /* Flush stale data out of the readahead cache */ - cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); - __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); - __raw_readl(cbr + BMIPS_RAC_CONFIG); + cfg = __raw_readl(bmips_cbr_addr + BMIPS_RAC_CONFIG); + __raw_writel(cfg | 0x100, bmips_cbr_addr + BMIPS_RAC_CONFIG); + __raw_readl(bmips_cbr_addr + BMIPS_RAC_CONFIG); } diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index 66a8ba19c287..18561d426f89 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -34,6 +34,8 @@ #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) #define BCM6328_TP1_DISABLED BIT(9) +/* CBR addr doesn't change and we can cache it */ +void __iomem *bmips_cbr_addr; extern bool bmips_rac_flush_disable; static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000; @@ -111,7 +113,7 @@ static void bcm6358_quirks(void) * because the bootloader is not initializing it properly. */ bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) || - !!BMIPS_GET_CBR(); + !!bmips_cbr_addr; } static void bcm6368_quirks(void) @@ -144,6 +146,8 @@ static void __init bmips_init_cfe(void) void __init prom_init(void) { + /* Cache CBR addr before CPU/DMA setup */ + bmips_cbr_addr = BMIPS_GET_CBR(); bmips_init_cfe(); bmips_cpu_setup(); register_bmips_smp_ops(); diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h index 581a6a3c66e4..3a1cdfddb987 100644 --- a/arch/mips/include/asm/bmips.h +++ b/arch/mips/include/asm/bmips.h @@ -81,6 +81,7 @@ extern char bmips_smp_movevec[]; extern char bmips_smp_int_vec[]; extern char bmips_smp_int_vec_end[]; +extern void __iomem *bmips_cbr_addr; extern int bmips_smp_enabled; extern int bmips_cpu_offset; extern cpumask_t bmips_booted_mask; diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index b3dbf9ecb0d6..6048c471b5ee 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -518,14 +518,12 @@ static void bmips_set_reset_vec(int cpu, u32 val) info.val = val; bmips_set_reset_vec_remote(&info); } else { - void __iomem *cbr = BMIPS_GET_CBR(); - if (cpu == 0) - __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); + __raw_writel(val, bmips_cbr_addr + BMIPS_RELO_VECTOR_CONTROL_0); else { if (current_cpu_type() != CPU_BMIPS4380) return; - __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1); + __raw_writel(val, bmips_cbr_addr + BMIPS_RELO_VECTOR_CONTROL_1); } } __sync(); @@ -591,7 +589,6 @@ asmlinkage void __weak plat_wired_tlb_setup(void) void bmips_cpu_setup(void) { - void __iomem __maybe_unused *cbr = BMIPS_GET_CBR(); u32 __maybe_unused cfg; switch (current_cpu_type()) { @@ -607,17 +604,17 @@ void bmips_cpu_setup(void) clear_c0_brcm_reset(BIT(16)); /* Flush and enable RAC */ - cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); - __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); - __raw_readl(cbr + BMIPS_RAC_CONFIG); + cfg = __raw_readl(bmips_cbr_addr + BMIPS_RAC_CONFIG); + __raw_writel(cfg | 0x100, bmips_cbr_addr + BMIPS_RAC_CONFIG); + __raw_readl(bmips_cbr_addr + BMIPS_RAC_CONFIG); - cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); - __raw_writel(cfg | 0xf, cbr + BMIPS_RAC_CONFIG); - __raw_readl(cbr + BMIPS_RAC_CONFIG); + cfg = __raw_readl(bmips_cbr_addr + BMIPS_RAC_CONFIG); + __raw_writel(cfg | 0xf, bmips_cbr_addr + BMIPS_RAC_CONFIG); + __raw_readl(bmips_cbr_addr + BMIPS_RAC_CONFIG); - cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); - __raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE); - __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); + cfg = __raw_readl(bmips_cbr_addr + BMIPS_RAC_ADDRESS_RANGE); + __raw_writel(cfg | 0x0fff0000, bmips_cbr_addr + BMIPS_RAC_ADDRESS_RANGE); + __raw_readl(bmips_cbr_addr + BMIPS_RAC_ADDRESS_RANGE); break; case CPU_BMIPS4380: @@ -627,9 +624,9 @@ void bmips_cpu_setup(void) case 0x2a042: case 0x2a044: case 0x2a060: - cfg = __raw_readl(cbr + BMIPS_L2_CONFIG); - __raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG); - __raw_readl(cbr + BMIPS_L2_CONFIG); + cfg = __raw_readl(bmips_cbr_addr + BMIPS_L2_CONFIG); + __raw_writel(cfg & ~0x07000000, bmips_cbr_addr + BMIPS_L2_CONFIG); + __raw_readl(bmips_cbr_addr + BMIPS_L2_CONFIG); } /* clear BHTD to enable branch history table */ From patchwork Fri May 3 13:54:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13652907 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D5CE154448; Fri, 3 May 2024 13:55:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[93.34.90.105]) by smtp.googlemail.com with ESMTPSA id k8-20020a05600c1c8800b00418a6d62ad0sm9537339wms.34.2024.05.03.06.55.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 May 2024 06:55:11 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , =?utf-8?q?=C3=81lvaro_Fern=C3=A1n?= =?utf-8?q?dez_Rojas?= , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Daniel_?= =?utf-8?q?Gonz=C3=A1lez_Cabanelas?= Subject: [PATCH 3/6] dt-bindings: mips: brcm: Document mips-cbr-reg property Date: Fri, 3 May 2024 15:54:03 +0200 Message-ID: <20240503135455.966-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240503135455.966-1-ansuelsmth@gmail.com> References: <20240503135455.966-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document mips-cbr-reg and mips-broken-cbr-reg property. Some SoC suffer from a BUG where read_c0_brcm_cbr() might return 0 if called from TP1. The CBR address is always the same on the SoC hence it can be provided in DT to handle broken case where bootloader doesn't init it or SMP where read_c0_brcm_cbr() returns 0 from TP1. Usage of this property is to give an address also in these broken configuration/bootloader. If the SoC/Bootloader ALWAYS provide a broken CBR address the property "mips-broken-cbr-reg" can be used to ignore any value already set in the registers for CBR address. Signed-off-by: Christian Marangi --- .../devicetree/bindings/mips/brcm/soc.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml index 975945ca2888..12d394b7e011 100644 --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml @@ -55,6 +55,21 @@ properties: under the "cpus" node. $ref: /schemas/types.yaml#/definitions/uint32 + mips-broken-cbr-reg: + description: Declare that the Bootloader init a broken + CBR address in the registers and the one provided from + DT should always be used. + type: boolean + + mips-cbr-reg: + description: Reference address of the CBR. + Some SoC suffer from a BUG where read_c0_brcm_cbr() might + return 0 if called from TP1. The CBR address is always the + same on the SoC hence it can be provided in DT to handle + broken case where bootloader doesn't init it or SMP where + read_c0_brcm_cbr() returns 0 from TP1. + $ref: /schemas/types.yaml#/definitions/uint32 + patternProperties: "^cpu@[0-9]$": type: object @@ -64,6 +79,23 @@ properties: required: - mips-hpt-frequency +dependencies: + mips-broken-cbr-reg: [ mips-cbr-reg ] + +if: + properties: + compatible: + contains: + anyOf: + - const: brcm,bcm6358 + - const: brcm,bcm6368 + +then: + properties: + cpus: + required: + - mips-cbr-reg + additionalProperties: true examples: From patchwork Fri May 3 13:54:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13652908 Received: from mail-lf1-f46.google.com (mail-lf1-f46.google.com [209.85.167.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC660154C08; Fri, 3 May 2024 13:55:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714744516; cv=none; b=CexBLQ+vGOgZXOGotUCNPzwGzJrgUQQYBYr69lW1iFY7kneMukT4GVWISHCnPb+F3iGSB6eGvDY99VWF9WO2tBYZF6cOFgpluDeah46pz/rEmyZ56RRtU9eXsktpv76tHKFgmpS1BG7PWV5ORj/cEtsfXRhvInwVS5wl3xI4Src= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714744516; c=relaxed/simple; bh=QJPkmarfxM3n5aUMQSNsh2BosQFMOvgiMQhvgrb1HVg=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q6Zp5hikV/McyjbYaFoTgOGZQ3jC/1EEfGKDKstKKTP/IolddFs+shCPzu5mlaqEZkXN2L/GgZeLVGAx7m/isObo2caPtUkHyeC2wdQjbCvW7RXWqqDBtEum/P2SOkrw0Vh27iZEnzncj7PDAKUVOOadAVyluRo24Ai/RlSjaPs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=BzPp27XW; arc=none smtp.client-ip=209.85.167.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BzPp27XW" Received: by mail-lf1-f46.google.com with SMTP id 2adb3069b0e04-51f60817e34so1656766e87.2; Fri, 03 May 2024 06:55:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1714744513; x=1715349313; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=mDycoc9tsSM3a5jvUVLZLpZSYhTTvzLmPmjIFvjcoO0=; b=BzPp27XWKXqwfSWy4xbsQrK0YpOeGSsmc7hus8kuK8truLVso8YVtODmYlMNFp5cjb NwKxELcgyNe7WkRcoZewa23sUjoJ1xm2LN4RM6eNcZrrx2OgARJXhwV525oJRBrYDFdY yQqnD8evIxU0kxhpWWHRdNJt1ICiKMXGzOcXLlxSSI1YvweM6cWeSCNfiZl6EUjPW4Fm TfYU0BT4oDjXUe5HwemR1Ohe3z3XJnccEwUt2tHlzKwi1TZpS2P+YBf+DMRrSM1wldcm horcECMtI12O9oE1B/7B1xvozL6b0lKNbi6P5zhhrBm6dKjAvOJLYccdU5fpYyLp/oW9 NUPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714744513; x=1715349313; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mDycoc9tsSM3a5jvUVLZLpZSYhTTvzLmPmjIFvjcoO0=; b=fIOcZfnpw4QjUYbDCZS1+FgIXCZ9DsOsm0i08EWKlnRsi5i+rQelF2FpqObs6SI7OE QDsYUEQXOLIGXy/e+aTAvVe3gkv83lU1FCTYF7lvQFr3SA15HK8fRrAXtxMuOgU+l2KQ XPSwrSYpUQ+N/hsr8LOIMlj4yqPg6HUBUw7vWh6QkxKfsVkrvIbAbEYwIYhiw5RgzaEe 0Da/W22Nf6Uxtm/pC3Wa0Gq+7nrWf7jkEPiUhUkZFtbzFOH7O0hVzLkxdSE0Ph0wz4vK Fg2/YWfRtMKIkKRmr6bLT4k0kMkZkMZZmgUsaxaCfX4PvKIeO5RcBrrKB6+n7xTghJhj XsMA== X-Forwarded-Encrypted: i=1; AJvYcCVG4Kn0tUGRFE3CHp1wpTHzug/McyUp6fLEnYnmZxOfJ2DD5WEscaqjxkzDM3C1f8FGlUPQ9pJ5nIihb00eUi1htDz67DZHPDPUcVBI4TUssOUg/UKjq8jZHEjF9u5jzFfpTrVf9x3XrJsuvkCYhCyQyjC6tHrO/aWhjmvfT4IXsnUoGfk= X-Gm-Message-State: AOJu0Yz8H8va1a1wE1z60HJHZ2qfIyfOjQ0lUdC7GS2ITjX/+3ujUXij rhxKRxeodJLQkSqeezgdHRsxbJfVa9EsFHqTHCpIA9KHzs4vFT4i X-Google-Smtp-Source: AGHT+IGu8h3zTpkduDA2g7DIC5z2V/dTwe21HH0z4Bc3Yy7oILJgBW91QW8ONT37izllzR3z5yRPrA== X-Received: by 2002:a19:5219:0:b0:51c:b8ec:c46f with SMTP id m25-20020a195219000000b0051cb8ecc46fmr1852797lfb.22.1714744512762; Fri, 03 May 2024 06:55:12 -0700 (PDT) Received: from localhost.localdomain (93-34-90-105.ip49.fastwebnet.it. [93.34.90.105]) by smtp.googlemail.com with ESMTPSA id k8-20020a05600c1c8800b00418a6d62ad0sm9537339wms.34.2024.05.03.06.55.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 May 2024 06:55:12 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , =?utf-8?q?=C3=81lvaro_Fern=C3=A1n?= =?utf-8?q?dez_Rojas?= , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Daniel_?= =?utf-8?q?Gonz=C3=A1lez_Cabanelas?= Subject: [PATCH 4/6] mips: bmips: setup: make CBR address configurable Date: Fri, 3 May 2024 15:54:04 +0200 Message-ID: <20240503135455.966-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240503135455.966-1-ansuelsmth@gmail.com> References: <20240503135455.966-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support to provide CBR address from DT to handle broken SoC/Bootloader that doesn't correctly init it. This permits to use the RAC flush even in these condition. To provide a CBR address from DT, the property "mips-cbr-reg" needs to be set in the "cpus" node. On DT init, this property presence will be checked and will set the bmips_cbr_addr value accordingly. Also bmips_rac_flush_disable will be set to false as RAC flush can be correctly supported. The CBR address from DT will be applied only if the CBR address from the registers is 0, if the CBR address from the registers is not 0 and is not equal to the one set in DT (if provided) a WARN is printed. To ALWAYS overwrite the CBR address the additional property "mips-broken-cbr-reg" needs to be set. Signed-off-by: Christian Marangi --- arch/mips/bmips/setup.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index 18561d426f89..bef84677248e 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -34,7 +34,11 @@ #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) #define BCM6328_TP1_DISABLED BIT(9) -/* CBR addr doesn't change and we can cache it */ +/* + * CBR addr doesn't change and we can cache it. + * For broken SoC/Bootloader CBR addr might also be provided via DT + * with "mips-cbr-reg" in the "cpus" node. + */ void __iomem *bmips_cbr_addr; extern bool bmips_rac_flush_disable; @@ -212,8 +216,28 @@ void __init device_tree_init(void) /* Disable SMP boot unless both CPUs are listed in DT and !disabled */ np = of_find_node_by_name(NULL, "cpus"); - if (np && of_get_available_child_count(np) <= 1) - bmips_smp_enabled = 0; + if (np) { + u32 addr; + + if (of_get_available_child_count(np) <= 1) + bmips_smp_enabled = 0; + + /* Check if DT provide a CBR address */ + if (!of_property_read_u32(np, "mips-cbr-reg", &addr)) { + if (!of_property_read_bool(np, "mips-broken-cbr-reg") && + bmips_cbr_addr && addr != (u32)bmips_cbr_addr) { + WARN(1, "register CBR %x differ from DT CBR %x. Ignoring DT CBR.\n", + (u32)bmips_cbr_addr, addr); + goto exit; + } + + bmips_cbr_addr = (void __iomem *)addr; + /* Since CBR is provided by DT, enable RAC flush */ + bmips_rac_flush_disable = false; + } + } + +exit: of_node_put(np); } From patchwork Fri May 3 13:54:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13652909 Received: from mail-lj1-f179.google.com (mail-lj1-f179.google.com [209.85.208.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFB861552EF; Fri, 3 May 2024 13:55:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714744517; cv=none; b=p/BqLYTPJs475UdAiKb3OS99yQzng92TPE/W8iR/PZkycK0eHulkKQQ2aLz/v288ORLEtm6d020HTT/3BkXSTxcbsbtwP2cglNalZDaMMSBLMp782jQl3kYYa5S874+sfCOOpUpQSZBSS2+2yuwp5KYH1IsK+z3Z+g5QtsRzd1E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714744517; c=relaxed/simple; bh=O1Ye1QLJNDCfy1rtmlUyY11EROkwDkBodNDwB1qlbcg=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eD7CoEXuj8c2AdO6L1AC5Tru5AB7DRF0LybRPLTkKz2Swqulg6Ee9Z/IhfzG3AiH+8piT9vKKbfP5sopEA6izKqTSwiKiv51yjmQhbDkkE0Vd2M9KMrkEn6bcxI7hyMPoCpRdRjvGz6RrSSgHyJOghZ+xHC49AEr1bVBScTFRHQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=hcC5XhPc; arc=none smtp.client-ip=209.85.208.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hcC5XhPc" Received: by mail-lj1-f179.google.com with SMTP id 38308e7fff4ca-2d8b2389e73so109511081fa.3; Fri, 03 May 2024 06:55:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1714744514; x=1715349314; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=gYk35mpszpWEiG5Dn8jXxaGvBzprHkHDi7l4DpSYmr8=; b=hcC5XhPcJnnzPMMeG4QBXwihLdNE0uCYkKZQtRYYoyYiaulCAv7diSnhlxgCkCFuW5 w4AtRlIf0JMx++gPOK4CDTN9nI/zA0FcRgCOY5fN58fCSG4DoXLRx7mpnWW8B8cdu5BP tgy/M2zGPKpLzxPIqmAeYY88zMR/lCKHywk4Z0hHFYCE72TooAos8njT4hCzEW+2v+uN S9Kn0g6lAhR0/UIeqUWxlIfHIuy6fWYrfGw+CwTUS8qrU85QXTPT3GoVN5yUUYr0LhD9 GCCQ8Tn+UNh+lOAnZqWUN1egM3tf/SwRutZT42X/3Q+YVjV3l4NEARsO36eGcWDujFR3 mjsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714744514; x=1715349314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gYk35mpszpWEiG5Dn8jXxaGvBzprHkHDi7l4DpSYmr8=; b=uu9LSpMXTlOgfrDUhOYUVLbZp9Hy2QoV6CN5dH+jHVYxVtPj+lvtLGU8pXo9eW6u/G JWoFGhKuqUYi7TUGprbGWCr8ExOucCaoLYJqCUlH/8IO9fUiv4GewZwIbmZB1fYMknYv T6EUkwrDFVwCq5TM560ocbHw0EStSqkcbCaUOEfm0hvMZLzLqDIwRzqhH2Seq7iWyVjO 01ukukBJ36tWLlSFNqsYlSSgtR+41F48194vaE1BAI0iUFV6ubh1hebJE5FNGzKhGpKv Y2CBZQmFLzZLZf9kX59p7yvXgjsa1vRPu53P3sJYm5D+KHJm0EXKNmHsOZVkSVK9dfJy Murg== X-Forwarded-Encrypted: i=1; AJvYcCXNqTBn4WMVMJBNCMlQlR4jwQIR9adkdv0BX6XHgl3vVHExWovdRE61cMpVGo+85z+I6pZZadlxtV5FVU3ft4WrPIBfqMgiXaj5WIawJOeluyqsurvvKV5pLhWS3wqBloFp19NwWsKGM9O+0Kyn+Xw088yPGMJ6DrvXtMSKjUfQ/urYZPs= X-Gm-Message-State: AOJu0Yyn9sCkgb9SHxyqxVKoINE90MAwile5VWklNc33UptJ6sl53ny+ nKnNU6ZVd1C5aBX0/tYtDK34KnxyEpSlWkn6AnBWTubVnzEUXWO+ X-Google-Smtp-Source: AGHT+IFiqd93L2MR1jV7r0gVwTS1l7NKYde8ybBT3jQi/Gx2sP/WJfeUJEoLJ1LXjnPLISMEF0AcQA== X-Received: by 2002:a05:651c:1026:b0:2da:49cc:ef39 with SMTP id w6-20020a05651c102600b002da49ccef39mr1772455ljm.0.1714744513927; Fri, 03 May 2024 06:55:13 -0700 (PDT) Received: from localhost.localdomain (93-34-90-105.ip49.fastwebnet.it. [93.34.90.105]) by smtp.googlemail.com with ESMTPSA id k8-20020a05600c1c8800b00418a6d62ad0sm9537339wms.34.2024.05.03.06.55.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 May 2024 06:55:13 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , =?utf-8?q?=C3=81lvaro_Fern=C3=A1n?= =?utf-8?q?dez_Rojas?= , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Daniel_?= =?utf-8?q?Gonz=C3=A1lez_Cabanelas?= Subject: [PATCH 5/6] mips: bmips: enable RAC on BMIPS4350 Date: Fri, 3 May 2024 15:54:05 +0200 Message-ID: <20240503135455.966-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240503135455.966-1-ansuelsmth@gmail.com> References: <20240503135455.966-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel González Cabanelas The data RAC is left disabled by the bootloader in some SoCs, at least in the core it boots from. Enabling this feature increases the performance up to +30% depending on the task. Signed-off-by: Daniel González Cabanelas Signed-off-by: Álvaro Fernández Rojas [ rework code and reduce code duplication ] Signed-off-by: Christian Marangi --- arch/mips/kernel/smp-bmips.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index 6048c471b5ee..7bde6bbaa41f 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -617,6 +617,18 @@ void bmips_cpu_setup(void) __raw_readl(bmips_cbr_addr + BMIPS_RAC_ADDRESS_RANGE); break; + case CPU_BMIPS4350: + u32 rac_addr = BMIPS_RAC_CONFIG_1; + + if (!(read_c0_brcm_cmt_local() & (1 << 31))) + rac_addr = BMIPS_RAC_CONFIG; + + /* Enable data RAC */ + cfg = __raw_readl(bmips_cbr_addr + rac_addr); + __raw_writel(cfg | 0xa, bmips_cbr_addr + rac_addr); + __raw_readl(bmips_cbr_addr + rac_addr); + break; + case CPU_BMIPS4380: /* CBG workaround for early BMIPS4380 CPUs */ switch (read_c0_prid()) { From patchwork Fri May 3 13:54:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13652910 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5EA8155317; Fri, 3 May 2024 13:55:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714744518; cv=none; b=p6FONY6+NsxcQxn4S/UEUbjqbhT/HQJ+9tXtzwsSCx9qeVMbqDByCx6EFhr8cXguYzI+1q44kFuZ7NwDM5EZgxlR8DJAxCAtIWHfyBpyCOOIacDj4zNnVH4n1mWeTHkQZkXIan5jbhGbnbaonNp9wJ9OqpoUobaJuJnVtiDJ/is= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714744518; c=relaxed/simple; bh=sv3bHJPSIAzAatSQs/bKdLt9FMtfOseslXyoRcccdI4=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Q4Lh+D4YYnd7RsVZzxBNipN/dZ1hNwrNBeAt1L8f2cOYoK4Ba2WCBYX/N3l6khPHHgvrXUzNwr3Bx4WPFKGqzq9ftLLzQNoom/dOqenSChDxxkdPYUcsKIGfAmi4LYo9BGNCAbyZyGVpv10OyPs+pyYqP6pZH0VrDHisP3JlJ/Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=QKmtYXce; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QKmtYXce" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-4196c62bb4eso67150245e9.2; Fri, 03 May 2024 06:55:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1714744515; x=1715349315; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ORf4L+Kc1pyBC8fE9YC0FQfG86LMRHTWb3C7SJM7A84=; b=QKmtYXcePf2kHemzC3alUjw4Dcd1/lDo8VxZ+h9Sqe3x0pqvzxBAZDtRdXui8YiAfK jRHD/UM3pkq0kzeSP6DVNdwKSzCpFva+CIdZgrAIpJqXMdew9ejH871FXOzlrPlSNKp8 qVgWRXLJ+4gvGwqBSllenR0Ai6e9xDuu0a+NSP7gL5ACCkL7hjpADVTLkErwjdmL/b5f Qa20oNvFIpeGq1if8PIAEO0rjRs2Zz6nJ6HCs6UrHtH87RrMTd6gTXAuXCDxIAXmAyql mCXMaFrNiBgv+3ua0ErPQYoa6AbGeMS8c+8oKjSqNVYdKVKsxoptPeQ+2WDmPaxrE9Bt p/Ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714744515; x=1715349315; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ORf4L+Kc1pyBC8fE9YC0FQfG86LMRHTWb3C7SJM7A84=; b=b/TU/yG2pk10lEQedB+p+WbaoPICXMmdyTuF12K4AZtO8g9g9IYgACnRgTo9ym8+oO oIx/VnGpnhMp4+41D4iCNF5/QY1QL9BpO4NtH66mBa7BmzdKs8LVNl0MrVrQoa/DUuyY bA8odean9ebTn91O23vZULSijAylcYSwn7yI2YrucEIlEgW0C3iDuI0gRw1HoYnkMreM +M7Q3f34qDKqWdPghJDwQE6tAAH5QjkkYIgi94VVTHAeDk6QhWMsL4zV+P/SwBS1cZkL cmvUZXucInlypMaPJYxSbE/FvaHYZC+FG7HveF4p3gcalhdSxeBSMbXfzo/h/IVqjEkO Lhow== X-Forwarded-Encrypted: i=1; AJvYcCUfPzpS9T+Ffm3WKg4gYfaGSotAIhkXWDORMMtchsCDpAuPgmqp2GoLXQZdL1ih7ojYdWLD5LbSuu6Fj+Bvb2AXUATavhk3qaOvaumQ9oRxvZWjB+rVW3ToP3NXIXUvTsHrH3mQ7mjdo5w4NGrYWG2VgkQrTdopyrSEqO383xc3Qg/e99o= X-Gm-Message-State: AOJu0YyaO8rDY113i71GAnZXXhAsThKVl3tcVxVxIdCFKJzDrW6svTCo t2M2vxNPI3HcUFfsWA9DA0NB+r0b3RZU5X8BW+8Uyq/4QlHypKJk X-Google-Smtp-Source: AGHT+IFkP1WaMT+0uGQZLaq5utzRvX1j8q6mLmJ2/l/tUpebX6xSKa77EdO0TBHbtqDy7Hi8FlWeYA== X-Received: by 2002:a05:600c:5494:b0:41a:b6bd:4de5 with SMTP id iv20-20020a05600c549400b0041ab6bd4de5mr2214660wmb.39.1714744515067; Fri, 03 May 2024 06:55:15 -0700 (PDT) Received: from localhost.localdomain (93-34-90-105.ip49.fastwebnet.it. [93.34.90.105]) by smtp.googlemail.com with ESMTPSA id k8-20020a05600c1c8800b00418a6d62ad0sm9537339wms.34.2024.05.03.06.55.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 May 2024 06:55:14 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , =?utf-8?q?=C3=81lvaro_Fern=C3=A1n?= =?utf-8?q?dez_Rojas?= , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?utf-8?q?Daniel_?= =?utf-8?q?Gonz=C3=A1lez_Cabanelas?= Subject: [PATCH 6/6] bmips: dma: drop redundant boot_cpu_type in arch_dma_sync Date: Fri, 3 May 2024 15:54:06 +0200 Message-ID: <20240503135455.966-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240503135455.966-1-ansuelsmth@gmail.com> References: <20240503135455.966-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Drop redundant boot_cpu_type in arch_sync_dma_for_cpu_all. These needs to be parsed only once and we can make use of bmips_rac_flush_disable to disable RAC flush on unsupported CPU. Set this value in bmips_cpu_setup for unsupported CPU to skip this redundant check every time DMA needs to be synced. Signed-off-by: Christian Marangi --- arch/mips/bmips/dma.c | 5 ----- arch/mips/bmips/setup.c | 1 - arch/mips/include/asm/bmips.h | 1 + arch/mips/kernel/smp-bmips.c | 7 +++++++ 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/mips/bmips/dma.c b/arch/mips/bmips/dma.c index 799cc3e12fc3..e9af34f82dcd 100644 --- a/arch/mips/bmips/dma.c +++ b/arch/mips/bmips/dma.c @@ -11,11 +11,6 @@ void arch_sync_dma_for_cpu_all(void) { u32 cfg; - if (boot_cpu_type() != CPU_BMIPS3300 && - boot_cpu_type() != CPU_BMIPS4350 && - boot_cpu_type() != CPU_BMIPS4380) - return; - if (unlikely(bmips_rac_flush_disable)) return; diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index bef84677248e..d27043b10405 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -40,7 +40,6 @@ * with "mips-cbr-reg" in the "cpus" node. */ void __iomem *bmips_cbr_addr; -extern bool bmips_rac_flush_disable; static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000; diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h index 3a1cdfddb987..4a48c8f1077e 100644 --- a/arch/mips/include/asm/bmips.h +++ b/arch/mips/include/asm/bmips.h @@ -82,6 +82,7 @@ extern char bmips_smp_int_vec[]; extern char bmips_smp_int_vec_end[]; extern void __iomem *bmips_cbr_addr; +extern bool bmips_rac_flush_disable; extern int bmips_smp_enabled; extern int bmips_cpu_offset; extern cpumask_t bmips_booted_mask; diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index 7bde6bbaa41f..63534af367c7 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -681,6 +681,13 @@ void bmips_cpu_setup(void) " or $8, $9\n" " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */ : : : "$8", "$9"); + + /* Disable RAC flush as not supported */ + bmips_rac_flush_disable = true; break; + + default: + /* Disable RAC flush as not supported */ + bmips_rac_flush_disable = true; } }