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[93.34.90.105]) by smtp.googlemail.com with ESMTPSA id fk12-20020a05600c0ccc00b0041c130520fbsm2921555wmb.46.2024.05.08.10.07.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 May 2024 10:07:38 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/4] mips: bmips: rework and cache CBR addr handling Date: Wed, 8 May 2024 19:07:17 +0200 Message-ID: <20240508170721.3023-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240508170721.3023-1-ansuelsmth@gmail.com> References: <20240508170721.3023-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Rework the handling of the CBR address and cache it. This address doesn't change and can be cached instead of reading the register every time. This is in preparation of permitting to tweak the CBR address in DT with broken SoC or bootloader. Signed-off-by: Christian Marangi Acked-by: Florian Fainelli --- arch/mips/bmips/dma.c | 2 +- arch/mips/bmips/setup.c | 6 +++++- arch/mips/include/asm/bmips.h | 1 + arch/mips/kernel/smp-bmips.c | 4 ++-- 4 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/mips/bmips/dma.c b/arch/mips/bmips/dma.c index 3779e7855bd7..2bc9c0d4402f 100644 --- a/arch/mips/bmips/dma.c +++ b/arch/mips/bmips/dma.c @@ -9,7 +9,7 @@ bool bmips_rac_flush_disable; void arch_sync_dma_for_cpu_all(void) { - void __iomem *cbr = BMIPS_GET_CBR(); + void __iomem *cbr = bmips_cbr_addr; u32 cfg; if (boot_cpu_type() != CPU_BMIPS3300 && diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index 66a8ba19c287..5e024399222f 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -34,6 +34,8 @@ #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) #define BCM6328_TP1_DISABLED BIT(9) +/* CBR addr doesn't change and we can cache it */ +void __iomem *bmips_cbr_addr __ro_after_init __read_mostly; extern bool bmips_rac_flush_disable; static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000; @@ -111,7 +113,7 @@ static void bcm6358_quirks(void) * because the bootloader is not initializing it properly. */ bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) || - !!BMIPS_GET_CBR(); + !!bmips_cbr_addr; } static void bcm6368_quirks(void) @@ -144,6 +146,8 @@ static void __init bmips_init_cfe(void) void __init prom_init(void) { + /* Cache CBR addr before CPU/DMA setup */ + bmips_cbr_addr = BMIPS_GET_CBR(); bmips_init_cfe(); bmips_cpu_setup(); register_bmips_smp_ops(); diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h index 581a6a3c66e4..3a1cdfddb987 100644 --- a/arch/mips/include/asm/bmips.h +++ b/arch/mips/include/asm/bmips.h @@ -81,6 +81,7 @@ extern char bmips_smp_movevec[]; extern char bmips_smp_int_vec[]; extern char bmips_smp_int_vec_end[]; +extern void __iomem *bmips_cbr_addr; extern int bmips_smp_enabled; extern int bmips_cpu_offset; extern cpumask_t bmips_booted_mask; diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index b3dbf9ecb0d6..a4f84667a901 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -518,7 +518,7 @@ static void bmips_set_reset_vec(int cpu, u32 val) info.val = val; bmips_set_reset_vec_remote(&info); } else { - void __iomem *cbr = BMIPS_GET_CBR(); + void __iomem *cbr = bmips_cbr_addr; if (cpu == 0) __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); @@ -591,7 +591,7 @@ asmlinkage void __weak plat_wired_tlb_setup(void) void bmips_cpu_setup(void) { - void __iomem __maybe_unused *cbr = BMIPS_GET_CBR(); + void __iomem __maybe_unused *cbr = bmips_cbr_addr; u32 __maybe_unused cfg; switch (current_cpu_type()) { From patchwork Wed May 8 17:07:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13658931 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9680A1C6AD; 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[93.34.90.105]) by smtp.googlemail.com with ESMTPSA id fk12-20020a05600c0ccc00b0041c130520fbsm2921555wmb.46.2024.05.08.10.07.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 May 2024 10:07:39 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property Date: Wed, 8 May 2024 19:07:18 +0200 Message-ID: <20240508170721.3023-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240508170721.3023-1-ansuelsmth@gmail.com> References: <20240508170721.3023-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document brcm,bmips-cbr-reg property. Some SoC suffer from a BUG where read_c0_brcm_cbr() might return 0 if called from TP1. The CBR address is always the same on the SoC hence it can be provided in DT to handle broken case where bootloader doesn't init it or SMP where read_c0_brcm_cbr() returns 0 from TP1. Usage of this property is to give an address also in these broken configuration/bootloader. Signed-off-by: Christian Marangi --- .../devicetree/bindings/mips/brcm/soc.yaml | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml index 975945ca2888..77f73ab48c11 100644 --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml @@ -55,6 +55,15 @@ properties: under the "cpus" node. $ref: /schemas/types.yaml#/definitions/uint32 + brcm,bmips-cbr-reg: + description: Reference address of the CBR. + Some SoC suffer from a BUG where read_c0_brcm_cbr() might + return 0 if called from TP1. The CBR address is always the + same on the SoC hence it can be provided in DT to handle + broken case where bootloader doesn't initialise it or SMP + where read_c0_brcm_cbr() returns 0 from TP1. + $ref: /schemas/types.yaml#/definitions/uint32 + patternProperties: "^cpu@[0-9]$": type: object @@ -64,6 +73,20 @@ properties: required: - mips-hpt-frequency +if: + properties: + compatible: + contains: + enum: + - brcm,bcm6358 + - brcm,bcm6368 + +then: + properties: + cpus: + required: + - brcm,bmips-cbr-reg + additionalProperties: true examples: From patchwork Wed May 8 17:07:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13658932 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A0A038F9A; Wed, 8 May 2024 17:07:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715188064; cv=none; b=SY8Ac7gJJraF/JsjWsI7AcadBcQEqQr4HBTI9aGglHJqxK6bYyd3KPKxtvGt/H2Mh8oIf56GoXtZ7HufLiKEDV03zvVGStbFv28VuKAOEuiNAng1Fi30pJjmpi9IlgMZ7kYg6KGnilx1xAHGjLP0VQ49Ocj2E9W4Pi+5uQt4zPU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715188064; c=relaxed/simple; bh=JlcOFQPjlt6QpzAow7qGWD8usG8/Mww4c6Fy9ThgjZU=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EkwnKLX8eGtePckuKs8X77YADu/QGcC9oVtZUS5fAwzJJ/tPvDnYC4j5ESeR+/n8TY+K7o9ybXge5cy6E6J3+jCminOGGojIeRvNiMkjS1ZTg5jpEcDU7nA2BVHU7pm98DJ7bvvuKGuldp5EIY4D2quYl5871O/t5ntVu0L6k+w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KL8+Vr/1; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KL8+Vr/1" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-41c7ac6f635so31189115e9.3; Wed, 08 May 2024 10:07:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715188061; x=1715792861; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=V9LIXMozHspZQG84dPZMvCKK2fcJoE/LYnXv511PO3I=; b=KL8+Vr/1rhPDdk+PhPlp4Diq2vQaor+IvLJh4I46y/NvpYGaeam5Gd9P8HX1nsiFS0 gWDoQC1CpbpaI8Lbx/eZR69N9f7kCUTl6B3MFul2i3TJNQqFAEW6it7qhjHXeF+o5WDG nwcCaao6TLS27MVbE9gjL7FhVPDUzTJ58R61wfEGoBKfj9EAgfZRSf2Dqudc5vnzkClW 4mMKtqsWD1nxfyuvqyrarcRBkmgaz3HZ6EWpYMGObtURDHCoUiUz/GVkOOOJ2t1VXoHx JAr6NxnbFCuMSs4mdaX1J70NQt3L9wHaKG4OOTQ6/cDz/e7Y17Es2wqedmE22TwJ81N2 Oigg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715188061; x=1715792861; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V9LIXMozHspZQG84dPZMvCKK2fcJoE/LYnXv511PO3I=; b=i9XIwIadbnRyfHq+CUB3MVcWQx7E4++4Gk/4Se1Nv9FYCkghJnTyWlPtE1vPhhEEuj EEUz5fi3FuGgA4kiMM6PjpQbLNeXYLe6Sl6B6uhqJ+9cIvSfbFlIjilDFVFajlwDwNfZ 02Z1fj/56bvjXJVRAnEOFrJ+gMtvmM+7JsXOVmHFkSr/AI8uzFkROifRyK/7MGTf6JBh DzdvwR5IJlr7pcOk2thslHbcRjuhqUmrKUe6ld+UWUY7NU0RKgBBZv1jnq1SsKTAaBe4 IcLPXIijvbxebjym5783lJ4TltSTk07L2PZQp6QKt4ZIIh/BojSaxs2WmJ9xFUn8bhAV eLjQ== X-Forwarded-Encrypted: i=1; AJvYcCXv0udZmMUClmMqI3u/Ria1RYb1LGkzP1qAFHdqXXHQ3udagPZPKoQ4ng6NN4sj6xZSMHLfjAvNUx04173yWeOZC2PuN6N7Nw0XU4hMTC5TYTW2No/Gv/1d5AreBTYHOfbu45g3ORFTa9rYo0jYUN5GZziYIht4SZPlcCzexAS/471OWM0= X-Gm-Message-State: AOJu0YzDbYW+AKB022XJgRWMSaVqvvBdq8SFqvOaOQ1wtHENglYxAthJ DSXbJiwDmKjtAmwZhrHY7UXCsoqpGvm6uyQG9KSg0QqFvKxscTzl X-Google-Smtp-Source: AGHT+IHxdmu8SGnQksk2mkLHyCRBMv8kDO7sVIMBGz+sbOjfEag5EQsEMpq5v5oXfHw0oG2L4/4HAA== X-Received: by 2002:a05:600c:4755:b0:41b:9e4f:d2b2 with SMTP id 5b1f17b1804b1-41f71cc1c66mr32468325e9.2.1715188060826; Wed, 08 May 2024 10:07:40 -0700 (PDT) Received: from localhost.localdomain (93-34-90-105.ip49.fastwebnet.it. [93.34.90.105]) by smtp.googlemail.com with ESMTPSA id fk12-20020a05600c0ccc00b0041c130520fbsm2921555wmb.46.2024.05.08.10.07.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 May 2024 10:07:40 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/4] mips: bmips: setup: make CBR address configurable Date: Wed, 8 May 2024 19:07:19 +0200 Message-ID: <20240508170721.3023-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240508170721.3023-1-ansuelsmth@gmail.com> References: <20240508170721.3023-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support to provide CBR address from DT to handle broken SoC/Bootloader that doesn't correctly init it. This permits to use the RAC flush even in these condition. To provide a CBR address from DT, the property "brcm,bmips-cbr-reg" needs to be set in the "cpus" node. On DT init, this property presence will be checked and will set the bmips_cbr_addr value accordingly. Also bmips_rac_flush_disable will be set to false as RAC flush can be correctly supported. The CBR address from DT will overwrite the cached one and the one set in the CBR register will be ignored. Also the DT CBR address is validated on being outside DRAM window. Signed-off-by: Christian Marangi --- arch/mips/bmips/setup.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index 5e024399222f..01463b2f125d 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -34,7 +34,11 @@ #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c)) #define BCM6328_TP1_DISABLED BIT(9) -/* CBR addr doesn't change and we can cache it */ +/* + * CBR addr doesn't change and we can cache it. + * For broken SoC/Bootloader CBR addr might also be provided via DT + * with "brcm,bmips-cbr-reg" in the "cpus" node. + */ void __iomem *bmips_cbr_addr __ro_after_init __read_mostly; extern bool bmips_rac_flush_disable; @@ -207,13 +211,35 @@ void __init plat_mem_setup(void) void __init device_tree_init(void) { struct device_node *np; + u32 addr; unflatten_and_copy_device_tree(); /* Disable SMP boot unless both CPUs are listed in DT and !disabled */ np = of_find_node_by_name(NULL, "cpus"); - if (np && of_get_available_child_count(np) <= 1) + if (!np) + return; + + if (of_get_available_child_count(np) <= 1) bmips_smp_enabled = 0; + + /* Check if DT provide a CBR address */ + if (of_property_read_u32(np, "brcm,bmips-cbr-reg", &addr)) + goto exit; + + /* Make sure CBR address is outside DRAM window */ + if (addr >= (u32)memblock_start_of_DRAM() && + addr < (u32)memblock_end_of_DRAM()) { + WARN(1, "DT CBR %x inside DRAM window. Ignoring DT CBR.\n", + addr); + goto exit; + } + + bmips_cbr_addr = (void __iomem *)addr; + /* Since CBR is provided by DT, enable RAC flush */ + bmips_rac_flush_disable = false; + +exit: of_node_put(np); } From patchwork Wed May 8 17:07:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13658933 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCBF1128806; Wed, 8 May 2024 17:07:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715188065; cv=none; b=TZqKv4Y6XFpxhI05mZFctPZyh5PsDc1ldPOqHItY96HIR9DiC5vOjJHjJsDPLhe+qB4IoDvOeOX6fX3o2priw3UDiwHMPQDYmgR60gWlll+wzvl1XBXUj43jF91JC0o13TelrV2jG4dXCkfqtdcDX1xNxYD/fPgA5DkM3D7wlXc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715188065; c=relaxed/simple; bh=jsv8eLzjlbF4u/0Mrmq/BFd2eJZK6yGKo7qJgRpCkys=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cFj7oms9ph5T5BkMteGMH9OMdlNS2OCURQLD+pcBjZZR/8Z7f1v9bsDueI3ad4aKda4zILAXF67T7qNbkpSBz0fXGbgVltyTB41tng1IEYnMCq5FUkkujZpK/gY64M8HuzmjaWOhD7DeeG7p4sHQ8vkGXhjJI/EP5ON+C46W5pk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=BS7fFe9L; arc=none smtp.client-ip=209.85.128.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BS7fFe9L" Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-41ebcf01013so149845e9.0; Wed, 08 May 2024 10:07:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715188062; x=1715792862; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/xbtyC2EsQVkdqMHpm1p6J7lTiGONlDxg+wu3ietGg4=; b=BS7fFe9LrqgtdKrc/cZFJl5gfHyuWv0tJxHdwsyAj1zF7NnKKY9sPn1OHD95KekLZz oVKAbBA6ftZ0fRlIY0WbNxASaBwxO3mp+PH5q/THB+oMpK0b84Eswd5kVq6EbX7KaAbU CmoskPcxy6JP7gUswOOfvsgLNH2uGBViECCv7S1mZ8vQg0/tablR5kCXtRwOYBnmaNgt IVUgpIpXRoKLATSN4BCFNAd8uIRr7GUB9m7uWMY4wvX53Rjz5o7/Y+SEGvH1fwa0g/3/ 32ADNwr5M98Z5Oslal59k4tXmBapG+5yxkdJ5RxBGnt3p/A8Ai1nO3wxbrvHGafAvIgZ WCPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715188062; x=1715792862; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/xbtyC2EsQVkdqMHpm1p6J7lTiGONlDxg+wu3ietGg4=; b=ixe6BlibEWKdto7MP1MIgG1PV3ooT3nPlA/OGrKEpIILz5jUbcoSSinge4W55Ctqx+ 7sYlxo4pI2e6/X3janBjiEXfM0evSBLdXgiT/spLp7hImnmyI+sD5v6YbrjEd2DGtscu Q7OaP1r4DPaVgryNbNPndVXwV1WFpTTmirkxZoQ5v/M2sARUCqLfJiLWgkDGT4KT8ucS T3BgaC+lwFN0G3cpJfL7Yp8PjrCYCyQjGX+b3yDzEWdtQPxCJN8NhBi5GnP8Yz38xRQG TmcSFq8GEBUu9/0uUHfUJI4FlwuA+dflUjpR4iZE7/3Tb/ZoIFrFOkOYYYmant9mUGoC Ur0w== X-Forwarded-Encrypted: i=1; AJvYcCXIDob2bQb+MURRBJeIo8zdSX1MdrSA1Y7RC/NLc/ovcImmJwfCoYIrZazTtqueTbU0FNDwbpGNb8RooTxH+BOSu7nLmJZ2c5ZwA0MVnKpEZVA//1TaxGwZCxx+Vjrp5IwQMyJcXyQ11REwQz9tiReMjjxVxOmncBqoOsBRPJEyo5wWpKk= X-Gm-Message-State: AOJu0Yyfhk55fXQwklq6hqJkrJJ/8v1O2JWN9EstaiwRgIqjYjrPYUcd DQJ9ZnIGtvhojltb3ho9+pUEgtblDVzsL4Y0w0/I8JgPJNpWKc1P X-Google-Smtp-Source: AGHT+IGHklCw3o2XHxFIadESzyyXM9h0yELRBYJCCmh9peT7r46PQ8WwtWQDAvCB2F0gpxwgav75Cw== X-Received: by 2002:a05:600c:3144:b0:419:c9e1:70b8 with SMTP id 5b1f17b1804b1-41fbcd7095fmr2135365e9.13.1715188061886; Wed, 08 May 2024 10:07:41 -0700 (PDT) Received: from localhost.localdomain (93-34-90-105.ip49.fastwebnet.it. [93.34.90.105]) by smtp.googlemail.com with ESMTPSA id fk12-20020a05600c0ccc00b0041c130520fbsm2921555wmb.46.2024.05.08.10.07.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 May 2024 10:07:41 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?utf-8?q?Daniel_Gonz=C3=A1lez_Cabanelas?= , =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= Subject: [PATCH v3 4/4] mips: bmips: enable RAC on BMIPS4350 Date: Wed, 8 May 2024 19:07:20 +0200 Message-ID: <20240508170721.3023-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240508170721.3023-1-ansuelsmth@gmail.com> References: <20240508170721.3023-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel González Cabanelas The data RAC is left disabled by the bootloader in some SoCs, at least in the core it boots from. Enabling this feature increases the performance up to +30% depending on the task. Signed-off-by: Daniel González Cabanelas Signed-off-by: Álvaro Fernández Rojas [ rework code and reduce code duplication ] Signed-off-by: Christian Marangi Acked-by: Florian Fainelli --- arch/mips/kernel/smp-bmips.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index a4f84667a901..0f93963c08e4 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -620,6 +620,23 @@ void bmips_cpu_setup(void) __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); break; + case CPU_BMIPS4350: + u32 rac_addr = BMIPS_RAC_CONFIG_1; + + if (!(read_c0_brcm_cmt_local() & (1 << 31))) + rac_addr = BMIPS_RAC_CONFIG; + + /* Enable data RAC */ + cfg = __raw_readl(bmips_cbr_addr + rac_addr); + __raw_writel(cfg | 0xf, bmips_cbr_addr + rac_addr); + __raw_readl(bmips_cbr_addr + rac_addr); + + /* Flush stale data out of the readahead cache */ + cfg = __raw_readl(bmips_cbr_addr + BMIPS_RAC_CONFIG); + __raw_writel(cfg | 0x100, bmips_cbr_addr + BMIPS_RAC_CONFIG); + __raw_readl(bmips_cbr_addr + BMIPS_RAC_CONFIG); + break; + case CPU_BMIPS4380: /* CBG workaround for early BMIPS4380 CPUs */ switch (read_c0_prid()) {