From patchwork Thu May 9 07:58:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13659519 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1ADCFC25B75 for ; Thu, 9 May 2024 08:04:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1466110E0FF; Thu, 9 May 2024 08:04:28 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="KLCf5l7p"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id BC61910E0FF for ; Thu, 9 May 2024 08:04:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715241867; x=1746777867; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=env05j4BmRBSun3CB2Cw+4FvjdwrH8U9j90V8eQbEQg=; b=KLCf5l7pvTQVrFVyBXn1YAdVPWVQP3ircJ9SluX6Szk2G+9sg0XwGhqt 9sVs71a27n6TPJLtPOnk3LkgiRPTPFWaosa00ypRfYMtoFEcCTQzFJGWw rycs7uh7W2eFi976xXn8A4Kr3K9uzDlv8ozGXn15AgwdGd3TmqHq+ckU5 BDmUiO8QySDzIZYJJutozMCmOIQsuP7GZtPG9EhpbEjuwh4sGt/DKwTGW PqM7qxVMXUGOouDo/vY2tcl3YidZNGWX+P7U1bmIjfYXiZJ+LK/iSiqjZ CYPcfL58G3TczBldFfc6n/k0zT6MSdzcRdknLqDS6PkigqEbzUTXZBtB3 g==; X-CSE-ConnectionGUID: Tx9azyYQR/66G/CA4txpCA== X-CSE-MsgGUID: gIojsnROQqqVx9R97k0Leg== X-IronPort-AV: E=McAfee;i="6600,9927,11067"; a="33656114" X-IronPort-AV: E=Sophos;i="6.08,147,1712646000"; d="scan'208";a="33656114" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2024 01:04:27 -0700 X-CSE-ConnectionGUID: vyWA/GW2R+WMqXnyP59PfQ== X-CSE-MsgGUID: RRH7j1T6QNetmEhJrbhiNA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,147,1712646000"; d="scan'208";a="29043534" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa010.jf.intel.com with ESMTP; 09 May 2024 01:04:26 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: uma.shankar@intel.com, jani.nikula@intel.com Subject: [PATCH v8 1/7] drm/i915: Define and compute Transcoder CMRR registers Date: Thu, 9 May 2024 13:28:27 +0530 Message-Id: <20240509075833.1858363-2-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240509075833.1858363-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240509075833.1858363-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add register definitions for Transcoder Fixed Average Vtotal mode/CMRR function, with the necessary bitfields. Compute these registers when CMRR is enabled, extending Adaptive refresh rate capabilities. --v2: - Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani] - Fix indent and order based on register offset. [Jani] --v3: - Removing RFC tag. --v4: - Update place holder for CMRR register definition. (Jani) Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_display.c | 23 ++++++++++++++++++- .../drm/i915/display/intel_display_types.h | 6 +++++ drivers/gpu/drm/i915/display/intel_vrr.c | 22 ++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++ 4 files changed, 60 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ef986b508431..258a78447fba 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1001,6 +1001,13 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state, old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full; } +static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m || + old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n; +} + static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -5051,6 +5058,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, } \ } while (0) +#define PIPE_CONF_CHECK_LLI(name) do { \ + if (current_config->name != pipe_config->name) { \ + pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ + "(expected %lli, found %lli)", \ + current_config->name, \ + pipe_config->name); \ + ret = false; \ + } \ +} while (0) + #define PIPE_CONF_CHECK_BOOL(name) do { \ if (current_config->name != pipe_config->name) { \ BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \ @@ -5415,10 +5432,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.guardband); PIPE_CONF_CHECK_I(vrr.vsync_start); PIPE_CONF_CHECK_I(vrr.vsync_end); + PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); + PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); } #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I +#undef PIPE_CONF_CHECK_LLI #undef PIPE_CONF_CHECK_BOOL #undef PIPE_CONF_CHECK_P #undef PIPE_CONF_CHECK_FLAGS @@ -6807,7 +6827,8 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, intel_crtc_needs_fastset(new_crtc_state)) icl_set_pipe_chicken(new_crtc_state); - if (vrr_params_changed(old_crtc_state, new_crtc_state)) + if (vrr_params_changed(old_crtc_state, new_crtc_state) || + cmrr_params_changed(old_crtc_state, new_crtc_state)) intel_vrr_set_transcoder_timings(new_crtc_state); } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index a06a154d587b..475fb5252dd4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1396,6 +1396,12 @@ struct intel_crtc_state { u32 vsync_end, vsync_start; } vrr; + /* Content Match Refresh Rate state */ + struct { + bool enable; + u64 cmrr_n, cmrr_m; + } cmrr; + /* Stream Splitter for eDP MSO */ struct { bool enable; diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 894ee97b3e1b..831554ea46b2 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -217,6 +217,19 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) return; } + if (crtc_state->cmrr.enable) { + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), + VRR_CTL_CMRR_ENABLE | trans_vrr_ctl(crtc_state)); + intel_de_write(dev_priv, TRANS_CMRR_M_HI(cpu_transcoder), + upper_32_bits(crtc_state->cmrr.cmrr_m)); + intel_de_write(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder), + lower_32_bits(crtc_state->cmrr.cmrr_m)); + intel_de_write(dev_priv, TRANS_CMRR_N_HI(cpu_transcoder), + upper_32_bits(crtc_state->cmrr.cmrr_n)); + intel_de_write(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder), + lower_32_bits(crtc_state->cmrr.cmrr_n)); + } + intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1); intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1); intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state)); @@ -296,6 +309,15 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + if (crtc_state->cmrr.enable) { + crtc_state->cmrr.cmrr_n = + intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(cpu_transcoder), + TRANS_CMRR_N_HI(cpu_transcoder)); + crtc_state->cmrr.cmrr_m = + intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(cpu_transcoder), + TRANS_CMRR_M_HI(cpu_transcoder)); + } + if (DISPLAY_VER(dev_priv) >= 13) crtc_state->vrr.guardband = REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5670eee4a498..a4a510793344 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1237,6 +1237,7 @@ #define VRR_CTL_VRR_ENABLE REG_BIT(31) #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) +#define VRR_CTL_CMRR_ENABLE REG_BIT(27) #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) @@ -1328,6 +1329,15 @@ #define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) #define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start)) +#define _TRANS_CMRR_M_LO_A 0x604F0 +#define _TRANS_CMRR_M_HI_A 0x604F4 +#define _TRANS_CMRR_N_LO_A 0x604F8 +#define _TRANS_CMRR_N_HI_A 0x604FC +#define TRANS_CMRR_M_LO(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_LO_A) +#define TRANS_CMRR_M_HI(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_HI_A) +#define TRANS_CMRR_N_LO(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_LO_A) +#define TRANS_CMRR_N_HI(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A) + /* VGA port control */ #define ADPA _MMIO(0x61100) #define PCH_ADPA _MMIO(0xe1100) From patchwork Thu May 9 07:58:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13659520 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB9DBC10F1A for ; Thu, 9 May 2024 08:04:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 31C9010E2CC; Thu, 9 May 2024 08:04:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Kawc2EjH"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 91DA410E249 for ; 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09 May 2024 01:04:28 -0700 X-CSE-ConnectionGUID: WSUzboDUR7WjmAMHuS1+jQ== X-CSE-MsgGUID: tPVLNZIARxCtL4Sikg47ng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,147,1712646000"; d="scan'208";a="29043537" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa010.jf.intel.com with ESMTP; 09 May 2024 01:04:27 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: uma.shankar@intel.com, jani.nikula@intel.com Subject: [PATCH v8 2/7] drm/i915: Add Enable/Disable for CMRR based on VRR state Date: Thu, 9 May 2024 13:28:28 +0530 Message-Id: <20240509075833.1858363-3-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240509075833.1858363-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240509075833.1858363-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add CMRR/Fixed Average Vtotal mode enable and disable functions based on change in VRR mode of operation. When Adaptive Sync Vtotal is enabled, Fixed Average Vtotal mode is disabled and vice versa. With this commit setting the stage for subsequent CMRR enablement. --v2: - Check pipe active state in cmrr enabling. [Jani] - Remove usage of bitwise OR on booleans. [Jani] - Revert unrelated changes. [Jani] - Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani] - Simplify whole if-ladder in intel_vrr_enable. [Jani] - Revert patch restructuring mistakes in intel_vrr_get_config. [Jani] --v3: - Check pipe active state in cmrr disabling.[Jani] - Correct messed up condition in intel_vrr_enable. [Jani] --v4: - Removing RFC tag. --v5: - CMRR handling in co-existatnce of LRR and DRRS. --v7: - Rebase on top of AS SDP merge. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_display.c | 37 ++++++++++++++++--- drivers/gpu/drm/i915/display/intel_vrr.c | 38 ++++++++++++-------- 2 files changed, 56 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 258a78447fba..4a5318ab017d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1020,6 +1020,18 @@ static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, vrr_params_changed(old_crtc_state, new_crtc_state))); } +static bool cmrr_enabling(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + if (!new_crtc_state->hw.active) + return false; + + return is_enabling(cmrr.enable, old_crtc_state, new_crtc_state) || + (new_crtc_state->cmrr.enable && + (new_crtc_state->update_m_n || new_crtc_state->update_lrr || + cmrr_params_changed(old_crtc_state, new_crtc_state))); +} + static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -1032,6 +1044,18 @@ static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state, vrr_params_changed(old_crtc_state, new_crtc_state))); } +static bool cmrr_disabling(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + if (!old_crtc_state->hw.active) + return false; + + return is_disabling(cmrr.enable, old_crtc_state, new_crtc_state) || + (old_crtc_state->cmrr.enable && + (new_crtc_state->update_m_n || new_crtc_state->update_lrr || + cmrr_params_changed(old_crtc_state, new_crtc_state))); +} + static bool audio_enabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -1053,7 +1077,6 @@ static bool audio_disabling(const struct intel_crtc_state *old_crtc_state, (old_crtc_state->has_audio && memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0); } - #undef is_disabling #undef is_enabling @@ -1175,7 +1198,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); enum pipe pipe = crtc->pipe; - if (vrr_disabling(old_crtc_state, new_crtc_state)) { + if (vrr_disabling(old_crtc_state, new_crtc_state) || + cmrr_disabling(old_crtc_state, new_crtc_state)) { intel_vrr_disable(old_crtc_state); intel_crtc_update_active_timings(old_crtc_state, false); } @@ -6767,7 +6791,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state, !intel_crtc_needs_modeset(new_crtc_state)) skl_detach_scalers(new_crtc_state); - if (vrr_enabling(old_crtc_state, new_crtc_state)) + if (vrr_enabling(old_crtc_state, new_crtc_state) || + cmrr_enabling(old_crtc_state, new_crtc_state)) intel_vrr_enable(new_crtc_state); } @@ -6868,9 +6893,11 @@ static void intel_update_crtc(struct intel_atomic_state *state, * FIXME Should be synchronized with the start of vblank somehow... */ if (vrr_enabling(old_crtc_state, new_crtc_state) || - new_crtc_state->update_m_n || new_crtc_state->update_lrr) + new_crtc_state->update_m_n || new_crtc_state->update_lrr || + cmrr_enabling(old_crtc_state, new_crtc_state)) intel_crtc_update_active_timings(new_crtc_state, - new_crtc_state->vrr.enable); + new_crtc_state->vrr.enable || + new_crtc_state->cmrr.enable); /* * We usually enable FIFO underrun interrupts as part of the diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 831554ea46b2..83ae56d22b5f 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -242,7 +242,7 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable)) return; intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), @@ -255,7 +255,7 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable)) return false; return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND; @@ -266,18 +266,28 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - if (!crtc_state->vrr.enable) + if (drm_WARN_ON(&dev_priv->drm, crtc_state->vrr.enable && + crtc_state->cmrr.enable)) return; - intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); - - if (HAS_AS_SDP(dev_priv)) - intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder), - VRR_VSYNC_END(crtc_state->vrr.vsync_end) | - VRR_VSYNC_START(crtc_state->vrr.vsync_start)); + if (crtc_state->vrr.enable) { + intel_de_write(dev_priv, + TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); + if (HAS_AS_SDP(dev_priv)) + intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder), + VRR_VSYNC_END(crtc_state->vrr.vsync_end) | + VRR_VSYNC_START(crtc_state->vrr.vsync_start)); + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + } - intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + if (crtc_state->cmrr.enable) { + intel_de_write(dev_priv, + TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); + intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), + VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | + trans_vrr_ctl(crtc_state)); + } } void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) @@ -286,7 +296,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; - if (!old_crtc_state->vrr.enable) + if (!(old_crtc_state->vrr.enable || old_crtc_state->cmrr.enable)) return; intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), @@ -332,10 +342,10 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; } - if (crtc_state->vrr.enable) { + if (crtc_state->vrr.enable || crtc_state->cmrr.enable) { crtc_state->mode_flags |= I915_MODE_FLAG_VRR; - if (HAS_AS_SDP(dev_priv)) { + if (HAS_AS_SDP(dev_priv) && crtc_state->vrr.enable) { trans_vrr_vsync = intel_de_read(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder)); crtc_state->vrr.vsync_start = From patchwork Thu May 9 07:58:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13659521 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E5E0C25B75 for ; Thu, 9 May 2024 08:04:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CD3B210E249; Thu, 9 May 2024 08:04:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="33656116" X-IronPort-AV: E=Sophos;i="6.08,147,1712646000"; d="scan'208";a="33656116" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2024 01:04:30 -0700 X-CSE-ConnectionGUID: qJMyX/imTqyL4B+q+KEHoQ== X-CSE-MsgGUID: byD/1raOToKInZO7wBPIfw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,147,1712646000"; d="scan'208";a="29043541" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa010.jf.intel.com with ESMTP; 09 May 2024 01:04:29 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: uma.shankar@intel.com, jani.nikula@intel.com Subject: [PATCH v8 3/7] drm/i915: Compute CMRR and calculate vtotal Date: Thu, 9 May 2024 13:28:29 +0530 Message-Id: <20240509075833.1858363-4-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240509075833.1858363-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240509075833.1858363-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Compute Fixed Average Vtotal/CMRR with resepect to userspace VRR enablement. Also calculate required parameters in case of CMRR is enabled. During intel_vrr_compute_config, CMRR is getting enabled based on userspace has enabled Adaptive Sync Vtotal mode (Legacy VRR) or not. Make CMRR as small subset of FAVT mode, when Panle is running on Fixed refresh rate and on VRR framework then only enable CMRR to match with actual refresh rate. --v2: - Update is_cmrr_frac_required function return as bool, not int. [Jani] - Use signed int math instead of unsigned in cmrr_get_vtotal2. [Jani] - Fix typo and usage of camel case in cmrr_get_vtotal. [Jani] - Use do_div in cmrr_get_vtotalwhile calculating cmrr_m. [ Jani] - Simplify cmrr and vrr compute config in intel_vrr_compute_config. [Jani] - Correct valiable name usage in is_cmrr_frac_required. [Ville] --v3: - Removing RFC tag. --v4: - Added edp check to address edp usecase for now. (ville) - Updated is_cmrr_fraction_required to more simplified calculation. - on longterm goal to be worked upon uapi as suggestion from ville. --v5: - Correct vtotal paramas accuracy and add 2 digit precision. - Avoid using DIV_ROUND_UP and improve scanline precision. --v6: - Make CMRR a small subset of FAVT mode. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_display.c | 1 + .../drm/i915/display/intel_display_device.h | 1 + drivers/gpu/drm/i915/display/intel_vrr.c | 99 ++++++++++++++++--- 3 files changed, 89 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 4a5318ab017d..8a76db59c85f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5458,6 +5458,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.vsync_end); PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); + PIPE_CONF_CHECK_BOOL(cmrr.enable); } #undef PIPE_CONF_CHECK_X diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 17ddf82f0b6e..b372b1acc19b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -71,6 +71,7 @@ struct drm_printer; BIT(trans)) != 0) #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) #define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13) +#define HAS_CMRR(i915) (DISPLAY_VER(i915) >= 20) #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask)) #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug) #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 83ae56d22b5f..f5ba87fa00fe 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -11,6 +11,9 @@ #include "intel_vrr.h" #include "intel_dp.h" +#define FIXED_POINT_PRECISION 100 +#define CMRR_PRECISION_TOLERANCE 10 + bool intel_vrr_is_capable(struct intel_connector *connector) { const struct drm_display_info *info = &connector->base.display_info; @@ -106,6 +109,59 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state) return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state); } +static bool +is_cmrr_frac_required(struct intel_crtc_state *crtc_state, bool is_edp) +{ + int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line; + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + + if (!(HAS_CMRR(i915) && is_edp)) + return false; + + actual_refresh_k = + drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION; + pixel_clock_per_line = + adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal; + calculated_refresh_k = + pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal; + + if ((actual_refresh_k - calculated_refresh_k) < CMRR_PRECISION_TOLERANCE) + return false; + + return true; +} + +static unsigned int +cmrr_get_vtotal(struct intel_crtc_state *crtc_state) +{ + int multiplier_m = 1, multiplier_n = 1, vtotal; + int actual_refresh_rate, desired_refresh_rate; + long long actual_pixel_rate, adjusted_pixel_rate, pixel_clock_per_line; + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + + pixel_clock_per_line = + adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal; + actual_refresh_rate = + pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal; + desired_refresh_rate = drm_mode_vrefresh(adjusted_mode); + actual_pixel_rate = actual_refresh_rate * adjusted_mode->crtc_vtotal; + actual_pixel_rate = + (actual_pixel_rate * adjusted_mode->crtc_htotal) / FIXED_POINT_PRECISION; + + multiplier_m = 1001; + multiplier_n = 1000; + + crtc_state->cmrr.cmrr_n = + ((desired_refresh_rate * adjusted_mode->crtc_htotal * multiplier_n) / multiplier_m); + crtc_state->cmrr.cmrr_n *= multiplier_n; + vtotal = (actual_pixel_rate * multiplier_n) / crtc_state->cmrr.cmrr_n; + adjusted_pixel_rate = actual_pixel_rate * multiplier_m; + crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n); + + return vtotal; +} + void intel_vrr_compute_config(struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -115,6 +171,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, struct intel_connector *connector = to_intel_connector(conn_state->connector); struct intel_dp *intel_dp = intel_attached_dp(connector); + bool is_edp = intel_dp_is_edp(intel_dp); struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; const struct drm_display_info *info = &connector->base.display_info; int vmin, vmax; @@ -159,18 +216,10 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; /* - * For XE_LPD+, we use guardband and pipeline override - * is deprecated. + * When panel is VRR capable and userspace has + * not enabled adaptive sync mode then Fixed Average + * Vtotal mode should be enabled. */ - if (DISPLAY_VER(i915) >= 13) { - crtc_state->vrr.guardband = - crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start; - } else { - crtc_state->vrr.pipeline_full = - min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start - - crtc_state->framestart_delay - 1); - } - if (crtc_state->uapi.vrr_enabled) { crtc_state->vrr.enable = true; crtc_state->mode_flags |= I915_MODE_FLAG_VRR; @@ -182,6 +231,25 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, (crtc_state->hw.adjusted_mode.crtc_vtotal - crtc_state->hw.adjusted_mode.vsync_end); } + } else if (is_cmrr_frac_required(crtc_state, is_edp)) { + crtc_state->cmrr.enable = true; + crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state); + crtc_state->vrr.vmin = crtc_state->vrr.vmax; + crtc_state->vrr.flipline = crtc_state->vrr.vmin; + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; + } + + /* + * For XE_LPD+, we use guardband and pipeline override + * is deprecated. + */ + if (DISPLAY_VER(i915) >= 13) { + crtc_state->vrr.guardband = + crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start; + } else { + crtc_state->vrr.pipeline_full = + min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start - + crtc_state->framestart_delay - 1); } } @@ -317,7 +385,14 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); - crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + if (HAS_CMRR(dev_priv)) { + crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE) && + (trans_vrr_ctl & VRR_CTL_VRR_ENABLE); + crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE && + !(trans_vrr_ctl & VRR_CTL_CMRR_ENABLE); + } else { + crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + } if (crtc_state->cmrr.enable) { crtc_state->cmrr.cmrr_n = From patchwork Thu May 9 07:58:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13659522 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87020C25B74 for ; Thu, 9 May 2024 08:04:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 155AB10E412; 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X-CSE-ConnectionGUID: DHQ2trknTteQoc+7DZnpug== X-CSE-MsgGUID: NhjPeSFVSQKdtyCRGk/x9w== X-IronPort-AV: E=McAfee;i="6600,9927,11067"; a="33656120" X-IronPort-AV: E=Sophos;i="6.08,147,1712646000"; d="scan'208";a="33656120" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2024 01:04:31 -0700 X-CSE-ConnectionGUID: Y6g/O3+MRb21gz+9nmfsUg== X-CSE-MsgGUID: 7FtUkX71R8Wt8z41ryyl0Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,147,1712646000"; d="scan'208";a="29043544" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa010.jf.intel.com with ESMTP; 09 May 2024 01:04:31 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: uma.shankar@intel.com, jani.nikula@intel.com Subject: [PATCH v8 4/7] Add refresh rate divider to struct representing AS SDP Date: Thu, 9 May 2024 13:28:30 +0530 Message-Id: <20240509075833.1858363-5-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240509075833.1858363-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240509075833.1858363-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add target_rr_divider to structure representing AS SDP. It is valid only in FAVT mode, sink device ignores the bit in AVT mode. Signed-off-by: Mitul Golani Reviewed-by: Arun R Murthy --- include/drm/display/drm_dp_helper.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h index 8bed890eec2c..393dbf8cf6ab 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -122,6 +122,7 @@ struct drm_dp_as_sdp { int target_rr; int duration_incr_ms; int duration_decr_ms; + bool target_rr_divider; enum operation_mode mode; }; From patchwork Thu May 9 07:58:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13659523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4616DC10F1A for ; Thu, 9 May 2024 08:04:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8512510E463; Thu, 9 May 2024 08:04:34 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="lzFwsA+i"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id D447510E463 for ; Thu, 9 May 2024 08:04:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715241873; x=1746777873; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=I2mFuoiwgH9k/3EyytpbrY6aCC0hbCodgv/T9LL7a7Y=; b=lzFwsA+iKb4nxGJkjnNdSNHj06Jay6/5ImGPMBRnc22B2xwQn3rOwhZg jsB3A/Hss53piVGDyR8iLHp77GE7elX8cKwFt3QYtevlxmC9VXCW5gj8S YtP6WIldyhxq+VjZz4fS8YELWDPw7C/tVGM+rp4Wf1+H2Dc7XCde+5RWp UOhc7g9aQVkzetj1m+zv+AR8NvTSp65NX0CDHi3yluudi6Ftbhis7o5ll 0C1+pHCta5rSy5Fn6lvlCffV4sAQIHX3a73z8v3okTJL2cA+nAmnSBJvs uZBvTjdJjzaloq8ug2r9r9uOdsigZ6NmhbRe7oZO0vJeeeXAnZfKXy8+N A==; X-CSE-ConnectionGUID: PNvFhgLbSWGzSLjvEkuMsw== X-CSE-MsgGUID: 9GYeCH6YThCBFVsO8TnPuA== X-IronPort-AV: E=McAfee;i="6600,9927,11067"; a="33656122" X-IronPort-AV: E=Sophos;i="6.08,147,1712646000"; d="scan'208";a="33656122" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2024 01:04:33 -0700 X-CSE-ConnectionGUID: eFlBYuZ9QMmGi+w6ODgUoA== X-CSE-MsgGUID: 6pl0IBHqQKStjEXoDeh5AQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,147,1712646000"; d="scan'208";a="29043548" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa010.jf.intel.com with ESMTP; 09 May 2024 01:04:32 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: uma.shankar@intel.com, jani.nikula@intel.com Subject: [PATCH v8 5/7] drm/i915/display: Add support for pack and unpack Date: Thu, 9 May 2024 13:28:31 +0530 Message-Id: <20240509075833.1858363-6-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240509075833.1858363-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240509075833.1858363-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add support of pack and unpack for target_rr_divider. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_dp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 486361eb0070..523956193fbf 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4228,7 +4228,7 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, sdp->db[1] = as_sdp->vtotal & 0xFF; sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF; sdp->db[3] = as_sdp->target_rr & 0xFF; - sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3; + sdp->db[4] = (as_sdp->target_rr >> 8) & 0x23; return length; } @@ -4410,6 +4410,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE; as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1]; as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3); + as_sdp->target_rr_divider = sdp->db[4] & 0x20; return 0; } From patchwork Thu May 9 07:58:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13659524 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 113B1C25B74 for ; Thu, 9 May 2024 08:04:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7DA6610E498; Thu, 9 May 2024 08:04:36 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="E7JGn77E"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4946610E463 for ; Thu, 9 May 2024 08:04:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715241874; x=1746777874; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iqZ4PqHtMEFb6OJlglC1mEAkcOq/cPt7kp6YOcnPUy8=; b=E7JGn77EW3L5YkurZNDetsRUcEz2vDmJsTphc9vqEmdgKCi8WtKyDdxn puWbz+nYREj9Zqs/hN3SY2VbuDWCV+iHlA0eP8XdXkCsXf+6nccziNlCE gwvifwfn/xEu/xM03IiuSzoHVVYTw6WubLbVZctFOSmdlrQKL2wpR0wjG OUmTqeOgR02ljFb/FYPRlmAMGEknrmb++XUXcpN4xSoL5gmURIeNd5/Fb nVllj1fGoMFeJ0rd34zCPba/H49TOBYC/ILlJ6csdQdvl98fuT5jUUoff eryHLj2r5d82wgIWlbMchpx4r1R4ce4Oi2tlA44OcJ2Z25Bx28txigTeI Q==; X-CSE-ConnectionGUID: o/FkR6y1S2KaL8jNemEAMg== X-CSE-MsgGUID: JBZT8yP9Teedy+XL7DoGGg== X-IronPort-AV: E=McAfee;i="6600,9927,11067"; a="33656124" X-IronPort-AV: E=Sophos;i="6.08,147,1712646000"; d="scan'208";a="33656124" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2024 01:04:34 -0700 X-CSE-ConnectionGUID: wFiro3bXQGW7q0bPCdUEzw== X-CSE-MsgGUID: VzR/VYoGSUCr4zzV9PEXSg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,147,1712646000"; d="scan'208";a="29043556" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa010.jf.intel.com with ESMTP; 09 May 2024 01:04:34 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: uma.shankar@intel.com, jani.nikula@intel.com Subject: [PATCH v8 6/7] drm/i915/display: Compute Adaptive sync SDP params Date: Thu, 9 May 2024 13:28:32 +0530 Message-Id: <20240509075833.1858363-7-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240509075833.1858363-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240509075833.1858363-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Compute params for Adaptive Sync SDP when Fixed Average Vtotal mode is enabled. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_dp.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 523956193fbf..380659f95b30 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2627,7 +2627,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - if (!crtc_state->vrr.enable || + if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable) || !intel_dp_as_sdp_supported(intel_dp)) return; @@ -2636,11 +2636,20 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, /* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */ as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; as_sdp->length = 0x9; - as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL; - as_sdp->vtotal = adjusted_mode->vtotal; - as_sdp->target_rr = 0; as_sdp->duration_incr_ms = 0; as_sdp->duration_incr_ms = 0; + + if (crtc_state->vrr.enable) { + as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL; + as_sdp->vtotal = adjusted_mode->vtotal; + as_sdp->target_rr = 0; + } else { + as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED; + as_sdp->vtotal = adjusted_mode->vtotal; + as_sdp->target_rr = DIV_ROUND_UP(adjusted_mode->clock * 1000, + adjusted_mode->htotal * adjusted_mode->vtotal); + as_sdp->target_rr_divider = true; + } } static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, From patchwork Thu May 9 07:58:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13659525 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C24BAC10F1A for ; Thu, 9 May 2024 08:04:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2D49510E4DA; Thu, 9 May 2024 08:04:37 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="BwCqCA9M"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id A9DC010E498 for ; Thu, 9 May 2024 08:04:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1715241876; x=1746777876; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0dZ2X86KdrXgkGO8BR9l/07zP5wdk5R1N+box/pG2aY=; b=BwCqCA9MxQC7dwxSNgLP11PJtB6VPMLvcmSTT8yrmYADbwLUDXZ9ZOYZ PuoaKApwE4zfEL/XrdsOUc1VCsbSJN1wxcNgFrjPPgJqvuHSfNfUutshp 677P0omJhFblbDLEKhhj7/0pOKCStlU1lCjE3NCJNdIS3iiIfrWUFE5sP omKJVy6Rph+fter8tKo16LLcgaI8yz9Vu9jyTm1LA4Zo0QrNsMYCeXL8d WkC8tCDcAU/XTWnk8AmsipP08zJcMrBugsTTGjUurSrbE8aMHlAvs4dps u2l76JbueYtX/hxHO+XUI89cTWHwCUUICL0Vr718S5+Oh3ITipZWcwiQg g==; X-CSE-ConnectionGUID: bsA7tlU7SE2i6Qf7VYp4Lw== X-CSE-MsgGUID: pqkWLyMIQWioh5ehQxvmcw== X-IronPort-AV: E=McAfee;i="6600,9927,11067"; a="33656126" X-IronPort-AV: E=Sophos;i="6.08,147,1712646000"; d="scan'208";a="33656126" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2024 01:04:36 -0700 X-CSE-ConnectionGUID: X1R/nO/bSdC5rUVcMCt/FQ== X-CSE-MsgGUID: 5465hz8WSV+bz0TNSdWjLQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,147,1712646000"; d="scan'208";a="29043562" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa010.jf.intel.com with ESMTP; 09 May 2024 01:04:35 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: uma.shankar@intel.com, jani.nikula@intel.com Subject: [PATCH v8 7/7] drm/i915/display: Compute vrr vsync params Date: Thu, 9 May 2024 13:28:33 +0530 Message-Id: <20240509075833.1858363-8-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240509075833.1858363-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240509075833.1858363-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Compute vrr vsync params in case of FAVT as well instead of only to AVT mode of operation. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_vrr.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index f5ba87fa00fe..3713e9b0829b 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -239,6 +239,15 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } + if (intel_dp_as_sdp_supported(intel_dp)) { + crtc_state->vrr.vsync_start = + (crtc_state->hw.adjusted_mode.crtc_vtotal - + crtc_state->hw.adjusted_mode.vsync_start); + crtc_state->vrr.vsync_end = + (crtc_state->hw.adjusted_mode.crtc_vtotal - + crtc_state->hw.adjusted_mode.vsync_end); + } + /* * For XE_LPD+, we use guardband and pipeline override * is deprecated.