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[93.34.90.105]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3502bbbbf08sm2588185f8f.96.2024.05.09.13.48.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 13:48:03 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/4] mips: bmips: rework and cache CBR addr handling Date: Thu, 9 May 2024 22:47:45 +0200 Message-ID: <20240509204750.1538-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240509204750.1538-1-ansuelsmth@gmail.com> References: <20240509204750.1538-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Rework the handling of the CBR address and cache it. This address doesn't change and can be cached instead of reading the register every time. This is in preparation of permitting to tweak the CBR address in DT with broken SoC or bootloader. bmips_cbr_addr is defined in smp-bmips.c to keep compatibility with legacy brcm47xx/brcm63xx and generic BMIPS target. Signed-off-by: Christian Marangi Acked-by: Florian Fainelli --- arch/mips/bcm47xx/prom.c | 2 ++ arch/mips/bcm63xx/prom.c | 3 +++ arch/mips/bmips/dma.c | 2 +- arch/mips/bmips/setup.c | 4 +++- arch/mips/include/asm/bmips.h | 1 + arch/mips/kernel/smp-bmips.c | 6 ++++-- 6 files changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c index 99a1ba5394e0..49fe4c535161 100644 --- a/arch/mips/bcm47xx/prom.c +++ b/arch/mips/bcm47xx/prom.c @@ -109,6 +109,8 @@ static __init void prom_init_mem(void) void __init prom_init(void) { + /* Cache CBR addr before CPU/DMA setup */ + bmips_cbr_addr = BMIPS_GET_CBR(); prom_init_mem(); setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0); } diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c index c3a2ea62c5c3..f21dd168171a 100644 --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -22,6 +22,9 @@ void __init prom_init(void) { u32 reg, mask; + /* Cache CBR addr before CPU/DMA setup */ + bmips_cbr_addr = BMIPS_GET_CBR(); + bcm63xx_cpu_init(); /* stop any running watchdog */ diff --git a/arch/mips/bmips/dma.c b/arch/mips/bmips/dma.c index 3779e7855bd7..2bc9c0d4402f 100644 --- a/arch/mips/bmips/dma.c +++ b/arch/mips/bmips/dma.c @@ -9,7 +9,7 @@ bool bmips_rac_flush_disable; void arch_sync_dma_for_cpu_all(void) { - void __iomem *cbr = BMIPS_GET_CBR(); + void __iomem *cbr = bmips_cbr_addr; u32 cfg; if (boot_cpu_type() != CPU_BMIPS3300 && diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index 66a8ba19c287..dba789ec75b3 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -111,7 +111,7 @@ static void bcm6358_quirks(void) * because the bootloader is not initializing it properly. */ bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) || - !!BMIPS_GET_CBR(); + !!bmips_cbr_addr; } static void bcm6368_quirks(void) @@ -144,6 +144,8 @@ static void __init bmips_init_cfe(void) void __init prom_init(void) { + /* Cache CBR addr before CPU/DMA setup */ + bmips_cbr_addr = BMIPS_GET_CBR(); bmips_init_cfe(); bmips_cpu_setup(); register_bmips_smp_ops(); diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h index 581a6a3c66e4..3a1cdfddb987 100644 --- a/arch/mips/include/asm/bmips.h +++ b/arch/mips/include/asm/bmips.h @@ -81,6 +81,7 @@ extern char bmips_smp_movevec[]; extern char bmips_smp_int_vec[]; extern char bmips_smp_int_vec_end[]; +extern void __iomem *bmips_cbr_addr; extern int bmips_smp_enabled; extern int bmips_cpu_offset; extern cpumask_t bmips_booted_mask; diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index b3dbf9ecb0d6..555a5b449ca8 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -46,6 +46,8 @@ int bmips_smp_enabled = 1; int bmips_cpu_offset; cpumask_t bmips_booted_mask; unsigned long bmips_tp1_irqs = IE_IRQ1; +/* CBR addr doesn't change and we can cache it */ +void __iomem *bmips_cbr_addr __read_mostly; #define RESET_FROM_KSEG0 0x80080800 #define RESET_FROM_KSEG1 0xa0080800 @@ -518,7 +520,7 @@ static void bmips_set_reset_vec(int cpu, u32 val) info.val = val; bmips_set_reset_vec_remote(&info); } else { - void __iomem *cbr = BMIPS_GET_CBR(); + void __iomem *cbr = bmips_cbr_addr; if (cpu == 0) __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); @@ -591,7 +593,7 @@ asmlinkage void __weak plat_wired_tlb_setup(void) void bmips_cpu_setup(void) { - void __iomem __maybe_unused *cbr = BMIPS_GET_CBR(); + void __iomem __maybe_unused *cbr = bmips_cbr_addr; u32 __maybe_unused cfg; switch (current_cpu_type()) { From patchwork Thu May 9 20:47:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13660408 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A38FC8061D; Thu, 9 May 2024 20:48:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal: i=1; 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[93.34.90.105]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3502bbbbf08sm2588185f8f.96.2024.05.09.13.48.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 13:48:04 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property Date: Thu, 9 May 2024 22:47:46 +0200 Message-ID: <20240509204750.1538-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240509204750.1538-1-ansuelsmth@gmail.com> References: <20240509204750.1538-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document brcm,bmips-cbr-reg property. Some SoC suffer from a BUG where CBR(Core Base Register) address might badly/never inizialized by the Bootloader or reaching it from co-processor registers if the system boots from secondary CPU results in invalid address. The CBR address is always the same on the SoC. Usage of this property is to give an address also in these broken configuration/bootloader. Signed-off-by: Christian Marangi Acked-by: Conor Dooley --- .../devicetree/bindings/mips/brcm/soc.yaml | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml index 975945ca2888..6b961b62aff2 100644 --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml @@ -55,6 +55,16 @@ properties: under the "cpus" node. $ref: /schemas/types.yaml#/definitions/uint32 + brcm,bmips-cbr-reg: + description: Reference address of the CBR. + Some SoC suffer from a BUG where CBR(Core Base Register) + address might badly/never inizialized by the Bootloader or + reaching it from co-processor registers if the system + boots from secondary CPU results in invalid address. + The CBR address is always the same on the SoC hence it + can be provided in DT to handle these broken case. + $ref: /schemas/types.yaml#/definitions/uint32 + patternProperties: "^cpu@[0-9]$": type: object @@ -64,6 +74,20 @@ properties: required: - mips-hpt-frequency +if: + properties: + compatible: + contains: + enum: + - brcm,bcm6358 + - brcm,bcm6368 + +then: + properties: + cpus: + required: + - brcm,bmips-cbr-reg + additionalProperties: true examples: From patchwork Thu May 9 20:47:47 2024 Content-Type: text/plain; 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[93.34.90.105]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3502bbbbf08sm2588185f8f.96.2024.05.09.13.48.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 13:48:06 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 3/4] mips: bmips: setup: make CBR address configurable Date: Thu, 9 May 2024 22:47:47 +0200 Message-ID: <20240509204750.1538-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240509204750.1538-1-ansuelsmth@gmail.com> References: <20240509204750.1538-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support to provide CBR address from DT to handle broken SoC/Bootloader that doesn't correctly init it. This permits to use the RAC flush even in these condition. To provide a CBR address from DT, the property "brcm,bmips-cbr-reg" needs to be set in the "cpus" node. On DT init, this property presence will be checked and will set the bmips_cbr_addr value accordingly. Also bmips_rac_flush_disable will be set to false as RAC flush can be correctly supported. The CBR address from DT will overwrite the cached one and the one set in the CBR register will be ignored. Also the DT CBR address is validated on being outside DRAM window. Signed-off-by: Christian Marangi Acked-by: Florian Fainelli --- arch/mips/bmips/setup.c | 24 +++++++++++++++++++++++- arch/mips/kernel/smp-bmips.c | 6 +++++- 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index dba789ec75b3..c7d83f0c7b05 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -205,13 +205,35 @@ void __init plat_mem_setup(void) void __init device_tree_init(void) { struct device_node *np; + u32 addr; unflatten_and_copy_device_tree(); /* Disable SMP boot unless both CPUs are listed in DT and !disabled */ np = of_find_node_by_name(NULL, "cpus"); - if (np && of_get_available_child_count(np) <= 1) + if (!np) + return; + + if (of_get_available_child_count(np) <= 1) bmips_smp_enabled = 0; + + /* Check if DT provide a CBR address */ + if (of_property_read_u32(np, "brcm,bmips-cbr-reg", &addr)) + goto exit; + + /* Make sure CBR address is outside DRAM window */ + if (addr >= (u32)memblock_start_of_DRAM() && + addr < (u32)memblock_end_of_DRAM()) { + WARN(1, "DT CBR %x inside DRAM window. Ignoring DT CBR.\n", + addr); + goto exit; + } + + bmips_cbr_addr = (void __iomem *)addr; + /* Since CBR is provided by DT, enable RAC flush */ + bmips_rac_flush_disable = false; + +exit: of_node_put(np); } diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index 555a5b449ca8..20e2fb10022d 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -46,7 +46,11 @@ int bmips_smp_enabled = 1; int bmips_cpu_offset; cpumask_t bmips_booted_mask; unsigned long bmips_tp1_irqs = IE_IRQ1; -/* CBR addr doesn't change and we can cache it */ +/* + * CBR addr doesn't change and we can cache it. + * For broken SoC/Bootloader CBR addr might also be provided via DT + * with "brcm,bmips-cbr-reg" in the "cpus" node. + */ void __iomem *bmips_cbr_addr __read_mostly; #define RESET_FROM_KSEG0 0x80080800 From patchwork Thu May 9 20:47:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 13660410 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 399F085264; Thu, 9 May 2024 20:48:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715287690; cv=none; b=p9aFaPiiA7mhdcxa3TSPR1oflFa8TmqwbUhy1AiUNc8n+JQ4IMNQOZ7OY0WdWgR7yD/I51lpnAEmGuBkr5Lehf2gc7L+EQ/mKMylRfd0kZ9/luUSDcVLafCjfpTw8IU8chYoNx7DNvzNXW52kjK5N1sv/FUnCgxvrpSzfxJairE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715287690; c=relaxed/simple; bh=yxOj5YfSwj2DTCNzCutbgmJ5WuKiiT3kbxTl71R4Wu4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nbzrkwahbbCQa5RFCY3DbLyL1hEdH61vVRiAJB/JwPLVkCZL7E8/Wfbw40JYpfEoZAfPWnQTYTbbt8J7oQFkeSAZTX4Q6cbIsRzqshhdIj3bxIUhhvDKxfnzbIPXNOPfIZhkevwjZJDKhJRqmQSa1WXXWXKqVqU908pZ5/ZuFTA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=iUNKQap1; arc=none smtp.client-ip=209.85.221.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="iUNKQap1" Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-3504f34a086so124023f8f.1; Thu, 09 May 2024 13:48:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715287687; x=1715892487; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CrwA2vIrlWfZjdips+U6g09WGPgGGcS7uLLAmHynIVM=; b=iUNKQap1Aa10dPNN79LVaKNnBoCMrqCSaSYgREGfufDqrRxbZUrn9SjGGpDd+OJmuy LrO+Pviiw+XBFXuvH7L02gt4OnNyUwfVbNrGzkfYJddp1HvutmqjpegdK+Eau0/CNE1W CrRPsy5WS3zEdLbsXd4eNaT1pU+I9mWG3yEdrMjmcgoHbypaktDNfq7kjmOzKuRWyNPa 1JGXABMjzMEdPeSpsliCV2DuZlAeBwL8hILY+dfhRb5x84vZVfDTK7nkhVtTjCn8ExgD +n9gJhCbOQIMXxKno6mamXsubRHJtoyHTRKra14UEPq9upQiEmAzHj29VS/GH2GuxbmQ IElw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715287687; x=1715892487; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CrwA2vIrlWfZjdips+U6g09WGPgGGcS7uLLAmHynIVM=; b=aWvrUmGHUhNLHMMPNOrE9bNq5B3tYUf8tyvYzUXnSdZYOMhec0/b/iviD6nY68QVWV 6Mk/jNO7BRtyih3Sv0ECEu9GTF9Qb4DPCimIZXQk9T0AeLiwfanY/tzD348dI9aPQaMX qMLxqK8KHemwjXmTToRMd9CZevdOopFrOobCC3mPk5KqzZEuBnIvbzqoWpZLTLMd30q4 gts0+xAFJo5CwRDDo+2gop98t/O7yeNQAa6Y+Nor112vyp0GXt7vzdmuYJcJ37LQp2tu vAqAhRZJPqxOf2IeY0Wp5Rpdj2drBqJTdn7AZ4QQS2/jvx0uhETK3o0mHFhPwmVcQakt dM1A== X-Forwarded-Encrypted: i=1; AJvYcCXdbe+QQcS9s+dyJE4gclTuIViVoVA9Man3VK49ZnsvtjsBT+C2H5BVGuK9C9zDk1Vlw9zhTZ3YaUuHTBzGc4lipJnwfUX9FUSwFGgJIvHXPwRIPd7BtMIM0f02hG/ZhPtfLJMPUC/47magDJTzdg7DUXw7Vl4ywsN6afLPyEBqY2YyYpg= X-Gm-Message-State: AOJu0Yzd0FK0WkL7qCvNWRtqrkdJ7IRzxcCwKQmW8hocqV9NRt549qmL RU62s2ZSBEfijuGKdxt38YXicNaLpdl72Z/DfjHY0FHcg4DANkwX X-Google-Smtp-Source: AGHT+IEqtNhXsWIapaiDKzX2IStHjSrOkOX+lqNW4IjUlE6Fw44bR12Dv2O0hQP7GdekuJ9XPwPVyA== X-Received: by 2002:adf:eb12:0:b0:347:9bec:9ba3 with SMTP id ffacd0b85a97d-3504aa64997mr464045f8f.66.1715287687547; Thu, 09 May 2024 13:48:07 -0700 (PDT) Received: from localhost.localdomain (93-34-90-105.ip49.fastwebnet.it. [93.34.90.105]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3502bbbbf08sm2588185f8f.96.2024.05.09.13.48.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 13:48:07 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?utf-8?q?Daniel_Gonz=C3=A1lez_Cabanelas?= , =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= Subject: [PATCH v4 4/4] mips: bmips: enable RAC on BMIPS4350 Date: Thu, 9 May 2024 22:47:48 +0200 Message-ID: <20240509204750.1538-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240509204750.1538-1-ansuelsmth@gmail.com> References: <20240509204750.1538-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Daniel González Cabanelas The data RAC is left disabled by the bootloader in some SoCs, at least in the core it boots from. Enabling this feature increases the performance up to +30% depending on the task. Signed-off-by: Daniel González Cabanelas Signed-off-by: Álvaro Fernández Rojas [ rework code and reduce code duplication ] Signed-off-by: Christian Marangi Acked-by: Florian Fainelli --- arch/mips/kernel/smp-bmips.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index 20e2fb10022d..52324738cbb3 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c @@ -626,6 +626,23 @@ void bmips_cpu_setup(void) __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); break; + case CPU_BMIPS4350: + u32 rac_addr = BMIPS_RAC_CONFIG_1; + + if (!(read_c0_brcm_cmt_local() & (1 << 31))) + rac_addr = BMIPS_RAC_CONFIG; + + /* Enable data RAC */ + cfg = __raw_readl(cbr + rac_addr); + __raw_writel(cfg | 0xf, cbr + rac_addr); + __raw_readl(cbr + rac_addr); + + /* Flush stale data out of the readahead cache */ + cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); + __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); + __raw_readl(cbr + BMIPS_RAC_CONFIG); + break; + case CPU_BMIPS4380: /* CBG workaround for early BMIPS4380 CPUs */ switch (read_c0_prid()) {