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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 May 2024 00:51:35.6540 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fdf3ad1f-ea6b-4ef1-3ccb-08dc71548251 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017096.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8796 It is possible that remote processor is already running before linux boot or remoteproc platform driver probe. Implement required remoteproc framework ops to provide resource table address and connect or disconnect with remote processor in such case. Signed-off-by: Tanmay Shah --- Changes in v2: - Fix following sparse warnings drivers/remoteproc/xlnx_r5_remoteproc.c:827:21: sparse: expected struct rsc_tbl_data *rsc_data_va drivers/remoteproc/xlnx_r5_remoteproc.c:844:18: sparse: expected struct resource_table *rsc_addr drivers/remoteproc/xlnx_r5_remoteproc.c:898:24: sparse: expected void volatile [noderef] __iomem *addr drivers/remoteproc/xlnx_r5_remoteproc.c | 164 +++++++++++++++++++++++- 1 file changed, 160 insertions(+), 4 deletions(-) diff --git a/drivers/remoteproc/xlnx_r5_remoteproc.c b/drivers/remoteproc/xlnx_r5_remoteproc.c index 84243d1dff9f..039370cffa32 100644 --- a/drivers/remoteproc/xlnx_r5_remoteproc.c +++ b/drivers/remoteproc/xlnx_r5_remoteproc.c @@ -25,6 +25,10 @@ /* RX mailbox client buffer max length */ #define MBOX_CLIENT_BUF_MAX (IPI_BUF_LEN_MAX + \ sizeof(struct zynqmp_ipi_message)) + +#define RSC_TBL_XLNX_MAGIC ((uint32_t)'x' << 24 | (uint32_t)'a' << 16 | \ + (uint32_t)'m' << 8 | (uint32_t)'p') + /* * settings for RPU cluster mode which * reflects possible values of xlnx,cluster-mode dt-property @@ -73,6 +77,15 @@ struct mbox_info { struct mbox_chan *rx_chan; }; +/* Xilinx Platform specific data structure */ +struct rsc_tbl_data { + const int version; + const u32 magic_num; + const u32 comp_magic_num; + const u32 rsc_tbl_size; + const uintptr_t rsc_tbl; +} __packed; + /* * Hardcoded TCM bank values. This will stay in driver to maintain backward * compatibility with device-tree that does not have TCM information. @@ -95,20 +108,24 @@ static const struct mem_bank_data zynqmp_tcm_banks_lockstep[] = { /** * struct zynqmp_r5_core * + * @rsc_tbl_va: resource table virtual address * @dev: device of RPU instance * @np: device node of RPU instance * @tcm_bank_count: number TCM banks accessible to this RPU * @tcm_banks: array of each TCM bank data * @rproc: rproc handle + * @rsc_tbl_size: resource table size retrieved from remote * @pm_domain_id: RPU CPU power domain id * @ipi: pointer to mailbox information */ struct zynqmp_r5_core { + struct resource_table *rsc_tbl_va; struct device *dev; struct device_node *np; int tcm_bank_count; struct mem_bank_data **tcm_banks; struct rproc *rproc; + u32 rsc_tbl_size; u32 pm_domain_id; struct mbox_info *ipi; }; @@ -621,10 +638,19 @@ static int zynqmp_r5_rproc_prepare(struct rproc *rproc) { int ret; - ret = add_tcm_banks(rproc); - if (ret) { - dev_err(&rproc->dev, "failed to get TCM banks, err %d\n", ret); - return ret; + /** + * For attach/detach use case, Firmware is already loaded so + * TCM isn't really needed at all. Also, for security TCM can be + * locked in such case and linux may not have access at all. + * So avoid adding TCM banks. TCM power-domains requested during attach + * callback. + */ + if (rproc->state != RPROC_DETACHED) { + ret = add_tcm_banks(rproc); + if (ret) { + dev_err(&rproc->dev, "failed to get TCM banks, err %d\n", ret); + return ret; + } } ret = add_mem_regions_carveout(rproc); @@ -662,6 +688,123 @@ static int zynqmp_r5_rproc_unprepare(struct rproc *rproc) return 0; } +static struct resource_table *zynqmp_r5_get_loaded_rsc_table(struct rproc *rproc, + size_t *size) +{ + struct zynqmp_r5_core *r5_core; + + r5_core = rproc->priv; + + *size = r5_core->rsc_tbl_size; + + return r5_core->rsc_tbl_va; +} + +static int zynqmp_r5_get_rsc_table_va(struct zynqmp_r5_core *r5_core) +{ + struct device *dev = r5_core->dev; + struct rsc_tbl_data *rsc_data_va; + struct resource_table *rsc_addr; + struct resource res_mem; + struct device_node *np; + int ret; + + /** + * It is expected from remote processor firmware to provide resource + * table address via struct rsc_tbl_data data structure. + * Start address of first entry under "memory-region" property list + * contains that data structure which holds resource table address, size + * and some magic number to validate correct resource table entry. + */ + np = of_parse_phandle(r5_core->np, "memory-region", 0); + if (!np) { + dev_err(dev, "failed to get memory region dev node\n"); + return -EINVAL; + } + + ret = of_address_to_resource(np, 0, &res_mem); + if (ret) { + dev_err(dev, "failed to get memory-region resource addr\n"); + return -EINVAL; + } + + rsc_data_va = (struct rsc_tbl_data *)devm_ioremap_wc(dev, res_mem.start, + sizeof(struct rsc_tbl_data)); + if (!rsc_data_va) { + dev_err(dev, "failed to map resource table data address\n"); + return -EIO; + } + + /** + * If RSC_TBL_XLNX_MAGIC number and its complement isn't found then + * do not consider resource table address valid and don't attach + */ + if (rsc_data_va->magic_num != RSC_TBL_XLNX_MAGIC || + rsc_data_va->comp_magic_num != ~RSC_TBL_XLNX_MAGIC) { + dev_dbg(dev, "invalid magic number, won't attach\n"); + return -EINVAL; + } + + rsc_addr = (struct resource_table *)ioremap_wc(rsc_data_va->rsc_tbl, + rsc_data_va->rsc_tbl_size); + if (!rsc_addr) { + dev_err(dev, "failed to get rsc_addr\n"); + return -EINVAL; + } + + /** + * As of now resource table version 1 is expected. Don't fail to attach + * but warn users about it. + */ + if (rsc_addr->ver != 1) + dev_warn(dev, "unexpected resource table version %d\n", + rsc_addr->ver); + + r5_core->rsc_tbl_size = rsc_data_va->rsc_tbl_size; + r5_core->rsc_tbl_va = rsc_addr; + + return 0; +} + +static int zynqmp_r5_attach(struct rproc *rproc) +{ + struct zynqmp_r5_core *r5_core = rproc->priv; + int i, pm_domain_id, ret; + + /* + * Firmware is loaded in TCM. Request TCM power domains to notify + * platform management controller that TCM is in use. This will be + * released during unprepare callback. + */ + for (i = 0; i < r5_core->tcm_bank_count; i++) { + pm_domain_id = r5_core->tcm_banks[i]->pm_domain_id; + ret = zynqmp_pm_request_node(pm_domain_id, + ZYNQMP_PM_CAPABILITY_ACCESS, 0, + ZYNQMP_PM_REQUEST_ACK_BLOCKING); + if (ret < 0) + pr_warn("TCM %d can't be requested\n", i); + } + + return 0; +} + +static int zynqmp_r5_detach(struct rproc *rproc) +{ + struct zynqmp_r5_core *r5_core = rproc->priv; + + /* + * Generate last notification to remote after clearing virtio flag. + * Remote can avoid polling on virtio reset flag if kick is generated + * during detach by host and check virtio reset flag on kick interrupt. + */ + zynqmp_r5_rproc_kick(rproc, 0); + + iounmap((void __iomem *)r5_core->rsc_tbl_va); + r5_core->rsc_tbl_va = NULL; + + return 0; +} + static const struct rproc_ops zynqmp_r5_rproc_ops = { .prepare = zynqmp_r5_rproc_prepare, .unprepare = zynqmp_r5_rproc_unprepare, @@ -673,6 +816,9 @@ static const struct rproc_ops zynqmp_r5_rproc_ops = { .sanity_check = rproc_elf_sanity_check, .get_boot_addr = rproc_elf_get_boot_addr, .kick = zynqmp_r5_rproc_kick, + .get_loaded_rsc_table = zynqmp_r5_get_loaded_rsc_table, + .attach = zynqmp_r5_attach, + .detach = zynqmp_r5_detach, }; /** @@ -723,6 +869,16 @@ static struct zynqmp_r5_core *zynqmp_r5_add_rproc_core(struct device *cdev) goto free_rproc; } + /* + * Move rproc state to DETACHED to give one time opportunity to attach + * if firmware is already available in the memory. This can happen if + * firmware is loaded via debugger or by any other agent in the system. + * If firmware isn't available in the memory and resource table isn't found, + * then rproc state stay OFFLINE. + */ + if (!zynqmp_r5_get_rsc_table_va(r5_core)) + r5_rproc->state = RPROC_DETACHED; + r5_core->rproc = r5_rproc; return r5_core; From patchwork Sat May 11 00:51:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tanmay Shah X-Patchwork-Id: 13662153 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2076.outbound.protection.outlook.com [40.107.101.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D30661BC23; Sat, 11 May 2024 00:51:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.101.76 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 May 2024 00:51:36.4196 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b92d6ced-472d-422a-7280-08dc715482c8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017096.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8723 AMD-Xilinx zynqmp platform contains on-chip sram memory (OCM). R5 cores can access OCM and access is faster than DDR memory but slower than TCM memories available. Sram region can have optional multiple power-domains. Signed-off-by: Tanmay Shah --- Changes in v2: - Fix integer assignement to variable that also fixes following sparse warnings drivers/remoteproc/xlnx_r5_remoteproc.c:995:26: sparse: warning: Using plain integer as NULL pointer drivers/remoteproc/xlnx_r5_remoteproc.c | 221 +++++++++++++++++++++++- 1 file changed, 220 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/xlnx_r5_remoteproc.c b/drivers/remoteproc/xlnx_r5_remoteproc.c index 039370cffa32..e0a78a5d4ad5 100644 --- a/drivers/remoteproc/xlnx_r5_remoteproc.c +++ b/drivers/remoteproc/xlnx_r5_remoteproc.c @@ -56,6 +56,21 @@ struct mem_bank_data { char *bank_name; }; +/** + * struct zynqmp_sram_bank - sram bank description + * + * @sram_res: sram address region information + * @power_domains: Array of pm domain id + * @num_pd: total pm domain id count + * @da: device address of sram + */ +struct zynqmp_sram_bank { + struct resource sram_res; + int *power_domains; + int num_pd; + u32 da; +}; + /** * struct mbox_info * @@ -109,6 +124,8 @@ static const struct mem_bank_data zynqmp_tcm_banks_lockstep[] = { * struct zynqmp_r5_core * * @rsc_tbl_va: resource table virtual address + * @sram: Array of sram memories assigned to this core + * @num_sram: number of sram for this core * @dev: device of RPU instance * @np: device node of RPU instance * @tcm_bank_count: number TCM banks accessible to this RPU @@ -120,6 +137,8 @@ static const struct mem_bank_data zynqmp_tcm_banks_lockstep[] = { */ struct zynqmp_r5_core { struct resource_table *rsc_tbl_va; + struct zynqmp_sram_bank **sram; + int num_sram; struct device *dev; struct device_node *np; int tcm_bank_count; @@ -483,6 +502,69 @@ static int add_mem_regions_carveout(struct rproc *rproc) return 0; } +static int add_sram_carveouts(struct rproc *rproc) +{ + struct zynqmp_r5_core *r5_core = rproc->priv; + struct rproc_mem_entry *rproc_mem; + struct zynqmp_sram_bank *sram; + dma_addr_t dma_addr; + int da, i, j, ret; + size_t len; + + for (i = 0; i < r5_core->num_sram; i++) { + sram = r5_core->sram[i]; + + dma_addr = (dma_addr_t)sram->sram_res.start; + len = resource_size(&sram->sram_res); + da = sram->da; + + for (j = 0; j < sram->num_pd; j++) { + ret = zynqmp_pm_request_node(sram->power_domains[j], + ZYNQMP_PM_CAPABILITY_ACCESS, 0, + ZYNQMP_PM_REQUEST_ACK_BLOCKING); + if (ret < 0) { + dev_err(r5_core->dev, + "failed to request on SRAM pd 0x%x", + sram->power_domains[j]); + goto fail_sram; + } else { + pr_err("sram pd 0x%x request success\n", + sram->power_domains[j]); + } + } + + /* Register associated reserved memory regions */ + rproc_mem = rproc_mem_entry_init(&rproc->dev, NULL, + (dma_addr_t)dma_addr, + len, da, + zynqmp_r5_mem_region_map, + zynqmp_r5_mem_region_unmap, + sram->sram_res.name); + + rproc_add_carveout(rproc, rproc_mem); + rproc_coredump_add_segment(rproc, da, len); + + dev_err(&rproc->dev, "sram carveout %s addr=%llx, da=0x%x, size=0x%lx", + sram->sram_res.name, dma_addr, da, len); + } + + return 0; + +fail_sram: + /* Release current sram pd. */ + while (--j >= 0) + zynqmp_pm_release_node(sram->power_domains[j]); + + /* Release previously requested sram pd. */ + while (--i >= 0) { + sram = r5_core->sram[i]; + for (j = 0; j < sram->num_pd; j++) + zynqmp_pm_release_node(sram->power_domains[j]); + } + + return ret; +} + /* * tcm_mem_unmap() * @rproc: single R5 core's corresponding rproc instance @@ -659,6 +741,12 @@ static int zynqmp_r5_rproc_prepare(struct rproc *rproc) return ret; } + ret = add_sram_carveouts(rproc); + if (ret) { + dev_err(&rproc->dev, "failed to get sram carveout %d\n", ret); + return ret; + } + return 0; } @@ -673,8 +761,9 @@ static int zynqmp_r5_rproc_prepare(struct rproc *rproc) static int zynqmp_r5_rproc_unprepare(struct rproc *rproc) { struct zynqmp_r5_core *r5_core; + struct zynqmp_sram_bank *sram; u32 pm_domain_id; - int i; + int i, j; r5_core = rproc->priv; @@ -685,6 +774,13 @@ static int zynqmp_r5_rproc_unprepare(struct rproc *rproc) "can't turn off TCM bank 0x%x", pm_domain_id); } + /* Release sram power-domains. */ + for (i = 0; i < r5_core->num_sram; i++) { + sram = r5_core->sram[i]; + for (j = 0; j < sram->num_pd; j++) + zynqmp_pm_release_node(sram->power_domains[j]); + } + return 0; } @@ -887,6 +983,123 @@ static struct zynqmp_r5_core *zynqmp_r5_add_rproc_core(struct device *cdev) return ERR_PTR(ret); } +static int zynqmp_r5_get_sram_pd(struct device *r5_core_dev, + struct device_node *sram_np, int **power_domains, + int *num_pd) +{ + struct of_phandle_args out_args; + int pd_count, i, ret; + int *pd_list; + + if (!of_find_property(sram_np, "power-domains", NULL)) { + *num_pd = 0; + return 0; + } + + pd_count = of_count_phandle_with_args(sram_np, "power-domains", + "#power-domain-cells"); + + pd_list = devm_kcalloc(r5_core_dev, pd_count, sizeof(int), GFP_KERNEL); + if (!pd_list) + return -ENOMEM; + + for (i = 0; i < pd_count; i++) { + ret = of_parse_phandle_with_args(sram_np, "power-domains", + "#power-domain-cells", + i, &out_args); + if (ret) { + dev_err(r5_core_dev, "%s: power-domains idx %d parsing failed\n", + sram_np->name, i); + return ret; + } + + of_node_put(out_args.np); + pd_list[i] = out_args.args[0]; + } + + *power_domains = pd_list; + *num_pd = pd_count; + + return 0; +} + +static int zynqmp_r5_get_sram_banks(struct zynqmp_r5_core *r5_core) +{ + struct zynqmp_sram_bank **sram, *sram_data; + struct device_node *np = r5_core->np; + struct device *dev = r5_core->dev; + struct device_node *sram_np; + int num_sram, i, ret; + u64 abs_addr, size; + + num_sram = of_property_count_elems_of_size(np, "sram", sizeof(phandle)); + if (num_sram <= 0) { + dev_err(dev, "Invalid sram property, ret = %d\n", + num_sram); + return -EINVAL; + } + + sram = devm_kcalloc(dev, num_sram, + sizeof(struct zynqmp_sram_bank *), GFP_KERNEL); + if (!sram) + return -ENOMEM; + + for (i = 0; i < num_sram; i++) { + sram_data = devm_kzalloc(dev, sizeof(struct zynqmp_sram_bank), + GFP_KERNEL); + if (!sram_data) + return -ENOMEM; + + sram_np = of_parse_phandle(np, "sram", i); + if (!sram_np) { + dev_err(dev, "failed to get sram %d phandle\n", i); + return -EINVAL; + } + + if (!of_device_is_available(sram_np)) { + of_node_put(sram_np); + dev_err(dev, "sram device not available\n"); + return -EINVAL; + } + + ret = of_address_to_resource(sram_np, 0, &sram_data->sram_res); + of_node_put(sram_np); + if (ret) { + dev_err(dev, "addr to res failed\n"); + return ret; + } + + /* Get SRAM device address */ + ret = of_property_read_reg(sram_np, i, &abs_addr, &size); + if (ret) { + dev_err(dev, "failed to get reg property\n"); + return ret; + } + + sram_data->da = (u32)abs_addr; + + ret = zynqmp_r5_get_sram_pd(r5_core->dev, sram_np, + &sram_data->power_domains, + &sram_data->num_pd); + if (ret) { + dev_err(dev, "failed to get power-domains for %d sram\n", i); + return ret; + } + + sram[i] = sram_data; + + dev_dbg(dev, "sram %d: name=%s, addr=0x%llx, da=0x%x, size=0x%llx, num_pd=%d\n", + i, sram[i]->sram_res.name, sram[i]->sram_res.start, + sram[i]->da, resource_size(&sram[i]->sram_res), + sram[i]->num_pd); + } + + r5_core->sram = sram; + r5_core->num_sram = num_sram; + + return 0; +} + static int zynqmp_r5_get_tcm_node_from_dt(struct zynqmp_r5_cluster *cluster) { int i, j, tcm_bank_count, ret, tcm_pd_idx, pd_count; @@ -1101,6 +1314,12 @@ static int zynqmp_r5_core_init(struct zynqmp_r5_cluster *cluster, return ret; } } + + if (of_find_property(r5_core->np, "sram", NULL)) { + ret = zynqmp_r5_get_sram_banks(r5_core); + if (ret) + return ret; + } } return 0;