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Sat, 11 May 2024 16:26:41 -0400 (EDT) From: Jiaxun Yang Date: Sat, 11 May 2024 21:26:35 +0100 Subject: [PATCH] mips64el-softmmu: Enable MTTCG MIME-Version: 1.0 Message-Id: <20240511-mips_mttcg-v1-1-1b71d9b85234@flygoat.com> X-B4-Tracking: v=1; b=H4sIAHrUP2YC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIxMDU0ND3dzMguL43JKS5HRdE/NEsyRDSwNzkyRjJaCGgqLUtMwKsGHRsbW 1AIaoWSdcAAAA To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2652; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=dQbwlpBpzTP6I6Mh3Lfo9FcvSurXB4/+FmQzeaP8ZP4=; b=owGbwMvMwCHmXMhTe71c8zDjabUkhjT7K81bee342az0ArifFsR0iSeH3Ju6rvSlauapRPFjy SG35uzsKGVhEONgkBVTZAkRUOrb0HhxwfUHWX9g5rAygQxh4OIUgInMOMfIcKEwTKpMXehyfIJq +vmLDI2CQY7vzRw4WQvsTkxiZz51kZHh4qvLmmxyNmEK9xbtYKz4Zb9lz5ymeg/3vHOT5lSJhN3 nAAA= X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Received-SPF: pass client-ip=64.147.123.147; envelope-from=jiaxun.yang@flygoat.com; helo=wfout4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org MTTCG was disabled in a092a9554771 ("configure: disable MTTCG for MIPS guests") due to test case instability. I was able to reproduce this issue with in latest QEMU and look into reason behind that. What actually happend is kernel's CP0 timer synchronisation mechanism assumed a consistent latency in memory access between cores, which TCG can't guarantee. Thus there is a huge drift in count value between cores, and in early kernel versions CP0 timer is always used as sched_clock. sched_clock drift back on some cores triggered RCU watchdog in some extreme cases. This can be resolved by setting clocksource to MIPS, which allows clocksource to drift together with sched_clock. However this will leed to other problems after boot. Another option would beupdating kernel to later version, which will use GIC as sched_clock. In non-MTTCG build, the execution is slow enough so kernel won't observe back drifts. Test results: With clocksource=MIPS ``` ~/tmp/retry/retry.py -n 100 -c -- ./qemu-system-mips64el \ -display none -vga none -serial mon:stdio \ -machine malta -kernel ./vmlinux-4.7.0-rc1.I6400 \ -cpu I6400 -smp 8 -vga std \ -append "printk.time=0 clocksource=MIPS console=tty0 console=ttyS0 panic=-1" \ --no-reboot 100, 0, PASS, 5.258126, 100, 100, - Results summary: 0: 100 times (100.00%), avg time 6.508 (55.53 varience/7.45 deviation) Ran command 100 times, 100 passes ``` With linux-next: ``` ~/tmp/retry/retry.py -n 100 -c -- ./qemu-system-mips64el \ -display none -vga none -serial mon:stdio \ -machine malta -kernel ~/linux-next/vmlinux \ -cpu I6400 -smp 8 -vga std \ -append "printk.time=0 console=tty0 console=ttyS0 panic=-1" \ --no-reboot 100, 0, PASS, 4.507921, 100, 100, - Results summary: 0: 100 times (100.00%), avg time 4.233 (0.04 varience/0.21 deviation) Ran command 100 times, 100 passes ``` Signed-off-by: Jiaxun Yang Reviewed-by: Pierrick Bouvier --- I'll leave the test case alone as it's already marked as QEMU_TEST_FLAKY_TESTS --- configs/targets/mips64el-softmmu.mak | 1 + 1 file changed, 1 insertion(+) --- base-commit: 248f6f62df073a3b4158fd0093863ab885feabb5 change-id: 20240511-mips_mttcg-47a6b19074b3 Best regards, diff --git a/configs/targets/mips64el-softmmu.mak b/configs/targets/mips64el-softmmu.mak index 8d9ab3ddc4b1..199b1d909a7d 100644 --- a/configs/targets/mips64el-softmmu.mak +++ b/configs/targets/mips64el-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=mips64 TARGET_BASE_ARCH=mips +TARGET_SUPPORTS_MTTCG=y TARGET_NEED_FDT=y