From patchwork Tue May 14 08:18:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13663853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3BC82C04FFE for ; Tue, 14 May 2024 08:18:44 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.721217.1124442 (Exim 4.92) (envelope-from ) id 1s6nMo-00048I-4R; Tue, 14 May 2024 08:18:34 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 721217.1124442; Tue, 14 May 2024 08:18:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s6nMo-00048B-19; Tue, 14 May 2024 08:18:34 +0000 Received: by outflank-mailman (input) for mailman id 721217; Tue, 14 May 2024 08:18:32 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s6nMm-000483-9G for xen-devel@lists.xenproject.org; Tue, 14 May 2024 08:18:32 +0000 Received: from pb-smtp2.pobox.com (pb-smtp2.pobox.com [64.147.108.71]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 89b10015-11ca-11ef-b4bb-af5377834399; Tue, 14 May 2024 10:18:28 +0200 (CEST) Received: from pb-smtp2.pobox.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id B6DF02C401; Tue, 14 May 2024 04:18:27 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp2.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id AC85F2C3FE; Tue, 14 May 2024 04:18:27 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp2.pobox.com (Postfix) with ESMTPSA id E52922C3FD; Tue, 14 May 2024 04:18:26 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 89b10015-11ca-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=6W+coo3XknLwYEm/aCICEBr73 mGn+RWQy4lYwn4OC8E=; b=kHbgHxQQKm/+QulFNZUHDx2aMocV6pEtUBc8WTbcO PGsoC2uOt32ES60IWdGfwKfuej/4+E0X3nMOA+AN9GgBR73g63MDrc9TKkVirt6u Y0gkNk7bHOXW7E4Y7DPx93xZYmqa0k1uWQdwmv/d5ZlGZ2naHvw+TfKyh8UboaPR dk= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini , Andrew Cooper Subject: [XEN PATCH v3 1/6] x86/vpmu: separate amd/intel vPMU code Date: Tue, 14 May 2024 11:18:25 +0300 Message-Id: <1deef9f4c7b362d8a0a33d0908293735953a066f.1715673586.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 8A16083A-11CA-11EF-A903-25B3960A682E-90055647!pb-smtp2.pobox.com Build AMD vPMU when CONFIG_AMD is on, and Intel vPMU when CONFIG_INTEL is on respectively, allowing for a plaftorm-specific build. No functional change intended. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini Acked-by: Jan Beulich CC: Andrew Cooper --- changes in v3: - neither of the blank lines dropped changes in v2: - drop static inline stubs, use #idef/#endif in vpmu_init)() changes in v1: - switch to CONFIG_{AMD,INTEL} instead of CONFIG_{SVM,VMX} --- xen/arch/x86/cpu/Makefile | 4 +++- xen/arch/x86/cpu/vpmu.c | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile index 35561fe51d..eafce5f204 100644 --- a/xen/arch/x86/cpu/Makefile +++ b/xen/arch/x86/cpu/Makefile @@ -10,4 +10,6 @@ obj-y += intel.o obj-y += intel_cacheinfo.o obj-y += mwait-idle.o obj-y += shanghai.o -obj-y += vpmu.o vpmu_amd.o vpmu_intel.o +obj-y += vpmu.o +obj-$(CONFIG_AMD) += vpmu_amd.o +obj-$(CONFIG_INTEL) += vpmu_intel.o diff --git a/xen/arch/x86/cpu/vpmu.c b/xen/arch/x86/cpu/vpmu.c index b2e9881e06..a7bc0cd1fc 100644 --- a/xen/arch/x86/cpu/vpmu.c +++ b/xen/arch/x86/cpu/vpmu.c @@ -827,6 +827,7 @@ static int __init cf_check vpmu_init(void) switch ( vendor ) { +#ifdef CONFIG_AMD case X86_VENDOR_AMD: ops = amd_vpmu_init(); break; @@ -834,10 +835,13 @@ static int __init cf_check vpmu_init(void) case X86_VENDOR_HYGON: ops = hygon_vpmu_init(); break; +#endif +#ifdef CONFIG_INTEL case X86_VENDOR_INTEL: ops = core2_vpmu_init(); break; +#endif default: printk(XENLOG_WARNING "VPMU: Unknown CPU vendor: %d. " From patchwork Tue May 14 08:20:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13663854 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F6EBC25B75 for ; Tue, 14 May 2024 08:20:41 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.721221.1124462 (Exim 4.92) (envelope-from ) id 1s6nOj-00069R-LB; Tue, 14 May 2024 08:20:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 721221.1124462; Tue, 14 May 2024 08:20:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s6nOj-00069K-Ha; Tue, 14 May 2024 08:20:33 +0000 Received: by outflank-mailman (input) for mailman id 721221; Tue, 14 May 2024 08:20:32 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s6nOi-0005rU-SE for xen-devel@lists.xenproject.org; Tue, 14 May 2024 08:20:32 +0000 Received: from pb-smtp2.pobox.com (pb-smtp2.pobox.com [64.147.108.71]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id d3fac39d-11ca-11ef-909d-e314d9c70b13; Tue, 14 May 2024 10:20:31 +0200 (CEST) Received: from pb-smtp2.pobox.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id BBFB52C412; Tue, 14 May 2024 04:20:30 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp2.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id B2F2A2C411; Tue, 14 May 2024 04:20:30 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp2.pobox.com (Postfix) with ESMTPSA id CD3482C410; Tue, 14 May 2024 04:20:29 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d3fac39d-11ca-11ef-909d-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=KEoZJ3ChXpAiFd7BWBK3KL6eW PK5BEYxIe+pdjJWFys=; b=gzaZXJpLENUGgDM0xBcRY9iqBUCnu/W/4g3hKSbYC e044cikyROYigZv3icqup4fQFXZUT1I5au323iBQE7BIK99lE5FGoJzPiiicO1/N czWi5Oezuy39R8iFByjujTCi8RxtHobuFdzLw2fLGLYOkc7PlAELeBDzBKcJR4Ex aA= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Jan Beulich , Stefano Stabellini Subject: [XEN PATCH v3 2/6] x86/intel: move vmce_has_lmce() routine to header Date: Tue, 14 May 2024 11:20:27 +0300 Message-Id: <77bc29d74cdc43539a060bca26495a4115171f6e.1715673586.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: D3578E1A-11CA-11EF-BD28-25B3960A682E-90055647!pb-smtp2.pobox.com Moving this function out of mce_intel.c would make it possible to disable build of Intel MCE code later on, because the function gets called from common x86 code. Also replace boilerplate code that checks for MCG_LMCE_P flag with vmce_has_lmce(), which might contribute to readability a bit. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini CC: Jan Beulich --- changes in v3: - do not check for CONFIG_INTEL - remove CONFIG_INTEL from patch description changes in v2: - move vmce_has_lmce() to cpu/mcheck/mce.h - move IS_ENABLED(CONFIG_INTEL) check inside vmce_has_lmce() - changed description --- xen/arch/x86/cpu/mcheck/mce.h | 5 +++++ xen/arch/x86/cpu/mcheck/mce_intel.c | 4 ---- xen/arch/x86/cpu/mcheck/vmce.c | 5 ++--- xen/arch/x86/include/asm/mce.h | 1 - xen/arch/x86/msr.c | 2 ++ 5 files changed, 9 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h index 4806405f96..eba4b536c7 100644 --- a/xen/arch/x86/cpu/mcheck/mce.h +++ b/xen/arch/x86/cpu/mcheck/mce.h @@ -170,6 +170,11 @@ static inline int mce_bank_msr(const struct vcpu *v, uint32_t msr) return 0; } +static inline bool vmce_has_lmce(const struct vcpu *v) +{ + return v->arch.vmce.mcg_cap & MCG_LMCE_P; +} + struct mce_callbacks { void (*handler)(const struct cpu_user_regs *regs); bool (*check_addr)(uint64_t status, uint64_t misc, int addr_type); diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c index 3f5199b531..af43281cc6 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -1050,7 +1050,3 @@ int vmce_intel_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) return 1; } -bool vmce_has_lmce(const struct vcpu *v) -{ - return v->arch.vmce.mcg_cap & MCG_LMCE_P; -} diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index 353d4f19b2..94d1f021e1 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -199,7 +199,7 @@ int vmce_rdmsr(uint32_t msr, uint64_t *val) * bits are always set in guest MSR_IA32_FEATURE_CONTROL by Xen, so it * does not need to check them here. */ - if ( cur->arch.vmce.mcg_cap & MCG_LMCE_P ) + if ( vmce_has_lmce(cur) ) { *val = cur->arch.vmce.mcg_ext_ctl; mce_printk(MCE_VERBOSE, "MCE: %pv: rd MCG_EXT_CTL %#"PRIx64"\n", @@ -324,8 +324,7 @@ int vmce_wrmsr(uint32_t msr, uint64_t val) break; case MSR_IA32_MCG_EXT_CTL: - if ( (cur->arch.vmce.mcg_cap & MCG_LMCE_P) && - !(val & ~MCG_EXT_CTL_LMCE_EN) ) + if ( vmce_has_lmce(cur) && !(val & ~MCG_EXT_CTL_LMCE_EN) ) cur->arch.vmce.mcg_ext_ctl = val; else ret = -1; diff --git a/xen/arch/x86/include/asm/mce.h b/xen/arch/x86/include/asm/mce.h index 6ce56b5b85..2ec47a71ae 100644 --- a/xen/arch/x86/include/asm/mce.h +++ b/xen/arch/x86/include/asm/mce.h @@ -41,7 +41,6 @@ extern void vmce_init_vcpu(struct vcpu *v); extern int vmce_restore_vcpu(struct vcpu *v, const struct hvm_vmce_vcpu *ctxt); extern int vmce_wrmsr(uint32_t msr, uint64_t val); extern int vmce_rdmsr(uint32_t msr, uint64_t *val); -extern bool vmce_has_lmce(const struct vcpu *v); extern int vmce_enable_mca_cap(struct domain *d, uint64_t cap); DECLARE_PER_CPU(unsigned int, nr_mce_banks); diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 9babd441f9..b0ec96f021 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -24,6 +24,8 @@ #include +#include "cpu/mcheck/mce.h" + DEFINE_PER_CPU(uint32_t, tsc_aux); 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Tue, 14 May 2024 04:22:33 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 1c6266cb-11cb-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=nwJV6QxpfW1VT27LacPTJtctg XhxVUKxAohHmFS/6/8=; b=l1PZlyraEegQH1RDFglOeRqO1bBQmuYIvdTzywUV8 883BMOSgeaVdATiPuQmfK0qaAQmo2uUvL/MPa4/DqpDzR4rwBwN5fd8vTmpc/rdb E7J08pHmX5jVJodHZwZJjEgQctZnkm1uQQHa3cZT+eOCea2qrls/oXVVEB1Qeans KU= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini Subject: [XEN PATCH v3 3/6] x86/MCE: guard access to Intel/AMD-specific MCA MSRs Date: Tue, 14 May 2024 11:22:30 +0300 Message-Id: <15b01508ca14265f643ddfb508481012c21a8c81.1715673586.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 1CE33192-11CB-11EF-B574-25B3960A682E-90055647!pb-smtp2.pobox.com Add build-time checks for newly introduced INTEL/AMD config options when calling vmce_{intel/amd}_{rdmsr/wrmsr}() routines. This way a platform-specific code can be omitted in vmce code, if this platform is disabled in config. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini Acked-by: Jan Beulich --- changes in v3: - neither of the blank lines dropped changes in v2: - use #ifdef/#endif in switch instead of IS_ENABLED - fallback to returning default 0 if vendor not recognized --- xen/arch/x86/cpu/mcheck/vmce.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index 94d1f021e1..5abdf4cb5f 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -138,16 +138,20 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) default: switch ( boot_cpu_data.x86_vendor ) { +#ifdef CONFIG_INTEL case X86_VENDOR_CENTAUR: case X86_VENDOR_SHANGHAI: case X86_VENDOR_INTEL: ret = vmce_intel_rdmsr(v, msr, val); break; +#endif +#ifdef CONFIG_AMD case X86_VENDOR_AMD: case X86_VENDOR_HYGON: ret = vmce_amd_rdmsr(v, msr, val); break; +#endif default: ret = 0; @@ -271,14 +275,18 @@ static int bank_mce_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) default: switch ( boot_cpu_data.x86_vendor ) { +#ifdef CONFIG_INTEL case X86_VENDOR_INTEL: ret = vmce_intel_wrmsr(v, msr, val); break; +#endif +#ifdef CONFIG_AMD case X86_VENDOR_AMD: case X86_VENDOR_HYGON: ret = vmce_amd_wrmsr(v, msr, val); break; +#endif default: ret = 0; From patchwork Tue May 14 08:24:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13663856 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 204EFC04FFE for ; Tue, 14 May 2024 08:24:56 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.721234.1124501 (Exim 4.92) (envelope-from ) id 1s6nSh-0000iq-Sg; Tue, 14 May 2024 08:24:39 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 721234.1124501; Tue, 14 May 2024 08:24:39 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s6nSh-0000ij-Q8; Tue, 14 May 2024 08:24:39 +0000 Received: by outflank-mailman (input) for mailman id 721234; Tue, 14 May 2024 08:24:38 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s6nSg-0000iZ-Cc for xen-devel@lists.xenproject.org; Tue, 14 May 2024 08:24:38 +0000 Received: from pb-smtp2.pobox.com (pb-smtp2.pobox.com [64.147.108.71]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 66826b46-11cb-11ef-909d-e314d9c70b13; Tue, 14 May 2024 10:24:37 +0200 (CEST) Received: from pb-smtp2.pobox.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 968412C438; Tue, 14 May 2024 04:24:36 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp2.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp2.pobox.com (Postfix) with ESMTP id 8E7272C437; Tue, 14 May 2024 04:24:36 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp2.pobox.com (Postfix) with ESMTPSA id AC54B2C436; Tue, 14 May 2024 04:24:35 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 66826b46-11cb-11ef-909d-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=DOe4Y1iXkxyUp7tFZfnk+wWTi 6MegcBusy617K955Vw=; b=dNnzQyHHXWisF2UCubKxGdLgpD9nzaxPIPYosfrfM s66sjbB3m2gP4ksCMxBS0LM600DhTUOMrCXG19R0A/Tb0cMxhWSKkhlKMJwTC/6I kVXYckDxmwS7mLtc5jhee8Fgrx+J9kexgsBbtT0t5Mp3AUW/DuOPaS78GvGh4kU1 fk= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Stefano Stabellini Subject: [XEN PATCH v3 4/6] x86/MCE: guard {intel/amd}_mcheck_init() calls Date: Tue, 14 May 2024 11:24:34 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: 65E4360C-11CB-11EF-B5B5-25B3960A682E-90055647!pb-smtp2.pobox.com Guard calls to CPU-specific mcheck init routines in common MCE code using new INTEL/AMD config options. The purpose is not to build platform-specific mcheck code and calls to it, if this platform is disabled in config. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini Acked-by: Jan Beulich --- changes in v3: - neither of the blank lines dropped changes in v2: - use #ifdef/#endif in switch instead of IS_ENABLED --- xen/arch/x86/cpu/mcheck/mce.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index d179e6b068..fb9dec5b89 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -760,11 +760,14 @@ void mcheck_init(struct cpuinfo_x86 *c, bool bsp) switch ( c->x86_vendor ) { +#ifdef CONFIG_AMD case X86_VENDOR_AMD: case X86_VENDOR_HYGON: inited = amd_mcheck_init(c, bsp); break; +#endif +#ifdef CONFIG_INTEL case X86_VENDOR_INTEL: switch ( c->x86 ) { @@ -774,6 +777,7 @@ void mcheck_init(struct cpuinfo_x86 *c, bool bsp) break; } break; +#endif default: break; From patchwork Tue May 14 08:26:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13663858 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 635A5C04FFE for ; Tue, 14 May 2024 08:26:51 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.721244.1124511 (Exim 4.92) (envelope-from ) id 1s6nUh-0001HF-6k; Tue, 14 May 2024 08:26:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 721244.1124511; Tue, 14 May 2024 08:26:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s6nUh-0001H8-45; Tue, 14 May 2024 08:26:43 +0000 Received: by outflank-mailman (input) for mailman id 721244; Tue, 14 May 2024 08:26:42 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s6nUg-0001Fw-IG for xen-devel@lists.xenproject.org; Tue, 14 May 2024 08:26:42 +0000 Received: from pb-smtp1.pobox.com (pb-smtp1.pobox.com [64.147.108.70]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id aed7ce1c-11cb-11ef-b4bb-af5377834399; Tue, 14 May 2024 10:26:39 +0200 (CEST) Received: from pb-smtp1.pobox.com (unknown [127.0.0.1]) by pb-smtp1.pobox.com (Postfix) with ESMTP id 9A8773A519; Tue, 14 May 2024 04:26:39 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp1.nyi.icgroup.com (unknown [127.0.0.1]) by pb-smtp1.pobox.com (Postfix) with ESMTP id 925253A518; Tue, 14 May 2024 04:26:39 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp1.pobox.com (Postfix) with ESMTPSA id AC8CB3A517; Tue, 14 May 2024 04:26:38 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: aed7ce1c-11cb-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=GoMafCLne/uUKmiYB7IOb56hQ 84XAcKbV1FNoVwd924=; b=kWgqULECWj7S5aPYR9geqJ712VegbpJ30HHUx9wt0 CudWqLcV13ohBJ8nf8myrELsuzJDcLaLwMd8kN53D7FIThuh/BWW+tP7UWs0SjaA P2EoIsSnWQvlh3FNtmCk0feTjhVEhgMYPvPrAg7/6f1n/kctj7+O3c8HhxA9GYuw UU= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Jan Beulich , Stefano Stabellini Subject: [XEN PATCH v3 5/6] x86/MCE: add default switch case in init_nonfatal_mce_checker() Date: Tue, 14 May 2024 11:26:36 +0300 Message-Id: <01aad263ad60f37ed74138b5abf2733361bb7d25.1715673586.git.Sergiy_Kibrik@epam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: AF33E1E0-11CB-11EF-B499-78DCEB2EC81B-90055647!pb-smtp1.pobox.com The default switch case block is likely wanted here, to handle situation e.g. of unexpected c->x86_vendor value -- then no mcheck init is done, but misleading message still gets logged anyway. Signed-off-by: Sergiy Kibrik CC: Jan Beulich --- xen/arch/x86/cpu/mcheck/non-fatal.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/arch/x86/cpu/mcheck/non-fatal.c b/xen/arch/x86/cpu/mcheck/non-fatal.c index 33cacd15c2..c5d8e3aea9 100644 --- a/xen/arch/x86/cpu/mcheck/non-fatal.c +++ b/xen/arch/x86/cpu/mcheck/non-fatal.c @@ -29,9 +29,13 @@ static int __init cf_check init_nonfatal_mce_checker(void) /* Assume we are on K8 or newer AMD or Hygon CPU here */ amd_nonfatal_mcheck_init(c); break; + case X86_VENDOR_INTEL: intel_nonfatal_mcheck_init(c); break; + + default: + return -ENODEV; } printk(KERN_INFO "mcheck_poll: Machine check polling timer started.\n"); return 0; From patchwork Tue May 14 08:28:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiy Kibrik X-Patchwork-Id: 13663859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D4539C04FFE for ; Tue, 14 May 2024 08:29:04 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.721247.1124522 (Exim 4.92) (envelope-from ) id 1s6nWk-0001qe-IL; Tue, 14 May 2024 08:28:50 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 721247.1124522; Tue, 14 May 2024 08:28:50 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s6nWk-0001qX-Fc; Tue, 14 May 2024 08:28:50 +0000 Received: by outflank-mailman (input) for mailman id 721247; Tue, 14 May 2024 08:28:49 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s6nWj-0001qM-Pe for xen-devel@lists.xenproject.org; Tue, 14 May 2024 08:28:49 +0000 Received: from pb-smtp21.pobox.com (pb-smtp21.pobox.com [173.228.157.53]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id fbb6f8a2-11cb-11ef-909d-e314d9c70b13; Tue, 14 May 2024 10:28:48 +0200 (CEST) Received: from pb-smtp21.pobox.com (unknown [127.0.0.1]) by pb-smtp21.pobox.com (Postfix) with ESMTP id 714143ABE3; Tue, 14 May 2024 04:28:46 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from pb-smtp21.sea.icgroup.com (unknown [127.0.0.1]) by pb-smtp21.pobox.com (Postfix) with ESMTP id 697223ABE2; Tue, 14 May 2024 04:28:46 -0400 (EDT) (envelope-from sakib@darkstar.site) Received: from localhost (unknown [185.130.54.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by pb-smtp21.pobox.com (Postfix) with ESMTPSA id 2047F3ABE1; Tue, 14 May 2024 04:28:43 -0400 (EDT) (envelope-from sakib@darkstar.site) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fbb6f8a2-11cb-11ef-909d-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed; d=pobox.com; h=from:to:cc :subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; s=sasl; bh=V/rp56yIvzwZLQTcJkKC13OhS ElWeNBBG3Y1G7bl8LU=; b=FX2BaCLA/Gq0MJ8Cs1ZR+MHETL5gc93Jc3p0/Issb 3c04s2Q/HEWrFeVdipup8iXCbyOIH+dFHvDnPY9e9owRGIGwld3Opj2ImqwwTKJ9 azu3C7xksbbu6EPs1FmDkzEidWadI3oSLqcB8/DVSkGQT/aaHZHJcax95JDlmZOt bI= From: Sergiy Kibrik To: xen-devel@lists.xenproject.org Cc: Sergiy Kibrik , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Jan Beulich , Stefano Stabellini Subject: [XEN PATCH v3 6/6] x86/MCE: optional build of AMD/Intel MCE code Date: Tue, 14 May 2024 11:28:39 +0300 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Pobox-Relay-ID: F95E0F20-11CB-11EF-ADA0-A19503B9AAD1-90055647!pb-smtp21.pobox.com Separate Intel/AMD-specific MCE code using CONFIG_{INTEL,AMD} config options. Now we can avoid build of mcheck code if support for specific platform is intentionally disabled by configuration. Also global variables lmce_support & cmci_support from Intel-specific mce_intel.c have to moved to common mce.c, as they get checked in common code. Signed-off-by: Sergiy Kibrik Reviewed-by: Stefano Stabellini CC: Jan Beulich Acked-by: Jan Beulich --- changes in v3: - default return value of init_nonfatal_mce_checker() done in separate patch - move lmce_support & cmci_support to common mce.c code - changed patch description changes in v2: - fallback to original ordering in Makefile - redefine lmce_support & cmci_support global vars to false when !INTEL - changed patch description --- xen/arch/x86/cpu/mcheck/Makefile | 8 ++++---- xen/arch/x86/cpu/mcheck/mce.c | 4 ++++ xen/arch/x86/cpu/mcheck/mce_intel.c | 4 ---- xen/arch/x86/cpu/mcheck/non-fatal.c | 4 ++++ 4 files changed, 12 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/Makefile b/xen/arch/x86/cpu/mcheck/Makefile index f927f10b4d..e6cb4dd503 100644 --- a/xen/arch/x86/cpu/mcheck/Makefile +++ b/xen/arch/x86/cpu/mcheck/Makefile @@ -1,12 +1,12 @@ -obj-y += amd_nonfatal.o -obj-y += mce_amd.o +obj-$(CONFIG_AMD) += amd_nonfatal.o +obj-$(CONFIG_AMD) += mce_amd.o obj-y += mcaction.o obj-y += barrier.o -obj-y += intel-nonfatal.o +obj-$(CONFIG_INTEL) += intel-nonfatal.o obj-y += mctelem.o obj-y += mce.o obj-y += mce-apei.o -obj-y += mce_intel.o +obj-$(CONFIG_INTEL) += mce_intel.o obj-y += non-fatal.o obj-y += util.o obj-y += vmce.o diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index fb9dec5b89..32c1b2756b 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -38,6 +38,10 @@ DEFINE_PER_CPU_READ_MOSTLY(unsigned int, nr_mce_banks); unsigned int __read_mostly firstbank; unsigned int __read_mostly ppin_msr; uint8_t __read_mostly cmci_apic_vector; +bool __read_mostly cmci_support; + +/* If mce_force_broadcast == 1, lmce_support will be disabled forcibly. */ +bool __read_mostly lmce_support; DEFINE_PER_CPU_READ_MOSTLY(struct mca_banks *, poll_bankmask); DEFINE_PER_CPU_READ_MOSTLY(struct mca_banks *, no_cmci_banks); diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c index af43281cc6..dd812f4b8a 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -26,16 +26,12 @@ #include "mcaction.h" static DEFINE_PER_CPU_READ_MOSTLY(struct mca_banks *, mce_banks_owned); -bool __read_mostly cmci_support; static bool __read_mostly ser_support; static bool __read_mostly mce_force_broadcast; boolean_param("mce_fb", mce_force_broadcast); static int __read_mostly nr_intel_ext_msrs; -/* If mce_force_broadcast == 1, lmce_support will be disabled forcibly. */ -bool __read_mostly lmce_support; - /* Intel SDM define bit15~bit0 of IA32_MCi_STATUS as the MC error code */ #define INTEL_MCCOD_MASK 0xFFFF diff --git a/xen/arch/x86/cpu/mcheck/non-fatal.c b/xen/arch/x86/cpu/mcheck/non-fatal.c index c5d8e3aea9..52e16ad499 100644 --- a/xen/arch/x86/cpu/mcheck/non-fatal.c +++ b/xen/arch/x86/cpu/mcheck/non-fatal.c @@ -24,15 +24,19 @@ static int __init cf_check init_nonfatal_mce_checker(void) * Check for non-fatal errors every MCE_RATE s */ switch (c->x86_vendor) { +#ifdef CONFIG_AMD case X86_VENDOR_AMD: case X86_VENDOR_HYGON: /* Assume we are on K8 or newer AMD or Hygon CPU here */ amd_nonfatal_mcheck_init(c); break; +#endif +#ifdef CONFIG_INTEL case X86_VENDOR_INTEL: intel_nonfatal_mcheck_init(c); break; +#endif default: return -ENODEV;