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Tsirkin" CC: , Huang Rui , Jiqian Chen Subject: [PATCH v10 1/2] virtio-pci: only reset pm state during resetting Date: Wed, 15 May 2024 15:35:25 +0800 Message-ID: <20240515073526.17297-2-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515073526.17297-1-Jiqian.Chen@amd.com> References: <20240515073526.17297-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD7:EE_|DM6PR12MB4203:EE_ X-MS-Office365-Filtering-Correlation-Id: 38bff349-2962-4780-97ac-08dc74b1a315 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|82310400017|36860700004|376005|1800799015; X-Microsoft-Antispam-Message-Info: MiF1KZYJCvg04CjEhkPcrc+1blT9WzRLvknOMDAUydrOxT+BIuLWLTWPbxWvrOsbOX03mMNUVhz+ltfugAe7Yc7x/hzFJOippc6gwYGPk/is+onybVxyrbv8KoStQJHUUnSzTdeWT+rUllnZaoEpxwazbKuW0gY9qxYnYFmRGBuO4aip2dvCQbA6Io8qp1JxIiMM6GcZOMOzQZ841ELYiqz5P3Jz22zxUwdr7ttXSsM74BbVYo9ISKbTI5r1+JUwpZSqqXD/xPk/ZJzidazzJPIN8GlFRT8M99gFrwZTHWKQhQ1Mcbut+rQQWfugVpLxOze6NzUG5ZHf5wUUoAyMXp+WR5tC05hH8GDAmGoJ3k+4R81B7ZuEj9UoQC/BxK4cd3VAx3qUc1RhttTl3jIrlm7itu1MxsQ711USQaNbNZG/wYldWzWfVh32r5rh45eMumfsiGWMWUts/YBogxVsY3iAFtswGQJzfadcmUfvfBYrjLKUz20zmTGZGRxunr9x1JkkF0BZ/iQH6sPqINAS0mkBtKlT5dQCgpIcMeFA5em0mVjcn5Cy/qJmRQ4IFmzvdqzTIo8g1LvHxgIPw8KjWMKlTkSfs29j6w+1ZFHkmUnrn4vA5PXdY0atia/RmSHuLm3zdj7WsOAbSdQdm7mnFBGysknAl1kSM/drua/H0G7scwbW4UuG6PBluMQjZlKK2tpSbs1j+TDA2/sdu/JC2jME6nlKYzoLF2AKGsh4CamC6HUsMqRVnhn0NA1VKatY06PATwk/QyWw1tWRewHXdLxG+plBOii3UdEyYx4X2A3NQPP1N8OpoS6nCKfzxSBzmhCf0/E6uTpDfq5Dzh/NA8Vj1zM2YJc1vQRRy8nSO3bZz4AixQc857KpsyISytY2fj1I7+74xMXWEUIOUKgy8HMj8fcJN5Av27ETatu8np9mpVIeZkRkH54B9w2MFUHsAeV/irIIxOdxc429e+bS7DwfEnrY4t/6Zgi8q6ROnzFTPAHBOS3wH83JJPc13gIrC/QSFxpyFFPkGPAPXuOC15PH2Rt3Kvcilr0+e1KukBEhkSRNR9/w4U9jWlgkLHGqgjK/FzqudGFVIJdiEdv0yuGP934ScugGgqJpapm6lZnnqcQAt8wKEYeHrTV2eal1hTelK3IyoDQolD+0gY1C4Mt9mEAuVMf0SllUdmtqPOjmNN9g+WjMN9AyJZaq9twfrmwXyZq6lJhlQmcCvDZ9JLV7CxlzdvrkmHdjlPe5gmoY0YWaVouJGayzOo+Ysj/YKD325AUeVXPz7Scu5HBrMI1wuThoUV4q2PhS9YZpvgFgnmddI40wK7KUIhSiyFg+shb5XJUZFM54enRYuxzzU1UQmTG9xDSri0fxHN/ly4A= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(82310400017)(36860700004)(376005)(1800799015); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 May 2024 07:35:47.2652 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 38bff349-2962-4780-97ac-08dc74b1a315 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4203 Received-SPF: permerror client-ip=40.107.94.46; envelope-from=Jiqian.Chen@amd.com; helo=NAM10-MW2-obe.outbound.protection.outlook.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.974, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Fix bug imported by 27ce0f3afc9dd ("fix Power Management Control Register for PCI Express virtio devices" After this change, observe that QEMU may erroneously clear the power status of the device, or may erroneously clear non writable registers, such as NO_SOFT_RESET, etc. Only state of PM_CTRL is writable. Only when flag VIRTIO_PCI_FLAG_INIT_PM is set, need to reset state. Fixes: 27ce0f3afc9dd ("fix Power Management Control Register for PCI Express virtio devices" Signed-off-by: Jiqian Chen --- hw/virtio/virtio-pci.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index b1d02f4b3de0..1b63bcb3f15c 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -2300,10 +2300,16 @@ static void virtio_pci_bus_reset_hold(Object *obj, ResetType type) virtio_pci_reset(qdev); if (pci_is_express(dev)) { + VirtIOPCIProxy *proxy = VIRTIO_PCI(dev); + pcie_cap_deverr_reset(dev); pcie_cap_lnkctl_reset(dev); - pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, 0); + if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) { + pci_word_test_and_clear_mask( + dev->config + dev->exp.pm_cap + PCI_PM_CTRL, + PCI_PM_CTRL_STATE_MASK); + } } } From patchwork Wed May 15 07:35:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chen, Jiqian" X-Patchwork-Id: 13664804 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C73EC25B75 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MN1PEPF0000ECD9.mail.protection.outlook.com (10.167.242.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7544.18 via Frontend Transport; Wed, 15 May 2024 07:35:47 +0000 Received: from cjq-desktop.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 15 May 2024 02:35:45 -0500 From: Jiqian Chen To: "Michael S . Tsirkin" CC: , Huang Rui , Jiqian Chen Subject: [PATCH v10 2/2] virtio-pci: implement No_Soft_Reset bit Date: Wed, 15 May 2024 15:35:26 +0800 Message-ID: <20240515073526.17297-3-Jiqian.Chen@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515073526.17297-1-Jiqian.Chen@amd.com> References: <20240515073526.17297-1-Jiqian.Chen@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD9:EE_|CH2PR12MB4150:EE_ X-MS-Office365-Filtering-Correlation-Id: 6209e5d6-d7ae-4b3e-06f0-08dc74b1a309 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|1800799015|376005|36860700004|82310400017; X-Microsoft-Antispam-Message-Info: M2MbbkII8snKUMXukIaLw3w1VVs0NZIn65+NZRK8kT2jdBRjw4EUB1wrJMmrYgVccNZeX0umQpRSodR/xLN4CdCmtx8hbVkLlPR1ZmnF2lXKT5BEYnQS+NObaKenvKVWvEeqae/cdHDEKDGXkjowYbmjpFjyZ/bmviseQQPZbz9a5ijeND1eHWaBtemVQ4ZBLbcjQLWH3TiDwlBaR6UiwH176IzuO2CXdzBkrweYZULA64653VCuqswVbXEpQv+mb0bWt4jv+3s20S2CyKaSJyC67noq2qUKcv/J/yEoTxOEJggLML1FOxzQIvUKYGysdSU5OorptDtJ3wrFqIKyGfq1H3fVqxgLG9SoP89F2i7N39AdqG6X+m7P0Qp2UMY6wLBNXUDCcObqGq+IiNrOMGOSUB98xlp6hz3lkT/IvDndc6Wz8NcgpIvkrSRRORdXk/5ZxfNr66OHHLS/jPTjPc1oYlLkI35nQt4kUdyL16psWoexxK9gFUVmmbrdAXgtPhJG2l5aZPfeeuRBks3M68mY6aO4sjQ7AcIBQurn8wmiV1K0o8pAfNqBo753bzSnYpA+y8e+Z/GWBgULAuhNCCR2BoFsVrc98sEhJfIBiOAiqJAE7+5m8zF43iIAuKD2Tm7LKV6Kk15MGMSWaRbjJ56iQ0ZbObonwrfqb36m7B6p8qCnoiksuPvUALB5Mnvb8R6Yc14t8SrYYmZrTXAjLjjqeKFSY4twwduZDUfxY7aI+pHiWGl2XHyQAfBYzE8dhPjCGCCQNEZnm3MkEHbTjw1qsrb7b+vV0dKrMLaROX+wBMHHNxTYunD5TMCyoJ/aByt4dDZEw/HB64GCgPfjd5aKvTbjgbi4GS9PjWTyNQZKEoQshLLeM3u5GLtD1p/MweslmhEp+3jtTLoC6a/xWjKEhBkITxnxe6TTllCQR4dg+PIoi0kCUNQ9T5dF/PGs+H3gIsEw/MFy+1yx8iZad1j/Oe4JBGk5I80kIqlfQSif+3mbpp8w7TmcOkPcIkguSGh/P7YOwb/y3JRJrCCAfeEenIuPeUaeZXVzuyJ5Y9M5JEY9yDWOmcDvfHcxWGkLMCeQkaRSJAyRPNFdcqPjA/7ScoBo0QLj+Kog+wMbPCDUi9ZLtnifJDq0/4nObuFM8zL+O3UIm0m8bWsMOySjzejbtqOssybhOf0qzIkGG9dhz7BOWaSkHyQrfDVimKq4kLRWIdoXiJWkl6rzaNEvlbANenrKQi1Be00emaYTAlNd8fHH19m2NFAkGCcIfLEkaY3x5AqDX2n3tDak6YabOP9ZlkQ2nyUlVLYk86khwFLu4/msXrYjjoM642s2YBVLWIx5SM5Dejy0R6e2FbDg0kQUpYfmTy53IQ+B6S8SDhjTrcCxSpalE5OQAgzkIA9j X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(1800799015)(376005)(36860700004)(82310400017); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 May 2024 07:35:47.2610 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6209e5d6-d7ae-4b3e-06f0-08dc74b1a309 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4150 Received-SPF: permerror client-ip=40.107.237.89; envelope-from=Jiqian.Chen@amd.com; helo=NAM12-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.974, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In current code, when guest does S3, virtio-gpu are reset due to the bit No_Soft_Reset is not set. After resetting, the display resources of virtio-gpu are destroyed, then the display can't come back and only show blank after resuming. Implement No_Soft_Reset bit of PCI_PM_CTRL register, then guest can check this bit, if this bit is set, the devices resetting will not be done, and then the display can work after resuming. No_Soft_Reset bit is implemented for all virtio devices, and was tested only on virtio-gpu device. Set it false by default for safety. Signed-off-by: Jiqian Chen --- hw/virtio/virtio-pci.c | 37 ++++++++++++++++++++++++++++++++++ include/hw/virtio/virtio-pci.h | 5 +++++ 2 files changed, 42 insertions(+) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 1b63bcb3f15c..3052528c0730 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -2230,6 +2230,11 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp) pcie_cap_lnkctl_init(pci_dev); } + if (proxy->flags & VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET) { + pci_set_word(pci_dev->config + pos + PCI_PM_CTRL, + PCI_PM_CTRL_NO_SOFT_RESET); + } + if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) { /* Init Power Management Control Register */ pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL, @@ -2292,11 +2297,37 @@ static void virtio_pci_reset(DeviceState *qdev) } } +static bool virtio_pci_no_soft_reset(PCIDevice *dev) +{ + uint16_t pmcsr; + + if (!pci_is_express(dev) || !dev->exp.pm_cap) { + return false; + } + + pmcsr = pci_get_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL); + + /* + * When No_Soft_Reset bit is set and the device + * is in D3hot state, don't reset device + */ + return (pmcsr & PCI_PM_CTRL_NO_SOFT_RESET) && + (pmcsr & PCI_PM_CTRL_STATE_MASK) == 3; +} + static void virtio_pci_bus_reset_hold(Object *obj, ResetType type) { PCIDevice *dev = PCI_DEVICE(obj); DeviceState *qdev = DEVICE(obj); + /* + * Note that: a proposal to add SUSPEND bit is being discussed, + * may need to consider the state of SUSPEND bit in future + */ + if (virtio_pci_no_soft_reset(dev)) { + return; + } + virtio_pci_reset(qdev); if (pci_is_express(dev)) { @@ -2336,6 +2367,12 @@ static Property virtio_pci_properties[] = { VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true), DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_INIT_PM_BIT, true), + /* + * For safety, set this false by default, if change it to true, + * need to consider compatible for old machine + */ + DEFINE_PROP_BIT("pcie-pm-no-soft-reset", VirtIOPCIProxy, flags, + VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT, false), DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_INIT_FLR_BIT, true), DEFINE_PROP_BIT("aer", VirtIOPCIProxy, flags, diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h index 59d88018c16a..9e67ba38c748 100644 --- a/include/hw/virtio/virtio-pci.h +++ b/include/hw/virtio/virtio-pci.h @@ -43,6 +43,7 @@ enum { VIRTIO_PCI_FLAG_INIT_FLR_BIT, VIRTIO_PCI_FLAG_AER_BIT, VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT, + VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT, }; /* Need to activate work-arounds for buggy guests at vmstate load. */ @@ -79,6 +80,10 @@ enum { /* Init Power Management */ #define VIRTIO_PCI_FLAG_INIT_PM (1 << VIRTIO_PCI_FLAG_INIT_PM_BIT) +/* Init The No_Soft_Reset bit of Power Management */ +#define VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET \ + (1 << VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT) + /* Init Function Level Reset capability */ #define VIRTIO_PCI_FLAG_INIT_FLR (1 << VIRTIO_PCI_FLAG_INIT_FLR_BIT)