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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0b9d1642sm111418795ad.31.2024.05.15.01.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 01:00:38 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Jim Shu , "Fea . Wang" , Frank Chang , LIU Zhiwei , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Andrew Jones , Max Chou Subject: [RESEND PATCH v2 1/5] target/riscv: Reuse the conversion function of priv_spec Date: Wed, 15 May 2024 16:05:58 +0800 Message-Id: <20240515080605.2675399-2-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515080605.2675399-1-fea.wang@sifive.com> References: <20240515080605.2675399-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=fea.wang@sifive.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Jim Shu Public the conversion function of priv_spec in cpu.h, so that tcg-cpu.c could also use it. Signed-off-by: Jim Shu Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 13 ++++--------- 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2946ac298a..6dd3d7f4a3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1786,7 +1786,7 @@ static int priv_spec_from_str(const char *priv_spec_str) return priv_version; } -static const char *priv_spec_to_str(int priv_version) +const char *priv_spec_to_str(int priv_version) { switch (priv_version) { case PRIV_VERSION_1_10_0: diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1501868008..140eb43fcb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -833,4 +833,5 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); /* Implemented in th_csr.c */ void th_register_custom_csrs(RISCVCPU *cpu); +const char *priv_spec_to_str(int priv_version); #endif /* RISCV_CPU_H */ diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f59b5d7f2d..fa186093fb 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -76,16 +76,11 @@ static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, static const char *cpu_priv_ver_to_str(int priv_ver) { - switch (priv_ver) { - case PRIV_VERSION_1_10_0: - return "v1.10.0"; - case PRIV_VERSION_1_11_0: - return "v1.11.0"; - case PRIV_VERSION_1_12_0: - return "v1.12.0"; - } + const char *priv_spec_str = priv_spec_to_str(priv_ver); - g_assert_not_reached(); + g_assert(priv_spec_str); + + return priv_spec_str; } static void riscv_cpu_synchronize_from_tb(CPUState *cs, From patchwork Wed May 15 08:05:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Fea.Wang" X-Patchwork-Id: 13664852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37330C25B7B for ; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0b9d1642sm111418795ad.31.2024.05.15.01.00.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 01:00:43 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: "Fea.Wang" , Frank Chang , Weiwei Li , LIU Zhiwei , Palmer Dabbelt , Alistair Francis , Bin Meng , Daniel Henrique Barboza , Andrew Jones , Max Chou Subject: [RESEND PATCH v2 2/5] target/riscv: Support the version for ss1p13 Date: Wed, 15 May 2024 16:05:59 +0800 Message-Id: <20240515080605.2675399-3-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515080605.2675399-1-fea.wang@sifive.com> References: <20240515080605.2675399-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=fea.wang@sifive.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 6 +++++- target/riscv/cpu.h | 4 +++- target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 4 ++++ 4 files changed, 13 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6dd3d7f4a3..ee2ec4c4e5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1775,7 +1775,9 @@ static int priv_spec_from_str(const char *priv_spec_str) { int priv_version = -1; - if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) { + if (!g_strcmp0(priv_spec_str, PRIV_VER_1_13_0_STR)) { + priv_version = PRIV_VERSION_1_13_0; + } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) { priv_version = PRIV_VERSION_1_12_0; } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_11_0_STR)) { priv_version = PRIV_VERSION_1_11_0; @@ -1795,6 +1797,8 @@ const char *priv_spec_to_str(int priv_version) return PRIV_VER_1_11_0_STR; case PRIV_VERSION_1_12_0: return PRIV_VER_1_12_0_STR; + case PRIV_VERSION_1_13_0: + return PRIV_VER_1_13_0_STR; default: return NULL; } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 140eb43fcb..f691c7d828 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -96,12 +96,14 @@ extern RISCVCPUProfile *riscv_profiles[]; #define PRIV_VER_1_10_0_STR "v1.10.0" #define PRIV_VER_1_11_0_STR "v1.11.0" #define PRIV_VER_1_12_0_STR "v1.12.0" +#define PRIV_VER_1_13_0_STR "v1.13.0" enum { PRIV_VERSION_1_10_0 = 0, PRIV_VERSION_1_11_0, PRIV_VERSION_1_12_0, + PRIV_VERSION_1_13_0, - PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0, + PRIV_VERSION_LATEST = PRIV_VERSION_1_13_0, }; #define VEXT_VERSION_1_00_0 0x00010000 diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index e1e4f32698..fb7eebde52 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -136,6 +136,7 @@ struct RISCVCPUConfig { * TCG always implement/can't be user disabled, * based on spec version. */ + bool has_priv_1_13; bool has_priv_1_12; bool has_priv_1_11; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index fa186093fb..f53422d605 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -318,6 +318,10 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu) cpu->cfg.has_priv_1_12 = true; } + if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) { + cpu->cfg.has_priv_1_13 = true; + } + /* zic64b is 1.12 or later */ cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && cpu->cfg.cbop_blocksize == 64 && From patchwork Wed May 15 08:06:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Fea.Wang" X-Patchwork-Id: 13664850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F9D4C25B7A for ; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0b9d1642sm111418795ad.31.2024.05.15.01.00.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 01:00:47 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: "Fea.Wang" , Frank Chang , Weiwei Li , Palmer Dabbelt , Alistair Francis , Bin Meng , Daniel Henrique Barboza , Liu Zhiwei Subject: [RESEND PATCH v2 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0 Date: Wed, 15 May 2024 16:06:00 +0800 Message-Id: <20240515080605.2675399-4-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515080605.2675399-1-fea.wang@sifive.com> References: <20240515080605.2675399-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=fea.wang@sifive.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in SMSTATEEN0 that controls access to the hedeleg. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 74318a925c..28bd3fb0b4 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -315,6 +315,7 @@ #define SMSTATEEN0_CS (1ULL << 0) #define SMSTATEEN0_FCSR (1ULL << 1) #define SMSTATEEN0_JVT (1ULL << 2) +#define SMSTATEEN0_P1P13 (1ULL << 56) #define SMSTATEEN0_HSCONTXT (1ULL << 57) #define SMSTATEEN0_IMSIC (1ULL << 58) #define SMSTATEEN0_AIA (1ULL << 59) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6b460ee0e8..bdbc8de0e2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2248,6 +2248,10 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno, wr_mask |= SMSTATEEN0_FCSR; } + if (env->priv_ver >= PRIV_VERSION_1_13_0) { + wr_mask |= SMSTATEEN0_P1P13; + } + return write_mstateen(env, csrno, wr_mask, new_val); } @@ -2283,6 +2287,10 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, { uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; + if (env->priv_ver >= PRIV_VERSION_1_13_0) { + wr_mask |= SMSTATEEN0_P1P13; + } + return write_mstateenh(env, csrno, wr_mask, new_val); } From patchwork Wed May 15 08:06:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Fea.Wang" X-Patchwork-Id: 13664845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 95A3FC25B77 for ; Wed, 15 May 2024 08:01:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1s79ZK-0003SO-47; Wed, 15 May 2024 04:00:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1s79ZI-0003GG-5v for qemu-devel@nongnu.org; Wed, 15 May 2024 04:00:56 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1s79ZF-0006YK-Vb for qemu-devel@nongnu.org; Wed, 15 May 2024 04:00:55 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1ee0132a6f3so50043205ad.0 for ; Wed, 15 May 2024 01:00:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1715760052; x=1716364852; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ldPciugSQGSMOBR5lY12EK6xTqHmCiheKzOXbbN7QuY=; b=R0yf//N8UrWVu38yePImrYbtPRFKk4kEDG82XTJ1ofL47cegF7mWctfCDvmjLKnQdC O0Oe+EKRftaerQChO/ZlSLb3NUdmF2ns6RS1pdy5HpnmnCEbrnlhwujOlRXQvzxKhoPR Le2PITcvo0VuvOQ3Oe4Cl567hNTLgq1RW03h3oJG7dsHS/ZzRJiwt+MPEo8pqwNiy/0q u5fMIBCVAH5wLEIl9si1dEb9U/cPjnz/ADkS9c23v8kOd27CLTKev45Mkf0+hVoDsYSV HpovPF2+Bl+7ev2eve2/H0uZ74So+p5fyd37HywSTJa+/gmTW8wCUKAcHOvvZlyKveg1 Mt5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715760052; x=1716364852; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ldPciugSQGSMOBR5lY12EK6xTqHmCiheKzOXbbN7QuY=; b=vtqbN6ewfyzw+S09dUQsbmWRzF4PPm286NgDGIGH2ahP+2Re2BQJPXrsyxuiFdlgVW HUDTvxeGDOCYle9RJAHPLdyKb/ws+N3D2t6wCEvA46n43G2U6G2zR3PS9d12/7OXTOnx F+yJCYw/5vw1kyNm3+ypvziIJ6CDD0HQpy8N6EmQp2k3qJTfppmxph3cvKxuNk/R6g0l 8wckW+MzcsY3rICls85qUpmfu1eaRoRg+vzp9HfW6FopEyRDdE82U0/MT1FCPNhWj6j9 AA5KYPFHp8JFdlBghGgxo5nLDyNlz8fPxyZapsXv7FjCv4ZVtuiMsAQ0Ru/MJMEyqoZQ 549A== X-Gm-Message-State: AOJu0YzGqjDNYIJ8t0oqxjtixB586CD0TvNgxxLdB9Gg/QYVwVfeNUsQ t0LJ1Tkr4x2I5dpXFXAHV+vBSBR1mHj4znzDY6b+UqWvv1mmGBbddRJSeeZATJzqDJ11IcnPRZY pBSkYItnoLSd9/p8Itg506ffEbjOvznVzix27yKlAQHHJ30P8bJJFzTAVKGW4+SV4l5mCZ8LhUn Z+8kgPyKMaj5M2quraN49i1/yvAxjMnbhruek= X-Google-Smtp-Source: AGHT+IEOETcKfrrU1uEm0beUNbuBaQbb8htmFHEguldiAwieAU/FQ7BtokJxkdENNtndQ7ZDKFs0Kw== X-Received: by 2002:a17:902:e943:b0:1ea:fb65:a0c9 with SMTP id d9443c01a7336-1ef43d170d2mr166415395ad.20.1715760052127; Wed, 15 May 2024 01:00:52 -0700 (PDT) Received: from hsinchu36-syssw02.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0b9d1642sm111418795ad.31.2024.05.15.01.00.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 01:00:51 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: "Fea.Wang" , Frank Chang , LIU Zhiwei , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza Subject: [RESEND PATCH v2 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 Date: Wed, 15 May 2024 16:06:01 +0800 Message-Id: <20240515080605.2675399-5-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515080605.2675399-1-fea.wang@sifive.com> References: <20240515080605.2675399-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=fea.wang@sifive.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH and HEDELEGH for exception codes 32-47 for reserving and exception codes 48-63 for custom use. Add the CSR number though the implementation is just reading zero and writing ignore. Besides, for accessing HEDELEGH, it should be controlled by mstateen0 'P1P13' bit. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 ++ target/riscv/csr.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 28bd3fb0b4..f888025c59 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -156,6 +156,8 @@ /* 32-bit only */ #define CSR_MSTATUSH 0x310 +#define CSR_MEDELEGH 0x312 +#define CSR_HEDELEGH 0x612 /* Machine Trap Handling */ #define CSR_MSCRATCH 0x340 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index bdbc8de0e2..c5ff40eed8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3225,6 +3225,33 @@ static RISCVException write_hedeleg(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static RISCVException read_hedelegh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + RISCVException ret; + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + + /* Reserved, now read zero */ + *val = 0; + return RISCV_EXCP_NONE; +} + +static RISCVException write_hedelegh(CPURISCVState *env, int csrno, + target_ulong val) +{ + RISCVException ret; + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + + /* Reserved, now write ignore */ + return RISCV_EXCP_NONE; +} + static RISCVException rmw_hvien64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) @@ -4672,6 +4699,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, + [CSR_MEDELEGH] = { "medelegh", any32, read_zero, write_ignore, + .min_priv_ver = PRIV_VERSION_1_13_0 }, + [CSR_HEDELEGH] = { "hedelegh", hmode32, read_hedelegh, write_hedelegh, + .min_priv_ver = PRIV_VERSION_1_13_0 }, /* Machine Trap Handling */ [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, From patchwork Wed May 15 08:06:02 2024 Content-Type: text/plain; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0b9d1642sm111418795ad.31.2024.05.15.01.00.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 May 2024 01:00:55 -0700 (PDT) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: "Fea.Wang" , Frank Chang , LIU Zhiwei , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza Subject: [RESEND PATCH v2 5/5] target/riscv: Reserve exception codes for sw-check and hw-err Date: Wed, 15 May 2024 16:06:02 +0800 Message-Id: <20240515080605.2675399-6-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240515080605.2675399-1-fea.wang@sifive.com> References: <20240515080605.2675399-1-fea.wang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=fea.wang@sifive.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Based on the priv-1.13.0, add the exception codes for Software-check and Hardware-error. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f888025c59..f037f727d9 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -673,6 +673,8 @@ typedef enum RISCVException { RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */ RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */ RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */ + RISCV_EXCP_SW_CHECK = 0x12, /* since: priv-1.13.0 */ + RISCV_EXCP_HW_ERR = 0x13, /* since: priv-1.13.0 */ RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14, RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15, RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,