From patchwork Wed May 15 18:47:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Rokosov X-Patchwork-Id: 13665491 Received: from mx1.sberdevices.ru (mx1.sberdevices.ru [37.18.73.165]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BABC33BBF6; Wed, 15 May 2024 18:51:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=37.18.73.165 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715799084; cv=none; b=QTineZaFxPMLWVWccwAJYASakjNlCuz3JuqOBH9xdcGgO2p1Z1gSzdQXHxyoxrXORFcfTQjLtlXcsjcKf9Mcf6jfh8OsKLq9J36R06VzOzAeTA06uVK2bldHYO4j40JajLE9k342XijGLv9pFW5dLEzsP5nl/GuIgrHXxhaRYcA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715799084; c=relaxed/simple; bh=1Xm0mqkdVgYKrfnpqTqMp2D6Bm4nYavxuLWU7KsUQfU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rCl26sHFt9ghEUhKivPosDvoOw5wIV6VwpTClT+Fxfov8ieWkEIjK7l1LVtXZ9qMZb2XFTRYEcT7SwsIPuEbkNWkuz2SChMsFKCC9sTViUgfLJLJntr01aLNSjT7fxueVz8RK0w+PPCp4ukFKclpoDYmEFBTvIVbft0k5wP9Ppk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=salutedevices.com; spf=pass smtp.mailfrom=salutedevices.com; dkim=pass (2048-bit key) header.d=salutedevices.com header.i=@salutedevices.com header.b=CHRrHs1l; arc=none smtp.client-ip=37.18.73.165 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=salutedevices.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=salutedevices.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=salutedevices.com header.i=@salutedevices.com header.b="CHRrHs1l" Received: from p-infra-ksmg-sc-msk01 (localhost [127.0.0.1]) by mx1.sberdevices.ru (Postfix) with ESMTP id 4383710002F; Wed, 15 May 2024 21:51:13 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.sberdevices.ru 4383710002F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=salutedevices.com; s=mail; t=1715799073; bh=R/Rk7IMA2QAbG9QFamVg+DaNOx10zL198u6wx8WO48M=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type:From; b=CHRrHs1l2+RBf7ujaiAfGVa7EQ248ugO5dmJzULBtWkYFxQBBVj4p8StmndROxBA2 OxAiQsNpsdKgiRYKR9KLLkZquYw5qQZ8VK8u44wENzqx1kFuHyWPFFLoLo5a/cRlrF daNuUbaeFVos15jH4AmiyP95ZdgHt49e7D936MWJ+VPiIoaODTKm3fQ8iJP8+B5u5v KtkWsmahks3WD+7HhfCJC1fczXUeqT5XwLI5Un+2aAJroTQ4vVN40/zOq2wzoO/Opu DJ9rEFB+JpyYpIO6ks8jTeyfCdOczPMrJy5kLVvFuCi6OxuevrbLZyNG/H4OM8VUyl 3ElrEekLKu19A== Received: from smtp.sberdevices.ru (p-i-exch-sc-m02.sberdevices.ru [172.16.192.103]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.sberdevices.ru (Postfix) with ESMTPS; Wed, 15 May 2024 21:51:13 +0300 (MSK) Received: from CAB-WSD-L081021.sberdevices.ru (100.64.160.123) by p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 15 May 2024 21:51:12 +0300 From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v3 1/7] clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLL Date: Wed, 15 May 2024 21:47:24 +0300 Message-ID: <20240515185103.20256-2-ddrokosov@salutedevices.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240515185103.20256-1-ddrokosov@salutedevices.com> References: <20240515185103.20256-1-ddrokosov@salutedevices.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) To p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 185260 [May 15 2024] X-KSMG-AntiSpam-Version: 6.1.0.4 X-KSMG-AntiSpam-Envelope-From: ddrokosov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 20 0.3.20 743589a8af6ec90b529f2124c2bbfc3ce1d2f20f, {Tracking_from_domain_doesnt_match_to}, 127.0.0.199:7.1.2;smtp.sberdevices.ru:7.1.1,5.0.1;100.64.160.123:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;salutedevices.com:7.1.1, FromAlignment: s, ApMailHostAddress: 100.64.160.123 X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/05/15 13:12:00 #25231738 X-KSMG-AntiVirus-Status: Clean, skipped When dealing with certain PLLs, it is necessary to avoid modifying them if they have already been initialized by lower levels. For instance, in the A1 SoC Family, the sys_pll is enabled as the parent for the cpuclk, and it cannot be disabled during the initialization sequence. Therefore, initialization phase must be skipped. Signed-off-by: Dmitry Rokosov --- drivers/clk/meson/clk-pll.c | 40 ++++++++++++++++++++++--------------- drivers/clk/meson/clk-pll.h | 1 + 2 files changed, 25 insertions(+), 16 deletions(-) diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 78d17b2415af..e1132a110aab 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -289,11 +289,35 @@ static int meson_clk_pll_wait_lock(struct clk_hw *hw) return -ETIMEDOUT; } +static int meson_clk_pll_is_enabled(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); + + if (MESON_PARM_APPLICABLE(&pll->rst) && + meson_parm_read(clk->map, &pll->rst)) + return 0; + + if (!meson_parm_read(clk->map, &pll->en) || + !meson_parm_read(clk->map, &pll->l)) + return 0; + + return 1; +} + static int meson_clk_pll_init(struct clk_hw *hw) { struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); + /* + * Keep the clock running, which was already initialized and enabled + * from the bootloader stage, to avoid any glitches. + */ + if ((pll->flags & CLK_MESON_PLL_NOINIT_ENABLED) && + meson_clk_pll_is_enabled(hw)) + return 0; + if (pll->init_count) { if (MESON_PARM_APPLICABLE(&pll->rst)) meson_parm_write(clk->map, &pll->rst, 1); @@ -308,22 +332,6 @@ static int meson_clk_pll_init(struct clk_hw *hw) return 0; } -static int meson_clk_pll_is_enabled(struct clk_hw *hw) -{ - struct clk_regmap *clk = to_clk_regmap(hw); - struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); - - if (MESON_PARM_APPLICABLE(&pll->rst) && - meson_parm_read(clk->map, &pll->rst)) - return 0; - - if (!meson_parm_read(clk->map, &pll->en) || - !meson_parm_read(clk->map, &pll->l)) - return 0; - - return 1; -} - static int meson_clk_pcie_pll_enable(struct clk_hw *hw) { int retries = 10; diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h index a2228c0fdce5..7b6b87274073 100644 --- a/drivers/clk/meson/clk-pll.h +++ b/drivers/clk/meson/clk-pll.h @@ -28,6 +28,7 @@ struct pll_mult_range { } #define CLK_MESON_PLL_ROUND_CLOSEST BIT(0) +#define CLK_MESON_PLL_NOINIT_ENABLED BIT(1) struct meson_clk_pll_data { struct parm en; From patchwork Wed May 15 18:47:25 2024 Content-Type: text/plain; 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Wed, 15 May 2024 21:51:13 +0300 From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v3 2/7] dt-bindings: clock: meson: a1: pll: introduce new syspll bindings Date: Wed, 15 May 2024 21:47:25 +0300 Message-ID: <20240515185103.20256-3-ddrokosov@salutedevices.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240515185103.20256-1-ddrokosov@salutedevices.com> References: <20240515185103.20256-1-ddrokosov@salutedevices.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) To p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 185260 [May 15 2024] X-KSMG-AntiSpam-Version: 6.1.0.4 X-KSMG-AntiSpam-Envelope-From: ddrokosov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 20 0.3.20 743589a8af6ec90b529f2124c2bbfc3ce1d2f20f, {Tracking_from_domain_doesnt_match_to}, 127.0.0.199:7.1.2;100.64.160.123:7.1.2;smtp.sberdevices.ru:5.0.1,7.1.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;salutedevices.com:7.1.1, FromAlignment: s, ApMailHostAddress: 100.64.160.123 X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/05/15 13:12:00 #25231738 X-KSMG-AntiVirus-Status: Clean, skipped The 'syspll' PLL is a general-purpose PLL designed specifically for the CPU clock. It is capable of producing output frequencies within the range of 768MHz to 1536MHz. The 'syspll_in' source clock is an optional parent connection from the peripherals clock controller. Signed-off-by: Dmitry Rokosov Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml | 9 +++++++-- include/dt-bindings/clock/amlogic,a1-pll-clkc.h | 1 + 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml index a59b188a8bf5..c99274d2a9bd 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml @@ -26,11 +26,15 @@ properties: items: - description: input fixpll_in - description: input hifipll_in + - description: input syspll_in + minItems: 2 # syspll_in is optional clock-names: items: - const: fixpll_in - const: hifipll_in + - const: syspll_in + minItems: 2 # syspll_in is optional required: - compatible @@ -53,7 +57,8 @@ examples: reg = <0 0x7c80 0 0x18c>; #clock-cells = <1>; clocks = <&clkc_periphs CLKID_FIXPLL_IN>, - <&clkc_periphs CLKID_HIFIPLL_IN>; - clock-names = "fixpll_in", "hifipll_in"; + <&clkc_periphs CLKID_HIFIPLL_IN>, + <&clkc_periphs CLKID_SYSPLL_IN>; + clock-names = "fixpll_in", "hifipll_in", "syspll_in"; }; }; diff --git a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h index 2b660c0f2c9f..0dfc5e78a2d5 100644 --- a/include/dt-bindings/clock/amlogic,a1-pll-clkc.h +++ b/include/dt-bindings/clock/amlogic,a1-pll-clkc.h @@ -21,5 +21,6 @@ #define CLKID_FCLK_DIV5 8 #define CLKID_FCLK_DIV7 9 #define CLKID_HIFI_PLL 10 +#define CLKID_SYS_PLL 11 #endif /* __A1_PLL_CLKC_H */ From patchwork Wed May 15 18:47:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Rokosov X-Patchwork-Id: 13665489 Received: from mx1.sberdevices.ru (mx1.sberdevices.ru [37.18.73.165]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BB60157A67; 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Wed, 15 May 2024 21:51:14 +0300 (MSK) Received: from CAB-WSD-L081021.sberdevices.ru (100.64.160.123) by p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 15 May 2024 21:51:14 +0300 From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v3 3/7] clk: meson: a1: pll: support 'syspll' general-purpose PLL for CPU clock Date: Wed, 15 May 2024 21:47:26 +0300 Message-ID: <20240515185103.20256-4-ddrokosov@salutedevices.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240515185103.20256-1-ddrokosov@salutedevices.com> References: <20240515185103.20256-1-ddrokosov@salutedevices.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) To p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 185260 [May 15 2024] X-KSMG-AntiSpam-Version: 6.1.0.4 X-KSMG-AntiSpam-Envelope-From: ddrokosov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 20 0.3.20 743589a8af6ec90b529f2124c2bbfc3ce1d2f20f, {Tracking_from_domain_doesnt_match_to}, 127.0.0.199:7.1.2;smtp.sberdevices.ru:7.1.1,5.0.1;100.64.160.123:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;salutedevices.com:7.1.1, FromAlignment: s, ApMailHostAddress: 100.64.160.123 X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/05/15 13:12:00 #25231738 X-KSMG-AntiVirus-Status: Clean, skipped The 'syspll' PLL, also known as the system PLL, is a general and essential PLL responsible for generating the CPU clock frequency. With its wide-ranging capabilities, it is designed to accommodate frequencies within the range of 768MHz to 1536MHz. Signed-off-by: Dmitry Rokosov --- drivers/clk/meson/a1-pll.c | 72 ++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/a1-pll.h | 6 ++++ 2 files changed, 78 insertions(+) diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c index 60b2e53e7e51..286e83199d17 100644 --- a/drivers/clk/meson/a1-pll.c +++ b/drivers/clk/meson/a1-pll.c @@ -138,6 +138,76 @@ static struct clk_regmap hifi_pll = { }, }; +static const struct pll_mult_range sys_pll_mult_range = { + .min = 32, + .max = 64, +}; + +static const struct reg_sequence sys_pll_init_regs[] = { + { .reg = ANACTRL_SYSPLL_CTRL1, .def = 0x01800000 }, + { .reg = ANACTRL_SYSPLL_CTRL2, .def = 0x00001100 }, + { .reg = ANACTRL_SYSPLL_CTRL3, .def = 0x10022300 }, + { .reg = ANACTRL_SYSPLL_CTRL4, .def = 0x00300000 }, + { .reg = ANACTRL_SYSPLL_CTRL0, .def = 0x01f18432 }, +}; + +static struct clk_regmap sys_pll = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = ANACTRL_SYSPLL_CTRL0, + .shift = 28, + .width = 1, + }, + .m = { + .reg_off = ANACTRL_SYSPLL_CTRL0, + .shift = 0, + .width = 8, + }, + .n = { + .reg_off = ANACTRL_SYSPLL_CTRL0, + .shift = 10, + .width = 5, + }, + .frac = { + .reg_off = ANACTRL_SYSPLL_CTRL1, + .shift = 0, + .width = 19, + }, + .l = { + .reg_off = ANACTRL_SYSPLL_STS, + .shift = 31, + .width = 1, + }, + .current_en = { + .reg_off = ANACTRL_SYSPLL_CTRL0, + .shift = 26, + .width = 1, + }, + .l_detect = { + .reg_off = ANACTRL_SYSPLL_CTRL2, + .shift = 6, + .width = 1, + }, + .range = &sys_pll_mult_range, + .init_regs = sys_pll_init_regs, + .init_count = ARRAY_SIZE(sys_pll_init_regs), + /* + * The sys_pll clock is usually enabled and initialized in the + * bootloader stage. Additionally, the cpu_clk is connected to + * sys_pll. As a result, it is not allowed to initialize the + * cpu_clk again, as doing so would prevent the CPU from + * executing any instructions. + */ + .flags = CLK_MESON_PLL_NOINIT_ENABLED, + }, + .hw.init = &(struct clk_init_data){ + .name = "sys_pll", + .ops = &meson_clk_pll_ops, + .parent_names = (const char *[]){ "syspll_in" }, + .num_parents = 1, + }, +}; + static struct clk_fixed_factor fclk_div2_div = { .mult = 1, .div = 2, @@ -283,6 +353,7 @@ static struct clk_hw *a1_pll_hw_clks[] = { [CLKID_FCLK_DIV5] = &fclk_div5.hw, [CLKID_FCLK_DIV7] = &fclk_div7.hw, [CLKID_HIFI_PLL] = &hifi_pll.hw, + [CLKID_SYS_PLL] = &sys_pll.hw, }; static struct clk_regmap *const a1_pll_regmaps[] = { @@ -293,6 +364,7 @@ static struct clk_regmap *const a1_pll_regmaps[] = { &fclk_div5, &fclk_div7, &hifi_pll, + &sys_pll, }; static struct regmap_config a1_pll_regmap_cfg = { diff --git a/drivers/clk/meson/a1-pll.h b/drivers/clk/meson/a1-pll.h index 4be17b2bf383..666d9b2137e9 100644 --- a/drivers/clk/meson/a1-pll.h +++ b/drivers/clk/meson/a1-pll.h @@ -18,6 +18,12 @@ #define ANACTRL_FIXPLL_CTRL0 0x0 #define ANACTRL_FIXPLL_CTRL1 0x4 #define ANACTRL_FIXPLL_STS 0x14 +#define ANACTRL_SYSPLL_CTRL0 0x80 +#define ANACTRL_SYSPLL_CTRL1 0x84 +#define ANACTRL_SYSPLL_CTRL2 0x88 +#define ANACTRL_SYSPLL_CTRL3 0x8c +#define ANACTRL_SYSPLL_CTRL4 0x90 +#define ANACTRL_SYSPLL_STS 0x94 #define ANACTRL_HIFIPLL_CTRL0 0xc0 #define ANACTRL_HIFIPLL_CTRL1 0xc4 #define ANACTRL_HIFIPLL_CTRL2 0xc8 From patchwork Wed May 15 18:47:27 2024 Content-Type: text/plain; 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Wed, 15 May 2024 21:51:14 +0300 From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v3 4/7] dt-bindings: clock: meson: a1: peripherals: support sys_pll input Date: Wed, 15 May 2024 21:47:27 +0300 Message-ID: <20240515185103.20256-5-ddrokosov@salutedevices.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240515185103.20256-1-ddrokosov@salutedevices.com> References: <20240515185103.20256-1-ddrokosov@salutedevices.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) To p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 185260 [May 15 2024] X-KSMG-AntiSpam-Version: 6.1.0.4 X-KSMG-AntiSpam-Envelope-From: ddrokosov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 20 0.3.20 743589a8af6ec90b529f2124c2bbfc3ce1d2f20f, {Tracking_from_domain_doesnt_match_to}, 127.0.0.199:7.1.2;100.64.160.123:7.1.2;smtp.sberdevices.ru:5.0.1,7.1.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;salutedevices.com:7.1.1, FromAlignment: s, ApMailHostAddress: 100.64.160.123 X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/05/15 13:12:00 #25231738 X-KSMG-AntiVirus-Status: Clean, skipped The 'sys_pll' input is an optional clock that can be used to generate 'sys_pll_div16', which serves as one of the sources for the GEN clock. Signed-off-by: Dmitry Rokosov Acked-by: Rob Herring (Arm) --- .../bindings/clock/amlogic,a1-peripherals-clkc.yaml | 9 +++++++-- include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h | 1 + 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml index 6d84cee1bd75..2568ad7dd0ac 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml @@ -30,6 +30,8 @@ properties: - description: input fixed pll div7 - description: input hifi pll - description: input oscillator (usually at 24MHz) + - description: input sys pll + minItems: 6 # sys_pll is optional clock-names: items: @@ -39,6 +41,8 @@ properties: - const: fclk_div7 - const: hifi_pll - const: xtal + - const: sys_pll + minItems: 6 # sys_pll is optional required: - compatible @@ -65,9 +69,10 @@ examples: <&clkc_pll CLKID_FCLK_DIV5>, <&clkc_pll CLKID_FCLK_DIV7>, <&clkc_pll CLKID_HIFI_PLL>, - <&xtal>; + <&xtal>, + <&clkc_pll CLKID_SYS_PLL>; clock-names = "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", - "hifi_pll", "xtal"; + "hifi_pll", "xtal", "sys_pll"; }; }; diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h index 06f198ee7623..2ce1a06dc735 100644 --- a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h +++ b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h @@ -164,5 +164,6 @@ #define CLKID_DMC_SEL 151 #define CLKID_DMC_DIV 152 #define CLKID_DMC_SEL2 153 +#define CLKID_SYS_PLL_DIV16 154 #endif /* __A1_PERIPHERALS_CLKC_H */ From patchwork Wed May 15 18:47:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Rokosov X-Patchwork-Id: 13665492 Received: from mx1.sberdevices.ru (mx1.sberdevices.ru [37.18.73.165]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A215C158DD1; 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Wed, 15 May 2024 21:51:15 +0300 (MSK) Received: from CAB-WSD-L081021.sberdevices.ru (100.64.160.123) by p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 15 May 2024 21:51:15 +0300 From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v3 5/7] clk: meson: a1: peripherals: support 'sys_pll_div16' clock as GEN input Date: Wed, 15 May 2024 21:47:28 +0300 Message-ID: <20240515185103.20256-6-ddrokosov@salutedevices.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240515185103.20256-1-ddrokosov@salutedevices.com> References: <20240515185103.20256-1-ddrokosov@salutedevices.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) To p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 185260 [May 15 2024] X-KSMG-AntiSpam-Version: 6.1.0.4 X-KSMG-AntiSpam-Envelope-From: ddrokosov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 20 0.3.20 743589a8af6ec90b529f2124c2bbfc3ce1d2f20f, {Tracking_from_domain_doesnt_match_to}, 127.0.0.199:7.1.2;smtp.sberdevices.ru:7.1.1,5.0.1;100.64.160.123:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;salutedevices.com:7.1.1, FromAlignment: s, ApMailHostAddress: 100.64.160.123 X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/05/15 13:12:00 #25231738 X-KSMG-AntiVirus-Status: Clean, skipped The clock 'sys_pll_div16' is one of the parents of the GEN clock. It is generated inside the A1 Peripherals clock controller from 'sys_pll' PLL clock source with a fixed factor. Signed-off-by: Dmitry Rokosov --- drivers/clk/meson/a1-peripherals.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peripherals.c index 621af1e6e4b2..56e44299982c 100644 --- a/drivers/clk/meson/a1-peripherals.c +++ b/drivers/clk/meson/a1-peripherals.c @@ -746,14 +746,27 @@ static struct clk_regmap fclk_div2_divn = { }, }; +static struct clk_fixed_factor sys_pll_div16 = { + .mult = 1, + .div = 16, + .hw.init = &(struct clk_init_data){ + .name = "sys_pll_div16", + .ops = &clk_fixed_factor_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "sys_pll", + }, + .num_parents = 1, + }, +}; + /* - * the index 2 is sys_pll_div16, it will be implemented in the CPU clock driver, * the index 4 is the clock measurement source, it's not supported yet */ -static u32 gen_table[] = { 0, 1, 3, 5, 6, 7, 8 }; +static u32 gen_table[] = { 0, 1, 2, 3, 5, 6, 7, 8 }; static const struct clk_parent_data gen_parent_data[] = { { .fw_name = "xtal", }, { .hw = &rtc.hw }, + { .hw = &sys_pll_div16.hw, }, { .fw_name = "hifi_pll", }, { .fw_name = "fclk_div2", }, { .fw_name = "fclk_div3", }, @@ -2024,6 +2037,7 @@ static struct clk_hw *a1_periphs_hw_clks[] = { [CLKID_DMC_SEL] = &dmc_sel.hw, [CLKID_DMC_DIV] = &dmc_div.hw, [CLKID_DMC_SEL2] = &dmc_sel2.hw, + [CLKID_SYS_PLL_DIV16] = &sys_pll_div16.hw, }; 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Wed, 15 May 2024 21:51:16 +0300 From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov , Rob Herring Subject: [PATCH v3 6/7] dt-bindings: clock: meson: add A1 CPU clock controller bindings Date: Wed, 15 May 2024 21:47:29 +0300 Message-ID: <20240515185103.20256-7-ddrokosov@salutedevices.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240515185103.20256-1-ddrokosov@salutedevices.com> References: <20240515185103.20256-1-ddrokosov@salutedevices.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) To p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 185260 [May 15 2024] X-KSMG-AntiSpam-Version: 6.1.0.4 X-KSMG-AntiSpam-Envelope-From: ddrokosov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 20 0.3.20 743589a8af6ec90b529f2124c2bbfc3ce1d2f20f, {Tracking_uf_ne_domains}, {Tracking_from_domain_doesnt_match_to}, 127.0.0.199:7.1.2;100.64.160.123:7.1.2;devicetree.org:7.1.1;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;smtp.sberdevices.ru:5.0.1,7.1.1;salutedevices.com:7.1.1, FromAlignment: s, ApMailHostAddress: 100.64.160.123 X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean, bases: 2024/05/15 12:35:00 X-KSMG-LinksScanning: Clean, bases: 2024/05/15 12:57:00 X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/05/15 13:12:00 #25231738 X-KSMG-AntiVirus-Status: Clean, skipped Add the documentation and dt bindings for Amlogic A1 CPU clock controller. This controller consists of the general 'cpu_clk' and two main parents: 'cpu fixed clock' and 'syspll'. The 'cpu fixed clock' is an internal fixed clock, while the 'syspll' serves as an external input from the A1 PLL clock controller. Signed-off-by: Dmitry Rokosov Reviewed-by: Rob Herring --- .../bindings/clock/amlogic,a1-cpu-clkc.yaml | 64 +++++++++++++++++++ .../dt-bindings/clock/amlogic,a1-cpu-clkc.h | 19 ++++++ 2 files changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-cpu-clkc.yaml create mode 100644 include/dt-bindings/clock/amlogic,a1-cpu-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-cpu-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-cpu-clkc.yaml new file mode 100644 index 000000000000..f4958b315ed4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-cpu-clkc.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a1-cpu-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A1 CPU Clock Control Unit + +maintainers: + - Neil Armstrong + - Jerome Brunet + - Dmitry Rokosov + +properties: + compatible: + const: amlogic,a1-cpu-clkc + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + + clocks: + items: + - description: input fixed pll div2 + - description: input fixed pll div3 + - description: input sys pll + - description: input oscillator (usually at 24MHz) + + clock-names: + items: + - const: fclk_div2 + - const: fclk_div3 + - const: sys_pll + - const: xtal + +required: + - compatible + - '#clock-cells' + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + apb { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@fd000000 { + compatible = "amlogic,a1-cpu-clkc"; + reg = <0 0xfd000080 0 0x8>; + #clock-cells = <1>; + clocks = <&clkc_pll CLKID_FCLK_DIV2>, + <&clkc_pll CLKID_FCLK_DIV3>, + <&clkc_pll CLKID_SYS_PLL>, + <&xtal>; + clock-names = "fclk_div2", "fclk_div3", "sys_pll", "xtal"; + }; + }; diff --git a/include/dt-bindings/clock/amlogic,a1-cpu-clkc.h b/include/dt-bindings/clock/amlogic,a1-cpu-clkc.h new file mode 100644 index 000000000000..1d321c6eddb7 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a1-cpu-clkc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2024, SaluteDevices. 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Wed, 15 May 2024 21:51:17 +0300 (MSK) Received: from CAB-WSD-L081021.sberdevices.ru (100.64.160.123) by p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 15 May 2024 21:51:16 +0300 From: Dmitry Rokosov To: , , , , , , , CC: , , , , , , , , Dmitry Rokosov Subject: [PATCH v3 7/7] clk: meson: a1: add Amlogic A1 CPU clock controller driver Date: Wed, 15 May 2024 21:47:30 +0300 Message-ID: <20240515185103.20256-8-ddrokosov@salutedevices.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240515185103.20256-1-ddrokosov@salutedevices.com> References: <20240515185103.20256-1-ddrokosov@salutedevices.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) To p-i-exch-sc-m02.sberdevices.ru (172.16.192.103) X-KSMG-Rule-ID: 10 X-KSMG-Message-Action: clean X-KSMG-AntiSpam-Lua-Profiles: 185260 [May 15 2024] X-KSMG-AntiSpam-Version: 6.1.0.4 X-KSMG-AntiSpam-Envelope-From: ddrokosov@salutedevices.com X-KSMG-AntiSpam-Rate: 0 X-KSMG-AntiSpam-Status: not_detected X-KSMG-AntiSpam-Method: none X-KSMG-AntiSpam-Auth: dkim=none X-KSMG-AntiSpam-Info: LuaCore: 20 0.3.20 743589a8af6ec90b529f2124c2bbfc3ce1d2f20f, {Tracking_from_domain_doesnt_match_to}, 127.0.0.199:7.1.2;smtp.sberdevices.ru:7.1.1,5.0.1;100.64.160.123:7.1.2;d41d8cd98f00b204e9800998ecf8427e.com:7.1.1;salutedevices.com:7.1.1, FromAlignment: s, ApMailHostAddress: 100.64.160.123 X-MS-Exchange-Organization-SCL: -1 X-KSMG-AntiSpam-Interceptor-Info: scan successful X-KSMG-AntiPhishing: Clean X-KSMG-LinksScanning: Clean X-KSMG-AntiVirus: Kaspersky Secure Mail Gateway, version 2.0.1.6960, bases: 2024/05/15 13:12:00 #25231738 X-KSMG-AntiVirus-Status: Clean, skipped The CPU clock controller plays a general role in the Amlogic A1 SoC family by generating CPU clocks. As an APB slave module, it offers the capability to inherit the CPU clock from two sources: the internal fixed clock known as 'cpu fixed clock' and the external input provided by the A1 PLL clock controller, referred to as 'syspll'. It is important for the driver to handle cpu_clk rate switching effectively by transitioning to the CPU fixed clock to avoid any potential execution freezes. Signed-off-by: Dmitry Rokosov --- drivers/clk/meson/Kconfig | 10 ++ drivers/clk/meson/Makefile | 1 + drivers/clk/meson/a1-cpu.c | 331 +++++++++++++++++++++++++++++++++++++ 3 files changed, 342 insertions(+) create mode 100644 drivers/clk/meson/a1-cpu.c diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 80c4a18c83d2..148d4495eee3 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -111,6 +111,16 @@ config COMMON_CLK_AXG_AUDIO Support for the audio clock controller on AmLogic A113D devices, aka axg, Say Y if you want audio subsystem to work. +config COMMON_CLK_A1_CPU + tristate "Amlogic A1 SoC CPU controller support" + depends on ARM64 + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS + help + Support for the CPU clock controller on Amlogic A113L based + device, A1 SoC Family. Say Y if you want A1 CPU clock controller + to work. + config COMMON_CLK_A1_PLL tristate "Amlogic A1 SoC PLL controller support" depends on ARM64 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 4968fc7ad555..2a06eb0303d6 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_COMMON_CLK_MESON_AUDIO_RSTC) += meson-audio-rstc.o obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o +obj-$(CONFIG_COMMON_CLK_A1_CPU) += a1-cpu.o obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o obj-$(CONFIG_COMMON_CLK_A1_AUDIO) += a1-audio.o diff --git a/drivers/clk/meson/a1-cpu.c b/drivers/clk/meson/a1-cpu.c new file mode 100644 index 000000000000..a9edabeafea9 --- /dev/null +++ b/drivers/clk/meson/a1-cpu.c @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Amlogic A1 SoC family CPU Clock Controller driver. + * + * Copyright (c) 2024, SaluteDevices. All Rights Reserved. + * Author: Dmitry Rokosov + */ + +#include +#include +#include +#include +#include "clk-regmap.h" +#include "meson-clkc-utils.h" + +#include + +/* CPU Clock Controller register offset */ +#define CPUCTRL_CLK_CTRL0 0x0 +#define CPUCTRL_CLK_CTRL1 0x4 + +static u32 cpu_fsource_sel_table[] = { 0, 1, 2 }; +static const struct clk_parent_data cpu_fsource_sel_parents[] = { + { .fw_name = "xtal" }, + { .fw_name = "fclk_div2" }, + { .fw_name = "fclk_div3" }, +}; + +static struct clk_regmap cpu_fsource_sel0 = { + .data = &(struct clk_regmap_mux_data) { + .offset = CPUCTRL_CLK_CTRL0, + .mask = 0x3, + .shift = 0, + .table = cpu_fsource_sel_table, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_fsource_sel0", + .ops = &clk_regmap_mux_ops, + .parent_data = cpu_fsource_sel_parents, + .num_parents = ARRAY_SIZE(cpu_fsource_sel_parents), + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cpu_fsource_div0 = { + .data = &(struct clk_regmap_div_data) { + .offset = CPUCTRL_CLK_CTRL0, + .shift = 4, + .width = 6, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_fsource_div0", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &cpu_fsource_sel0.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cpu_fsel0 = { + .data = &(struct clk_regmap_mux_data) { + .offset = CPUCTRL_CLK_CTRL0, + .mask = 0x1, + .shift = 2, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_fsel0", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &cpu_fsource_sel0.hw, + &cpu_fsource_div0.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cpu_fsource_sel1 = { + .data = &(struct clk_regmap_mux_data) { + .offset = CPUCTRL_CLK_CTRL0, + .mask = 0x3, + .shift = 16, + .table = cpu_fsource_sel_table, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_fsource_sel1", + .ops = &clk_regmap_mux_ops, + .parent_data = cpu_fsource_sel_parents, + .num_parents = ARRAY_SIZE(cpu_fsource_sel_parents), + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cpu_fsource_div1 = { + .data = &(struct clk_regmap_div_data) { + .offset = CPUCTRL_CLK_CTRL0, + .shift = 20, + .width = 6, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_fsource_div1", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &cpu_fsource_sel1.hw + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cpu_fsel1 = { + .data = &(struct clk_regmap_mux_data) { + .offset = CPUCTRL_CLK_CTRL0, + .mask = 0x1, + .shift = 18, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_fsel1", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &cpu_fsource_sel1.hw, + &cpu_fsource_div1.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cpu_fclk = { + .data = &(struct clk_regmap_mux_data) { + .offset = CPUCTRL_CLK_CTRL0, + .mask = 0x1, + .shift = 10, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_fclk", + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &cpu_fsel0.hw, + &cpu_fsel1.hw, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap cpu_clk = { + .data = &(struct clk_regmap_mux_data) { + .offset = CPUCTRL_CLK_CTRL0, + .mask = 0x1, + .shift = 11, + }, + .hw.init = &(struct clk_init_data) { + .name = "cpu_clk", + .ops = &clk_regmap_mux_ops, + .parent_data = (const struct clk_parent_data []) { + { .hw = &cpu_fclk.hw }, + { .fw_name = "sys_pll", }, + }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + }, +}; + +/* Array of all clocks registered by this provider */ +static struct clk_hw *a1_cpu_hw_clks[] = { + [CLKID_CPU_FSOURCE_SEL0] = &cpu_fsource_sel0.hw, + [CLKID_CPU_FSOURCE_DIV0] = &cpu_fsource_div0.hw, + [CLKID_CPU_FSEL0] = &cpu_fsel0.hw, + [CLKID_CPU_FSOURCE_SEL1] = &cpu_fsource_sel1.hw, + [CLKID_CPU_FSOURCE_DIV1] = &cpu_fsource_div1.hw, + [CLKID_CPU_FSEL1] = &cpu_fsel1.hw, + [CLKID_CPU_FCLK] = &cpu_fclk.hw, + [CLKID_CPU_CLK] = &cpu_clk.hw, +}; + +static struct clk_regmap *const a1_cpu_regmaps[] = { + &cpu_fsource_sel0, + &cpu_fsource_div0, + &cpu_fsel0, + &cpu_fsource_sel1, + &cpu_fsource_div1, + &cpu_fsel1, + &cpu_fclk, + &cpu_clk, +}; + +static struct regmap_config a1_cpu_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = CPUCTRL_CLK_CTRL1, +}; + +static struct meson_clk_hw_data a1_cpu_clks = { + .hws = a1_cpu_hw_clks, + .num = ARRAY_SIZE(a1_cpu_hw_clks), +}; + +struct a1_sys_pll_nb_data { + struct notifier_block nb; + struct clk_hw *cpu_clk; + struct clk_hw *cpu_fclk; + struct clk *sys_pll; +}; + +static int meson_a1_sys_pll_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct a1_sys_pll_nb_data *nbd; + int ret = 0; + + nbd = container_of(nb, struct a1_sys_pll_nb_data, nb); + + switch (event) { + case PRE_RATE_CHANGE: + /* + * Clock sys_pll will be changed to feed cpu_clk, + * configure cpu_clk to use cpu_fclk fixed clock. + */ + ret = clk_hw_set_parent(nbd->cpu_clk, nbd->cpu_fclk); + + /* Wait for clock propagation */ + if (!ret) + udelay(100); + + break; + + case POST_RATE_CHANGE: + /* + * Clock sys_pll rate has ben calculated, + * switch back cpu_clk to sys_pll + */ + ret = clk_set_parent(nbd->cpu_clk->clk, nbd->sys_pll); + + /* Wait for clock propagation */ + if (!ret) + udelay(100); + break; + + default: + pr_warn("Unknown event %lu for sys_pll notifier\n", event); + break; + } + + return notifier_from_errno(ret); +} + +static struct a1_sys_pll_nb_data a1_sys_pll_nb_data = { + .nb.notifier_call = meson_a1_sys_pll_notifier_cb, + .cpu_clk = &cpu_clk.hw, + .cpu_fclk = &cpu_fclk.hw, +}; + +static int meson_a1_dvfs_setup(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct clk *sys_pll; + int ret; + + /* Setup clock notifier for sys_pll clk */ + sys_pll = devm_clk_get(dev, "sys_pll"); + if (IS_ERR(sys_pll)) + return dev_err_probe(dev, PTR_ERR(sys_pll), + "can't get sys_pll as notifier clock\n"); + + a1_sys_pll_nb_data.sys_pll = sys_pll; + ret = devm_clk_notifier_register(dev, sys_pll, + &a1_sys_pll_nb_data.nb); + if (ret) + return dev_err_probe(dev, ret, + "can't register sys_pll notifier\n"); + + return ret; +} + +static int meson_a1_cpu_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + void __iomem *base; + struct regmap *map; + int clkid, i, err; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), + "can't ioremap resource\n"); + + map = devm_regmap_init_mmio(dev, base, &a1_cpu_regmap_cfg); + if (IS_ERR(map)) + return dev_err_probe(dev, PTR_ERR(map), + "can't init regmap mmio region\n"); + + /* Populate regmap for the regmap backed clocks */ + for (i = 0; i < ARRAY_SIZE(a1_cpu_regmaps); i++) + a1_cpu_regmaps[i]->map = map; + + for (clkid = 0; clkid < a1_cpu_clks.num; clkid++) { + err = devm_clk_hw_register(dev, a1_cpu_clks.hws[clkid]); + if (err) + return dev_err_probe(dev, err, + "clock[%d] registration failed\n", + clkid); + } + + err = devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &a1_cpu_clks); + if (err) + return dev_err_probe(dev, err, "can't add clk hw provider\n"); + + return meson_a1_dvfs_setup(pdev); +} + +static const struct of_device_id a1_cpu_clkc_match_table[] = { + { .compatible = "amlogic,a1-cpu-clkc", }, + {} +}; +MODULE_DEVICE_TABLE(of, a1_cpu_clkc_match_table); + +static struct platform_driver a1_cpu_clkc_driver = { + .probe = meson_a1_cpu_probe, + .driver = { + .name = "a1-cpu-clkc", + .of_match_table = a1_cpu_clkc_match_table, + }, +}; + +module_platform_driver(a1_cpu_clkc_driver); +MODULE_AUTHOR("Dmitry Rokosov "); +MODULE_LICENSE("GPL");