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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by BN2PEPF000044A7.mail.protection.outlook.com (10.167.243.101) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7587.21 via Frontend Transport; Thu, 16 May 2024 08:12:19 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 16 May 2024 03:12:16 -0500 Received: from xcbalucerop41x.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Thu, 16 May 2024 03:12:16 -0500 From: To: , , , , CC: Alejandro Lucero Subject: [RFC PATCH 01/13] cxl: move header files for absolute references Date: Thu, 16 May 2024 09:11:50 +0100 Message-ID: <20240516081202.27023-2-alucerop@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240516081202.27023-1-alucerop@amd.com> References: <20240516081202.27023-1-alucerop@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: alucerop@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A7:EE_|DM4PR12MB6256:EE_ X-MS-Office365-Filtering-Correlation-Id: 7bd61ccd-481b-4824-78e0-08dc757fe7ed X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|1800799015|376005|36860700004; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2024 08:12:19.1382 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7bd61ccd-481b-4824-78e0-08dc757fe7ed X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6256 From: Alejandro Lucero CXL Type 2 devices imply specific vendor drivers binding to those devices instead of generic ones offered by CXL core like the PCI driver. Those drivers need to use CXL core functions and structs for initialization, create memdevs and create CXL regions. This patch avoids referencing those files based on relative paths from inside the kernel sources tree. Signed-off-by: Alejandro Lucero --- drivers/cxl/acpi.c | 4 ++-- drivers/cxl/core/cdat.c | 6 +++--- drivers/cxl/core/hdm.c | 2 +- drivers/cxl/core/mbox.c | 6 +++--- drivers/cxl/core/memdev.c | 2 +- drivers/cxl/core/pci.c | 6 +++--- drivers/cxl/core/pmem.c | 4 ++-- drivers/cxl/core/pmu.c | 4 ++-- drivers/cxl/core/port.c | 6 +++--- drivers/cxl/core/region.c | 4 ++-- drivers/cxl/core/regs.c | 4 ++-- drivers/cxl/core/suspend.c | 2 +- drivers/cxl/core/trace.c | 2 +- drivers/cxl/core/trace.h | 4 ++-- drivers/cxl/mem.c | 4 ++-- drivers/cxl/pci.c | 6 +++--- drivers/cxl/pmem.c | 4 ++-- drivers/cxl/port.c | 4 ++-- drivers/cxl/security.c | 4 ++-- drivers/dax/cxl.c | 2 +- drivers/perf/cxl_pmu.c | 4 ++-- {drivers/cxl => include/linux}/cxl.h | 0 {drivers/cxl => include/linux}/cxlmem.h | 2 +- {drivers/cxl => include/linux}/cxlpci.h | 0 tools/testing/cxl/cxl_core_exports.c | 2 +- tools/testing/cxl/mock_acpi.c | 2 +- tools/testing/cxl/test/cxl.c | 2 +- tools/testing/cxl/test/mem.c | 2 +- tools/testing/cxl/test/mock.c | 4 ++-- tools/testing/cxl/test/mock.h | 2 +- 30 files changed, 50 insertions(+), 50 deletions(-) rename {drivers/cxl => include/linux}/cxl.h (100%) rename {drivers/cxl => include/linux}/cxlmem.h (99%) rename {drivers/cxl => include/linux}/cxlpci.h (100%) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index cb8c155a2c9b..f023898382bc 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -8,8 +8,8 @@ #include #include #include -#include "cxlpci.h" -#include "cxl.h" +#include +#include #define CXL_RCRB_SIZE SZ_8K diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index bb83867d9fec..97ff1dfd63d6 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -5,10 +5,10 @@ #include #include #include -#include "cxlpci.h" -#include "cxlmem.h" +#include +#include #include "core.h" -#include "cxl.h" +#include #include "core.h" struct dsmas_entry { diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 7d97790b893d..47d9faf5897f 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -4,7 +4,7 @@ #include #include -#include "cxlmem.h" +#include #include "core.h" /** diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c index f0f54aeccc87..d312b82f7f36 100644 --- a/drivers/cxl/core/mbox.c +++ b/drivers/cxl/core/mbox.c @@ -5,9 +5,9 @@ #include #include #include -#include -#include -#include +#include +#include +#include #include "core.h" #include "trace.h" diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c index d4e259f3a7e9..07cd0b8b026f 100644 --- a/drivers/cxl/core/memdev.c +++ b/drivers/cxl/core/memdev.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include "trace.h" #include "core.h" diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 0df09bd79408..a494a03b4a83 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -7,9 +7,9 @@ #include #include #include -#include -#include -#include +#include +#include +#include #include "core.h" #include "trace.h" diff --git a/drivers/cxl/core/pmem.c b/drivers/cxl/core/pmem.c index e69625a8d6a1..d1a5f8d9cf91 100644 --- a/drivers/cxl/core/pmem.c +++ b/drivers/cxl/core/pmem.c @@ -3,8 +3,8 @@ #include #include #include -#include -#include +#include +#include #include "core.h" /** diff --git a/drivers/cxl/core/pmu.c b/drivers/cxl/core/pmu.c index 5d8e06b0ba6e..aa02ea582184 100644 --- a/drivers/cxl/core/pmu.c +++ b/drivers/cxl/core/pmu.c @@ -4,9 +4,9 @@ #include #include #include -#include +#include #include -#include +#include #include "core.h" static void cxl_pmu_release(struct device *dev) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 762783bb091a..fdd76306260d 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -11,9 +11,9 @@ #include #include #include -#include -#include -#include +#include +#include +#include #include "core.h" /** diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 5c186e0a39b9..70e86a7c241d 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -9,8 +9,8 @@ #include #include #include -#include -#include +#include +#include #include "core.h" /** diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 3c42f984eeaf..fd165e718cf2 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -4,8 +4,8 @@ #include #include #include -#include -#include +#include +#include #include #include "core.h" diff --git a/drivers/cxl/core/suspend.c b/drivers/cxl/core/suspend.c index a5984d96ea1d..117b3398ee56 100644 --- a/drivers/cxl/core/suspend.c +++ b/drivers/cxl/core/suspend.c @@ -2,7 +2,7 @@ /* Copyright(c) 2022 Intel Corporation. All rights reserved. */ #include #include -#include "cxlmem.h" +#include static atomic_t mem_active; diff --git a/drivers/cxl/core/trace.c b/drivers/cxl/core/trace.c index d0403dc3c8ab..1e6ba0de237a 100644 --- a/drivers/cxl/core/trace.c +++ b/drivers/cxl/core/trace.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright(c) 2022 Intel Corporation. All rights reserved. */ -#include +#include #include "core.h" #define CREATE_TRACE_POINTS diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index e5f13260fc52..e3b1156a01ad 100644 --- a/drivers/cxl/core/trace.h +++ b/drivers/cxl/core/trace.h @@ -10,8 +10,8 @@ #include #include -#include -#include +#include +#include #include "core.h" #define CXL_RAS_UC_CACHE_DATA_PARITY BIT(0) diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 0c79d9ce877c..6dc2bf1e2b1a 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -5,8 +5,8 @@ #include #include -#include "cxlmem.h" -#include "cxlpci.h" +#include +#include /** * DOC: cxl mem diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 2ff361e756d6..ccde33ac9c1c 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -11,9 +11,9 @@ #include #include #include -#include "cxlmem.h" -#include "cxlpci.h" -#include "cxl.h" +#include +#include +#include #include "pmu.h" /** diff --git a/drivers/cxl/pmem.c b/drivers/cxl/pmem.c index 7cb8994f8809..deadc5ffc2c2 100644 --- a/drivers/cxl/pmem.c +++ b/drivers/cxl/pmem.c @@ -8,8 +8,8 @@ #include #include #include -#include "cxlmem.h" -#include "cxl.h" +#include +#include extern const struct nvdimm_security_ops *cxl_security_ops; diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 97c21566677a..928ebff774ce 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -4,8 +4,8 @@ #include #include -#include "cxlmem.h" -#include "cxlpci.h" +#include +#include /** * DOC: cxl port diff --git a/drivers/cxl/security.c b/drivers/cxl/security.c index 21856a3f408e..129b36928a05 100644 --- a/drivers/cxl/security.c +++ b/drivers/cxl/security.c @@ -6,8 +6,8 @@ #include #include #include -#include "cxlmem.h" -#include "cxl.h" +#include +#include static unsigned long cxl_pmem_get_security_flags(struct nvdimm *nvdimm, enum nvdimm_passphrase_type ptype) diff --git a/drivers/dax/cxl.c b/drivers/dax/cxl.c index c696837ab23c..89a5c8eb666e 100644 --- a/drivers/dax/cxl.c +++ b/drivers/dax/cxl.c @@ -3,7 +3,7 @@ #include #include -#include "../cxl/cxl.h" +#include #include "bus.h" static int cxl_dax_region_probe(struct device *dev) diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c index 308c9969642e..9b93ba215bdb 100644 --- a/drivers/perf/cxl_pmu.c +++ b/drivers/perf/cxl_pmu.c @@ -20,8 +20,8 @@ #include #include -#include "../cxl/cxlpci.h" -#include "../cxl/cxl.h" +#include +#include #include "../cxl/pmu.h" #define CXL_PMU_CAP_REG 0x0 diff --git a/drivers/cxl/cxl.h b/include/linux/cxl.h similarity index 100% rename from drivers/cxl/cxl.h rename to include/linux/cxl.h diff --git a/drivers/cxl/cxlmem.h b/include/linux/cxlmem.h similarity index 99% rename from drivers/cxl/cxlmem.h rename to include/linux/cxlmem.h index 36cee9c30ceb..0d26a45a4af2 100644 --- a/drivers/cxl/cxlmem.h +++ b/include/linux/cxlmem.h @@ -8,7 +8,7 @@ #include #include #include -#include "cxl.h" +#include /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */ #define CXLMDEV_STATUS_OFFSET 0x0 diff --git a/drivers/cxl/cxlpci.h b/include/linux/cxlpci.h similarity index 100% rename from drivers/cxl/cxlpci.h rename to include/linux/cxlpci.h diff --git a/tools/testing/cxl/cxl_core_exports.c b/tools/testing/cxl/cxl_core_exports.c index 077e6883921d..737b49ed3e46 100644 --- a/tools/testing/cxl/cxl_core_exports.c +++ b/tools/testing/cxl/cxl_core_exports.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright(c) 2022 Intel Corporation. All rights reserved. */ -#include "cxl.h" +#include /* Exporting of cxl_core symbols that are only used by cxl_test */ EXPORT_SYMBOL_NS_GPL(cxl_num_decoders_committed, CXL); diff --git a/tools/testing/cxl/mock_acpi.c b/tools/testing/cxl/mock_acpi.c index 55813de26d46..4e440a9c0cb2 100644 --- a/tools/testing/cxl/mock_acpi.c +++ b/tools/testing/cxl/mock_acpi.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include "test/mock.h" struct acpi_device *to_cxl_host_bridge(struct device *host, struct device *dev) diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index 61c69297e797..848c42c2c158 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include "../watermark.h" #include "mock.h" diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c index 35ee41e435ab..dcddb6affc0d 100644 --- a/tools/testing/cxl/test/mem.c +++ b/tools/testing/cxl/test/mem.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include "trace.h" diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c index 6f737941dc0e..a1366a24677f 100644 --- a/tools/testing/cxl/test/mock.c +++ b/tools/testing/cxl/test/mock.c @@ -7,8 +7,8 @@ #include #include #include -#include -#include +#include +#include #include "mock.h" static LIST_HEAD(mock); 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Thu, 16 May 2024 03:12:17 -0500 From: To: , , , , CC: Alejandro Lucero Subject: [RFC PATCH 02/13] cxl: add type2 device basic support Date: Thu, 16 May 2024 09:11:51 +0100 Message-ID: <20240516081202.27023-3-alucerop@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240516081202.27023-1-alucerop@amd.com> References: <20240516081202.27023-1-alucerop@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: alucerop@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A9:EE_|DM6PR12MB4170:EE_ X-MS-Office365-Filtering-Correlation-Id: b14c2c3d-d01f-49cc-f11a-08dc757fe815 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|36860700004|1800799015|82310400017; X-Microsoft-Antispam-Message-Info: B+k1AXiind9KpMpV0ucn4rzc8Yet3XTMSBmqcPenCXnWvBbyhVdP90exJqSKrEYWUYGpHOI+sJP8rjo2wXQh4kwuRdiwdQ8Pga0Lmhje7VEUd16FqWU0mSKScODOLWmC4U2n+d2Fp8P0W9kgHVHncZG2CTExDRjnXYiToeovEcGqNS/fTCRMUPrJwtgbXVsFVHK9r/ksczR7Lc66vgCnDs0Cms00pJcGy5VsbQbuiamRqQtldaZjeW5xHENwMsFEM/8HtKvAcxui4M1mRN7M5vJJZEEzmtJK0uavgFIntKjwOX+QFTAcyD5EkMDaKMgRua3M/vgL5FjJZ8LAS9hwlwnd1bVHWvAwlBHSQaIGsbfbQqMEhEuMP7LZVNCQbjXPWYUC2Pt1JrKqeqzebSCi/YI1xjig8ghBcyuFCDuhlBnGs3KYhx+ps2ezdgwZiYRlYsE0ODKRLvMz6f9dovSovb+WHfhtJEhMM3oiv6+vb2EIb8k/4/bjq4HBpe3DijkJwuP5XITfOFDOBs36TKHeKACXlL2czaVgX4dQ0VbmIYiq2pwJDWg3G0OIzPvrzZRn7w/T0DE5G0S6+sasRERP5xZQ7xPeq79L4yu3f7wlah6H++I12MpocNjKhMlVyhh6tnXbNxZ944FcZESYrPvkC2g19PBVHvoXNQSeQz9AMqeaQx9v5ciItpI5ogYF5EkRbE7/vQ/vIe2NBmYt9FLW3eyKMQz+a2vKkZuQxhJaV3m30InMW5YW99DZ0W7EPjF0pAXq/DYxHk/xi/f6JvT+xomZEuxJa44JB0PccjmTlI5dBhWmEd8emMVvZFujquPV5AZDDlcrfyikx2/2FX8BMF7icsvC+M/haoKnmeXEVQIICy3BmiJKQNoz244G9ojrHegge6srZEsNz1T5jYQlqZ05aTNPJESEX9gpuhSomjUA8RMwbQ5dKqgbaXkzjQuxZflwKsWeubHH3bWy+rvFwX3Y+XFZ7NaRQDrrL3h5LjX+1kqLVwLnxY6sqgNdw/T3kbs8UDORhxgjkuW4VE2c1vGxK9sPHrfCNCy5E8K37YSPQZjiGzlP6lEu3o2LphFDxQtuIZ9dpwvIf2qrRwt1dFViX6NIFzv75fB+hu1z6Mx7D76R/6tg2y2HyTjrvApHLjSgwvZumT3aaTvJAy/Euq1KzZEQ1dgO5VHqujiM8243MRS9rsb413msZc9uXT2Bj/uQ6QUXIgshQjBocl0QPORDz0R6mTZa8OTGpK5q7CdQu8cVGHUoKVZktz72SJHZQc4NYoDdmkq/FNv+w84jfjO70LF21hfQ+Rf6LV1YD7xN33ZiAa/ACU8KpBRFmRCIMBb2LutqmilmyBzcCP+Dr6bQT3B0XoNSLcN2qNxTnx6wOub7K4l5LWLquyi6XHiu X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(376005)(36860700004)(1800799015)(82310400017);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2024 08:12:19.4191 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b14c2c3d-d01f-49cc-f11a-08dc757fe815 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4170 From: Alejandro Lucero Differientiating Type3, aka memory expanders, from Type2, aka device accelerators, with a new function for initializing cxl_dev_state. Adding a type2 driver for a CXL emulated device inside CXL kernel testing infrastructure as a client for the functionality added. Signed-off-by: Alejandro Lucero Signed-off-by: Dan Williams Signed-off-by: Alejandro Lucero --- drivers/cxl/core/memdev.c | 15 ++++++ include/linux/cxlmem.h | 2 + tools/testing/cxl/Kbuild | 1 + tools/testing/cxl/type2/Kbuild | 7 +++ tools/testing/cxl/type2/pci_type2.c | 80 +++++++++++++++++++++++++++++ 5 files changed, 105 insertions(+) create mode 100644 tools/testing/cxl/type2/Kbuild create mode 100644 tools/testing/cxl/type2/pci_type2.c diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c index 07cd0b8b026f..0336b3f14f4a 100644 --- a/drivers/cxl/core/memdev.c +++ b/drivers/cxl/core/memdev.c @@ -659,6 +659,21 @@ static void detach_memdev(struct work_struct *work) static struct lock_class_key cxl_memdev_key; +struct cxl_dev_state *cxl_accel_state_create(struct device *dev) +{ + struct cxl_dev_state *cxlds; + + cxlds = devm_kzalloc(dev, sizeof(*cxlds), GFP_KERNEL); + if (!cxlds) + return ERR_PTR(-ENOMEM); + + cxlds->dev = dev; + cxlds->type = CXL_DEVTYPE_DEVMEM; + + return cxlds; +} +EXPORT_SYMBOL_NS_GPL(cxl_accel_state_create, CXL); + static struct cxl_memdev *cxl_memdev_alloc(struct cxl_dev_state *cxlds, const struct file_operations *fops) { diff --git a/include/linux/cxlmem.h b/include/linux/cxlmem.h index 0d26a45a4af2..e8d12b543db1 100644 --- a/include/linux/cxlmem.h +++ b/include/linux/cxlmem.h @@ -859,4 +859,6 @@ struct cxl_hdm { struct seq_file; struct dentry *cxl_debugfs_create_dir(const char *dir); void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); + +struct cxl_dev_state *cxl_accel_state_create(struct device *dev); #endif /* __CXL_MEM_H__ */ diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 030b388800f0..a285719c4db6 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -69,3 +69,4 @@ cxl_core-y += cxl_core_exports.o KBUILD_CFLAGS := $(filter-out -Wmissing-prototypes -Wmissing-declarations, $(KBUILD_CFLAGS)) obj-m += test/ +obj-m += type2/ diff --git a/tools/testing/cxl/type2/Kbuild b/tools/testing/cxl/type2/Kbuild new file mode 100644 index 000000000000..a96ad4d64924 --- /dev/null +++ b/tools/testing/cxl/type2/Kbuild @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-m += pci_type2.o + +cxl_pci_type2-y := cxl_pci_type2.o + +KBUILD_CFLAGS := $(filter-out -Wmissing-prototypes -Wmissing-declarations, $(KBUILD_CFLAGS)) diff --git a/tools/testing/cxl/type2/pci_type2.c b/tools/testing/cxl/type2/pci_type2.c new file mode 100644 index 000000000000..863ce7dc28ef --- /dev/null +++ b/tools/testing/cxl/type2/pci_type2.c @@ -0,0 +1,80 @@ +#include +#include +#include +#include +#include + +struct cxl_dev_state *cxlds; + +#define CXL_TYPE2_MEM_SIZE (1024*1024*256) + +static int type2_pci_probe(struct pci_dev *pci_dev, + const struct pci_device_id *entry) + +{ + u16 dvsec; + + dvsec = pci_find_dvsec_capability(pci_dev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); + + if (!dvsec) { + pci_info(pci_dev, "No CXL capability (vendor: %x\n", pci_dev->vendor); + return 0; + } else { + pci_info(pci_dev, "CXL CXL_DVSEC_PCIE_DEVICE capability found"); + } + + cxlds = cxl_accel_state_create(&pci_dev->dev); + if (IS_ERR(cxlds)) + return PTR_ERR(cxlds); + + pci_info(pci_dev, "Initializing cxlds..."); + cxlds->cxl_dvsec = dvsec; + cxlds->serial = pci_dev->dev.id; + + /* Should not this be based on DVSEC range size registers */ + cxlds->dpa_res = DEFINE_RES_MEM(0, CXL_TYPE2_MEM_SIZE); + cxlds->ram_res = DEFINE_RES_MEM_NAMED(0, CXL_TYPE2_MEM_SIZE, "ram"); + + return 0; +} + +static void type2_pci_remove(struct pci_dev *pci_dev) +{ + +} + +/* PCI device ID table */ +static const struct pci_device_id type2_pci_table[] = { + {PCI_DEVICE(PCI_VENDOR_ID_AMD, 0xbabe)}, + {0} /* end of list */ +}; + +static struct pci_driver type2_pci_driver = { + .name = KBUILD_MODNAME, + .id_table = type2_pci_table, + .probe = type2_pci_probe, + .remove = type2_pci_remove, +}; + +static int __init type2_cxl_init(void) +{ + int rc; + + rc = pci_register_driver(&type2_pci_driver); + + return rc; +} + +static void __exit type2_cxl_exit(void) +{ + pci_unregister_driver(&type2_pci_driver); +} + +module_init(type2_cxl_init); +module_exit(type2_cxl_exit); + +MODULE_AUTHOR("Alejadro Lucero "); +MODULE_DESCRIPTION("CXL Type2 device support, driver test"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(CXL); +MODULE_DEVICE_TABLE(pci, type2_pci_table); From patchwork Thu May 16 08:11:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Lucero Palau X-Patchwork-Id: 13665830 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2047.outbound.protection.outlook.com [40.107.244.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC55D4501A for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2024 08:12:19.7632 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6bf35c2a-2ab9-46dd-120a-08dc757fe848 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5675 From: Alejandro Lucero CXL initialization by type2 devices requires to use current CXL kernel infrastructure only available to such core code. Type2 devices are by definition owned by specific vendor drivers which need to use part of that infrastructure for initialization. Signed-off-by: Alejandro Lucero --- drivers/cxl/pci.c | 3 ++- include/linux/cxlpci.h | 2 ++ tools/testing/cxl/type2/pci_type2.c | 31 +++++++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index ccde33ac9c1c..497276302017 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -500,7 +500,7 @@ static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, return 0; } -static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map) { int rc; @@ -520,6 +520,7 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, return cxl_setup_regs(map); } +EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, CXL); static int cxl_pci_ras_unmask(struct pci_dev *pdev) { diff --git a/include/linux/cxlpci.h b/include/linux/cxlpci.h index 93992a1c8eec..28fa4861a4f9 100644 --- a/include/linux/cxlpci.h +++ b/include/linux/cxlpci.h @@ -130,4 +130,6 @@ void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, + struct cxl_register_map *map); #endif /* __CXL_PCI_H__ */ diff --git a/tools/testing/cxl/type2/pci_type2.c b/tools/testing/cxl/type2/pci_type2.c index 863ce7dc28ef..b12f13e676fb 100644 --- a/tools/testing/cxl/type2/pci_type2.c +++ b/tools/testing/cxl/type2/pci_type2.c @@ -12,7 +12,9 @@ static int type2_pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *entry) { + struct cxl_register_map map; u16 dvsec; + int rc; dvsec = pci_find_dvsec_capability(pci_dev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); @@ -35,6 +37,35 @@ static int type2_pci_probe(struct pci_dev *pci_dev, cxlds->dpa_res = DEFINE_RES_MEM(0, CXL_TYPE2_MEM_SIZE); cxlds->ram_res = DEFINE_RES_MEM_NAMED(0, CXL_TYPE2_MEM_SIZE, "ram"); + rc = cxl_pci_setup_regs(pci_dev, CXL_REGLOC_RBI_MEMDEV, &map); + if (rc) + return rc; + + rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); + if (rc) + return rc; + + rc = cxl_pci_setup_regs(pci_dev, CXL_REGLOC_RBI_COMPONENT, + &cxlds->reg_map); + if (rc) + dev_warn(&pci_dev->dev, "No component registers (%d)\n", rc); + + rc = cxl_map_component_regs(&cxlds->reg_map, &cxlds->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS)); + if (rc) + dev_dbg(&pci_dev->dev, "Failed to map RAS capability.\n"); + + pci_info(pci_dev, "requesting resource..."); + rc = request_resource(&cxlds->dpa_res, &cxlds->ram_res); + if (rc) + return rc; + + rc = cxl_await_media_ready(cxlds); + if (rc == 0) + cxlds->media_ready = true; + else + dev_warn(&pci_dev->dev, "Media not active (%d)\n", rc); + return 0; } From patchwork Thu May 16 08:11:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Lucero Palau X-Patchwork-Id: 13665835 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2046.outbound.protection.outlook.com [40.107.220.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F4467E58D for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2024 08:12:24.7941 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c0ee4924-b57f-45f7-ba31-08dc757feb47 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7287 From: Alejandro Lucero A device not implementing the CXL memory-device class code, aka Type2 devices, has mailbox capability as optional. If the device registers mapping does not show such capability, do not treat that as an error. Signed-off-by: Alejandro Lucero --- drivers/cxl/core/regs.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index fd165e718cf2..5434a7c899fd 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -437,11 +437,10 @@ static int cxl_probe_regs(struct cxl_register_map *map) case CXL_REGLOC_RBI_MEMDEV: dev_map = &map->device_map; cxl_probe_device_regs(host, base, dev_map); - if (!dev_map->status.valid || !dev_map->mbox.valid || + if (!dev_map->status.valid || !dev_map->memdev.valid) { - dev_err(host, "registers not found: %s%s%s\n", + dev_err(host, "registers not found: %s%s\n", !dev_map->status.valid ? "status " : "", - !dev_map->mbox.valid ? "mbox " : "", !dev_map->memdev.valid ? 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Thu, 16 May 2024 03:12:20 -0500 From: To: , , , , CC: Alejandro Lucero Subject: [RFC PATCH 05/13] cxl: fix check about pmem resource Date: Thu, 16 May 2024 09:11:54 +0100 Message-ID: <20240516081202.27023-6-alucerop@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240516081202.27023-1-alucerop@amd.com> References: <20240516081202.27023-1-alucerop@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: alucerop@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A9:EE_|CY5PR12MB6321:EE_ X-MS-Office365-Filtering-Correlation-Id: 9f72d333-6daa-45e6-25bb-08dc757fec36 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|1800799015|36860700004|82310400017; X-Microsoft-Antispam-Message-Info: =?utf-8?q?7eeoMwnOFnVOMs3apr+D68X+sfM6SA4?= =?utf-8?q?DOz3970OamiiytYflFwrekVedC/jZFBzC5jNrhYdBerv2AosPkFUBX+wMW+GBGOpG?= =?utf-8?q?epCR0iiqIj1JPRqxYq5Hwl6i3XNxgm2Y5mu5akDgDZhemO9oPMpI5dwVFGF8Z/P3A?= =?utf-8?q?gILy2HTDm0ifLhBSUldtePd0KOPF9sm6Zprh/DcU+1eoypj7Ozsva6z7DBSDhxeiK?= =?utf-8?q?Tn1O8Yt/Xd3QfD3qLENvKv2AASoW/DwlzKxmHZd7mvcDvzKLadv1DJ/uIF6ERHC6E?= =?utf-8?q?IfBrajcg69n7SqexOGVVbkYnbsYDxTSHsMAh+sX0M1x4QuRKiZoAMQ/c8eyvCZ2PC?= =?utf-8?q?2Qo8BKBwJy407kwDQxCwCrJBfXWJvWPTsuva13aAi+HxI8LYMVsd/xNzuPRV1hz+J?= =?utf-8?q?+BhGySN3fUM5I24FTZySoeX9oPRwsDNdAKdrmD+k2ejkfckWfeme7PxdpVCHpV6CP?= =?utf-8?q?MNnfCBe0xemghCWCkxjB1UqYB8ChHcKdQJneNMHyQzK7cY14rB6BakT84asD7ncK/?= =?utf-8?q?CVmDmpb95xg/g+lgjmSC07ROqMYdJp+YRlVRDxLnsTPPdgXXaNDwChv9E3GVeG+c2?= =?utf-8?q?0fl1Y5VuBmyAQS/3WjMiMiC8v2bi9qmwnfgYzfBwIuXF662YnzVqQTjUAHzOR7Z+K?= =?utf-8?q?wpCJ3OfH7ZiDhmtdItxj0P9+u2L4J6PvbByZPooqt8h9tF8Ta83tbW6WjaX1yaOlH?= =?utf-8?q?YMjQQMcmvEGw4KXYzz8NDXLJonhjF/ebCy8BXGScB1vjbnS/SC9m3hSpsKbRvwvMQ?= =?utf-8?q?3giKgBJi7Jk8qLX0dMwar+CX/Xp7sMj5ylWOUyEyArJVF4j8txTOCoj/8zsajKEiq?= =?utf-8?q?FqHfYBMCYEX3z0q9uzui4CEXW3kZk2DK3oKOyj6NihkNQ/DSJkexXtxgXodqeUDCv?= =?utf-8?q?L6mDaR7eJlYTfHA9+j2+d++KJXEHwQMadRwyicGxQs/dsN4Hn4OJEIoXzYhhYrBBd?= =?utf-8?q?DxY8eufHFtiyyV70z0FyC5CKbOPp5taUGWPH//YzVrRRdJeGH1nU2bfZOOuDCuqDu?= =?utf-8?q?Ra2sam7rHN/KiFip3GM2y5xb+jTEDklCANuCASuEOnSYOM2uljLE8bNAFj7up6Cr9?= =?utf-8?q?KZ97VKcbCYeicAP5g1Ujd0b7Ydf+4qXquVpf//0D+y6EMk8IL2hP5WQUI67WNTjxf?= =?utf-8?q?2HZwtZy/nK7qorTaSn8IgmnBOwoHfJVg6hT2WHfriB0/tbQ8snDfANnSg3QJqMsyw?= =?utf-8?q?cWe3cEgKoQf1g+fIkcHy/alCFnqMCvR1HtE7ktvhAjMQ72s0BSSMvBhqIHLWzGA2F?= =?utf-8?q?SxxmUFFOaUmZ+h1iP05lL3/awNT0FKYGGXVLRPdI5CaODEIfhDiHqlJEX/MQl9WR0?= =?utf-8?q?gH8IdNZ2srnz?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(376005)(1800799015)(36860700004)(82310400017);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2024 08:12:26.3567 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f72d333-6daa-45e6-25bb-08dc757fec36 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6321 From: Alejandro Lucero Current check is using resource_size which counts on a range bigger than 0. For a resource with start and end being 0, resource_size returns 1 and implying a false positive. Use the end not being zero as the new check. Note: If I´m not missing anything here, this should be extended to the whole linux kernel where resource_size is being used in conditionals, and where the likely right fix is to modify resource_size itself checking for the range not being 0. Signed-off-by: Alejandro Lucero --- drivers/cxl/core/hdm.c | 4 ++-- drivers/cxl/core/memdev.c | 8 ++++---- drivers/cxl/mem.c | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 47d9faf5897f..c5f70741d70a 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -432,12 +432,12 @@ int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled, * Only allow modes that are supported by the current partition * configuration */ - if (mode == CXL_DECODER_PMEM && !resource_size(&cxlds->pmem_res)) { + if (mode == CXL_DECODER_PMEM && !cxlds->pmem_res.end) { dev_dbg(dev, "no available pmem capacity\n"); rc = -ENXIO; goto out; } - if (mode == CXL_DECODER_RAM && !resource_size(&cxlds->ram_res)) { + if (mode == CXL_DECODER_RAM && !cxlds->ram_res.end) { dev_dbg(dev, "no available ram capacity\n"); rc = -ENXIO; goto out; diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c index 0336b3f14f4a..b61d57d0d4f4 100644 --- a/drivers/cxl/core/memdev.c +++ b/drivers/cxl/core/memdev.c @@ -197,14 +197,14 @@ static int cxl_get_poison_by_memdev(struct cxl_memdev *cxlmd) int rc = 0; /* CXL 3.0 Spec 8.2.9.8.4.1 Separate pmem and ram poison requests */ - if (resource_size(&cxlds->pmem_res)) { + if (cxlds->pmem_res.end) { offset = cxlds->pmem_res.start; length = resource_size(&cxlds->pmem_res); rc = cxl_mem_get_poison(cxlmd, offset, length, NULL); if (rc) return rc; } - if (resource_size(&cxlds->ram_res)) { + if (cxlds->ram_res.end) { offset = cxlds->ram_res.start; length = resource_size(&cxlds->ram_res); rc = cxl_mem_get_poison(cxlmd, offset, length, NULL); @@ -266,7 +266,7 @@ static int __cxl_dpa_to_region(struct device *dev, void *arg) return 0; cxled = to_cxl_endpoint_decoder(dev); - if (!cxled->dpa_res || !resource_size(cxled->dpa_res)) + if (!cxled->dpa_res || !cxled->dpa_res->end) return 0; if (dpa > cxled->dpa_res->end || dpa < cxled->dpa_res->start) @@ -302,7 +302,7 @@ static int cxl_validate_poison_dpa(struct cxl_memdev *cxlmd, u64 dpa) if (!IS_ENABLED(CONFIG_DEBUG_FS)) return 0; - if (!resource_size(&cxlds->dpa_res)) { + if (!cxlds->dpa_res.end) { dev_dbg(cxlds->dev, "device has no dpa resource\n"); return -EINVAL; } diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 6dc2bf1e2b1a..a168343d2d4d 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -174,7 +174,7 @@ static int cxl_mem_probe(struct device *dev) if (rc) return rc; - if (resource_size(&cxlds->pmem_res) && IS_ENABLED(CONFIG_CXL_PMEM)) { + if (cxlds->pmem_res.end && IS_ENABLED(CONFIG_CXL_PMEM)) { rc = devm_cxl_add_nvdimm(cxlmd); if (rc == -ENODEV) dev_info(dev, "PMEM disabled by platform\n"); From patchwork Thu May 16 08:11:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Lucero Palau X-Patchwork-Id: 13665839 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2074.outbound.protection.outlook.com [40.107.244.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 419D4282EF for ; Thu, 16 May 2024 08:12:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 16 May 2024 03:12:22 -0500 Received: from xcbalucerop41x.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Thu, 16 May 2024 03:12:21 -0500 From: To: , , , , CC: Alejandro Lucero Subject: [RFC PATCH 06/13] cxl: support type2 memdev creation Date: Thu, 16 May 2024 09:11:55 +0100 Message-ID: <20240516081202.27023-7-alucerop@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240516081202.27023-1-alucerop@amd.com> References: <20240516081202.27023-1-alucerop@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: alucerop@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A9:EE_|DM4PR12MB8449:EE_ X-MS-Office365-Filtering-Correlation-Id: 92e4be0e-cd53-40ec-4374-08dc757fed16 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|1800799015|376005|36860700004; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2024 08:12:27.8098 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 92e4be0e-cd53-40ec-4374-08dc757fed16 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8449 From: Alejandro Lucero Adding memdev creation to the cxl type2 test driver. Current cxl core is relying on a CXL_DEVTYPE_CLASSMEM type device when creating a memdev leading to problems when obtaining cxl_memdev_state references from a CXL_DEVTYPE_DEVMEM type. This last device type is managed by a specific vendor driver and does not need same sysfs files since not userspace intervention is expected. This patch checks for the right device type in those functions using cxl_memdev_state. Signed-off-by: Alejandro Lucero --- drivers/cxl/core/cdat.c | 3 +++ drivers/cxl/core/memdev.c | 9 +++++++++ drivers/cxl/mem.c | 17 +++++++++++------ tools/testing/cxl/type2/pci_type2.c | 6 ++++++ 4 files changed, 29 insertions(+), 6 deletions(-) diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c index 97ff1dfd63d6..292efd7e68ad 100644 --- a/drivers/cxl/core/cdat.c +++ b/drivers/cxl/core/cdat.c @@ -558,6 +558,9 @@ void cxl_region_perf_data_calculate(struct cxl_region *cxlr, }; struct cxl_dpa_perf *perf; + if (!mds) + return; + switch (cxlr->mode) { case CXL_DECODER_RAM: perf = &mds->ram_perf; diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c index b61d57d0d4f4..27063cd4ea73 100644 --- a/drivers/cxl/core/memdev.c +++ b/drivers/cxl/core/memdev.c @@ -511,6 +511,9 @@ static umode_t cxl_ram_visible(struct kobject *kobj, struct attribute *a, int n) struct cxl_memdev *cxlmd = to_cxl_memdev(dev); struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds); + if (!mds) + return 0; + if (a == &dev_attr_ram_qos_class.attr) if (mds->ram_perf.qos_class == CXL_QOS_CLASS_INVALID) return 0; @@ -530,6 +533,9 @@ static umode_t cxl_pmem_visible(struct kobject *kobj, struct attribute *a, int n struct cxl_memdev *cxlmd = to_cxl_memdev(dev); struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds); + if (!mds) + return 0; + if (a == &dev_attr_pmem_qos_class.attr) if (mds->pmem_perf.qos_class == CXL_QOS_CLASS_INVALID) return 0; @@ -550,6 +556,9 @@ static umode_t cxl_memdev_security_visible(struct kobject *kobj, struct cxl_memdev *cxlmd = to_cxl_memdev(dev); struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds); + if (!mds) + return 0; + if (a == &dev_attr_security_sanitize.attr && !test_bit(CXL_SEC_ENABLED_SANITIZE, mds->security.enabled_cmds)) return 0; diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index a168343d2d4d..da63ce486e1a 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -131,12 +131,14 @@ static int cxl_mem_probe(struct device *dev) dentry = cxl_debugfs_create_dir(dev_name(dev)); debugfs_create_devm_seqfile(dev, "dpamem", dentry, cxl_mem_dpa_show); - if (test_bit(CXL_POISON_ENABLED_INJECT, mds->poison.enabled_cmds)) - debugfs_create_file("inject_poison", 0200, dentry, cxlmd, - &cxl_poison_inject_fops); - if (test_bit(CXL_POISON_ENABLED_CLEAR, mds->poison.enabled_cmds)) - debugfs_create_file("clear_poison", 0200, dentry, cxlmd, - &cxl_poison_clear_fops); + if (mds) { + if (test_bit(CXL_POISON_ENABLED_INJECT, mds->poison.enabled_cmds)) + debugfs_create_file("inject_poison", 0200, dentry, cxlmd, + &cxl_poison_inject_fops); + if (test_bit(CXL_POISON_ENABLED_CLEAR, mds->poison.enabled_cmds)) + debugfs_create_file("clear_poison", 0200, dentry, cxlmd, + &cxl_poison_clear_fops); + } rc = devm_add_action_or_reset(dev, remove_debugfs, dentry); if (rc) @@ -221,6 +223,9 @@ static umode_t cxl_mem_visible(struct kobject *kobj, struct attribute *a, int n) struct cxl_memdev *cxlmd = to_cxl_memdev(dev); struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds); + if (!mds) + return 0; + if (a == &dev_attr_trigger_poison_list.attr) if (!test_bit(CXL_POISON_ENABLED_LIST, mds->poison.enabled_cmds)) diff --git a/tools/testing/cxl/type2/pci_type2.c b/tools/testing/cxl/type2/pci_type2.c index b12f13e676fb..f157139b712f 100644 --- a/tools/testing/cxl/type2/pci_type2.c +++ b/tools/testing/cxl/type2/pci_type2.c @@ -5,6 +5,7 @@ #include struct cxl_dev_state *cxlds; +struct cxl_memdev *cxlmd; #define CXL_TYPE2_MEM_SIZE (1024*1024*256) @@ -66,6 +67,11 @@ static int type2_pci_probe(struct pci_dev *pci_dev, else dev_warn(&pci_dev->dev, "Media not active (%d)\n", rc); + pci_info(pci_dev, "cxl adding memdev..."); + cxlmd = devm_cxl_add_memdev(&pci_dev->dev, cxlds); + if (IS_ERR(cxlmd)) + return PTR_ERR(cxlmd); + return 0; } From patchwork Thu May 16 08:11:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Lucero Palau X-Patchwork-Id: 13665837 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2072.outbound.protection.outlook.com [40.107.220.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 520124501A for ; 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Thu, 16 May 2024 03:12:23 -0500 Received: from xcbalucerop41x.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Thu, 16 May 2024 03:12:22 -0500 From: To: , , , , CC: Alejandro Lucero Subject: [RFC PATCH 07/13] cxl: add functions for exclusive access to endpoint port topology Date: Thu, 16 May 2024 09:11:56 +0100 Message-ID: <20240516081202.27023-8-alucerop@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240516081202.27023-1-alucerop@amd.com> References: <20240516081202.27023-1-alucerop@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: alucerop@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A8:EE_|SN7PR12MB7274:EE_ X-MS-Office365-Filtering-Correlation-Id: 40de3214-9247-4957-4baa-08dc757fed68 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|1800799015|376005|82310400017; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2024 08:12:28.3630 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40de3214-9247-4957-4baa-08dc757fed68 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7274 From: Alejandro Lucero Prevent concurrent access to endpoint port topology. Signed-off-by: Alejandro Lucero Signed-off-by: Dan Williams Signed-off-by: Alejandro Lucero --- drivers/cxl/core/memdev.c | 41 +++++++++++++++++++++++++++++ include/linux/cxlmem.h | 4 +++ tools/testing/cxl/type2/pci_type2.c | 9 +++++++ 3 files changed, 54 insertions(+) diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c index 27063cd4ea73..16e356ef5b6d 100644 --- a/drivers/cxl/core/memdev.c +++ b/drivers/cxl/core/memdev.c @@ -1124,6 +1124,47 @@ struct cxl_memdev *devm_cxl_add_memdev(struct device *host, } EXPORT_SYMBOL_NS_GPL(devm_cxl_add_memdev, CXL); +/* + * Try to get a locked reference on a memdev's CXL port topology + * connection. Be careful to observe when cxl_mem_probe() has deposited + * a probe deferral awaiting the arrival of the CXL root driver +*/ +struct cxl_port *cxl_acquire_endpoint(struct cxl_memdev *cxlmd) +{ + struct cxl_port *endpoint; + int rc = -ENXIO; + + device_lock(&cxlmd->dev); + endpoint = cxlmd->endpoint; + if (!endpoint) + goto err; + + if (IS_ERR(endpoint)) { + rc = PTR_ERR(endpoint); + goto err; + } + + device_lock(&endpoint->dev); + if (!endpoint->dev.driver) + goto err_endpoint; + + return endpoint; + +err_endpoint: + device_unlock(&endpoint->dev); +err: + device_unlock(&cxlmd->dev); + return ERR_PTR(rc); +} +EXPORT_SYMBOL_NS(cxl_acquire_endpoint, CXL); + +void cxl_release_endpoint(struct cxl_memdev *cxlmd, struct cxl_port *endpoint) +{ + device_unlock(&endpoint->dev); + device_unlock(&cxlmd->dev); +} +EXPORT_SYMBOL_NS(cxl_release_endpoint, CXL); + static void sanitize_teardown_notifier(void *data) { struct cxl_memdev_state *mds = data; diff --git a/include/linux/cxlmem.h b/include/linux/cxlmem.h index e8d12b543db1..11fe8367b046 100644 --- a/include/linux/cxlmem.h +++ b/include/linux/cxlmem.h @@ -88,6 +88,10 @@ static inline bool is_cxl_endpoint(struct cxl_port *port) struct cxl_memdev *devm_cxl_add_memdev(struct device *host, struct cxl_dev_state *cxlds); + +struct cxl_port *cxl_acquire_endpoint(struct cxl_memdev *cxlmd); +void cxl_release_endpoint(struct cxl_memdev *cxlmd, struct cxl_port *endpoint); + int devm_cxl_sanitize_setup_notifier(struct device *host, struct cxl_memdev *cxlmd); struct cxl_memdev_state; diff --git a/tools/testing/cxl/type2/pci_type2.c b/tools/testing/cxl/type2/pci_type2.c index f157139b712f..948cc95c5780 100644 --- a/tools/testing/cxl/type2/pci_type2.c +++ b/tools/testing/cxl/type2/pci_type2.c @@ -6,6 +6,7 @@ struct cxl_dev_state *cxlds; struct cxl_memdev *cxlmd; +struct cxl_port *endpoint; #define CXL_TYPE2_MEM_SIZE (1024*1024*256) @@ -72,6 +73,14 @@ static int type2_pci_probe(struct pci_dev *pci_dev, if (IS_ERR(cxlmd)) return PTR_ERR(cxlmd); + endpoint = cxl_acquire_endpoint(cxlmd); + if (IS_ERR(endpoint)) { + dev_dbg(&pci_dev->dev, "cxl_acquire_endpoint failed\n"); + return PTR_ERR(endpoint); + } + + cxl_release_endpoint(cxlmd, endpoint); + return 0; } From patchwork Thu May 16 08:11:57 2024 Content-Type: text/plain; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by BN2PEPF000044AB.mail.protection.outlook.com (10.167.243.106) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7587.21 via Frontend Transport; Thu, 16 May 2024 08:12:29 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 16 May 2024 03:12:24 -0500 Received: from xcbalucerop41x.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Thu, 16 May 2024 03:12:23 -0500 From: To: , , , , CC: Alejandro Lucero Subject: [RFC PATCH 08/13] cxl: add cxl_get_hpa_freespace Date: Thu, 16 May 2024 09:11:57 +0100 Message-ID: <20240516081202.27023-9-alucerop@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240516081202.27023-1-alucerop@amd.com> References: <20240516081202.27023-1-alucerop@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: alucerop@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044AB:EE_|CY8PR12MB7516:EE_ X-MS-Office365-Filtering-Correlation-Id: 582bd528-eb4e-4d66-7cd3-08dc757fedd3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|82310400017|36860700004|376005; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2024 08:12:29.0499 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 582bd528-eb4e-4d66-7cd3-08dc757fedd3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044AB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7516 From: Alejandro Lucero Based on the requirements from the endpoint and the topology such an endpoint is attached to, this function informs about maximum host physical address space possible to request. This is not a reservation but only information which could change at the point the request based on this information is made. Signed-off-by: Alejandro Lucero Signed-off-by: Dan Williams Signed-off-by: Alejandro Lucero --- drivers/cxl/core/region.c | 163 ++++++++++++++++++++++++++++ include/linux/cxl.h | 5 + include/linux/cxlmem.h | 5 + tools/testing/cxl/type2/pci_type2.c | 23 +++- 4 files changed, 195 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 70e86a7c241d..2731fd4243a1 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -702,6 +702,169 @@ static int free_hpa(struct cxl_region *cxlr) return 0; } + +struct cxlrd_max_context { + struct device * const *host_bridges; + int interleave_ways; + unsigned long flags; + resource_size_t max_hpa; + struct cxl_root_decoder *cxlrd; +}; + +static int find_max_hpa(struct device *dev, void *data) +{ + struct cxlrd_max_context *ctx = data; + struct cxl_switch_decoder *cxlsd; + struct cxl_root_decoder *cxlrd; + struct resource *res, *prev; + struct cxl_decoder *cxld; + resource_size_t max; + int found; + + if (!is_root_decoder(dev)) + return 0; + + cxlrd = to_cxl_root_decoder(dev); + cxld = &cxlrd->cxlsd.cxld; + if ((cxld->flags & ctx->flags) != ctx->flags) { + dev_dbg(dev, "find_max_hpa, flags not matching: %08lx vs %08lx\n", + cxld->flags, ctx->flags); + return 0; + } + + /* A Host bridge could have more interleave ways than an + * endpoint, couldn´t it? + * + * What does interleave ways mean here in terms of the requestor? + * Why the FFMWS has 0 interleave ways but root port has 1? + */ + if (cxld->interleave_ways != ctx->interleave_ways) { + dev_dbg(dev, "find_max_hpa, interleave_ways not matching\n"); + return 0; + } + + cxlsd = &cxlrd->cxlsd; + + guard(rwsem_read)(&cxl_region_rwsem); + found = 0; + for (int i = 0; i < ctx->interleave_ways; i++) + for (int j = 0; j < ctx->interleave_ways; j++) + if (ctx->host_bridges[i] == + cxlsd->target[j]->dport_dev) { + found++; + break; + } + + if (found != ctx->interleave_ways) { + dev_dbg(dev, "find_max_hpa, no interleave_ways found\n"); + return 0; + } + + /* + * Walk the root decoder resource range relying on cxl_region_rwsem to + * preclude sibling arrival/departure and find the largest free space + * gap. + */ + lockdep_assert_held_read(&cxl_region_rwsem); + max = 0; + res = cxlrd->res->child; + if (!res) + max = resource_size(cxlrd->res); + else + max = 0; + + for (prev = NULL; res; prev = res, res = res->sibling) { + struct resource *next = res->sibling; + resource_size_t free = 0; + + if (!prev && res->start > cxlrd->res->start) { + free = res->start - cxlrd->res->start; + max = max(free, max); + } + if (prev && res->start > prev->end + 1) { + free = res->start - prev->end + 1; + max = max(free, max); + } + if (next && res->end + 1 < next->start) { + free = next->start - res->end + 1; + max = max(free, max); + } + if (!next && res->end + 1 < cxlrd->res->end + 1) { + free = cxlrd->res->end + 1 - res->end + 1; + max = max(free, max); + } + } + + if (max > ctx->max_hpa) { + if (ctx->cxlrd) + put_device(CXLRD_DEV(ctx->cxlrd)); + get_device(CXLRD_DEV(cxlrd)); + ctx->cxlrd = cxlrd; + ctx->max_hpa = max; + dev_info(CXLRD_DEV(cxlrd), "found %pa bytes of free space\n", &max); + } + return 0; +} + +/** + * cxl_get_hpa_freespace - find a root decoder with free capacity per constraints + * @endpoint: an endpoint that is mapped by the returned decoder + * @host_bridges: array of host-bridges that the decoder must interleave + * @interleave_ways: number of entries in @host_bridges + * @flags: CXL_DECODER_F flags for selecting RAM vs PMEM, and HDM-H vs HDM-D[B] + * @max: output parameter of bytes available in the returned decoder + * + * The return tuple of a 'struct cxl_root_decoder' and 'bytes available (@max)' + * is a point in time snapshot. If by the time the caller goes to use this root + * decoder's capacity the capacity is reduced then caller needs to loop and + * retry. + * + * The returned root decoder has an elevated reference count that needs to be + * put with put_device(cxlrd_dev(cxlrd)). Locking context is with + * cxl_{acquire,release}_endpoint(), that ensures removal of the root decoder + * does not race. + */ +struct cxl_root_decoder *cxl_get_hpa_freespace(struct cxl_port *endpoint, + struct device *const *host_bridges, + int interleave_ways, + unsigned long flags, + resource_size_t *max) +{ + + struct cxlrd_max_context ctx = { + .host_bridges = host_bridges, + .interleave_ways = interleave_ways, + .flags = flags, + }; + struct cxl_port *root_port; + struct cxl_root *root; + + if (!is_cxl_endpoint(endpoint)) { + dev_dbg(&endpoint->dev, "hpa requestor is not an endpointr\n"); + return ERR_PTR(-EINVAL); + } + + root = find_cxl_root(endpoint); + if (!root) { + dev_dbg(&endpoint->dev, "endpoint can not be related to a root port\n"); + return ERR_PTR(-ENXIO); + } + + root_port = &root->port; + down_read(&cxl_region_rwsem); + device_for_each_child(&root_port->dev, &ctx, find_max_hpa); + up_read(&cxl_region_rwsem); + put_device(&root_port->dev); + + if (!ctx.cxlrd) + return ERR_PTR(-ENOMEM); + + *max = ctx.max_hpa; + return ctx.cxlrd; +} +EXPORT_SYMBOL_NS_GPL(cxl_get_hpa_freespace, CXL); + + static ssize_t size_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { diff --git a/include/linux/cxl.h b/include/linux/cxl.h index 036d17db68e0..1b2377062693 100644 --- a/include/linux/cxl.h +++ b/include/linux/cxl.h @@ -766,6 +766,11 @@ struct cxl_decoder *to_cxl_decoder(struct device *dev); struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); struct cxl_endpoint_decoder *to_cxl_endpoint_decoder(struct device *dev); + +#define CXLED_DEV(cxled) &cxled->cxld.dev + +#define CXLRD_DEV(cxlrd) &cxlrd->cxlsd.cxld.dev + bool is_root_decoder(struct device *dev); bool is_switch_decoder(struct device *dev); bool is_endpoint_decoder(struct device *dev); diff --git a/include/linux/cxlmem.h b/include/linux/cxlmem.h index 11fe8367b046..342ccd5486d3 100644 --- a/include/linux/cxlmem.h +++ b/include/linux/cxlmem.h @@ -865,4 +865,9 @@ struct dentry *cxl_debugfs_create_dir(const char *dir); void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds); struct cxl_dev_state *cxl_accel_state_create(struct device *dev); +struct cxl_root_decoder *cxl_get_hpa_freespace(struct cxl_port *endpoint, + struct device *const *host_bridges, + int interleave_ways, + unsigned long flags, + resource_size_t *max); #endif /* __CXL_MEM_H__ */ diff --git a/tools/testing/cxl/type2/pci_type2.c b/tools/testing/cxl/type2/pci_type2.c index 948cc95c5780..deb5eeae501b 100644 --- a/tools/testing/cxl/type2/pci_type2.c +++ b/tools/testing/cxl/type2/pci_type2.c @@ -4,6 +4,7 @@ #include #include +struct cxl_root_decoder *cxlrd; struct cxl_dev_state *cxlds; struct cxl_memdev *cxlmd; struct cxl_port *endpoint; @@ -15,6 +16,7 @@ static int type2_pci_probe(struct pci_dev *pci_dev, { struct cxl_register_map map; + resource_size_t max = 0; u16 dvsec; int rc; @@ -79,9 +81,28 @@ static int type2_pci_probe(struct pci_dev *pci_dev, return PTR_ERR(endpoint); } + pci_info(pci_dev, "cxl hpa_freespace..."); + cxlrd = cxl_get_hpa_freespace(endpoint, &endpoint->host_bridge, 1, + CXL_DECODER_F_RAM | CXL_DECODER_F_TYPE2, + &max); + + if (IS_ERR(cxlrd)) { + dev_dbg(&pci_dev->dev, "cxl_get_hpa_freespace failed\n"); + rc = PTR_ERR(cxlrd); + goto out; + } + + if (max < CXL_TYPE2_MEM_SIZE) { + dev_dbg(&pci_dev->dev, "%s: no enough free HPA space %llu < %u\n", + __func__, max, CXL_TYPE2_MEM_SIZE); + rc = -ENOMEM; + goto out; + } + +out: cxl_release_endpoint(cxlmd, endpoint); - return 0; + return rc; } static void type2_pci_remove(struct pci_dev *pci_dev) From patchwork Thu May 16 08:11:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Lucero Palau X-Patchwork-Id: 13665842 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2073.outbound.protection.outlook.com [40.107.243.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F08E6DCE3 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2024 08:12:29.2224 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b28783f2-2146-451c-6cfe-08dc757fedeb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6844 From: Alejandro Lucero Search and reserve DPA given input constraints. Signed-off-by: Alejandro Lucero Signed-off-by: Dan Williams Signed-off-by: Alejandro Lucero --- drivers/cxl/core/core.h | 1 - drivers/cxl/core/hdm.c | 153 +++++++++++++++++++++++----- include/linux/cxlmem.h | 5 + tools/testing/cxl/type2/pci_type2.c | 12 ++- 4 files changed, 145 insertions(+), 26 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index bc5a95665aa0..c0a2e2c1ccb3 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -61,7 +61,6 @@ struct dentry *cxl_debugfs_create_dir(const char *dir); int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled, enum cxl_decoder_mode mode); int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size); -int cxl_dpa_free(struct cxl_endpoint_decoder *cxled); resource_size_t cxl_dpa_size(struct cxl_endpoint_decoder *cxled); resource_size_t cxl_dpa_resource_start(struct cxl_endpoint_decoder *cxled); diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index c5f70741d70a..6459b6ecde88 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -404,6 +404,7 @@ int cxl_dpa_free(struct cxl_endpoint_decoder *cxled) up_write(&cxl_dpa_rwsem); return rc; } +EXPORT_SYMBOL_NS_GPL(cxl_dpa_free, CXL); int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled, enum cxl_decoder_mode mode) @@ -451,30 +452,17 @@ int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled, return rc; } -int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size) +static resource_size_t cxl_dpa_freespace(struct cxl_endpoint_decoder *cxled, + resource_size_t *start_out, + resource_size_t *skip_out) { struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); resource_size_t free_ram_start, free_pmem_start; - struct cxl_port *port = cxled_to_port(cxled); struct cxl_dev_state *cxlds = cxlmd->cxlds; - struct device *dev = &cxled->cxld.dev; resource_size_t start, avail, skip; struct resource *p, *last; - int rc; - - down_write(&cxl_dpa_rwsem); - if (cxled->cxld.region) { - dev_dbg(dev, "decoder attached to %s\n", - dev_name(&cxled->cxld.region->dev)); - rc = -EBUSY; - goto out; - } - if (cxled->cxld.flags & CXL_DECODER_F_ENABLE) { - dev_dbg(dev, "decoder enabled\n"); - rc = -EBUSY; - goto out; - } + lockdep_assert_held(&cxl_dpa_rwsem); for (p = cxlds->ram_res.child, last = NULL; p; p = p->sibling) last = p; @@ -496,7 +484,6 @@ int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size) skip = 0; } else if (cxled->mode == CXL_DECODER_PMEM) { resource_size_t skip_start, skip_end; - start = free_pmem_start; avail = cxlds->pmem_res.end - start + 1; skip_start = free_ram_start; @@ -506,21 +493,50 @@ int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size) * already handled the skip. */ if (cxlds->pmem_res.child && - skip_start == cxlds->pmem_res.child->start) + skip_start == cxlds->pmem_res.child->start) skip_end = skip_start - 1; else skip_end = start - 1; skip = skip_end - skip_start + 1; } else { - dev_dbg(dev, "mode not set\n"); - rc = -EINVAL; + avail = 0; + } + + if (!avail) + return 0; + if (start_out) + *start_out = start; + if (skip_out) + *skip_out = skip; + return avail; +} + +int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size) +{ + struct cxl_port *port = cxled_to_port(cxled); + struct device *dev = &cxled->cxld.dev; + resource_size_t start, avail, skip; + int rc; + + down_write(&cxl_dpa_rwsem); + if (cxled->cxld.region) { + dev_dbg(dev, "EBUSY, decoder attached to %s\n", + dev_name(&cxled->cxld.region->dev)); + rc = -EBUSY; goto out; } + if (cxled->cxld.flags & CXL_DECODER_F_ENABLE) { + dev_dbg(dev, "EBUSY, decoder enabled\n"); + rc = -EBUSY; + goto out; + } + + avail = cxl_dpa_freespace(cxled, &start, &skip); if (size > avail) { dev_dbg(dev, "%pa exceeds available %s capacity: %pa\n", &size, - cxled->mode == CXL_DECODER_RAM ? "ram" : "pmem", - &avail); + cxled->mode == CXL_DECODER_RAM ? "ram" : "pmem", + &avail); rc = -ENOSPC; goto out; } @@ -532,9 +548,98 @@ int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size) if (rc) return rc; - return devm_add_action_or_reset(&port->dev, cxl_dpa_release, cxled); + return devm_add_action_or_reset(&port->dev, cxl_dpa_release, cxled); } +static int find_free_decoder(struct device *dev, void *data) +{ + struct cxl_endpoint_decoder *cxled; + struct cxl_port *port; + + if (!is_endpoint_decoder(dev)) + return 0; + + cxled = to_cxl_endpoint_decoder(dev); + port = cxled_to_port(cxled); + + if (cxled->cxld.id != port->hdm_end + 1) { + return 0; + } + return 1; +} + +/** + * cxl_request_dpa - search and reserve DPA given input constraints + * @endpoint: an endpoint port with available decoders + * @mode: DPA operation mode (ram vs pmem) + * @min: the minimum amount of capacity the call needs + * @max: extra capacity to allocate after min is satisfied + * + * Given that a region needs to allocate from limited HPA capacity it + * may be the case that a device has more mappable DPA capacity than + * available HPA. So, the expectation is that @min is a driver known + * value for how much capacity is needed, and @max is based the limit of + * how much HPA space is available for a new region. + * + * Returns a pinned cxl_decoder with at least @min bytes of capacity + * reserved, or an error pointer. The caller is also expected to own the + * lifetime of the memdev registration associated with the endpoint to + * pin the decoder registered as well. + */ +struct cxl_endpoint_decoder *cxl_request_dpa(struct cxl_port *endpoint, + enum cxl_decoder_mode mode, + resource_size_t min, + resource_size_t max) +{ + struct cxl_endpoint_decoder *cxled; + struct device *cxled_dev; + resource_size_t alloc; + int rc; + + if (!IS_ALIGNED(min | max, SZ_256M)) + return ERR_PTR(-EINVAL); + + down_read(&cxl_dpa_rwsem); + + cxled_dev = device_find_child(&endpoint->dev, NULL, find_free_decoder); + if (!cxled_dev) + cxled = ERR_PTR(-ENXIO); + else + cxled = to_cxl_endpoint_decoder(cxled_dev); + + up_read(&cxl_dpa_rwsem); + + if (IS_ERR(cxled)) { + return cxled; + } + + rc = cxl_dpa_set_mode(cxled, mode); + if (rc) + goto err; + + down_read(&cxl_dpa_rwsem); + alloc = cxl_dpa_freespace(cxled, NULL, NULL); + up_read(&cxl_dpa_rwsem); + + if (max) + alloc = min(max, alloc); + if (alloc < min) { + rc = -ENOMEM; + goto err; + } + + rc = cxl_dpa_alloc(cxled, alloc); + if (rc) + goto err; + + return cxled; +err: + put_device(cxled_dev); + return ERR_PTR(rc); +} +EXPORT_SYMBOL_NS_GPL(cxl_request_dpa, CXL); + + static void cxld_set_interleave(struct cxl_decoder *cxld, u32 *ctrl) { u16 eig; diff --git a/include/linux/cxlmem.h b/include/linux/cxlmem.h index 342ccd5486d3..caf1cd86421c 100644 --- a/include/linux/cxlmem.h +++ b/include/linux/cxlmem.h @@ -870,4 +870,9 @@ struct cxl_root_decoder *cxl_get_hpa_freespace(struct cxl_port *endpoint, int interleave_ways, unsigned long flags, resource_size_t *max); +struct cxl_endpoint_decoder *cxl_request_dpa(struct cxl_port *endpoint, + enum cxl_decoder_mode mode, + resource_size_t min, + resource_size_t max); +int cxl_dpa_free(struct cxl_endpoint_decoder *cxled); #endif /* __CXL_MEM_H__ */ diff --git a/tools/testing/cxl/type2/pci_type2.c b/tools/testing/cxl/type2/pci_type2.c index deb5eeae501b..6499d709f54d 100644 --- a/tools/testing/cxl/type2/pci_type2.c +++ b/tools/testing/cxl/type2/pci_type2.c @@ -4,6 +4,7 @@ #include #include +struct cxl_endpoint_decoder *cxled; struct cxl_root_decoder *cxlrd; struct cxl_dev_state *cxlds; struct cxl_memdev *cxlmd; @@ -99,6 +100,15 @@ static int type2_pci_probe(struct pci_dev *pci_dev, goto out; } + pci_info(pci_dev, "cxl request_dpa..."); + cxled = cxl_request_dpa(endpoint, CXL_DECODER_RAM, CXL_TYPE2_MEM_SIZE, + CXL_TYPE2_MEM_SIZE); + if (IS_ERR(cxled)) { + dev_dbg(&pci_dev->dev, "cxl_request_dpa error\n"); + rc = PTR_ERR(cxled); + goto out; + } + out: cxl_release_endpoint(cxlmd, endpoint); @@ -107,7 +117,7 @@ static int type2_pci_probe(struct pci_dev *pci_dev, static void type2_pci_remove(struct pci_dev *pci_dev) { - + cxl_dpa_free(cxled); } /* PCI device ID table */ From patchwork Thu May 16 08:11:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Lucero Palau X-Patchwork-Id: 13665836 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2069.outbound.protection.outlook.com [40.107.223.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B44AB4120A for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2024 08:12:29.4661 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eca808e9-783f-45cb-9b09-08dc757fee10 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8125 From: Alejandro Lucero Current code is expecting Type3 or CXL_DECODER_HOSTONLYMEM devices only. Suport for Type2 implies region type needs to be based on the endpoint type instead. Signed-off-by: Alejandro Lucero --- drivers/cxl/core/region.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 2731fd4243a1..8228b7e96d8d 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -2574,7 +2574,8 @@ static ssize_t create_ram_region_show(struct device *dev, } static struct cxl_region *__create_region(struct cxl_root_decoder *cxlrd, - enum cxl_decoder_mode mode, int id) + enum cxl_decoder_mode mode, int id, + enum cxl_decoder_type target_type) { int rc; @@ -2587,7 +2588,7 @@ static struct cxl_region *__create_region(struct cxl_root_decoder *cxlrd, return ERR_PTR(-EBUSY); } - return devm_cxl_add_region(cxlrd, id, mode, CXL_DECODER_HOSTONLYMEM); + return devm_cxl_add_region(cxlrd, id, mode, target_type); } static ssize_t create_pmem_region_store(struct device *dev, @@ -2602,7 +2603,8 @@ static ssize_t create_pmem_region_store(struct device *dev, if (rc != 1) return -EINVAL; - cxlr = __create_region(cxlrd, CXL_DECODER_PMEM, id); + cxlr = __create_region(cxlrd, CXL_DECODER_PMEM, id, + CXL_DECODER_HOSTONLYMEM); if (IS_ERR(cxlr)) return PTR_ERR(cxlr); @@ -2622,7 +2624,8 @@ static ssize_t create_ram_region_store(struct device *dev, if (rc != 1) return -EINVAL; - cxlr = __create_region(cxlrd, CXL_DECODER_RAM, id); + cxlr = __create_region(cxlrd, CXL_DECODER_RAM, id, + CXL_DECODER_HOSTONLYMEM); if (IS_ERR(cxlr)) return PTR_ERR(cxlr); @@ -3146,7 +3149,8 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, do { cxlr = __create_region(cxlrd, cxled->mode, - atomic_read(&cxlrd->region_id)); + atomic_read(&cxlrd->region_id), + cxled->cxld.target_type); } while (IS_ERR(cxlr) && PTR_ERR(cxlr) == -EBUSY); if (IS_ERR(cxlr)) { From patchwork Thu May 16 08:12:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Lucero Palau X-Patchwork-Id: 13665840 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2047.outbound.protection.outlook.com [40.107.101.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C13596CDA8 for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2024 08:12:29.7843 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4f98d85c-b48a-4d7d-8b5b-08dc757fee43 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044AB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9336 From: Alejandro Lucero Creating a CXL region requires userspace intervention through the cxl sysfs files. Type2 support should allow accelerator drivers to create such cxl region from kernel code. Adding that functionality and integrating it with current support for memory expanders. Signed-off-by: Alejandro Lucero Signed-off-by: Dan Williams Signed-off-by: Alejandro Lucero --- drivers/cxl/core/region.c | 262 ++++++++++++++++++++++------ include/linux/cxlmem.h | 4 + tools/testing/cxl/type2/pci_type2.c | 18 ++ 3 files changed, 228 insertions(+), 56 deletions(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 8228b7e96d8d..014684ff4343 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -479,22 +479,14 @@ static ssize_t interleave_ways_show(struct device *dev, static const struct attribute_group *get_cxl_region_target_group(void); -static ssize_t interleave_ways_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t len) +static int set_interleave_ways(struct cxl_region *cxlr, int val) { - struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev->parent); + struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent); struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld; - struct cxl_region *cxlr = to_cxl_region(dev); struct cxl_region_params *p = &cxlr->params; - unsigned int val, save; - int rc; + int save, rc; u8 iw; - rc = kstrtouint(buf, 0, &val); - if (rc) - return rc; - rc = ways_to_eiw(val, &iw); if (rc) return rc; @@ -509,25 +501,42 @@ static ssize_t interleave_ways_store(struct device *dev, return -EINVAL; } - rc = down_write_killable(&cxl_region_rwsem); - if (rc) - return rc; - if (p->state >= CXL_CONFIG_INTERLEAVE_ACTIVE) { - rc = -EBUSY; - goto out; - } + lockdep_assert_held_write(&cxl_region_rwsem); + if (p->state >= CXL_CONFIG_INTERLEAVE_ACTIVE) + return -EBUSY; save = p->interleave_ways; p->interleave_ways = val; rc = sysfs_update_group(&cxlr->dev.kobj, get_cxl_region_target_group()); if (rc) p->interleave_ways = save; -out: + + return rc; +} + +static ssize_t interleave_ways_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct cxl_region *cxlr = to_cxl_region(dev); + unsigned int val; + int rc; + + rc = kstrtouint(buf, 0, &val); + if (rc) + return rc; + + rc = down_write_killable(&cxl_region_rwsem); + if (rc) + return rc; + + rc = set_interleave_ways(cxlr, val); up_write(&cxl_region_rwsem); if (rc) return rc; return len; } + static DEVICE_ATTR_RW(interleave_ways); static ssize_t interleave_granularity_show(struct device *dev, @@ -547,21 +556,14 @@ static ssize_t interleave_granularity_show(struct device *dev, return rc; } -static ssize_t interleave_granularity_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t len) +static int set_interleave_granularity(struct cxl_region *cxlr, int val) { - struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(dev->parent); + struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent); struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld; - struct cxl_region *cxlr = to_cxl_region(dev); struct cxl_region_params *p = &cxlr->params; - int rc, val; + int rc; u16 ig; - rc = kstrtoint(buf, 0, &val); - if (rc) - return rc; - rc = granularity_to_eig(val, &ig); if (rc) return rc; @@ -577,21 +579,36 @@ static ssize_t interleave_granularity_store(struct device *dev, if (cxld->interleave_ways > 1 && val != cxld->interleave_granularity) return -EINVAL; + lockdep_assert_held_write(&cxl_region_rwsem); + if (p->state >= CXL_CONFIG_INTERLEAVE_ACTIVE) + return -EBUSY; + + p->interleave_granularity = val; + return 0; +} + +static ssize_t interleave_granularity_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct cxl_region *cxlr = to_cxl_region(dev); + int rc, val; + + rc = kstrtoint(buf, 0, &val); + if (rc) + return rc; + rc = down_write_killable(&cxl_region_rwsem); if (rc) return rc; - if (p->state >= CXL_CONFIG_INTERLEAVE_ACTIVE) { - rc = -EBUSY; - goto out; - } - p->interleave_granularity = val; -out: + rc = set_interleave_granularity(cxlr, val); up_write(&cxl_region_rwsem); if (rc) return rc; return len; } + static DEVICE_ATTR_RW(interleave_granularity); static ssize_t resource_show(struct device *dev, struct device_attribute *attr, @@ -2666,6 +2683,14 @@ cxl_find_region_by_name(struct cxl_root_decoder *cxlrd, const char *name) return to_cxl_region(region_dev); } +static void drop_region(struct cxl_region *cxlr) +{ + struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent); + struct cxl_port *port = cxlrd_to_port(cxlrd); + + devm_release_action(port->uport_dev, unregister_region, cxlr); +} + static ssize_t delete_region_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) @@ -3135,17 +3160,18 @@ static int match_region_by_range(struct device *dev, void *data) return rc; } -/* Establish an empty region covering the given HPA range */ -static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, - struct cxl_endpoint_decoder *cxled) +static void construct_region_end(void) +{ + up_write(&cxl_region_rwsem); +} + +static struct cxl_region *construct_region_begin(struct cxl_root_decoder *cxlrd, + struct cxl_endpoint_decoder *cxled) { struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); - struct cxl_port *port = cxlrd_to_port(cxlrd); - struct range *hpa = &cxled->cxld.hpa_range; struct cxl_region_params *p; struct cxl_region *cxlr; - struct resource *res; - int rc; + int err = 0; do { cxlr = __create_region(cxlrd, cxled->mode, @@ -3154,8 +3180,7 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, } while (IS_ERR(cxlr) && PTR_ERR(cxlr) == -EBUSY); if (IS_ERR(cxlr)) { - dev_err(cxlmd->dev.parent, - "%s:%s: %s failed assign region: %ld\n", + dev_err(cxlmd->dev.parent,"%s:%s: %s failed assign region: %ld\n", dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), __func__, PTR_ERR(cxlr)); return cxlr; @@ -3165,23 +3190,47 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, p = &cxlr->params; if (p->state >= CXL_CONFIG_INTERLEAVE_ACTIVE) { dev_err(cxlmd->dev.parent, - "%s:%s: %s autodiscovery interrupted\n", + "%s:%s: %s region setup interrupted\n", dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), __func__); - rc = -EBUSY; - goto err; + err = -EBUSY; + } + + if (err) { + construct_region_end(); + drop_region(cxlr); + return ERR_PTR(err); } + return cxlr; +} + + +/* Establish an empty region covering the given HPA range */ +static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, + struct cxl_endpoint_decoder *cxled) +{ + struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); + struct range *hpa = &cxled->cxld.hpa_range; + struct cxl_region_params *p; + struct cxl_region *cxlr; + struct resource *res; + int rc; + + cxlr = construct_region_begin(cxlrd, cxled); + if (IS_ERR(cxlr)) + return cxlr; set_bit(CXL_REGION_F_AUTO, &cxlr->flags); res = kmalloc(sizeof(*res), GFP_KERNEL); if (!res) { rc = -ENOMEM; - goto err; + goto out; } *res = DEFINE_RES_MEM_NAMED(hpa->start, range_len(hpa), dev_name(&cxlr->dev)); + rc = insert_resource(cxlrd->res, res); if (rc) { /* @@ -3194,6 +3243,7 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, __func__, dev_name(&cxlr->dev)); } + p = &cxlr->params; p->res = res; p->interleave_ways = cxled->cxld.interleave_ways; p->interleave_granularity = cxled->cxld.interleave_granularity; @@ -3201,24 +3251,124 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd, rc = sysfs_update_group(&cxlr->dev.kobj, get_cxl_region_target_group()); if (rc) - goto err; + goto out; dev_dbg(cxlmd->dev.parent, "%s:%s: %s %s res: %pr iw: %d ig: %d\n", - dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), __func__, - dev_name(&cxlr->dev), p->res, p->interleave_ways, - p->interleave_granularity); + dev_name(&cxlmd->dev), + dev_name(&cxled->cxld.dev), __func__, + dev_name(&cxlr->dev), p->res, + p->interleave_ways, + p->interleave_granularity); /* ...to match put_device() in cxl_add_to_region() */ get_device(&cxlr->dev); up_write(&cxl_region_rwsem); +out: + construct_region_end(); + if (rc) { + drop_region(cxlr); + return ERR_PTR(rc); + } + return cxlr; +} + +static struct cxl_region * +__construct_new_region(struct cxl_root_decoder *cxlrd, + struct cxl_endpoint_decoder **cxled, int ways) +{ + struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld; + struct cxl_region_params *p; + resource_size_t size = 0; + struct cxl_region *cxlr; + int rc, i; + + /* If interleaving is not supported, why does ways need to be at least 1? */ + if (ways < 1) + return ERR_PTR(-EINVAL); + + cxlr = construct_region_begin(cxlrd, cxled[0]); + if (IS_ERR(cxlr)) + return cxlr; + + rc = set_interleave_ways(cxlr, ways); + if (rc) + goto out; + + rc = set_interleave_granularity(cxlr, cxld->interleave_granularity); + if (rc) + goto out; + + down_read(&cxl_dpa_rwsem); + for (i = 0; i < ways; i++) { + if (!cxled[i]->dpa_res) + break; + size += resource_size(cxled[i]->dpa_res); + } + up_read(&cxl_dpa_rwsem); + + if (i < ways) + goto out; + + rc = alloc_hpa(cxlr, size); + if (rc) + goto out; + + down_read(&cxl_dpa_rwsem); + for (i = 0; i < ways; i++) { + rc = cxl_region_attach(cxlr, cxled[i], i); + if (rc) + break; + } + up_read(&cxl_dpa_rwsem); + + if (rc) + goto out; + + rc = cxl_region_decode_commit(cxlr); + if (rc) + goto out; + p = &cxlr->params; + p->state = CXL_CONFIG_COMMIT; +out: + construct_region_end(); + if (rc) { + drop_region(cxlr); + return ERR_PTR(rc); + } return cxlr; +} -err: - up_write(&cxl_region_rwsem); - devm_release_action(port->uport_dev, unregister_region, cxlr); - return ERR_PTR(rc); +/** + * cxl_create_region - Establish a region given an array of endpoint decoders + * @cxlrd: root decoder to allocate HPA + * @cxled: array of endpoint decoders with reserved DPA capacity + * @ways: size of @cxled array + * + * Returns a fully formed region in the commit state and attached to the + * cxl_region driver. + */ +struct cxl_region *cxl_create_region(struct cxl_root_decoder *cxlrd, + struct cxl_endpoint_decoder **cxled, + int ways) +{ + struct cxl_region *cxlr; + + mutex_lock(&cxlrd->range_lock); + cxlr = __construct_new_region(cxlrd, cxled, ways); + mutex_unlock(&cxlrd->range_lock); + + if (IS_ERR(cxlr)) + return cxlr; + + if (device_attach(&cxlr->dev) <= 0) { + dev_err(&cxlr->dev, "failed to create region\n"); + drop_region(cxlr); + return ERR_PTR(-ENODEV); + } + return cxlr; } +EXPORT_SYMBOL_NS_GPL(cxl_create_region, CXL); int cxl_add_to_region(struct cxl_port *root, struct cxl_endpoint_decoder *cxled) { diff --git a/include/linux/cxlmem.h b/include/linux/cxlmem.h index caf1cd86421c..fc963c2c2dc4 100644 --- a/include/linux/cxlmem.h +++ b/include/linux/cxlmem.h @@ -875,4 +875,8 @@ struct cxl_endpoint_decoder *cxl_request_dpa(struct cxl_port *endpoint, resource_size_t min, resource_size_t max); int cxl_dpa_free(struct cxl_endpoint_decoder *cxled); +struct cxl_region *cxl_create_region(struct cxl_root_decoder *cxlrd, + struct cxl_endpoint_decoder **cxled, + int ways); + #endif /* __CXL_MEM_H__ */ diff --git a/tools/testing/cxl/type2/pci_type2.c b/tools/testing/cxl/type2/pci_type2.c index 6499d709f54d..0e7f17c0c920 100644 --- a/tools/testing/cxl/type2/pci_type2.c +++ b/tools/testing/cxl/type2/pci_type2.c @@ -4,8 +4,10 @@ #include #include +struct cxl_region_params *region_params; struct cxl_endpoint_decoder *cxled; struct cxl_root_decoder *cxlrd; +struct cxl_region *efx_region; struct cxl_dev_state *cxlds; struct cxl_memdev *cxlmd; struct cxl_port *endpoint; @@ -109,6 +111,22 @@ static int type2_pci_probe(struct pci_dev *pci_dev, goto out; } + pci_info(pci_dev, "cxl create_region..."); + efx_region = cxl_create_region(cxlrd, &cxled, 1); + if (!efx_region) { + rc = PTR_ERR(cxled); + goto out_dpa; + } + + region_params = &efx_region->params; + pci_info(pci_dev, "CXL region: start=%llx, end=%llx\n", region_params->res->start, + region_params->res->end); + + cxl_release_endpoint(cxlmd, endpoint); + return 0; + +out_dpa: + cxl_dpa_free(cxled); out: cxl_release_endpoint(cxlmd, endpoint); From patchwork Thu May 16 08:12:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Lucero Palau X-Patchwork-Id: 13665843 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2050.outbound.protection.outlook.com [40.107.92.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF4A16D1AF for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2024 08:12:29.9036 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 77d4dac0-a24e-4b9c-5d18-08dc757fee53 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6907 From: Alejandro Lucero By definition a type2 cxl device will use the host managed memory for specific functionality, therefore it should not be available to other uses. Signed-off-by: Alejandro Lucero --- drivers/cxl/core/region.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 014684ff4343..0716c2b8d456 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -3485,6 +3485,9 @@ static int cxl_region_probe(struct device *dev) case CXL_DECODER_PMEM: return devm_cxl_add_pmem_region(cxlr); case CXL_DECODER_RAM: + if (cxlr->type != CXL_DECODER_HOSTONLYMEM) + return 0; + /* * The region can not be manged by CXL if any portion of * it is already online as 'System RAM' From patchwork Thu May 16 08:12:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Lucero Palau X-Patchwork-Id: 13665838 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2073.outbound.protection.outlook.com [40.107.94.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 158E87829C for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2024 08:12:30.7843 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 74b1d7b1-ab02-41af-bf6e-08dc757feed9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044AB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8045 From: Alejandro Lucero Based on the cxl region allocated, map it internally and do a write and read to a random offset. Signed-off-by: Alejandro Lucero --- tools/testing/cxl/type2/pci_type2.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/tools/testing/cxl/type2/pci_type2.c b/tools/testing/cxl/type2/pci_type2.c index 0e7f17c0c920..4bd71e444ab4 100644 --- a/tools/testing/cxl/type2/pci_type2.c +++ b/tools/testing/cxl/type2/pci_type2.c @@ -4,6 +4,7 @@ #include #include +void __iomem *ctpio_cxl = NULL, *ctpio_target = NULL; struct cxl_region_params *region_params; struct cxl_endpoint_decoder *cxled; struct cxl_root_decoder *cxlrd; @@ -20,6 +21,8 @@ static int type2_pci_probe(struct pci_dev *pci_dev, { struct cxl_register_map map; resource_size_t max = 0; + u32 data_read; + u32 offset; u16 dvsec; int rc; @@ -122,6 +125,28 @@ static int type2_pci_probe(struct pci_dev *pci_dev, pci_info(pci_dev, "CXL region: start=%llx, end=%llx\n", region_params->res->start, region_params->res->end); + ctpio_cxl = ioremap(region_params->res->start, region_params->res->end - + region_params->res->start); + if (!ctpio_cxl) { + printk("%s: ioremap failed\n", __func__); + } else { + printk("%s: ioremap OK. ctpio_cxl=%p\n", __func__, ctpio_cxl); + } + + get_random_bytes(&offset, sizeof(offset)); + + offset &= (CXL_TYPE2_MEM_SIZE - 1); + offset &= ~0xf; + ctpio_target = ctpio_cxl + offset; + printk("%s: ctpio_target=%p\n", __func__, ctpio_target); + + *(uint32_t *)ctpio_target = 0xdeadbeef; + + data_read = 0; + data_read = *(uint32_t *)ctpio_target; + + printk("%s: ctpio_target=%p read back, %08x\n", __func__, ctpio_target, data_read); + cxl_release_endpoint(cxlmd, endpoint); return 0; @@ -135,6 +160,7 @@ static int type2_pci_probe(struct pci_dev *pci_dev, static void type2_pci_remove(struct pci_dev *pci_dev) { + iounmap(ctpio_cxl); cxl_dpa_free(cxled); }