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Smith" Subject: [PATCH v10 01/14] xen/riscv: disable unnecessary configs Date: Fri, 17 May 2024 15:54:50 +0200 Message-ID: <9924f75e0173813a654db4805301995a3af41abb.1715952103.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Disables unnecessary configs for two cases: 1. By utilizing EXTRA_FIXED_RANDCONFIG for randconfig builds (GitLab CI jobs). 2. By using tiny64_defconfig for non-randconfig builds. Only configs which lead to compilation issues were disabled. Remove lines related to disablement of configs which aren't affected compilation: -# CONFIG_SCHED_CREDIT is not set -# CONFIG_SCHED_RTDS is not set -# CONFIG_SCHED_NULL is not set -# CONFIG_SCHED_ARINC653 is not set -# CONFIG_TRACEBUFFER is not set -# CONFIG_HYPFS is not set -# CONFIG_SPECULATIVE_HARDEN_ARRAY is not set To allow CONFIG_ARGO build happy it was included to as ARGO requires p2m_type_t ( p2m_ram_rw ) and declaration of check_get_page_from_gfn() from xen/p2m-common.h. Also, it was included to asm/p2m.h as after the latter was included to the compilation error that EINVAL, EOPNOTSUPP aren't declared started to occur. CONFIG_XSM=n as it requires an introduction of: * boot_module_find_by_kind() * BOOTMOD_XSM * struct bootmodule * copy_from_paddr() The mentioned things aren't introduced now. CPU_BOOT_TIME_CPUPOOLS requires an introduction of cpu_physical_id() and acpi_disabled, so it is disabled for now. PERF_COUNTERS requires asm/perf.h and asm/perfc-defn.h, so it is also disabled for now, as RISC-V hasn't introduced this headers yet. LIVEPATCH isn't ready for RISC-V too and it can be overriden by randconfig, so to avoid compilation errors for randconfig it is disabled for now. Signed-off-by: Oleksii Kurochko --- Changes in V10: - Nothing changed. Only rebase. --- Changes in V9: - update the commit message: add info about LIVEPATCH and PERF_COUNTERS. --- Changes in V8: - disabled CPU_BOOT_TIME_CPUPOOLS as it requires an introduction of cpu_physical_id() and acpi_disabled. - leave XSM disabled, add explanation in the commit message. - drop HYPFS as the patch was provided to resolve compilation issue when this condif is enabled for RISC-V. - include asm/p2m.h to asm/domain.h, and xen/errno.h to asm/p2m.h to drop ARGO config from tiny64_defconfing and build.yaml. - update the commit message. --- Changes in V7: - Disable only configs which cause compilation issues. - Update the commit message. --- Changes in V6: - Nothing changed. Only rebase. --- Changes in V5: - Rebase and drop duplicated configs in EXTRA_FIXED_RANDCONFIG list - Update the commit message --- Changes in V4: - Nothing changed. Only rebase --- Changes in V3: - Remove EXTRA_FIXED_RANDCONFIG for non-randconfig jobs. For non-randconfig jobs, it is sufficient to disable configs by using the defconfig. - Remove double blank lines in build.yaml file before archlinux-current-gcc-riscv64-debug --- Changes in V2: - update the commit message. - remove xen/arch/riscv/Kconfig changes. --- automation/gitlab-ci/build.yaml | 4 ++++ xen/arch/riscv/configs/tiny64_defconfig | 12 +++++------- xen/arch/riscv/include/asm/domain.h | 2 ++ xen/arch/riscv/include/asm/p2m.h | 2 ++ 4 files changed, 13 insertions(+), 7 deletions(-) diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml index 49d6265ad5..ff5c9055d1 100644 --- a/automation/gitlab-ci/build.yaml +++ b/automation/gitlab-ci/build.yaml @@ -494,10 +494,14 @@ alpine-3.18-gcc-debug-arm64-earlyprintk: .riscv-fixed-randconfig: variables: &riscv-fixed-randconfig EXTRA_FIXED_RANDCONFIG: | + CONFIG_BOOT_TIME_CPUPOOLS=n CONFIG_COVERAGE=n CONFIG_EXPERT=y CONFIG_GRANT_TABLE=n CONFIG_MEM_ACCESS=n + CONFIG_PERF_COUNTERS=n + CONFIG_LIVEPATCH=n + CONFIG_XSM=n archlinux-current-gcc-riscv64: extends: .gcc-riscv64-cross-build diff --git a/xen/arch/riscv/configs/tiny64_defconfig b/xen/arch/riscv/configs/tiny64_defconfig index 09defe236b..fc7a04872f 100644 --- a/xen/arch/riscv/configs/tiny64_defconfig +++ b/xen/arch/riscv/configs/tiny64_defconfig @@ -1,12 +1,10 @@ -# CONFIG_SCHED_CREDIT is not set -# CONFIG_SCHED_RTDS is not set -# CONFIG_SCHED_NULL is not set -# CONFIG_SCHED_ARINC653 is not set -# CONFIG_TRACEBUFFER is not set -# CONFIG_HYPFS is not set +# CONFIG_BOOT_TIME_CPUPOOLS is not set # CONFIG_GRANT_TABLE is not set -# CONFIG_SPECULATIVE_HARDEN_ARRAY is not set # CONFIG_MEM_ACCESS is not set +# CONFIG_PERF_COUNTERS is not set +# CONFIG_COVERAGE is not set +# CONFIG_LIVEPATCH is not set +# CONFIG_XSM is not set CONFIG_RISCV_64=y CONFIG_DEBUG=y diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/asm/domain.h index 027bfa8a93..16a9dd57aa 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -5,6 +5,8 @@ #include #include +#include + struct hvm_domain { uint64_t params[HVM_NR_PARAMS]; diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/p2m.h index 387f372b5d..26860c0ae7 100644 --- a/xen/arch/riscv/include/asm/p2m.h +++ b/xen/arch/riscv/include/asm/p2m.h @@ -2,6 +2,8 @@ #ifndef __ASM_RISCV_P2M_H__ #define __ASM_RISCV_P2M_H__ +#include + #include #define paddr_bits PADDR_BITS From patchwork Fri May 17 13:54:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13667029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 643C0C04FFE for ; Fri, 17 May 2024 13:55:23 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.724180.1129368 (Exim 4.92) (envelope-from ) id 1s7y3E-0001zh-Kt; Fri, 17 May 2024 13:55:12 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 724180.1129368; Fri, 17 May 2024 13:55:12 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3E-0001yl-Dk; Fri, 17 May 2024 13:55:12 +0000 Received: by outflank-mailman (input) for mailman id 724180; Fri, 17 May 2024 13:55:11 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3D-0001cB-3M for xen-devel@lists.xenproject.org; Fri, 17 May 2024 13:55:11 +0000 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [2a00:1450:4864:20::132]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 1341fefd-1455-11ef-909e-e314d9c70b13; Fri, 17 May 2024 15:55:10 +0200 (CEST) Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-52389c1308dso767289e87.3 for ; Fri, 17 May 2024 06:55:10 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a179c81b4sm1117456466b.113.2024.05.17.06.55.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 06:55:08 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 1341fefd-1455-11ef-909e-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715954109; x=1716558909; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=54376BKXaMRj0bU8DqMJL73bnzloZBB1RI+aKenu2eI=; b=gdP/4CI5TOgI/sY/pNh+WFS4+XybeGcT1WuN6QrFkaQ4JFfbQuBsbhCeZertfIEhV3 69LA4PywRqRIGyU3Cn8h8mSC5tgYJEG9SE0BloJoGtNVre7+LkqrJBAzLZoPonu8o9kZ XvDy96JtXu7gKGCLfSW65UblpDTvzUCGHCXj7+ou/D1z1Kb5IuUxR+0cNqWqxTPFOnhW XKIEI0Am24RD6pzMKN0c4kOFPB+TLyNpC4Sgpv/lvtaJnaP4+aAnuDgNfbyOYSB6ssJE 5vDs0wfBh+OIAoGtyzi9zP5IArq2qPwP8YYtRug4B+4KhPt0XfqMOS7x4xndQXQpR+8E 6TCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715954109; x=1716558909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=54376BKXaMRj0bU8DqMJL73bnzloZBB1RI+aKenu2eI=; b=Y/8Yp/59OpnUNW8pYT3D3QSE7fN7NNjLc9yXkUiZeYPeiCMari0sCEYLswm89steCB CBOfvGzPb8eTbAACd7Su08GrQ1D34WwMRUk/Ybreul9fCMGY4V4fJH0ov3lT62dpVrXi 1N2KDbeKWedse3cf99pJyPcNCcbFzr/7kSQCHhl95gddbVnBF9PL+MEHEHJKUaZvDiax hQIuAMAY845ftd2RBA1P2miGzMukWjRe1j1EnJG8mTRtT51VuOLPQLAnuIcunIy7evIo /n/SuiyZkdWUQRJaO8p57SlTJAoYJHkhHf2wTD3PDnTcsF3pDOId4J1G8cg6T17c3esK X4hw== X-Gm-Message-State: AOJu0YzBbBrhRZMSMP8OVOzAUBTZDM1cEy+MmcXAhfxL4tujukVvjlMj pR2YlZvy6FysaQ2xEB7wydPohuySEv8db5Xs27/apBlJ+JjgTiCmjg6RYTn7 X-Google-Smtp-Source: AGHT+IFTfWDRo3Tqa1PCPq1VbAzDPpfputSHVqpLpWWJ1xgDRzivP3CQXXKgxgm1Xq7uMSyW791i5A== X-Received: by 2002:a05:6512:2254:b0:523:294f:7fe6 with SMTP id 2adb3069b0e04-523294f806bmr11415779e87.44.1715954109015; Fri, 17 May 2024 06:55:09 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , =?utf-8?q?Roger_Pau_Monn?= =?utf-8?q?=C3=A9?= , Ross Lagerwall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , George Dunlap , Jan Beulich , Shawn Anastasio Subject: [PATCH v10 02/14] xen: introduce generic non-atomic test_*bit() Date: Fri, 17 May 2024 15:54:51 +0200 Message-ID: <219df9d840a183fc55de02aff011c0972a68587c.1715952103.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 The following generic functions were introduced: * test_bit * generic__test_and_set_bit * generic__test_and_clear_bit * generic__test_and_change_bit These functions and macros can be useful for architectures that don't have corresponding arch-specific instructions. Also, the patch introduces the following generics which are used by the functions mentioned above: * BITOP_BITS_PER_WORD * BITOP_MASK * BITOP_WORD * BITOP_TYPE The following approach was chosen for generic*() and arch*() bit operation functions: If the bit operation function that is going to be generic starts with the prefix "__", then the corresponding generic/arch function will also contain the "__" prefix. For example: * test_bit() will be defined using arch_test_bit() and generic_test_bit(). * __test_and_set_bit() will be defined using arch__test_and_set_bit() and generic__test_and_set_bit(). Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- The context ("* Find First Set bit. Bits are labelled from 1." in xen/bitops.h ) suggests there's a dependency on an uncommitted patch. It happens becuase the current patch series is based on Andrew's patch series ( https://lore.kernel.org/xen-devel/20240313172716.2325427-1-andrew.cooper3@citrix.com/T/#t ), but if everything is okay with the current one patch it can be merged without Andrew's patch series being merged. --- Changes in V10: - update the commit message. ( re-order paragraphs and add explanation usage of prefix "__" in bit operation function names ) - add parentheses around the whole expression of bitop_bad_size() macros. - move macros bitop_bad_size() above asm/bitops.h as it is not arch-specific anymore and there is no need for overriding it. - drop macros check_bitop_size() and use "if ( bitop_bad_size(addr) ) __bitop_bad_size();" implictly where it is needed. - in use 'int' as a first parameter for __test_and_*(), generic__test_and_*() to be consistent with how the mentioned functions were declared in the original per-arch functions. - add 'const' to p variable in generic_test_bit(). - move definition of BITOP_BITS_PER_WORD and bitop_uint_t to xen/bitops.h as we don't allow for arch overrides these definitions anymore. --- Changes in V9: - move up xen/bitops.h in ppc/asm/page.h. - update defintion of arch_check_bitop_size. And drop correspondent macros from x86/asm/bitops.h - drop parentheses in generic__test_and_set_bit() for definition of local variable p. - fix indentation inside #ifndef BITOP_TYPE...#endif - update the commit message. --- Changes in V8: - drop __pure for function which uses volatile. - drop unnessary () in generic__test_and_change_bit() for addr casting. - update prototype of generic_test_bit() and test_bit(): now it returns bool instead of int. - update generic_test_bit() to use BITOP_MASK(). - Deal with fls{l} changes: it should be in the patch with introduced generic fls{l}. - add a footer with explanation of dependency on an uncommitted patch after Signed-off. - abstract bitop_size(). - move BITOP_TYPE define to . --- Changes in V7: - move everything to xen/bitops.h to follow the same approach for all generic bit ops. - put together BITOP_BITS_PER_WORD and bitops_uint_t. - make BITOP_MASK more generic. - drop #ifdef ... #endif around BITOP_MASK, BITOP_WORD as they are generic enough. - drop "_" for generic__{test_and_set_bit,...}(). - drop " != 0" for functions which return bool. - add volatile during the cast for generic__{...}(). - update the commit message. - update arch related code to follow the proposed generic approach. --- Changes in V6: - Nothing changed ( only rebase ) --- Changes in V5: - new patch --- xen/arch/arm/arm64/livepatch.c | 1 - xen/arch/arm/include/asm/bitops.h | 67 --------------- xen/arch/ppc/include/asm/bitops.h | 52 ------------ xen/arch/ppc/include/asm/page.h | 2 +- xen/arch/ppc/mm-radix.c | 2 +- xen/arch/x86/include/asm/bitops.h | 31 ++----- xen/include/xen/bitops.h | 131 ++++++++++++++++++++++++++++++ 7 files changed, 142 insertions(+), 144 deletions(-) diff --git a/xen/arch/arm/arm64/livepatch.c b/xen/arch/arm/arm64/livepatch.c index df2cebedde..4bc8ed9be5 100644 --- a/xen/arch/arm/arm64/livepatch.c +++ b/xen/arch/arm/arm64/livepatch.c @@ -10,7 +10,6 @@ #include #include -#include #include #include #include diff --git a/xen/arch/arm/include/asm/bitops.h b/xen/arch/arm/include/asm/bitops.h index 5104334e48..8e16335e76 100644 --- a/xen/arch/arm/include/asm/bitops.h +++ b/xen/arch/arm/include/asm/bitops.h @@ -22,9 +22,6 @@ #define __set_bit(n,p) set_bit(n,p) #define __clear_bit(n,p) clear_bit(n,p) -#define BITOP_BITS_PER_WORD 32 -#define BITOP_MASK(nr) (1UL << ((nr) % BITOP_BITS_PER_WORD)) -#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) #define BITS_PER_BYTE 8 #define ADDR (*(volatile int *) addr) @@ -76,70 +73,6 @@ bool test_and_change_bit_timeout(int nr, volatile void *p, bool clear_mask16_timeout(uint16_t mask, volatile void *p, unsigned int max_try); -/** - * __test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_set_bit(int nr, volatile void *addr) -{ - unsigned int mask = BITOP_MASK(nr); - volatile unsigned int *p = - ((volatile unsigned int *)addr) + BITOP_WORD(nr); - unsigned int old = *p; - - *p = old | mask; - return (old & mask) != 0; -} - -/** - * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned int mask = BITOP_MASK(nr); - volatile unsigned int *p = - ((volatile unsigned int *)addr) + BITOP_WORD(nr); - unsigned int old = *p; - - *p = old & ~mask; - return (old & mask) != 0; -} - -/* WARNING: non atomic and it can be reordered! */ -static inline int __test_and_change_bit(int nr, - volatile void *addr) -{ - unsigned int mask = BITOP_MASK(nr); - volatile unsigned int *p = - ((volatile unsigned int *)addr) + BITOP_WORD(nr); - unsigned int old = *p; - - *p = old ^ mask; - return (old & mask) != 0; -} - -/** - * test_bit - Determine whether a bit is set - * @nr: bit number to test - * @addr: Address to start counting from - */ -static inline int test_bit(int nr, const volatile void *addr) -{ - const volatile unsigned int *p = (const volatile unsigned int *)addr; - return 1UL & (p[BITOP_WORD(nr)] >> (nr & (BITOP_BITS_PER_WORD-1))); -} - /* * On ARMv5 and above those functions can be implemented around * the clz instruction for much better code efficiency. diff --git a/xen/arch/ppc/include/asm/bitops.h b/xen/arch/ppc/include/asm/bitops.h index 20f7865358..049aa62b89 100644 --- a/xen/arch/ppc/include/asm/bitops.h +++ b/xen/arch/ppc/include/asm/bitops.h @@ -15,9 +15,6 @@ #define __set_bit(n, p) set_bit(n, p) #define __clear_bit(n, p) clear_bit(n, p) -#define BITOP_BITS_PER_WORD 32 -#define BITOP_MASK(nr) (1U << ((nr) % BITOP_BITS_PER_WORD)) -#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) #define BITS_PER_BYTE 8 /* PPC bit number conversion */ @@ -69,17 +66,6 @@ static inline void clear_bit(int nr, volatile void *addr) clear_bits(BITOP_MASK(nr), (volatile unsigned int *)addr + BITOP_WORD(nr)); } -/** - * test_bit - Determine whether a bit is set - * @nr: bit number to test - * @addr: Address to start counting from - */ -static inline int test_bit(int nr, const volatile void *addr) -{ - const volatile unsigned int *p = addr; - return 1 & (p[BITOP_WORD(nr)] >> (nr & (BITOP_BITS_PER_WORD - 1))); -} - static inline unsigned int test_and_clear_bits( unsigned int mask, volatile unsigned int *p) @@ -133,44 +119,6 @@ static inline int test_and_set_bit(unsigned int nr, volatile void *addr) (volatile unsigned int *)addr + BITOP_WORD(nr)) != 0; } -/** - * __test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_set_bit(int nr, volatile void *addr) -{ - unsigned int mask = BITOP_MASK(nr); - volatile unsigned int *p = (volatile unsigned int *)addr + BITOP_WORD(nr); - unsigned int old = *p; - - *p = old | mask; - return (old & mask) != 0; -} - -/** - * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned int mask = BITOP_MASK(nr); - volatile unsigned int *p = (volatile unsigned int *)addr + BITOP_WORD(nr); - unsigned int old = *p; - - *p = old & ~mask; - return (old & mask) != 0; -} - #define flsl(x) generic_flsl(x) #define fls(x) generic_fls(x) diff --git a/xen/arch/ppc/include/asm/page.h b/xen/arch/ppc/include/asm/page.h index 890e285051..6d4cd2611c 100644 --- a/xen/arch/ppc/include/asm/page.h +++ b/xen/arch/ppc/include/asm/page.h @@ -2,9 +2,9 @@ #ifndef _ASM_PPC_PAGE_H #define _ASM_PPC_PAGE_H +#include #include -#include #include #define PDE_VALID PPC_BIT(0) diff --git a/xen/arch/ppc/mm-radix.c b/xen/arch/ppc/mm-radix.c index ab5a10695c..9055730997 100644 --- a/xen/arch/ppc/mm-radix.c +++ b/xen/arch/ppc/mm-radix.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include #include #include #include #include -#include #include #include #include diff --git a/xen/arch/x86/include/asm/bitops.h b/xen/arch/x86/include/asm/bitops.h index dd439b69a0..23f09fdb7a 100644 --- a/xen/arch/x86/include/asm/bitops.h +++ b/xen/arch/x86/include/asm/bitops.h @@ -19,9 +19,6 @@ #define ADDR (*(volatile int *) addr) #define CONST_ADDR (*(const volatile int *) addr) -extern void __bitop_bad_size(void); -#define bitop_bad_size(addr) (sizeof(*(addr)) < 4) - /** * set_bit - Atomically set a bit in memory * @nr: the bit to set @@ -175,7 +172,7 @@ static inline int test_and_set_bit(int nr, volatile void *addr) }) /** - * __test_and_set_bit - Set a bit and return its old value + * arch__test_and_set_bit - Set a bit and return its old value * @nr: Bit to set * @addr: Address to count from * @@ -183,7 +180,7 @@ static inline int test_and_set_bit(int nr, volatile void *addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static inline int __test_and_set_bit(int nr, void *addr) +static inline int arch__test_and_set_bit(int nr, volatile void *addr) { int oldbit; @@ -194,10 +191,7 @@ static inline int __test_and_set_bit(int nr, void *addr) return oldbit; } -#define __test_and_set_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ - __test_and_set_bit(nr, addr); \ -}) +#define arch__test_and_set_bit arch__test_and_set_bit /** * test_and_clear_bit - Clear a bit and return its old value @@ -224,7 +218,7 @@ static inline int test_and_clear_bit(int nr, volatile void *addr) }) /** - * __test_and_clear_bit - Clear a bit and return its old value + * arch__test_and_clear_bit - Clear a bit and return its old value * @nr: Bit to set * @addr: Address to count from * @@ -232,7 +226,7 @@ static inline int test_and_clear_bit(int nr, volatile void *addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static inline int __test_and_clear_bit(int nr, void *addr) +static inline int arch__test_and_clear_bit(int nr, volatile void *addr) { int oldbit; @@ -243,13 +237,10 @@ static inline int __test_and_clear_bit(int nr, void *addr) return oldbit; } -#define __test_and_clear_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ - __test_and_clear_bit(nr, addr); \ -}) +#define arch__test_and_clear_bit arch__test_and_clear_bit /* WARNING: non atomic and it can be reordered! */ -static inline int __test_and_change_bit(int nr, void *addr) +static inline int arch__test_and_change_bit(int nr, volatile void *addr) { int oldbit; @@ -260,10 +251,7 @@ static inline int __test_and_change_bit(int nr, void *addr) return oldbit; } -#define __test_and_change_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ - __test_and_change_bit(nr, addr); \ -}) +#define arch__test_and_change_bit arch__test_and_change_bit /** * test_and_change_bit - Change a bit and return its new value @@ -307,8 +295,7 @@ static inline int variable_test_bit(int nr, const volatile void *addr) return oldbit; } -#define test_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ +#define arch_test_bit(nr, addr) ({ \ __builtin_constant_p(nr) ? \ constant_test_bit(nr, addr) : \ variable_test_bit(nr, addr); \ diff --git a/xen/include/xen/bitops.h b/xen/include/xen/bitops.h index f14ad0d33a..6eeeff0117 100644 --- a/xen/include/xen/bitops.h +++ b/xen/include/xen/bitops.h @@ -65,10 +65,141 @@ static inline int generic_flsl(unsigned long x) * scope */ +#define BITOP_BITS_PER_WORD 32 +typedef uint32_t bitop_uint_t; + +#define BITOP_MASK(nr) ((bitop_uint_t)1 << ((nr) % BITOP_BITS_PER_WORD)) + +#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) + +extern void __bitop_bad_size(void); + +#define bitop_bad_size(addr) (sizeof(*(addr)) < sizeof(bitop_uint_t)) + /* --------------------- Please tidy above here --------------------- */ #include +/** + * generic__test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +generic__test_and_set_bit(int nr, volatile void *addr) +{ + bitop_uint_t mask = BITOP_MASK(nr); + volatile bitop_uint_t *p = (volatile bitop_uint_t *)addr + BITOP_WORD(nr); + bitop_uint_t old = *p; + + *p = old | mask; + return (old & mask); +} + +/** + * generic__test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +generic__test_and_clear_bit(int nr, volatile void *addr) +{ + bitop_uint_t mask = BITOP_MASK(nr); + volatile bitop_uint_t *p = (volatile bitop_uint_t *)addr + BITOP_WORD(nr); + bitop_uint_t old = *p; + + *p = old & ~mask; + return (old & mask); +} + +/* WARNING: non atomic and it can be reordered! */ +static always_inline bool +generic__test_and_change_bit(int nr, volatile void *addr) +{ + bitop_uint_t mask = BITOP_MASK(nr); + volatile bitop_uint_t *p = (volatile bitop_uint_t *)addr + BITOP_WORD(nr); + bitop_uint_t old = *p; + + *p = old ^ mask; + return (old & mask); +} +/** + * generic_test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + */ +static always_inline bool generic_test_bit(int nr, const volatile void *addr) +{ + bitop_uint_t mask = BITOP_MASK(nr); + const volatile bitop_uint_t *p = + (const volatile bitop_uint_t *)addr + BITOP_WORD(nr); + + return (*p & mask); +} + +static always_inline bool +__test_and_set_bit(int nr, volatile void *addr) +{ +#ifndef arch__test_and_set_bit +#define arch__test_and_set_bit generic__test_and_set_bit +#endif + + return arch__test_and_set_bit(nr, addr); +} +#define __test_and_set_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + __test_and_set_bit(nr, addr); \ +}) + +static always_inline bool +__test_and_clear_bit(int nr, volatile void *addr) +{ +#ifndef arch__test_and_clear_bit +#define arch__test_and_clear_bit generic__test_and_clear_bit +#endif + + return arch__test_and_clear_bit(nr, addr); +} +#define __test_and_clear_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + __test_and_clear_bit(nr, addr); \ +}) + +static always_inline bool +__test_and_change_bit(int nr, volatile void *addr) +{ +#ifndef arch__test_and_change_bit +#define arch__test_and_change_bit generic__test_and_change_bit +#endif + + return arch__test_and_change_bit(nr, addr); +} +#define __test_and_change_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + __test_and_change_bit(nr, addr); \ +}) + +static always_inline bool test_bit(int nr, const volatile void *addr) +{ +#ifndef arch_test_bit +#define arch_test_bit generic_test_bit +#endif + + return arch_test_bit(nr, addr); +} +#define test_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + test_bit(nr, addr); \ +}) + /* * Find First Set bit. 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a179c81b4sm1117456466b.113.2024.05.17.06.55.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 06:55:09 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 13be8d67-1455-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715954110; x=1716558910; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=woatuozuOyseeL4cnN4KyDezDGVt7DBVcd4a7zZ/GoA=; b=WdzIylq215iprKTArZcnSdkcdpYaKOtSS+C2mhpMFtBrV+GcbPnPf3PMmmjxPeC2Yu 4K+k8YXTpyYcjOAHkMMBNTKk9+Bk9PeKc1VXbgnkJYWIz7C+6lxzU+sOD8uuRZwOPI82 R4eMkGtSybEpuBw+caCMR2UHyp2OVdNnTNbK45fuExWA33CEtiCDqISm7ABaj0PEe79S OMrb3N9BMZeAOqZTR9PyUlBzkcMBtFJpjPPPb4bwI1I7I358jmTXXHuuPtjNWP8SItwA rbfB0hq5EYoLnZl8ubnsTaA6+BAFefYeOWZVcu5uecM/zvJ5x15BRFsk4LD6Yc5yq7W4 TdUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715954110; x=1716558910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=woatuozuOyseeL4cnN4KyDezDGVt7DBVcd4a7zZ/GoA=; b=SNBogpROmET7WwsdeRG7rEQeQd1kR6BzS1vwOgRjrQ3cyUSBSNbIYoAvXg1X0RrTXj SzxBTWedRYrm7zVn4DuWgckYM3ExL/iWmKsz1TgaEDjOHrzg9MCHs2EuRvCBiQ4+mV4h l+7IN53BrKlSWBmiGbOcqY7uD6J+ugrTBc1Ub59k3JaGzkrC9AeM8EPHzCUGas76dPiD BR2GufdBlvR7L1U4SA5BBL06boHhIb5cOogJJmkGtVXd+deCwyZUcvhduLbC7qysjktg b75yV2Vw7gp5uu8Q0694JeS/xh3ow+xvasEthwiudA2I7CDaOx4ZG2s++fVhVnl66C11 uilQ== X-Gm-Message-State: AOJu0YxFDJs4oGgndC7ItssMbvnuWgefuENZJ5rplRH9Arz+6uLA4Z4e tbtkrLVjSZC4Nqc0gelrGFZqylqTXbCeMkIP/NqBs3Bo8ii/WI1p62VtU7cL X-Google-Smtp-Source: AGHT+IHsehvx8pqw/g9Quv5gEW1QWWYdyQ7L1VBT233xZ+7+m0DFfBk+bO2yECVK8fjtIZ1/kLvG1A== X-Received: by 2002:a17:906:2746:b0:a5a:84f9:df73 with SMTP id a640c23a62f3a-a5a84f9dfd2mr736182166b.38.1715954110155; Fri, 17 May 2024 06:55:10 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , George Dunlap , Jan Beulich , Shawn Anastasio , =?utf-8?q?Roger_Pau_Mon?= =?utf-8?q?n=C3=A9?= Subject: [PATCH v10 03/14] xen/bitops: implement fls{l}() in common logic Date: Fri, 17 May 2024 15:54:52 +0200 Message-ID: <43df611d1c7b7ac16b181fb819f5d886daa31bad.1715952103.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 To avoid the compilation error below, it is needed to update to places in common/page_alloc.c where flsl() is used as now flsl() returns unsigned int: ./include/xen/kernel.h:18:21: error: comparison of distinct pointer types lacks a cast [-Werror] 18 | (void) (&_x == &_y); \ | ^~ common/page_alloc.c:1843:34: note: in expansion of macro 'min' 1843 | unsigned int inc_order = min(MAX_ORDER, flsl(e - s) - 1); generic_fls{l} was used instead of __builtin_clz{l}(x) as if x is 0, the result in undefined. The prototype of the per-architecture fls{l}() functions was changed to return 'unsigned int' to align with the generic implementation of these functions and avoid introducing signed/unsigned mismatches. Signed-off-by: Oleksii Kurochko --- The patch is almost independent from Andrew's patch series ( https://lore.kernel.org/xen-devel/20240313172716.2325427-1-andrew.cooper3@citrix.com/T/#t) except test_fls() function which IMO can be merged as a separate patch after Andrew's patch will be fully ready. --- Changes in V10: - update return type of arch_flsl() across arcitectures to 'unsigned int' to be aligned with return type of generic flsl() in xen/bitops.h. - switch inline to always_inline for arch_flsl() across architectures to be in sync with other similar changes. - define arch_flsl as arch_fls not just only fls. - update the commit message ( add information that per-arch fls{l)() protypes were changed ). --- Changes in V9: - update return type of fls and flsl() to unsigned int to be aligned with other bit ops. - update places where return value of fls() and flsl() is compared with int. - update the commit message. --- Changes in V8: - do proper rebase: back definition of fls{l} to the current patch. - drop the changes which removed ffz() in PPC. it should be done not in this patch. - add a message after Signed-off. --- Changes in V7: - Code style fixes --- Changes in V6: - new patch for the patch series. --- xen/arch/arm/include/asm/arm32/bitops.h | 2 +- xen/arch/arm/include/asm/arm64/bitops.h | 6 ++---- xen/arch/arm/include/asm/bitops.h | 9 +++------ xen/arch/ppc/include/asm/bitops.h | 3 --- xen/arch/x86/include/asm/bitops.h | 12 +++++++----- xen/common/bitops.c | 22 ++++++++++++++++++++++ xen/common/page_alloc.c | 4 ++-- xen/include/xen/bitops.h | 24 ++++++++++++++++++++++++ 8 files changed, 61 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/bitops.h b/xen/arch/arm/include/asm/arm32/bitops.h index d0309d47c1..9ee96f568b 100644 --- a/xen/arch/arm/include/asm/arm32/bitops.h +++ b/xen/arch/arm/include/asm/arm32/bitops.h @@ -1,7 +1,7 @@ #ifndef _ARM_ARM32_BITOPS_H #define _ARM_ARM32_BITOPS_H -#define flsl fls +#define arch_flsl arch_fls /* * Little endian assembly bitops. nr = 0 -> byte 0 bit 0. diff --git a/xen/arch/arm/include/asm/arm64/bitops.h b/xen/arch/arm/include/asm/arm64/bitops.h index 906d84e5f2..d942077392 100644 --- a/xen/arch/arm/include/asm/arm64/bitops.h +++ b/xen/arch/arm/include/asm/arm64/bitops.h @@ -1,17 +1,15 @@ #ifndef _ARM_ARM64_BITOPS_H #define _ARM_ARM64_BITOPS_H -static inline int flsl(unsigned long x) +static always_inline unsigned int arch_flsl(unsigned long x) { uint64_t ret; - if (__builtin_constant_p(x)) - return generic_flsl(x); - asm("clz\t%0, %1" : "=r" (ret) : "r" (x)); return BITS_PER_LONG - ret; } +#define arch_flsl arch_flsl /* Based on linux/include/asm-generic/bitops/find.h */ diff --git a/xen/arch/arm/include/asm/bitops.h b/xen/arch/arm/include/asm/bitops.h index 8e16335e76..f428cf8338 100644 --- a/xen/arch/arm/include/asm/bitops.h +++ b/xen/arch/arm/include/asm/bitops.h @@ -78,17 +78,14 @@ bool clear_mask16_timeout(uint16_t mask, volatile void *p, * the clz instruction for much better code efficiency. */ -static inline int fls(unsigned int x) +static always_inline unsigned int arch_fls(unsigned int x) { - int ret; - - if (__builtin_constant_p(x)) - return generic_fls(x); + unsigned int ret; asm("clz\t%"__OP32"0, %"__OP32"1" : "=r" (ret) : "r" (x)); return 32 - ret; } - +#define arch_fls arch_fls #define arch_ffs(x) ({ unsigned int __t = (x); fls(ISOLATE_LSB(__t)); }) #define arch_ffsl(x) ({ unsigned long __t = (x); flsl(ISOLATE_LSB(__t)); }) diff --git a/xen/arch/ppc/include/asm/bitops.h b/xen/arch/ppc/include/asm/bitops.h index 049aa62b89..46154fc957 100644 --- a/xen/arch/ppc/include/asm/bitops.h +++ b/xen/arch/ppc/include/asm/bitops.h @@ -119,9 +119,6 @@ static inline int test_and_set_bit(unsigned int nr, volatile void *addr) (volatile unsigned int *)addr + BITOP_WORD(nr)) != 0; } -#define flsl(x) generic_flsl(x) -#define fls(x) generic_fls(x) - /** * hweightN - returns the hamming weight of a N-bit word * @x: the word to weigh diff --git a/xen/arch/x86/include/asm/bitops.h b/xen/arch/x86/include/asm/bitops.h index 23f09fdb7a..17849fae97 100644 --- a/xen/arch/x86/include/asm/bitops.h +++ b/xen/arch/x86/include/asm/bitops.h @@ -425,20 +425,21 @@ static always_inline unsigned int arch_ffsl(unsigned long x) * * This is defined the same way as ffs. */ -static inline int flsl(unsigned long x) +static always_inline unsigned int arch_flsl(unsigned long x) { - long r; + unsigned long r; asm ( "bsr %1,%0\n\t" "jnz 1f\n\t" "mov $-1,%0\n" "1:" : "=r" (r) : "rm" (x)); - return (int)r+1; + return (unsigned int)r+1; } +#define arch_flsl arch_flsl -static inline int fls(unsigned int x) +static always_inline unsigned int arch_fls(unsigned int x) { - int r; + unsigned int r; asm ( "bsr %1,%0\n\t" "jnz 1f\n\t" @@ -446,6 +447,7 @@ static inline int fls(unsigned int x) "1:" : "=r" (r) : "rm" (x)); return r + 1; } +#define arch_fls arch_fls /** * hweightN - returns the hamming weight of a N-bit word diff --git a/xen/common/bitops.c b/xen/common/bitops.c index a8c32f6767..95bc47176b 100644 --- a/xen/common/bitops.c +++ b/xen/common/bitops.c @@ -62,9 +62,31 @@ static void test_ffs(void) CHECK(ffs64, (uint64_t)0x8000000000000000, 64); } +static void test_fls(void) +{ + /* unsigned int ffs(unsigned int) */ + CHECK(fls, 1, 1); + CHECK(fls, 3, 2); + CHECK(fls, 3U << 30, 32); + + /* unsigned int flsl(unsigned long) */ + CHECK(flsl, 1, 1); + CHECK(flsl, 1UL << (BITS_PER_LONG - 1), BITS_PER_LONG); +#if BITS_PER_LONG > 32 + CHECK(flsl, 3UL << 32, 34); +#endif + + /* unsigned int fls64(uint64_t) */ + CHECK(fls64, 1, 1); + CHECK(fls64, 0x00000000C0000000ULL, 32); + CHECK(fls64, 0x0000000180000000ULL, 33); + CHECK(fls64, 0xC000000000000000ULL, 64); +} + static int __init cf_check test_bitops(void) { test_ffs(); + test_fls(); return 0; } diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index be4ba3962a..eed6b2a901 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -1842,7 +1842,7 @@ static void _init_heap_pages(const struct page_info *pg, * Note that the value of ffsl() and flsl() starts from 1 so we need * to decrement it by 1. */ - unsigned int inc_order = min(MAX_ORDER, flsl(e - s) - 1); + unsigned int inc_order = min(MAX_ORDER + 0U, flsl(e - s) - 1); if ( s ) inc_order = min(inc_order, ffsl(s) - 1U); @@ -2266,7 +2266,7 @@ void __init xenheap_max_mfn(unsigned long mfn) ASSERT(!first_node_initialised); ASSERT(!xenheap_bits); BUILD_BUG_ON((PADDR_BITS - PAGE_SHIFT) >= BITS_PER_LONG); - xenheap_bits = min(flsl(mfn + 1) - 1 + PAGE_SHIFT, PADDR_BITS); + xenheap_bits = min(flsl(mfn + 1) - 1 + PAGE_SHIFT, PADDR_BITS + 0U); printk(XENLOG_INFO "Xen heap: %u bits\n", xenheap_bits); } diff --git a/xen/include/xen/bitops.h b/xen/include/xen/bitops.h index 6eeeff0117..59b8028894 100644 --- a/xen/include/xen/bitops.h +++ b/xen/include/xen/bitops.h @@ -200,6 +200,30 @@ static always_inline bool test_bit(int nr, const volatile void *addr) test_bit(nr, addr); \ }) +static always_inline __pure unsigned int fls(unsigned int x) +{ + if ( __builtin_constant_p(x) ) + return generic_fls(x); + +#ifndef arch_fls +#define arch_fls generic_fls +#endif + + return arch_fls(x); +} + +static always_inline __pure unsigned int flsl(unsigned long x) +{ + if ( __builtin_constant_p(x) ) + return generic_flsl(x); + +#ifndef arch_flsl +#define arch_flsl generic_flsl +#endif + + return arch_flsl(x); +} + /* * Find First Set bit. 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Fri, 17 May 2024 06:55:11 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v10 04/14] xen/riscv: introduce bitops.h Date: Fri, 17 May 2024 15:54:53 +0200 Message-ID: <91a359cb03c150ca01b52bfcab696612a847d283.1715952103.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Taken from Linux-6.4.0-rc1 Xen's bitops.h consists of several Linux's headers: * linux/arch/include/asm/bitops.h: * The following function were removed as they aren't used in Xen: * test_and_set_bit_lock * clear_bit_unlock * __clear_bit_unlock * The following functions were renamed in the way how they are used by common code: * __test_and_set_bit * __test_and_clear_bit * The declaration and implementation of the following functios were updated to make Xen build happy: * clear_bit * set_bit * __test_and_clear_bit * __test_and_set_bit Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V10: - update the error message BITS_PER_LONG -> BITOP_BITS_PER_WORD --- Changes in V9: - add Acked-by: Jan Beulich - drop redefinition of bitop_uint_t in asm/types.h as some operation in Xen common code expects to work with 32-bit quantities. - s/BITS_PER_LONG/BITOP_BITS_PER_WORD in asm/bitops.h around __AMO() macros. --- Changes in V8: - define bitop_uint_t in after the changes in patch related to introduction of "introduce generic non-atomic test_*bit()". - drop duplicated __set_bit() and __clear_bit(). - drop duplicated comment: /* Based on linux/arch/include/asm/bitops.h */. - update type of res and mask in test_and_op_bit_ord(): unsigned long -> bitop_uint_t. - drop 1 padding blank in test_and_op_bit_ord(). - update definition of test_and_set_bit(),test_and_clear_bit(),test_and_change_bit: change return type to bool. - change addr argument type of test_and_change_bit(): unsigned long * -> void *. - move test_and_change_bit() closer to other test_and-s function. - Code style fixes: tabs -> space. - s/#undef __op_bit/#undef op_bit. - update the commit message: delete information about generic-non-atomic.h changes as now it is a separate patch. --- Changes in V7: - Update the commit message. - Drop "__" for __op_bit and __op_bit_ord as they are atomic. - add comment above __set_bit and __clear_bit about why they are defined as atomic. - align bitops_uint_t with __AMO(). - make changes after generic non-atomic test_*bit() were changed. - s/__asm__ __volatile__/asm volatile --- Changes in V6: - rebase clean ups were done: drop unused asm-generic includes --- Changes in V5: - new patch --- xen/arch/riscv/include/asm/bitops.h | 137 ++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) create mode 100644 xen/arch/riscv/include/asm/bitops.h diff --git a/xen/arch/riscv/include/asm/bitops.h b/xen/arch/riscv/include/asm/bitops.h new file mode 100644 index 0000000000..7f7af3fda1 --- /dev/null +++ b/xen/arch/riscv/include/asm/bitops.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2012 Regents of the University of California */ + +#ifndef _ASM_RISCV_BITOPS_H +#define _ASM_RISCV_BITOPS_H + +#include + +#if BITOP_BITS_PER_WORD == 64 +#define __AMO(op) "amo" #op ".d" +#elif BITOP_BITS_PER_WORD == 32 +#define __AMO(op) "amo" #op ".w" +#else +#error "Unexpected BITOP_BITS_PER_WORD" +#endif + +/* Based on linux/arch/include/asm/bitops.h */ + +/* + * Non-atomic bit manipulation. + * + * Implemented using atomics to be interrupt safe. Could alternatively + * implement with local interrupt masking. + */ +#define __set_bit(n, p) set_bit(n, p) +#define __clear_bit(n, p) clear_bit(n, p) + +#define test_and_op_bit_ord(op, mod, nr, addr, ord) \ +({ \ + bitop_uint_t res, mask; \ + mask = BITOP_MASK(nr); \ + asm volatile ( \ + __AMO(op) #ord " %0, %2, %1" \ + : "=r" (res), "+A" (addr[BITOP_WORD(nr)]) \ + : "r" (mod(mask)) \ + : "memory"); \ + ((res & mask) != 0); \ +}) + +#define op_bit_ord(op, mod, nr, addr, ord) \ + asm volatile ( \ + __AMO(op) #ord " zero, %1, %0" \ + : "+A" (addr[BITOP_WORD(nr)]) \ + : "r" (mod(BITOP_MASK(nr))) \ + : "memory"); + +#define test_and_op_bit(op, mod, nr, addr) \ + test_and_op_bit_ord(op, mod, nr, addr, .aqrl) +#define op_bit(op, mod, nr, addr) \ + op_bit_ord(op, mod, nr, addr, ) + +/* Bitmask modifiers */ +#define NOP(x) (x) +#define NOT(x) (~(x)) + +/** + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + */ +static inline bool test_and_set_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr = p; + + return test_and_op_bit(or, NOP, nr, addr); +} + +/** + * test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + */ +static inline bool test_and_clear_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr = p; + + return test_and_op_bit(and, NOT, nr, addr); +} + +/** + * test_and_change_bit - Toggle (change) a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +static inline bool test_and_change_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr = p; + + return test_and_op_bit(xor, NOP, nr, addr); +} + +/** + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void set_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr = p; + + op_bit(or, NOP, nr, addr); +} + +/** + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + */ +static inline void clear_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr = p; + + op_bit(and, NOT, nr, addr); +} + +#undef test_and_op_bit +#undef op_bit +#undef NOP +#undef NOT +#undef __AMO + +#endif /* _ASM_RISCV_BITOPS_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri May 17 13:54:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13667032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD04CC25B7C for ; Fri, 17 May 2024 13:55:26 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.724183.1129397 (Exim 4.92) (envelope-from ) id 1s7y3H-0002fU-Rk; Fri, 17 May 2024 13:55:15 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 724183.1129397; Fri, 17 May 2024 13:55:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3H-0002bx-Gd; Fri, 17 May 2024 13:55:15 +0000 Received: by outflank-mailman (input) for mailman id 724183; Fri, 17 May 2024 13:55:14 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3G-0001cB-5R for xen-devel@lists.xenproject.org; Fri, 17 May 2024 13:55:14 +0000 Received: from mail-ed1-x529.google.com (mail-ed1-x529.google.com [2a00:1450:4864:20::529]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 150695c4-1455-11ef-909e-e314d9c70b13; Fri, 17 May 2024 15:55:13 +0200 (CEST) Received: by mail-ed1-x529.google.com with SMTP id 4fb4d7f45d1cf-572f6ee87c1so4572333a12.2 for ; Fri, 17 May 2024 06:55:13 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a179c81b4sm1117456466b.113.2024.05.17.06.55.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 06:55:11 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 150695c4-1455-11ef-909e-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715954112; x=1716558912; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dmyFXVNnt+hxL3zbiepowjxUxD57Pi8IWfGlJVjPZ2c=; b=HNhUOPj1KLI1pWjId5P8dNr1Yh2P/HvbmXQwAxKnf68YZtdtHxaxl7F7z640eEuwSA /gI3I5xyyJwvmfHWTw8e2/ZtJ9Ct8puVz1DAHUraKTuFz8wxm+LEQaaynSghtpOowlZR OIFS6j3AJ538vrq6Mscl3kAVdfiJGr3DnK52ykxiLMAgH3bGr5eu0NsfqKp6srK3wpSR LVBjTK5Q7TIDk643qxatkp6lVzr6sHZTguwr/cgaOR/lpAmVVDmatSEcEdY+5pyHHsaS YX9Tp6hiAAJBJqBuYa7OrOkLXuGfONJ9XduqA+OYINC9/9SIJAw4tjoMLLkj/XiVe+E3 ZfZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715954112; x=1716558912; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dmyFXVNnt+hxL3zbiepowjxUxD57Pi8IWfGlJVjPZ2c=; b=YalY2mKMe1qNAoT6/L6w5x6Uazx3vxfgNWE6EqNUNPqQLH3ZHayLsmlVozwMFCBU8L 2HgBel2Njs+b25i4aa3Jtwa56CfBR+qpzVhSEM4irf2wFVFsb5qm1EjAqoCqVglt8g0E Hju6WOr3syaxZ0h5QHC2BkDjHYcMWlnMKenNKx1JXbwJ3Q2vUGtA5GyCkkaOoUE35eSD bNAxntyytbSZ8UaYv3HTiYmUxSLNXBV7lDzmqTE6E44m4YMW01IBeMyrTrjQ/erbtosq yrhQ6Re42aa49n6sBvw3vsrk0qZ3AgN3eZUJV+WUGipTBRM1p5jkNG5Gnf5d72QbFHS3 HZhQ== X-Gm-Message-State: AOJu0Yy47P5Kj3wxMu61tt7MczzPsHZLlsknl6u9TZaUThPPTBs6xCOm ly65CFyWfprQBhP6dB4KUycH1rG7R/u+hRA5iopAg7+XwngwJUumfS7SgEv9 X-Google-Smtp-Source: AGHT+IGcyYgqw7vHA3eICyUNiTI1THyvqb+ALgLMhYDvqNtVqiPJ30pnF69tErln8kIe4xgeQcGPvg== X-Received: by 2002:a17:906:c2c7:b0:a59:beb2:62d7 with SMTP id a640c23a62f3a-a5a2d665449mr1453259066b.56.1715954111845; Fri, 17 May 2024 06:55:11 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v10 05/14] xen/riscv: introduce cmpxchg.h Date: Fri, 17 May 2024 15:54:54 +0200 Message-ID: <79303bd6ba08b8c3bad96cb4e47d46f61a42d081.1715952103.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 The header was taken from Linux kernl 6.4.0-rc1. Addionally, were updated: * add emulation of {cmp}xchg for 1/2 byte types using 32-bit atomic access. * replace tabs with spaces * replace __* variale with *__ * introduce generic version of xchg_* and cmpxchg_*. * drop {cmp}xchg{release,relaxed,acquire} as Xen doesn't use them * drop barries and use instruction suffixices instead ( .aq, .rl, .aqrl ) Implementation of 4- and 8-byte cases were updated according to the spec: ``` .... Linux Construct RVWMO AMO Mapping ... atomic amo.{w|d}.aqrl Linux Construct RVWMO LR/SC Mapping ... atomic loop: lr.{w|d}.aq; ; sc.{w|d}.aqrl; bnez loop Table A.5: Mappings from Linux memory primitives to RISC-V primitives ``` The current implementation is the same with 8e86f0b409a4 ("arm64: atomics: fix use of acquire + release for full barrier semantics") [1]. RISC-V could combine acquire and release into the SC instructions and it could reduce a fence instruction to gain better performance. Here is related description from RISC-V ISA 10.2 Load-Reserved/Store-Conditional Instructions: - .aq: The LR/SC sequence can be given acquire semantics by setting the aq bit on the LR instruction. - .rl: The LR/SC sequence can be given release semantics by setting the rl bit on the SC instruction. - .aqrl: Setting the aq bit on the LR instruction, and setting both the aq and the rl bit on the SC instruction makes the LR/SC sequence sequentially consistent, meaning that it cannot be reordered with earlier or later memory operations from the same hart. Software should not set the rl bit on an LR instruction unless the aq bit is also set, nor should software set the aq bit on an SC instruction unless the rl bit is also set. LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those with both bits clear, but may result in lower performance. Also, I way of transforming ".rl + full barrier" to ".aqrl" was approved by (the author of the RVWMO spec) [2] [1] https://patchwork.kernel.org/project/linux-arm-kernel/patch/1391516953-14541-1-git-send-email-will.deacon@arm.com/ [2] https://lore.kernel.org/linux-riscv/41e01514-74ca-84f2-f5cc-2645c444fd8e@nvidia.com/ Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V10: - Code style fixes for __xchg, __cmpxchg ( the line was too long ) - change type of size argument from int to unsigned int for __bad_{cmp}xchg(), __{cmp}xchg(). - drop parentheses around ptr in {cmp}xchg() when ptr is an argument of __{cmp}xchg(). - add Acked-by: Jan Beulich --- Changes in V9: - update return type of __bad_xchg(); - update the comment above __bad_cmpxchg(); - update the default case inside __xchg() to be aligned with similar default case in __cmpxchg(). --- Changes in V8: - use __bad_{xchg,cmpxch}(ptr,size) insetead of STATIC_ASSERT_UNREACHABLE() to make this patch be independent from the macros that haven't been committed yet and may never be. --- Changes in V7: - replace __*() -> _*() in cmpxchg.h - add () around ptr in _amoswap_generic(), emulate_xchg_1_2() - fix typos - code style fixes. - refactor emulate_xcgh_1_2(): - add parentheses for new argument. - use instead of constant 0x4 -> sizeof(*aligned_ptr). - add alignment_mask to save sizeof(*aligned_ptr) - sizeof(*(ptr)); - s/CONFIG_32BIT/CONFIG_RISCV_32 - drop unnecessary parentheses in xchg() - drop register in _generic_cmpxchg() - refactor and update prototype of _generic_cmpxchg(): add named operands, return value instead of passing ret as an argument, drop %z and J constraints for mask operand as it can't be zero - refactor and code style fixes in emulate_cmpxchg_1_2(): - add explanatory comment for emulate_cmpxchg_1_2(). - add parentheses for old and new arguments. - use instead of constant 0x4 -> sizeof(*aligned_ptr). - add alignment_mask to save sizeof(*aligned_ptr) - sizeof(*(ptr)); - drop unnessary parenthesses in cmpxchg(). - update the commit message. - s/__asm__ __volatile__/asm volatile --- Changes in V6: - update the commit message? ( As before I don't understand this point. Can you give an example of what sort of opcode / instruction is missing?) - Code style fixes - change sizeof(*ptr) -> sizeof(*(ptr)) - update operands names and some local variables for macros emulate_xchg_1_2() and emulate_cmpxchg_1_2() - drop {cmp}xchg_{relaxed,acquire,release) versions as they aren't needed for Xen - update __amoswap_generic() prototype and defintion: drop pre and post barries. - update emulate_xchg_1_2() prototype and definion: add lr_sfx, drop pre and post barries. - rename __xchg_generic to __xchg(), make __xchg as static inline function to be able to "#ifndef CONFIG_32BIT case 8:... " --- Changes in V5: - update the commit message. - drop ALIGN_DOWN(). - update the definition of emulate_xchg_1_2(): - lr.d -> lr.w, sc.d -> sc.w. - drop ret argument. - code style fixes around asm volatile. - update prototype. - use asm named operands. - rename local variables. - add comment above the macros - update the definition of __xchg_generic: - rename to __xchg() - transform it to static inline - code style fixes around switch() - update prototype. - redefine cmpxchg() - update emulate_cmpxchg_1_2(): - update prototype - update local variables names and usage of them - use name asm operands. - add comment above the macros - drop pre and post, and use .aq,.rl, .aqrl suffixes. - drop {cmp}xchg_{relaxed, aquire, release} as they are not used by Xen. - drop unnessary details in comment above emulate_cmpxchg_1_2() --- Changes in V4: - Code style fixes. - enforce in __xchg_*() has the same type for new and *ptr, also "\n" was removed at the end of asm instruction. - dependency from https://lore.kernel.org/xen-devel/cover.1706259490.git.federico.serafini@bugseng.com/ - switch from ASSERT_UNREACHABLE to STATIC_ASSERT_UNREACHABLE(). - drop xchg32(ptr, x) and xchg64(ptr, x) as they aren't used. - drop cmpxcg{32,64}_{local} as they aren't used. - introduce generic version of xchg_* and cmpxchg_*. - update the commit message. --- Changes in V3: - update the commit message - add emulation of {cmp}xchg_... for 1 and 2 bytes types --- Changes in V2: - update the comment at the top of the header. - change xen/lib.h to xen/bug.h. - sort inclusion of headers properly. --- xen/arch/riscv/include/asm/cmpxchg.h | 241 +++++++++++++++++++++++++++ xen/arch/riscv/include/asm/config.h | 2 + 2 files changed, 243 insertions(+) create mode 100644 xen/arch/riscv/include/asm/cmpxchg.h diff --git a/xen/arch/riscv/include/asm/cmpxchg.h b/xen/arch/riscv/include/asm/cmpxchg.h new file mode 100644 index 0000000000..38e241a4e5 --- /dev/null +++ b/xen/arch/riscv/include/asm/cmpxchg.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (C) 2014 Regents of the University of California */ + +#ifndef _ASM_RISCV_CMPXCHG_H +#define _ASM_RISCV_CMPXCHG_H + +#include +#include + +#include +#include +#include + +#define _amoswap_generic(ptr, new, ret, sfx) \ + asm volatile ( \ + " amoswap" sfx " %0, %2, %1" \ + : "=r" (ret), "+A" (*(ptr)) \ + : "r" (new) \ + : "memory" ); + +/* + * For LR and SC, the A extension requires that the address held in rs1 be + * naturally aligned to the size of the operand (i.e., eight-byte aligned + * for 64-bit words and four-byte aligned for 32-bit words). + * If the address is not naturally aligned, an address-misaligned exception + * or an access-fault exception will be generated. + * + * Thereby: + * - for 1-byte xchg access the containing word by clearing low two bits. + * - for 2-byte xchg access the containing word by clearing bit 1. + * + * If resulting 4-byte access is still misalgined, it will fault just as + * non-emulated 4-byte access would. + */ +#define emulate_xchg_1_2(ptr, new, lr_sfx, sc_sfx) \ +({ \ + uint32_t *aligned_ptr; \ + unsigned long alignment_mask = sizeof(*aligned_ptr) - sizeof(*(ptr)); \ + unsigned int new_val_bit = \ + ((unsigned long)(ptr) & alignment_mask) * BITS_PER_BYTE; \ + unsigned long mask = \ + GENMASK(((sizeof(*(ptr))) * BITS_PER_BYTE) - 1, 0) << new_val_bit; \ + unsigned int new_ = (new) << new_val_bit; \ + unsigned int old; \ + unsigned int scratch; \ + \ + aligned_ptr = (uint32_t *)((unsigned long)(ptr) & ~alignment_mask); \ + \ + asm volatile ( \ + "0: lr.w" lr_sfx " %[old], %[ptr_]\n" \ + " andn %[scratch], %[old], %[mask]\n" \ + " or %[scratch], %[scratch], %z[new_]\n" \ + " sc.w" sc_sfx " %[scratch], %[scratch], %[ptr_]\n" \ + " bnez %[scratch], 0b\n" \ + : [old] "=&r" (old), [scratch] "=&r" (scratch), \ + [ptr_] "+A" (*aligned_ptr) \ + : [new_] "rJ" (new_), [mask] "r" (mask) \ + : "memory" ); \ + \ + (__typeof__(*(ptr)))((old & mask) >> new_val_bit); \ +}) + +/* + * This function doesn't exist, so you'll get a linker error + * if something tries to do an invalid xchg(). + */ +extern unsigned long __bad_xchg(volatile void *ptr, unsigned int size); + +static always_inline unsigned long __xchg(volatile void *ptr, + unsigned long new, + unsigned int size) +{ + unsigned long ret; + + switch ( size ) + { + case 1: + ret = emulate_xchg_1_2((volatile uint8_t *)ptr, new, ".aq", ".aqrl"); + break; + case 2: + ret = emulate_xchg_1_2((volatile uint16_t *)ptr, new, ".aq", ".aqrl"); + break; + case 4: + _amoswap_generic((volatile uint32_t *)ptr, new, ret, ".w.aqrl"); + break; +#ifndef CONFIG_RISCV_32 + case 8: + _amoswap_generic((volatile uint64_t *)ptr, new, ret, ".d.aqrl"); + break; +#endif + default: + return __bad_xchg(ptr, size); + } + + return ret; +} + +#define xchg(ptr, x) \ +({ \ + __typeof__(*(ptr)) n_ = (x); \ + (__typeof__(*(ptr))) \ + __xchg(ptr, (unsigned long)n_, sizeof(*(ptr))); \ +}) + +#define _generic_cmpxchg(ptr, old, new, lr_sfx, sc_sfx) \ + ({ \ + unsigned int rc; \ + unsigned long ret; \ + unsigned long mask = GENMASK(((sizeof(*(ptr))) * BITS_PER_BYTE) - 1, 0); \ + asm volatile ( \ + "0: lr" lr_sfx " %[ret], %[ptr_]\n" \ + " and %[ret], %[ret], %[mask]\n" \ + " bne %[ret], %z[old_], 1f\n" \ + " sc" sc_sfx " %[rc], %z[new_], %[ptr_]\n" \ + " bnez %[rc], 0b\n" \ + "1:\n" \ + : [ret] "=&r" (ret), [rc] "=&r" (rc), [ptr_] "+A" (*ptr) \ + : [old_] "rJ" (old), [new_] "rJ" (new), [mask] "r" (mask) \ + : "memory" ); \ + ret; \ + }) + +/* + * For LR and SC, the A extension requires that the address held in rs1 be + * naturally aligned to the size of the operand (i.e., eight-byte aligned + * for 64-bit words and four-byte aligned for 32-bit words). + * If the address is not naturally aligned, an address-misaligned exception + * or an access-fault exception will be generated. + * + * Thereby: + * - for 1-byte xchg access the containing word by clearing low two bits + * - for 2-byte xchg ccess the containing word by clearing first bit. + * + * If resulting 4-byte access is still misalgined, it will fault just as + * non-emulated 4-byte access would. + * + * old_val was casted to unsigned long for cmpxchgptr() + */ +#define emulate_cmpxchg_1_2(ptr, old, new, lr_sfx, sc_sfx) \ +({ \ + uint32_t *aligned_ptr; \ + unsigned long alignment_mask = sizeof(*aligned_ptr) - sizeof(*(ptr)); \ + uint8_t new_val_bit = \ + ((unsigned long)(ptr) & alignment_mask) * BITS_PER_BYTE; \ + unsigned long mask = \ + GENMASK(((sizeof(*(ptr))) * BITS_PER_BYTE) - 1, 0) << new_val_bit; \ + unsigned int old_ = (old) << new_val_bit; \ + unsigned int new_ = (new) << new_val_bit; \ + unsigned int old_val; \ + unsigned int scratch; \ + \ + aligned_ptr = (uint32_t *)((unsigned long)ptr & ~alignment_mask); \ + \ + asm volatile ( \ + "0: lr.w" lr_sfx " %[scratch], %[ptr_]\n" \ + " and %[old_val], %[scratch], %[mask]\n" \ + " bne %[old_val], %z[old_], 1f\n" \ + /* the following line is an equivalent to: \ + * scratch = old_val & ~mask; \ + * And to elimanate one ( likely register ) input it was decided \ + * to use: \ + * scratch = old_val ^ scratch \ + */ \ + " xor %[scratch], %[old_val], %[scratch]\n" \ + " or %[scratch], %[scratch], %z[new_]\n" \ + " sc.w" sc_sfx " %[scratch], %[scratch], %[ptr_]\n" \ + " bnez %[scratch], 0b\n" \ + "1:\n" \ + : [old_val] "=&r" (old_val), [scratch] "=&r" (scratch), \ + [ptr_] "+A" (*aligned_ptr) \ + : [old_] "rJ" (old_), [new_] "rJ" (new_), \ + [mask] "r" (mask) \ + : "memory" ); \ + \ + (__typeof__(*(ptr)))((unsigned long)old_val >> new_val_bit); \ +}) + +/* + * This function doesn't exist, so you'll get a linker error + * if something tries to do an invalid cmpxchg(). + */ +extern unsigned long __bad_cmpxchg(volatile void *ptr, unsigned int size); + +/* + * Atomic compare and exchange. Compare OLD with MEM, if identical, + * store NEW in MEM. Return the initial value in MEM. Success is + * indicated by comparing RETURN with OLD. + */ +static always_inline unsigned long __cmpxchg(volatile void *ptr, + unsigned long old, + unsigned long new, + unsigned int size) +{ + unsigned long ret; + + switch ( size ) + { + case 1: + ret = emulate_cmpxchg_1_2((volatile uint8_t *)ptr, old, new, + ".aq", ".aqrl"); + break; + case 2: + ret = emulate_cmpxchg_1_2((volatile uint16_t *)ptr, old, new, + ".aq", ".aqrl"); + break; + case 4: + ret = _generic_cmpxchg((volatile uint32_t *)ptr, old, new, + ".w.aq", ".w.aqrl"); + break; +#ifndef CONFIG_32BIT + case 8: + ret = _generic_cmpxchg((volatile uint64_t *)ptr, old, new, + ".d.aq", ".d.aqrl"); + break; +#endif + default: + return __bad_cmpxchg(ptr, size); + } + + return ret; +} + +#define cmpxchg(ptr, o, n) \ +({ \ + __typeof__(*(ptr)) o_ = (o); \ + __typeof__(*(ptr)) n_ = (n); \ + (__typeof__(*(ptr))) \ + __cmpxchg(ptr, (unsigned long)o_, (unsigned long)n_, \ + sizeof(*(ptr))); \ +}) + +#endif /* _ASM_RISCV_CMPXCHG_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/riscv/include/asm/config.h b/xen/arch/riscv/include/asm/config.h index c5f93e6a01..50583aafdc 100644 --- a/xen/arch/riscv/include/asm/config.h +++ b/xen/arch/riscv/include/asm/config.h @@ -119,6 +119,8 @@ #define BITS_PER_LLONG 64 +#define BITS_PER_BYTE 8 + /* xen_ulong_t is always 64 bits */ #define BITS_PER_XEN_ULONG 64 From patchwork Fri May 17 13:54:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13667034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DD567C25B79 for ; Fri, 17 May 2024 13:55:28 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.724185.1129418 (Exim 4.92) (envelope-from ) id 1s7y3K-0003Lh-MG; Fri, 17 May 2024 13:55:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 724185.1129418; Fri, 17 May 2024 13:55:18 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3K-0003K5-Ea; Fri, 17 May 2024 13:55:18 +0000 Received: by outflank-mailman (input) for mailman id 724185; Fri, 17 May 2024 13:55:17 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3I-0001sq-Pp for xen-devel@lists.xenproject.org; Fri, 17 May 2024 13:55:16 +0000 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [2a00:1450:4864:20::633]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 15822ea0-1455-11ef-b4bb-af5377834399; Fri, 17 May 2024 15:55:13 +0200 (CEST) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-a5a7d28555bso515552566b.1 for ; Fri, 17 May 2024 06:55:13 -0700 (PDT) Received: from fedora.. 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The following changes were done on top of Bobby's changes: - atomic##prefix##_*xchg_*(atomic##prefix##_t *v, c_t n) were updated to use__*xchg_generic() - drop casts in write_atomic() as they are unnecessary - drop introduction of WRITE_ONCE() and READ_ONCE(). Xen provides ACCESS_ONCE() - remove zero-length array access in read_atomic() - drop defines similar to pattern: #define atomic_add_return_relaxed atomic_add_return_relaxed - move not RISC-V specific functions to asm-generic/atomics-ops.h - drop atomic##prefix##_{cmp}xchg_{release, aquire, release}() as they are not used in Xen. - update the defintion of atomic##prefix##_{cmp}xchg according to {cmp}xchg() implementation in Xen. - some ATOMIC_OP() macros were updated: - drop size argument for ATOMIC_OP which defines atomic##prefix##_xchg() and atomic##prefix##_cmpxchg(). - drop c_op argument for ATOMIC_OPS which defines ATOMIC_OPS(and, and), ATOMIC_OPS( or, or), ATOMIC_OPS(xor, xor), ATOMIC_OPS(add, add, +), ATOMIC_OPS(sub, add, -) as c_op is always "+" for them. - drop "" from definition of __atomic_{acquire/release"}_fence. The current implementation is the same with 8e86f0b409a4 ("arm64: atomics: fix use of acquire + release for full barrier semantics") [1]. RISC-V could combine acquire and release into the SC instructions and it could reduce a fence instruction to gain better performance. Here is related description from RISC-V ISA 10.2 Load-Reserved/Store-Conditional Instructions: - .aq: The LR/SC sequence can be given acquire semantics by setting the aq bit on the LR instruction. - .rl: The LR/SC sequence can be given release semantics by setting the rl bit on the SC instruction. - .aqrl: Setting the aq bit on the LR instruction, and setting both the aq and the rl bit on the SC instruction makes the LR/SC sequence sequentially consistent, meaning that it cannot be reordered with earlier or later memory operations from the same hart. Software should not set the rl bit on an LR instruction unless the aq bit is also set, nor should software set the aq bit on an SC instruction unless the rl bit is also set. LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those with both bits clear, but may result in lower performance. Also, I way of transforming ".rl + full barrier" to ".aqrl" was approved by (the author of the RVWMO spec) [2] [1] https://patchwork.kernel.org/project/linux-arm-kernel/patch/1391516953-14541-1-git-send-email-will.deacon@arm.com/ [2] https://lore.kernel.org/linux-riscv/41e01514-74ca-84f2-f5cc-2645c444fd8e@nvidia.com/ Signed-off-by: Bobby Eshleman Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V10: - drop unnessary parentheses around p in add_sized() - add Acked-by: Jan Beulich --- Changes in V9: - update the defintion of write_atomic macros: drop the return value as this macros isn't expeceted to return something drop unnessary parentheses around p. - drop casts inside _add_sized() for ptr variable as they aren't necessary. --- Changes in V8: - ???? add the explanatory comment to _add_sized(). - drop "" in __atomic_{acquire, release}_fence(). - code style fixes in atomic##prefix##_##op##_return(): indentation. - drop an unary_op argument ("+") for ATOMIC_OPS(and, and), ATOMIC_OPS( or, or), ATOMIC_OPS(xor, xor) and use "+" directly inside definition of ATOMIC_OPS(). - drop c_op for ATOMIC_OPS(add, add, +) and ATOMIC_OPS(sub, add, -) as it is always "+" for now. Just use "+" inside definition of ATOMIC_OPS(). - drop size argument for ATOMIC_OP() defintions of atomic##prefix##_{xchg,cmpxchg}() - update the commit message. --- Changes in V7: - drop relaxed version of atomic ops as they are not used. - update the commit message - code style fixes - refactor functions write_atomic(), add_sized() to be able to use #ifdef CONFIG_RISCV_32 ... #endif for {write,read}q(). - update ATOMIC_OPS to receive unary operator. - update the header on top of atomic-ops.h. - some minor movements of function inside atomic-ops.h header. --- Changes in V6: - drop atomic##prefix##_{cmp}xchg_{release, aquire, relaxed} as they aren't used by Xen - code style fixes. - %s/__asm__ __volatile__/asm volatile - add explanational comments. - move inclusion of "#include " further down in atomic.h header. --- Changes in V5: - fence.h changes were moved to separate patch as patches related to io.h and cmpxchg.h, which are dependecies for this patch, also needed changes in fence.h - remove accessing of zero-length array - drops cast in write_atomic() - drop introduction of WRITE_ONCE() and READ_ONCE(). - drop defines similar to pattern #define atomic_add_return_relaxed atomic_add_return_relaxed - Xen code style fixes - move not RISC-V specific functions to asm-generic/atomics-ops.h --- Changes in V4: - do changes related to the updates of [PATCH v3 13/34] xen/riscv: introduce cmpxchg.h - drop casts in read_atomic_size(), write_atomic(), add_sized() - tabs -> spaces - drop #ifdef CONFIG_SMP ... #endif in fence.ha as it is simpler to handle NR_CPUS=1 the same as NR_CPUS>1 with accepting less than ideal performance. --- Changes in V3: - update the commit message - add SPDX for fence.h - code style fixes - Remove /* TODO: ... */ for add_sized macros. It looks correct to me. - re-order the patch - merge to this patch fence.h --- Changes in V2: - Change an author of commit. I got this header from Bobby's old repo. --- xen/arch/riscv/include/asm/atomic.h | 280 +++++++++++++++++++++++++++ xen/include/asm-generic/atomic-ops.h | 97 ++++++++++ 2 files changed, 377 insertions(+) create mode 100644 xen/arch/riscv/include/asm/atomic.h create mode 100644 xen/include/asm-generic/atomic-ops.h diff --git a/xen/arch/riscv/include/asm/atomic.h b/xen/arch/riscv/include/asm/atomic.h new file mode 100644 index 0000000000..554bcc2087 --- /dev/null +++ b/xen/arch/riscv/include/asm/atomic.h @@ -0,0 +1,280 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Taken and modified from Linux. + * + * The following changes were done: + * - * atomic##prefix##_*xchg_*(atomic##prefix##_t *v, c_t n) were updated + * to use__*xchg_generic() + * - drop casts in write_atomic() as they are unnecessary + * - drop introduction of WRITE_ONCE() and READ_ONCE(). + * Xen provides ACCESS_ONCE() + * - remove zero-length array access in read_atomic() + * - drop defines similar to pattern + * #define atomic_add_return_relaxed atomic_add_return_relaxed + * - move not RISC-V specific functions to asm-generic/atomics-ops.h + * + * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. + * Copyright (C) 2012 Regents of the University of California + * Copyright (C) 2017 SiFive + * Copyright (C) 2024 Vates SAS + */ + +#ifndef _ASM_RISCV_ATOMIC_H +#define _ASM_RISCV_ATOMIC_H + +#include + +#include +#include +#include +#include + +void __bad_atomic_size(void); + +/* + * Legacy from Linux kernel. For some reason they wanted to have ordered + * read/write access. Thereby read* is used instead of read*_cpu() + */ +static always_inline void read_atomic_size(const volatile void *p, + void *res, + unsigned int size) +{ + switch ( size ) + { + case 1: *(uint8_t *)res = readb(p); break; + case 2: *(uint16_t *)res = readw(p); break; + case 4: *(uint32_t *)res = readl(p); break; +#ifndef CONFIG_RISCV_32 + case 8: *(uint32_t *)res = readq(p); break; +#endif + default: __bad_atomic_size(); break; + } +} + +#define read_atomic(p) ({ \ + union { typeof(*(p)) val; char c[sizeof(*(p))]; } x_; \ + read_atomic_size(p, x_.c, sizeof(*(p))); \ + x_.val; \ +}) + +static always_inline void _write_atomic(volatile void *p, + unsigned long x, unsigned int size) +{ + switch ( size ) + { + case 1: writeb(x, p); break; + case 2: writew(x, p); break; + case 4: writel(x, p); break; +#ifndef CONFIG_RISCV_32 + case 8: writeq(x, p); break; +#endif + default: __bad_atomic_size(); break; + } +} + +#define write_atomic(p, x) \ +({ \ + typeof(*(p)) x_ = (x); \ + _write_atomic(p, x_, sizeof(*(p))); \ +}) + +static always_inline void _add_sized(volatile void *p, + unsigned long x, unsigned int size) +{ + switch ( size ) + { + case 1: + { + volatile uint8_t *ptr = p; + write_atomic(ptr, read_atomic(ptr) + x); + break; + } + case 2: + { + volatile uint16_t *ptr = p; + write_atomic(ptr, read_atomic(ptr) + x); + break; + } + case 4: + { + volatile uint32_t *ptr = p; + write_atomic(ptr, read_atomic(ptr) + x); + break; + } +#ifndef CONFIG_RISCV_32 + case 8: + { + volatile uint64_t *ptr = p; + write_atomic(ptr, read_atomic(ptr) + x); + break; + } +#endif + default: __bad_atomic_size(); break; + } +} + +#define add_sized(p, x) \ +({ \ + typeof(*(p)) x_ = (x); \ + _add_sized(p, x_, sizeof(*(p))); \ +}) + +#define __atomic_acquire_fence() \ + asm volatile ( RISCV_ACQUIRE_BARRIER ::: "memory" ) + +#define __atomic_release_fence() \ + asm volatile ( RISCV_RELEASE_BARRIER ::: "memory" ) + +/* + * First, the atomic ops that have no ordering constraints and therefor don't + * have the AQ or RL bits set. These don't return anything, so there's only + * one version to worry about. + */ +#define ATOMIC_OP(op, asm_op, unary_op, asm_type, c_type, prefix) \ +static inline \ +void atomic##prefix##_##op(c_type i, atomic##prefix##_t *v) \ +{ \ + asm volatile ( \ + " amo" #asm_op "." #asm_type " zero, %1, %0" \ + : "+A" (v->counter) \ + : "r" (unary_op i) \ + : "memory" ); \ +} \ + +/* + * Only CONFIG_GENERIC_ATOMIC64=y was ported to Xen that is the reason why + * last argument for ATOMIC_OP isn't used. + */ +#define ATOMIC_OPS(op, asm_op, unary_op) \ + ATOMIC_OP (op, asm_op, unary_op, w, int, ) + +ATOMIC_OPS(add, add, +) +ATOMIC_OPS(sub, add, -) +ATOMIC_OPS(and, and, +) +ATOMIC_OPS( or, or, +) +ATOMIC_OPS(xor, xor, +) + +#undef ATOMIC_OP +#undef ATOMIC_OPS + +#include + +/* + * Atomic ops that have ordered variant. + * There's two flavors of these: the arithmatic ops have both fetch and return + * versions, while the logical ops only have fetch versions. + */ +#define ATOMIC_FETCH_OP(op, asm_op, unary_op, asm_type, c_type, prefix) \ +static inline \ +c_type atomic##prefix##_fetch_##op(c_type i, atomic##prefix##_t *v) \ +{ \ + register c_type ret; \ + asm volatile ( \ + " amo" #asm_op "." #asm_type ".aqrl %1, %2, %0" \ + : "+A" (v->counter), "=r" (ret) \ + : "r" (unary_op i) \ + : "memory" ); \ + return ret; \ +} + +#define ATOMIC_OP_RETURN(op, asm_op, c_op, unary_op, asm_type, c_type, prefix) \ +static inline \ +c_type atomic##prefix##_##op##_return(c_type i, atomic##prefix##_t *v) \ +{ \ + return atomic##prefix##_fetch_##op(i, v) c_op (unary_op i); \ +} + +/* + * Only CONFIG_GENERIC_ATOMIC64=y was ported to Xen that is the reason why + * last argument of ATOMIC_FETCH_OP, ATOMIC_OP_RETURN isn't used. + */ +#define ATOMIC_OPS(op, asm_op, unary_op) \ + ATOMIC_FETCH_OP( op, asm_op, unary_op, w, int, ) \ + ATOMIC_OP_RETURN(op, asm_op, +, unary_op, w, int, ) + +ATOMIC_OPS(add, add, +) +ATOMIC_OPS(sub, add, -) + +#undef ATOMIC_OPS + +#define ATOMIC_OPS(op, asm_op) \ + ATOMIC_FETCH_OP(op, asm_op, +, w, int, ) + +ATOMIC_OPS(and, and) +ATOMIC_OPS( or, or) +ATOMIC_OPS(xor, xor) + +#undef ATOMIC_OPS + +#undef ATOMIC_FETCH_OP +#undef ATOMIC_OP_RETURN + +/* This is required to provide a full barrier on success. */ +static inline int atomic_add_unless(atomic_t *v, int a, int u) +{ + int prev, rc; + + asm volatile ( + "0: lr.w %[p], %[c]\n" + " beq %[p], %[u], 1f\n" + " add %[rc], %[p], %[a]\n" + " sc.w.aqrl %[rc], %[rc], %[c]\n" + " bnez %[rc], 0b\n" + "1:\n" + : [p] "=&r" (prev), [rc] "=&r" (rc), [c] "+A" (v->counter) + : [a] "r" (a), [u] "r" (u) + : "memory"); + return prev; +} + +static inline int atomic_sub_if_positive(atomic_t *v, int offset) +{ + int prev, rc; + + asm volatile ( + "0: lr.w %[p], %[c]\n" + " sub %[rc], %[p], %[o]\n" + " bltz %[rc], 1f\n" + " sc.w.aqrl %[rc], %[rc], %[c]\n" + " bnez %[rc], 0b\n" + "1:\n" + : [p] "=&r" (prev), [rc] "=&r" (rc), [c] "+A" (v->counter) + : [o] "r" (offset) + : "memory" ); + return prev - offset; +} + +/* + * atomic_{cmp,}xchg is required to have exactly the same ordering semantics as + * {cmp,}xchg and the operations that return. + */ +#define ATOMIC_OP(c_t, prefix) \ +static inline \ +c_t atomic##prefix##_xchg(atomic##prefix##_t *v, c_t n) \ +{ \ + return __xchg(&v->counter, n, sizeof(c_t)); \ +} \ +static inline \ +c_t atomic##prefix##_cmpxchg(atomic##prefix##_t *v, c_t o, c_t n) \ +{ \ + return __cmpxchg(&v->counter, o, n, sizeof(c_t)); \ +} + +#define ATOMIC_OPS() \ + ATOMIC_OP(int, ) + +ATOMIC_OPS() + +#undef ATOMIC_OPS +#undef ATOMIC_OP + +#endif /* _ASM_RISCV_ATOMIC_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/asm-generic/atomic-ops.h b/xen/include/asm-generic/atomic-ops.h new file mode 100644 index 0000000000..98dd907942 --- /dev/null +++ b/xen/include/asm-generic/atomic-ops.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * The header provides default implementations for every xen/atomic.h-provided + * forward inline declaration that can be synthesized from other atomic + * functions or being created from scratch. + */ +#ifndef _ASM_GENERIC_ATOMIC_OPS_H_ +#define _ASM_GENERIC_ATOMIC_OPS_H_ + +#include +#include + +#ifndef ATOMIC_READ +static inline int atomic_read(const atomic_t *v) +{ + return ACCESS_ONCE(v->counter); +} +#endif + +#ifndef _ATOMIC_READ +static inline int _atomic_read(atomic_t v) +{ + return v.counter; +} +#endif + +#ifndef ATOMIC_SET +static inline void atomic_set(atomic_t *v, int i) +{ + ACCESS_ONCE(v->counter) = i; +} +#endif + +#ifndef _ATOMIC_SET +static inline void _atomic_set(atomic_t *v, int i) +{ + v->counter = i; +} +#endif + +#ifndef ATOMIC_SUB_AND_TEST +static inline int atomic_sub_and_test(int i, atomic_t *v) +{ + return atomic_sub_return(i, v) == 0; +} +#endif + +#ifndef ATOMIC_INC_AND_TEST +static inline int atomic_inc_and_test(atomic_t *v) +{ + return atomic_add_return(1, v) == 0; +} +#endif + +#ifndef ATOMIC_INC +static inline void atomic_inc(atomic_t *v) +{ + atomic_add(1, v); +} +#endif + +#ifndef ATOMIC_INC_RETURN +static inline int atomic_inc_return(atomic_t *v) +{ + return atomic_add_return(1, v); +} +#endif + +#ifndef ATOMIC_DEC +static inline void atomic_dec(atomic_t *v) +{ + atomic_sub(1, v); +} +#endif + +#ifndef ATOMIC_DEC_RETURN +static inline int atomic_dec_return(atomic_t *v) +{ + return atomic_sub_return(1, v); +} +#endif + +#ifndef ATOMIC_DEC_AND_TEST +static inline int atomic_dec_and_test(atomic_t *v) +{ + return atomic_sub_return(1, v) == 0; +} +#endif + +#ifndef ATOMIC_ADD_NEGATIVE +static inline int atomic_add_negative(int i, atomic_t *v) +{ + return atomic_add_return(i, v) < 0; +} +#endif + +#endif /* _ASM_GENERIC_ATOMIC_OPS_H_ */ From patchwork Fri May 17 13:54:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13667030 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C1F6C25B7B for ; Fri, 17 May 2024 13:55:25 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.724184.1129412 (Exim 4.92) (envelope-from ) id 1s7y3K-0003HV-6F; Fri, 17 May 2024 13:55:18 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 724184.1129412; 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Only rebase. --- Changes in V3: - new patch. --- xen/arch/riscv/include/asm/monitor.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 xen/arch/riscv/include/asm/monitor.h diff --git a/xen/arch/riscv/include/asm/monitor.h b/xen/arch/riscv/include/asm/monitor.h new file mode 100644 index 0000000000..f4fe2c0690 --- /dev/null +++ b/xen/arch/riscv/include/asm/monitor.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_RISCV_MONITOR_H__ +#define __ASM_RISCV_MONITOR_H__ + +#include + +#include + +struct domain; + +static inline uint32_t arch_monitor_get_capabilities(struct domain *d) +{ + BUG_ON("unimplemented"); + return 0; +} + +#endif /* __ASM_RISCV_MONITOR_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri May 17 13:54:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13667033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38FD6C04FFE for ; Fri, 17 May 2024 13:55:29 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.724186.1129425 (Exim 4.92) (envelope-from ) id 1s7y3L-0003Uc-6B; Fri, 17 May 2024 13:55:19 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 724186.1129425; Fri, 17 May 2024 13:55:19 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3K-0003Tc-SO; Fri, 17 May 2024 13:55:18 +0000 Received: by outflank-mailman (input) for mailman id 724186; Fri, 17 May 2024 13:55:17 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3J-0001sq-Pp for xen-devel@lists.xenproject.org; Fri, 17 May 2024 13:55:17 +0000 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [2a00:1450:4864:20::533]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 163a8bba-1455-11ef-b4bb-af5377834399; Fri, 17 May 2024 15:55:15 +0200 (CEST) Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-574f7c0bab4so5527038a12.0 for ; Fri, 17 May 2024 06:55:15 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a179c81b4sm1117456466b.113.2024.05.17.06.55.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 06:55:14 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 163a8bba-1455-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715954114; x=1716558914; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IyBSZPlFHowbije2gbqJW9jX49ovLzWsyAVo7e+9BiA=; b=L/z7WBYDgtlz3Lq4W6ov/xA4GNcwQVp/Zjhg1t3/AkqFmrIRlQYKGepOR5nbkZSkrv qC/Hkw+79y8BWMrEBThMFFQZGdFJtggHDq8U52+sMrdivxRRCVAptk7w/v2kAjj47tef Fzb7cxpQNgHLGz7HiwtcyHkQuGi7AQNAiqLqmVnp/SCn7mfZKdv055ItSlIf9yapoKk5 bLqqTbHMfZkG/UkVHyGTdBKh4R6vWcb7xTXmGbETWNQhKmAZXFjWOWkAGvHG9EM5q2Yn 4qY7kQI/OPI0vlkgd1LNHKaHEnJJJ/xU1cs3ttbWIsmizrtWjLIFh7v7OYAvWtPGw7e+ pyuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715954114; x=1716558914; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IyBSZPlFHowbije2gbqJW9jX49ovLzWsyAVo7e+9BiA=; b=ZgaqBM5ym7KUFoxAkmCb7tm6Xl3ZF59uh9xLW4jdZF6D6+Sw3l7vmlxbRYdC9bfwAC pZD4FdQGHhieJcv7NLHrlT6WX2bec75We9u9+0qLgjzCsSRaFIE29GrHMRrI60mLDZho vQEN8icbC4ypMRKn1w+Ly0PJX+vlArFss9UvVIRDK4YWXTCuoGHWnuizEtHYYVB5cQs0 lGyW+sihN4Zoz1RddY6zJO8t0WGcRQhrXqJK6kfx6YQPFRQZ+csrIzrkGvVGtvoYoCJE w9yDsYDQ/12SocHYqAtVTpnZhlOY8E4QsVOHq6q2t6RNM5DIN2MHh/ajg8KLuRS4yU7X 3X8g== X-Gm-Message-State: AOJu0YwK6rEERgHvvAF40wmJ3qyGkwKzelZObnCcYq6S2k4suFoT6anl DanyIkZNtbDI6vqhhLsUgjB4HsDYdzAfSAjR8w/wMf+UCGA+iP5hMTw7xKKp X-Google-Smtp-Source: AGHT+IEH4GixmiF/ZnYd2IrHPQ6pJGJyu1Ytdqrigw3Z/aFxvE19tc1zBfWvqXV4dA53oYRV9fQxng== X-Received: by 2002:a17:906:240e:b0:a5c:dce0:9f4e with SMTP id a640c23a62f3a-a5cdce0a0camr589738166b.28.1715954114429; Fri, 17 May 2024 06:55:14 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v10 08/14] xen/riscv: add definition of __read_mostly Date: Fri, 17 May 2024 15:54:57 +0200 Message-ID: <834486ff8e3233e067a0e4603f700182826eca94.1715952103.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 The definition of __read_mostly should be removed in: https://lore.kernel.org/xen-devel/f25eb5c9-7c14-6e23-8535-2c66772b333e@suse.com/ The patch introduces it in arch-specific header to not block enabling of full Xen build for RISC-V. Signed-off-by: Oleksii Kurochko --- - [PATCH] move __read_mostly to xen/cache.h [2] Right now, the patch series doesn't have a direct dependency on [2] and it provides __read_mostly in the patch: [PATCH v3 26/34] xen/riscv: add definition of __read_mostly However, it will be dropped as soon as [2] is merged or at least when the final version of the patch [2] is provided. Considering that there is still no still final decision regarding patch [2] my suggestion is to merge RISC-V specific patch and just drop the changes in patch [2]. [2] https://lore.kernel.org/xen-devel/f25eb5c9-7c14-6e23-8535-2c66772b333e@suse.com/ --- Changes in V9-V10: - Only rebase was done. --- Change in V8: - update the footer after Signed-off. --- Changes in V4-V7: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/cache.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/riscv/include/asm/cache.h b/xen/arch/riscv/include/asm/cache.h index 69573eb051..94bd94db53 100644 --- a/xen/arch/riscv/include/asm/cache.h +++ b/xen/arch/riscv/include/asm/cache.h @@ -3,4 +3,6 @@ #ifndef _ASM_RISCV_CACHE_H #define _ASM_RISCV_CACHE_H +#define __read_mostly __section(".data.read_mostly") + #endif /* _ASM_RISCV_CACHE_H */ From patchwork Fri May 17 13:54:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13667036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C5C9BC25B7B for ; Fri, 17 May 2024 13:55:29 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.724188.1129441 (Exim 4.92) (envelope-from ) id 1s7y3N-00041H-5N; Fri, 17 May 2024 13:55:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 724188.1129441; Fri, 17 May 2024 13:55:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3M-0003z6-Ug; Fri, 17 May 2024 13:55:20 +0000 Received: by outflank-mailman (input) for mailman id 724188; Fri, 17 May 2024 13:55:19 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3K-0001sq-QG for xen-devel@lists.xenproject.org; Fri, 17 May 2024 13:55:18 +0000 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [2a00:1450:4864:20::12a]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 16e13c8c-1455-11ef-b4bb-af5377834399; Fri, 17 May 2024 15:55:16 +0200 (CEST) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-51fb14816f6so766853e87.0 for ; Fri, 17 May 2024 06:55:16 -0700 (PDT) Received: from fedora.. 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Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V5-V10: - Nothing changed. Only rebase. --- Changes in V4: - BUG() was changed to BUG_ON("unimplemented"); - Change "xen/bug.h" to "xen/lib.h" as BUG_ON is defined in xen/lib.h. - Add Acked-by: Jan Beulich --- Changes in V3: - add SPDX - drop a forward declaration of struct vcpu; - update guest_cpu_user_regs() macros - replace get_processor_id with smp_processor_id - update the commit message - code style fixes --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/current.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/xen/arch/riscv/include/asm/current.h b/xen/arch/riscv/include/asm/current.h index d84f15dc50..aedb6dc732 100644 --- a/xen/arch/riscv/include/asm/current.h +++ b/xen/arch/riscv/include/asm/current.h @@ -3,6 +3,21 @@ #ifndef __ASM_CURRENT_H #define __ASM_CURRENT_H +#include +#include +#include + +#ifndef __ASSEMBLY__ + +/* Which VCPU is "current" on this PCPU. */ +DECLARE_PER_CPU(struct vcpu *, curr_vcpu); + +#define current this_cpu(curr_vcpu) +#define set_current(vcpu) do { current = (vcpu); } while (0) +#define get_cpu_current(cpu) per_cpu(curr_vcpu, cpu) + +#define guest_cpu_user_regs() ({ BUG_ON("unimplemented"); NULL; }) + #define switch_stack_and_jump(stack, fn) do { \ asm volatile ( \ "mv sp, %0\n" \ @@ -10,4 +25,8 @@ unreachable(); \ } while ( false ) +#define get_per_cpu_offset() __per_cpu_offset[smp_processor_id()] + +#endif /* __ASSEMBLY__ */ + #endif /* __ASM_CURRENT_H */ From patchwork Fri May 17 13:54:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13667035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A96ACC25B7A for ; Fri, 17 May 2024 13:55:29 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.724187.1129437 (Exim 4.92) (envelope-from ) id 1s7y3M-0003u3-OH; Fri, 17 May 2024 13:55:20 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 724187.1129437; Fri, 17 May 2024 13:55:20 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3M-0003sm-Fb; Fri, 17 May 2024 13:55:20 +0000 Received: by outflank-mailman (input) for mailman id 724187; Fri, 17 May 2024 13:55:18 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3J-0001cB-V2 for xen-devel@lists.xenproject.org; Fri, 17 May 2024 13:55:18 +0000 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [2a00:1450:4864:20::630]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 17726393-1455-11ef-909e-e314d9c70b13; Fri, 17 May 2024 15:55:17 +0200 (CEST) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-a5d02b45262so123719866b.1 for ; Fri, 17 May 2024 06:55:17 -0700 (PDT) Received: from fedora.. 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Fri, 17 May 2024 06:55:16 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v10 10/14] xen/riscv: add minimal stuff to mm.h to build full Xen Date: Fri, 17 May 2024 15:54:59 +0200 Message-ID: X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V8-V10: - Nothing changed only rebase. --- Changes in V7: - update argument type of maddr_to_virt() function: unsigned long -> paddr_t - rename argument of PFN_ORDER(): pfn -> pg. - add Acked-by: Jan Beulich --- Changes in V6: - drop __virt_to_maddr() ( transform to macro ) and __maddr_to_virt ( rename to maddr_to_virt ). - parenthesize va in definition of vmap_to_mfn(). - Code style fixes. --- Changes in V5: - update the comment around "struct domain *domain;" : zero -> NULL - fix ident. for unsigned long val; - put page_to_virt() and virt_to_page() close to each other. - drop unnessary leading underscore - drop a space before the comment: /* Count of uses of this frame as its current type. */ - drop comment about a page 'not as a shadow'. it is not necessary for RISC-V --- Changes in V4: - update an argument name of PFN_ORDERN macros. - drop pad at the end of 'struct page_info'. - Change message -> subject in "Changes in V3" - delete duplicated macros from riscv/mm.h - fix identation in struct page_info - align comment for PGC_ macros - update definitions of domain_set_alloc_bitsize() and domain_clamp_alloc_bitsize() - drop unnessary comments. - s/BUG/BUG_ON("...") - define __virt_to_maddr, __maddr_to_virt as stubs - add inclusion of xen/mm-frame.h for mfn_x and others - include "xen/mm.h" instead of "asm/mm.h" to fix compilation issues: In file included from arch/riscv/setup.c:7: ./arch/riscv/include/asm/mm.h:60:28: error: field 'list' has incomplete type 60 | struct page_list_entry list; | ^~~~ ./arch/riscv/include/asm/mm.h:81:43: error: 'MAX_ORDER' undeclared here (not in a function) 81 | unsigned long first_dirty:MAX_ORDER + 1; | ^~~~~~~~~ ./arch/riscv/include/asm/mm.h:81:31: error: bit-field 'first_dirty' width not an integer constant 81 | unsigned long first_dirty:MAX_ORDER + 1; - Define __virt_to_mfn() and __mfn_to_virt() using maddr_to_mfn() and mfn_to_maddr(). --- Changes in V3: - update the commit title - introduce DIRECTMAP_VIRT_START. - drop changes related pfn_to_paddr() and paddr_to_pfn as they were remvoe in [PATCH v2 32/39] xen/riscv: add minimal stuff to asm/page.h to build full Xen - code style fixes. - drop get_page_nr and put_page_nr as they don't need for time being - drop CONFIG_STATIC_MEMORY related things - code style fixes --- Changes in V2: - define stub for arch_get_dma_bitsize(void) --- xen/arch/riscv/include/asm/mm.h | 240 ++++++++++++++++++++++++++++++++ xen/arch/riscv/mm.c | 2 +- xen/arch/riscv/setup.c | 2 +- 3 files changed, 242 insertions(+), 2 deletions(-) diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/mm.h index 07c7a0abba..cc4a07a71c 100644 --- a/xen/arch/riscv/include/asm/mm.h +++ b/xen/arch/riscv/include/asm/mm.h @@ -3,11 +3,246 @@ #ifndef _ASM_RISCV_MM_H #define _ASM_RISCV_MM_H +#include +#include +#include +#include +#include + #include #define pfn_to_paddr(pfn) ((paddr_t)(pfn) << PAGE_SHIFT) #define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT)) +#define paddr_to_pdx(pa) mfn_to_pdx(maddr_to_mfn(pa)) +#define gfn_to_gaddr(gfn) pfn_to_paddr(gfn_x(gfn)) +#define gaddr_to_gfn(ga) _gfn(paddr_to_pfn(ga)) +#define mfn_to_maddr(mfn) pfn_to_paddr(mfn_x(mfn)) +#define maddr_to_mfn(ma) _mfn(paddr_to_pfn(ma)) +#define vmap_to_mfn(va) maddr_to_mfn(virt_to_maddr((vaddr_t)(va))) +#define vmap_to_page(va) mfn_to_page(vmap_to_mfn(va)) + +static inline void *maddr_to_virt(paddr_t ma) +{ + BUG_ON("unimplemented"); + return NULL; +} + +#define virt_to_maddr(va) ({ BUG_ON("unimplemented"); 0; }) + +/* Convert between Xen-heap virtual addresses and machine frame numbers. */ +#define __virt_to_mfn(va) mfn_x(maddr_to_mfn(virt_to_maddr(va))) +#define __mfn_to_virt(mfn) maddr_to_virt(mfn_to_maddr(_mfn(mfn))) + +/* + * We define non-underscored wrappers for above conversion functions. + * These are overriden in various source files while underscored version + * remain intact. + */ +#define virt_to_mfn(va) __virt_to_mfn(va) +#define mfn_to_virt(mfn) __mfn_to_virt(mfn) + +struct page_info +{ + /* Each frame can be threaded onto a doubly-linked list. */ + struct page_list_entry list; + + /* Reference count and various PGC_xxx flags and fields. */ + unsigned long count_info; + + /* Context-dependent fields follow... */ + union { + /* Page is in use: ((count_info & PGC_count_mask) != 0). */ + struct { + /* Type reference count and various PGT_xxx flags and fields. */ + unsigned long type_info; + } inuse; + + /* Page is on a free list: ((count_info & PGC_count_mask) == 0). */ + union { + struct { + /* + * Index of the first *possibly* unscrubbed page in the buddy. + * One more bit than maximum possible order to accommodate + * INVALID_DIRTY_IDX. + */ +#define INVALID_DIRTY_IDX ((1UL << (MAX_ORDER + 1)) - 1) + unsigned long first_dirty:MAX_ORDER + 1; + + /* Do TLBs need flushing for safety before next page use? */ + bool need_tlbflush:1; + +#define BUDDY_NOT_SCRUBBING 0 +#define BUDDY_SCRUBBING 1 +#define BUDDY_SCRUB_ABORT 2 + unsigned long scrub_state:2; + }; + + unsigned long val; + } free; + } u; + + union { + /* Page is in use */ + struct { + /* Owner of this page (NULL if page is anonymous). */ + struct domain *domain; + } inuse; + + /* Page is on a free list. */ + struct { + /* Order-size of the free chunk this page is the head of. */ + unsigned int order; + } free; + } v; + + union { + /* + * Timestamp from 'TLB clock', used to avoid extra safety flushes. + * Only valid for: a) free pages, and b) pages with zero type count + */ + uint32_t tlbflush_timestamp; + }; +}; + +#define frame_table ((struct page_info *)FRAMETABLE_VIRT_START) + +/* PDX of the first page in the frame table. */ +extern unsigned long frametable_base_pdx; + +/* Convert between machine frame numbers and page-info structures. */ +#define mfn_to_page(mfn) \ + (frame_table + (mfn_to_pdx(mfn) - frametable_base_pdx)) +#define page_to_mfn(pg) \ + pdx_to_mfn((unsigned long)((pg) - frame_table) + frametable_base_pdx) + +static inline void *page_to_virt(const struct page_info *pg) +{ + return mfn_to_virt(mfn_x(page_to_mfn(pg))); +} + +/* Convert between Xen-heap virtual addresses and page-info structures. */ +static inline struct page_info *virt_to_page(const void *v) +{ + BUG_ON("unimplemented"); + return NULL; +} + +/* + * Common code requires get_page_type and put_page_type. + * We don't care about typecounts so we just do the minimum to make it + * happy. + */ +static inline int get_page_type(struct page_info *page, unsigned long type) +{ + return 1; +} + +static inline void put_page_type(struct page_info *page) +{ +} + +static inline void put_page_and_type(struct page_info *page) +{ + put_page_type(page); + put_page(page); +} + +/* + * RISC-V does not have an M2P, but common code expects a handful of + * M2P-related defines and functions. Provide dummy versions of these. + */ +#define INVALID_M2P_ENTRY (~0UL) +#define SHARED_M2P_ENTRY (~0UL - 1UL) +#define SHARED_M2P(_e) ((_e) == SHARED_M2P_ENTRY) + +#define set_gpfn_from_mfn(mfn, pfn) do { (void)(mfn), (void)(pfn); } while (0) +#define mfn_to_gfn(d, mfn) ((void)(d), _gfn(mfn_x(mfn))) + +#define PDX_GROUP_SHIFT (PAGE_SHIFT + VPN_BITS) + +static inline unsigned long domain_get_maximum_gpfn(struct domain *d) +{ + BUG_ON("unimplemented"); + return 0; +} + +static inline long arch_memory_op(int op, XEN_GUEST_HANDLE_PARAM(void) arg) +{ + BUG_ON("unimplemented"); + return 0; +} + +/* + * On RISCV, all the RAM is currently direct mapped in Xen. + * Hence return always true. + */ +static inline bool arch_mfns_in_directmap(unsigned long mfn, unsigned long nr) +{ + return true; +} + +#define PG_shift(idx) (BITS_PER_LONG - (idx)) +#define PG_mask(x, idx) (x ## UL << PG_shift(idx)) + +#define PGT_none PG_mask(0, 1) /* no special uses of this page */ +#define PGT_writable_page PG_mask(1, 1) /* has writable mappings? */ +#define PGT_type_mask PG_mask(1, 1) /* Bits 31 or 63. */ + +/* Count of uses of this frame as its current type. */ +#define PGT_count_width PG_shift(2) +#define PGT_count_mask ((1UL << PGT_count_width) - 1) + +/* + * Page needs to be scrubbed. Since this bit can only be set on a page that is + * free (i.e. in PGC_state_free) we can reuse PGC_allocated bit. + */ +#define _PGC_need_scrub _PGC_allocated +#define PGC_need_scrub PGC_allocated + +/* Cleared when the owning guest 'frees' this page. */ +#define _PGC_allocated PG_shift(1) +#define PGC_allocated PG_mask(1, 1) +/* Page is Xen heap? */ +#define _PGC_xen_heap PG_shift(2) +#define PGC_xen_heap PG_mask(1, 2) +/* Page is broken? */ +#define _PGC_broken PG_shift(7) +#define PGC_broken PG_mask(1, 7) +/* Mutually-exclusive page states: { inuse, offlining, offlined, free }. */ +#define PGC_state PG_mask(3, 9) +#define PGC_state_inuse PG_mask(0, 9) +#define PGC_state_offlining PG_mask(1, 9) +#define PGC_state_offlined PG_mask(2, 9) +#define PGC_state_free PG_mask(3, 9) +#define page_state_is(pg, st) (((pg)->count_info&PGC_state) == PGC_state_##st) + +/* Count of references to this frame. */ +#define PGC_count_width PG_shift(9) +#define PGC_count_mask ((1UL << PGC_count_width) - 1) + +#define _PGC_extra PG_shift(10) +#define PGC_extra PG_mask(1, 10) + +#define is_xen_heap_page(page) ((page)->count_info & PGC_xen_heap) +#define is_xen_heap_mfn(mfn) \ + (mfn_valid(mfn) && is_xen_heap_page(mfn_to_page(mfn))) + +#define is_xen_fixed_mfn(mfn) \ + ((mfn_to_maddr(mfn) >= virt_to_maddr((vaddr_t)_start)) && \ + (mfn_to_maddr(mfn) <= virt_to_maddr((vaddr_t)_end - 1))) + +#define page_get_owner(p) (p)->v.inuse.domain +#define page_set_owner(p, d) ((p)->v.inuse.domain = (d)) + +/* TODO: implement */ +#define mfn_valid(mfn) ({ (void)(mfn); 0; }) + +#define domain_set_alloc_bitsize(d) ((void)(d)) +#define domain_clamp_alloc_bitsize(d, b) ((void)(d), (b)) + +#define PFN_ORDER(pg) ((pg)->v.free.order) + extern unsigned char cpu0_boot_stack[]; void setup_initial_pagetables(void); @@ -20,4 +255,9 @@ unsigned long calc_phys_offset(void); void turn_on_mmu(unsigned long ra); +static inline unsigned int arch_get_dma_bitsize(void) +{ + return 32; /* TODO */ +} + #endif /* _ASM_RISCV_MM_H */ diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index 053f043a3d..fe3a43be20 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -5,12 +5,12 @@ #include #include #include +#include #include #include #include #include -#include #include #include diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 6593f601c1..98a94c4c48 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -2,9 +2,9 @@ #include #include +#include #include -#include /* Xen stack for bringing up the first CPU. */ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] From patchwork Fri May 17 13:55:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13667037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E8CBC25B7C for ; Fri, 17 May 2024 13:55:30 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.724189.1129452 (Exim 4.92) (envelope-from ) id 1s7y3O-0004Az-8p; Fri, 17 May 2024 13:55:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 724189.1129452; Fri, 17 May 2024 13:55:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3N-000489-Je; Fri, 17 May 2024 13:55:21 +0000 Received: by outflank-mailman (input) for mailman id 724189; Fri, 17 May 2024 13:55:19 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3K-0001cB-VD for xen-devel@lists.xenproject.org; Fri, 17 May 2024 13:55:18 +0000 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [2a00:1450:4864:20::52d]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 17fcc428-1455-11ef-909e-e314d9c70b13; Fri, 17 May 2024 15:55:18 +0200 (CEST) Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-572e48f91e9so5322423a12.0 for ; Fri, 17 May 2024 06:55:18 -0700 (PDT) Received: from fedora.. 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Fri, 17 May 2024 06:55:17 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Tamas K Lengyel , Alexandru Isaila , Petre Pircalabu Subject: [PATCH v10 11/14] xen/riscv: introduce vm_event_*() functions Date: Fri, 17 May 2024 15:55:00 +0200 Message-ID: <050567a35805361edc0e222f4ddebfa91403cfb6.1715952103.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko Acked-by: Tamas K Lengyel --- Changes in V5-V10: - Only rebase was done. --- Changes in V4: - New patch. --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/vm_event.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 xen/arch/riscv/vm_event.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 2fefe14e7c..1ed1a8369b 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_RISCV_64) += riscv64/ obj-y += sbi.o obj-y += setup.o obj-y += traps.o +obj-y += vm_event.o $(TARGET): $(TARGET)-syms $(OBJCOPY) -O binary -S $< $@ diff --git a/xen/arch/riscv/vm_event.c b/xen/arch/riscv/vm_event.c new file mode 100644 index 0000000000..bb1fc73bc1 --- /dev/null +++ b/xen/arch/riscv/vm_event.c @@ -0,0 +1,19 @@ +#include + +struct vm_event_st; +struct vcpu; + +void vm_event_fill_regs(struct vm_event_st *req) +{ + BUG_ON("unimplemented"); +} + +void vm_event_set_registers(struct vcpu *v, struct vm_event_st *rsp) +{ + BUG_ON("unimplemented"); +} + +void vm_event_monitor_next_interrupt(struct vcpu *v) +{ + /* Not supported on RISCV. */ +} From patchwork Fri May 17 13:55:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13667038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81822C04FFE for ; Fri, 17 May 2024 13:55:32 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.724190.1129457 (Exim 4.92) (envelope-from ) id 1s7y3P-0004J9-02; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a179c81b4sm1117456466b.113.2024.05.17.06.55.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 06:55:17 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 1879612e-1455-11ef-909e-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715954118; x=1716558918; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VqZoxeXcvwG6qA/xb5N6kbA45uUp111KA2sPPRW9tSw=; b=YfjpJ3DD8d5yHl1Y7JGRtcoK5vvYrXqM4QhZ9++KywKJzyveL6gnP7ivCMyUKJBTUN oPFp34DbfRG98+5ePTZIybkxa9mRJGafcwfhVEfVFzrdAqwFCrEoxz7K/Bv0mfHRBn90 xD68AdxYD7Yd/PgkTAeXyLWSYs+8INf2FIN6RPf1oDGALn1kvrqgXyZ5XtGbUEYPWH8F wjWIOza1fqpOW43Ppz3AcuFfzM/gZEpjiUNtWulVTDN9GUuBbszrN0n2lTroogPuehkH ZqAt2ojNN1CNa/wCazfRIvvsyQLqLdrJh0LJvAdADu2YGLaVF2ey305Wgli6wNYZHnNa a50A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715954118; x=1716558918; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VqZoxeXcvwG6qA/xb5N6kbA45uUp111KA2sPPRW9tSw=; b=BPoB1zpvwczIOfpyMb6Vh7I23U3u5yux5bs9PKxGCPWiIgvgDfsGv69781njK4gtT/ qeXBjoRJfPtONjJVeTpmsTGHUA0oJZy53Jw5P5RSIy8wecDrtfeTY147t48bVnIfqpEs EbDjKB6O5v5v0o2zVMVEQVmkpDtZF1Mty5nl9R14fZOApyhgkI+K8xvHYtiN5HCQwMUr VUpYh/9kjZdJTbvxcuRrMGFGW+gt1Zeyjh9YC6nf75WjHdEOlKk3fQZVE8/+fUtSgHG0 ozUWJvS6H3Ew0jbRjFrFksK6MsdczSqBEUK4GPrmqjTDaAvJlq0mQm+W9KHvJiMxg0qB iJRw== X-Gm-Message-State: AOJu0YyCV05hhOM1OMFYq85AIUDtS1mreJ6wRstETqMa+e//NjmguvO7 HQJnMCTNzikdt9i0TFECG3HH0HcIhGc3LWVJwfo1WlhuJan+fg2+F9HSRc+w X-Google-Smtp-Source: AGHT+IHxHmV3A0bcwpvmuR0omarL/kP79NpLAVNtxStRnNja9z9394gkxZ5NreQvFMSAtX5EU/ulbg== X-Received: by 2002:a05:6512:688:b0:523:dab3:39 with SMTP id 2adb3069b0e04-523dab300c6mr2292690e87.55.1715954118080; Fri, 17 May 2024 06:55:18 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v10 12/14] xen/riscv: add minimal amount of stubs to build full Xen Date: Fri, 17 May 2024 15:55:01 +0200 Message-ID: <7ecaf3a902db375eec5936ff98c98916e7bc8895.1715952103.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V7-V10: - Only rebase was done. --- Changes in V6: - update the commit in stubs.c around /* ... common/irq.c ... */ - add Acked-by: Jan Beulich --- Changes in V5: - drop unrelated changes - assert_failed("unimplmented...") change to BUG_ON() --- Changes in V4: - added new stubs which are necessary for compilation after rebase: __cpu_up(), __cpu_disable(), __cpu_die() from smpboot.c - back changes related to printk() in early_printk() as they should be removed in the next patch to avoid compilation error. - update definition of cpu_khz: __read_mostly -> __ro_after_init. - drop vm_event_reset_vmtrace(). It is defibed in asm-generic/vm_event.h. - move vm_event_*() functions from stubs.c to riscv/vm_event.c. - s/BUG/BUG_ON("unimplemented") in stubs.c - back irq_actor_none() and irq_actor_none() as common/irq.c isn't compiled at this moment, so this function are needed to avoid compilation error. - defined max_page to avoid compilation error, it will be removed as soon as common/page_alloc.c will be compiled. --- Changes in V3: - code style fixes. - update attribute for frametable_base_pdx and frametable_virt_end to __ro_after_init. insteaf of read_mostly. - use BUG() instead of assert_failed/WARN for newly introduced stubs. - drop "#include " in stubs.c and use forward declaration instead. - drop ack_node() and end_node() as they aren't used now. --- Changes in V2: - define udelay stub - remove 'select HAS_PDX' from RISC-V Kconfig because of https://lore.kernel.org/xen-devel/20231006144405.1078260-1-andrew.cooper3@citrix.com/ --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/mm.c | 50 +++++ xen/arch/riscv/setup.c | 8 + xen/arch/riscv/stubs.c | 439 ++++++++++++++++++++++++++++++++++++++++ xen/arch/riscv/traps.c | 25 +++ 5 files changed, 523 insertions(+) create mode 100644 xen/arch/riscv/stubs.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 1ed1a8369b..60afbc0ad9 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -4,6 +4,7 @@ obj-y += mm.o obj-$(CONFIG_RISCV_64) += riscv64/ obj-y += sbi.o obj-y += setup.o +obj-y += stubs.o obj-y += traps.o obj-y += vm_event.o diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index fe3a43be20..2c3fb7d72e 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -14,6 +15,9 @@ #include #include +unsigned long __ro_after_init frametable_base_pdx; +unsigned long __ro_after_init frametable_virt_end; + struct mmu_desc { unsigned int num_levels; unsigned int pgtbl_count; @@ -294,3 +298,49 @@ unsigned long __init calc_phys_offset(void) phys_offset = load_start - XEN_VIRT_START; return phys_offset; } + +void put_page(struct page_info *page) +{ + BUG_ON("unimplemented"); +} + +unsigned long get_upper_mfn_bound(void) +{ + /* No memory hotplug yet, so current memory limit is the final one. */ + return max_page - 1; +} + +void arch_dump_shared_mem_info(void) +{ + BUG_ON("unimplemented"); +} + +int populate_pt_range(unsigned long virt, unsigned long nr_mfns) +{ + BUG_ON("unimplemented"); + return -1; +} + +int xenmem_add_to_physmap_one(struct domain *d, unsigned int space, + union add_to_physmap_extra extra, + unsigned long idx, gfn_t gfn) +{ + BUG_ON("unimplemented"); + + return 0; +} + +int destroy_xen_mappings(unsigned long s, unsigned long e) +{ + BUG_ON("unimplemented"); + return -1; +} + +int map_pages_to_xen(unsigned long virt, + mfn_t mfn, + unsigned long nr_mfns, + unsigned int flags) +{ + BUG_ON("unimplemented"); + return -1; +} diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 98a94c4c48..8bb5bdb2ae 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -1,11 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include +#include + #include +void arch_get_xen_caps(xen_capabilities_info_t *info) +{ + BUG_ON("unimplemented"); +} + /* Xen stack for bringing up the first CPU. */ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] __aligned(STACK_SIZE); diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c new file mode 100644 index 0000000000..8285bcffef --- /dev/null +++ b/xen/arch/riscv/stubs.c @@ -0,0 +1,439 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include +#include +#include +#include + +#include + +/* smpboot.c */ + +cpumask_t cpu_online_map; +cpumask_t cpu_present_map; +cpumask_t cpu_possible_map; + +/* ID of the PCPU we're running on */ +DEFINE_PER_CPU(unsigned int, cpu_id); +/* XXX these seem awfully x86ish... */ +/* representing HT siblings of each logical CPU */ +DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_mask); +/* representing HT and core siblings of each logical CPU */ +DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_mask); + +nodemask_t __read_mostly node_online_map = { { [0] = 1UL } }; + +/* + * max_page is defined in page_alloc.c which isn't complied for now. + * definition of max_page will be remove as soon as page_alloc is built. + */ +unsigned long __read_mostly max_page; + +/* time.c */ + +unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ + +s_time_t get_s_time(void) +{ + BUG_ON("unimplemented"); +} + +int reprogram_timer(s_time_t timeout) +{ + BUG_ON("unimplemented"); +} + +void send_timer_event(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void domain_set_time_offset(struct domain *d, int64_t time_offset_seconds) +{ + BUG_ON("unimplemented"); +} + +/* shutdown.c */ + +void machine_restart(unsigned int delay_millisecs) +{ + BUG_ON("unimplemented"); +} + +void machine_halt(void) +{ + BUG_ON("unimplemented"); +} + +/* domctl.c */ + +long arch_do_domctl(struct xen_domctl *domctl, struct domain *d, + XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) +{ + BUG_ON("unimplemented"); +} + +void arch_get_domain_info(const struct domain *d, + struct xen_domctl_getdomaininfo *info) +{ + BUG_ON("unimplemented"); +} + +void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) +{ + BUG_ON("unimplemented"); +} + +/* monitor.c */ + +int arch_monitor_domctl_event(struct domain *d, + struct xen_domctl_monitor_op *mop) +{ + BUG_ON("unimplemented"); +} + +/* smp.c */ + +void arch_flush_tlb_mask(const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +void smp_send_event_check_mask(const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +void smp_send_call_function_mask(const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +/* irq.c */ + +struct pirq *alloc_pirq_struct(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +int pirq_guest_bind(struct vcpu *v, struct pirq *pirq, int will_share) +{ + BUG_ON("unimplemented"); +} + +void pirq_guest_unbind(struct domain *d, struct pirq *pirq) +{ + BUG_ON("unimplemented"); +} + +void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +hw_irq_controller no_irq_type = { + .typename = "none", + .startup = irq_startup_none, + .shutdown = irq_shutdown_none, + .enable = irq_enable_none, + .disable = irq_disable_none, +}; + +int arch_init_one_irq_desc(struct irq_desc *desc) +{ + BUG_ON("unimplemented"); +} + +void smp_send_state_dump(unsigned int cpu) +{ + BUG_ON("unimplemented"); +} + +/* domain.c */ + +DEFINE_PER_CPU(struct vcpu *, curr_vcpu); +unsigned long __per_cpu_offset[NR_CPUS]; + +void context_switch(struct vcpu *prev, struct vcpu *next) +{ + BUG_ON("unimplemented"); +} + +void continue_running(struct vcpu *same) +{ + BUG_ON("unimplemented"); +} + +void sync_local_execstate(void) +{ + BUG_ON("unimplemented"); +} + +void sync_vcpu_execstate(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void startup_cpu_idle_loop(void) +{ + BUG_ON("unimplemented"); +} + +void free_domain_struct(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void dump_pageframe_info(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void free_vcpu_struct(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +int arch_vcpu_create(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void arch_vcpu_destroy(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_switch_to_aarch64_mode(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) +{ + BUG_ON("unimplemented"); +} + +int arch_domain_create(struct domain *d, + struct xen_domctl_createdomain *config, + unsigned int flags) +{ + BUG_ON("unimplemented"); +} + +int arch_domain_teardown(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_destroy(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_shutdown(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_pause(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_unpause(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +int arch_domain_soft_reset(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_creation_finished(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c) +{ + BUG_ON("unimplemented"); +} + +int arch_initialise_vcpu(struct vcpu *v, XEN_GUEST_HANDLE_PARAM(void) arg) +{ + BUG_ON("unimplemented"); +} + +int arch_vcpu_reset(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +int domain_relinquish_resources(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_dump_domain_info(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_dump_vcpu_info(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_mark_events_pending(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_update_evtchn_irq(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_block_unless_event_pending(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_kick(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +struct domain *alloc_domain_struct(void) +{ + BUG_ON("unimplemented"); +} + +struct vcpu *alloc_vcpu_struct(const struct domain *d) +{ + BUG_ON("unimplemented"); +} + +unsigned long +hypercall_create_continuation(unsigned int op, const char *format, ...) +{ + BUG_ON("unimplemented"); +} + +int __init parse_arch_dom0_param(const char *s, const char *e) +{ + BUG_ON("unimplemented"); +} + +/* guestcopy.c */ + +unsigned long raw_copy_to_guest(void *to, const void *from, unsigned int len) +{ + BUG_ON("unimplemented"); +} + +unsigned long raw_copy_from_guest(void *to, const void __user *from, + unsigned int len) +{ + BUG_ON("unimplemented"); +} + +/* sysctl.c */ + +long arch_do_sysctl(struct xen_sysctl *sysctl, + XEN_GUEST_HANDLE_PARAM(xen_sysctl_t) u_sysctl) +{ + BUG_ON("unimplemented"); +} + +void arch_do_physinfo(struct xen_sysctl_physinfo *pi) +{ + BUG_ON("unimplemented"); +} + +/* p2m.c */ + +int arch_set_paging_mempool_size(struct domain *d, uint64_t size) +{ + BUG_ON("unimplemented"); +} + +int unmap_mmio_regions(struct domain *d, + gfn_t start_gfn, + unsigned long nr, + mfn_t mfn) +{ + BUG_ON("unimplemented"); +} + +int map_mmio_regions(struct domain *d, + gfn_t start_gfn, + unsigned long nr, + mfn_t mfn) +{ + BUG_ON("unimplemented"); +} + +int set_foreign_p2m_entry(struct domain *d, const struct domain *fd, + unsigned long gfn, mfn_t mfn) +{ + BUG_ON("unimplemented"); +} + +/* Return the size of the pool, in bytes. */ +int arch_get_paging_mempool_size(struct domain *d, uint64_t *size) +{ + BUG_ON("unimplemented"); +} + +/* delay.c */ + +void udelay(unsigned long usecs) +{ + BUG_ON("unimplemented"); +} + +/* guest_access.h */ + +static inline unsigned long raw_clear_guest(void *to, unsigned int len) +{ + BUG_ON("unimplemented"); +} + +/* smpboot.c */ + +int __cpu_up(unsigned int cpu) +{ + BUG_ON("unimplemented"); +} + +void __cpu_disable(void) +{ + BUG_ON("unimplemented"); +} + +void __cpu_die(unsigned int cpu) +{ + BUG_ON("unimplemented"); +} + +/* + * The following functions are defined in common/irq.c, but common/irq.c isn't + * built for now. These changes will be removed there when common/irq.c is + * ready. + */ + +void cf_check irq_actor_none(struct irq_desc *desc) +{ + BUG_ON("unimplemented"); +} + +unsigned int cf_check irq_startup_none(struct irq_desc *desc) +{ + BUG_ON("unimplemented"); + + return 0; +} diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index ccd3593f5a..5415cf8d90 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -4,6 +4,10 @@ * * RISC-V Trap handlers */ + +#include +#include + #include #include @@ -11,3 +15,24 @@ void do_trap(struct cpu_user_regs *cpu_regs) { die(); } + +void vcpu_show_execution_state(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void show_execution_state(const struct cpu_user_regs *regs) +{ + printk("implement show_execution_state(regs)\n"); +} + +void arch_hypercall_tasklet_result(struct vcpu *v, long res) +{ + BUG_ON("unimplemented"); +} + +enum mc_disposition arch_do_multicall_call(struct mc_state *state) +{ + BUG_ON("unimplemented"); + return mc_continue; +} From patchwork Fri May 17 13:55:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13667040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 713ACC25B7B for ; Fri, 17 May 2024 13:55:34 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.724192.1129468 (Exim 4.92) (envelope-from ) id 1s7y3R-0004lt-1o; Fri, 17 May 2024 13:55:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 724192.1129468; Fri, 17 May 2024 13:55:24 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3Q-0004h1-6t; Fri, 17 May 2024 13:55:24 +0000 Received: by outflank-mailman (input) for mailman id 724192; Fri, 17 May 2024 13:55:22 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3N-0001sq-KR for xen-devel@lists.xenproject.org; Fri, 17 May 2024 13:55:21 +0000 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [2a00:1450:4864:20::52d]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 1913a501-1455-11ef-b4bb-af5377834399; Fri, 17 May 2024 15:55:19 +0200 (CEST) Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-571ba432477so5469260a12.1 for ; Fri, 17 May 2024 06:55:19 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a179c81b4sm1117456466b.113.2024.05.17.06.55.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 06:55:18 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 1913a501-1455-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715954119; x=1716558919; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UdmrjijEC2ETr1rKEtwKxNjLUtWchNNAW7Shb3Uh3Pk=; b=FmfbrQDOXUAVP205ADDm0zHkwd0z1HGKQll7Fmt+CrBCNFCy0JJx4LDRcR/2hWmvSe 4GDemVEUSfzoXCRg01fIZi2LieS36UjI8koO6zX9Acv0nJz7prdQAbkhqyCUoEEehi/f t/XopJz2y/89mncWwwYPy88IAJhm02onNvMXzGQddJ+Wg5pD9q/uxC3epkhdSgkiJ1NK xKgB3IA2ONN86sgc0o4KWtPh050/R2lknrLarGguzDoephZbHCjLa9nPPl8vS/8kBms5 6m4RV9l0CN91BSkphw7HYRP+as28kBpmQWiMjqh9Fhfi7NUYbqWUXs/IKQiw0EQaDp8a bn3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715954119; x=1716558919; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UdmrjijEC2ETr1rKEtwKxNjLUtWchNNAW7Shb3Uh3Pk=; b=LkBqNyLsUqhzUO9y64Zro+jhwwMMcnct/ajuy9xSrHx1Dn9LqZB+ESJ6dmUQvakX9k jc724cRa1n+sYt1zVV6KXvh/xAyHlaiQJfmVFIW1D4L8jfGg58w4UXvTbjwCqqN4WPgJ bF/ZYZXW0Xu9vi3QoS8iTSFDOaOdP2xu1dBAWqdrdW+M5rclCys5zxiZ9c1ESldC8spF no1H/s3E0i1X8SvsjYlvOEeVEl1z8gvU2QflBGrvxYSxVdgMGRrt0zSqroJLJNVQssWk CtfnS0dl3lZmvL2GBCsgOLwLmDkMGJIBn88sF0wWZF9IsdxQe0lsf+cZiE3JmlDoNxxf 0cog== X-Gm-Message-State: AOJu0Yx8TckBoUErKjNe2vST6/zvFcLCALGw/fQ2BzCqqGYSLzYGzA5T Ar1iXzlumTDPG+Kpvk5/6XBaZMseVtbLqL+YV9VOoGrqHCW4NtrERE+DTSu9 X-Google-Smtp-Source: AGHT+IHq3shkhryXGz9XXJbte1obJO0HoEvZW7GV+zdjdgt1z8nh7+hS9zDS82ax8/7rp4mc1dsXZQ== X-Received: by 2002:a17:906:9e08:b0:a5a:8b17:d851 with SMTP id a640c23a62f3a-a5a8b17db00mr585229966b.20.1715954119103; Fri, 17 May 2024 06:55:19 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v10 13/14] xen/riscv: enable full Xen build Date: Fri, 17 May 2024 15:55:02 +0200 Message-ID: X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- Changes in V5-V10: - Nothing changed. Only rebase. --- Changes in V4: - drop stubs for irq_actor_none() and irq_actor_none() as common/irq.c is compiled now. - drop defintion of max_page in stubs.c as common/page_alloc.c is compiled now. - drop printk() related changes in riscv/early_printk.c as common version will be used. --- Changes in V3: - Reviewed-by: Jan Beulich - unrealted change dropped in tiny64_defconfig --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/Makefile | 16 +++- xen/arch/riscv/arch.mk | 4 - xen/arch/riscv/early_printk.c | 168 ---------------------------------- xen/arch/riscv/stubs.c | 24 ----- 4 files changed, 15 insertions(+), 197 deletions(-) diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 60afbc0ad9..81b77b13d6 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -12,10 +12,24 @@ $(TARGET): $(TARGET)-syms $(OBJCOPY) -O binary -S $< $@ $(TARGET)-syms: $(objtree)/prelink.o $(obj)/xen.lds - $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) -o $@ + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(objtree)/common/symbols-dummy.o -o $(dot-target).0 + $(NM) -pa --format=sysv $(dot-target).0 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).0.S + $(MAKE) $(build)=$(@D) $(dot-target).0.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(dot-target).0.o -o $(dot-target).1 + $(NM) -pa --format=sysv $(dot-target).1 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).1.S + $(MAKE) $(build)=$(@D) $(dot-target).1.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) \ + $(dot-target).1.o -o $@ $(NM) -pa --format=sysv $@ \ | $(objtree)/tools/symbols --all-symbols --xensyms --sysv --sort \ > $@.map + rm -f $(@D)/.$(@F).[0-9]* $(obj)/xen.lds: $(src)/xen.lds.S FORCE $(call if_changed_dep,cpp_lds_S) diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk index 8c071aff65..17827c302c 100644 --- a/xen/arch/riscv/arch.mk +++ b/xen/arch/riscv/arch.mk @@ -38,7 +38,3 @@ extensions := $(subst $(space),,$(extensions)) # -mcmodel=medlow would force Xen into the lower half. CFLAGS += $(riscv-generic-flags)$(extensions) -mstrict-align -mcmodel=medany - -# TODO: Drop override when more of the build is working -override ALL_OBJS-y = arch/$(SRCARCH)/built_in.o -override ALL_LIBS-y = diff --git a/xen/arch/riscv/early_printk.c b/xen/arch/riscv/early_printk.c index 60742a042d..610c814f54 100644 --- a/xen/arch/riscv/early_printk.c +++ b/xen/arch/riscv/early_printk.c @@ -40,171 +40,3 @@ void early_printk(const char *str) str++; } } - -/* - * The following #if 1 ... #endif should be removed after printk - * and related stuff are ready. - */ -#if 1 - -#include -#include - -/** - * strlen - Find the length of a string - * @s: The string to be sized - */ -size_t (strlen)(const char * s) -{ - const char *sc; - - for (sc = s; *sc != '\0'; ++sc) - /* nothing */; - return sc - s; -} - -/** - * memcpy - Copy one area of memory to another - * @dest: Where to copy to - * @src: Where to copy from - * @count: The size of the area. - * - * You should not use this function to access IO space, use memcpy_toio() - * or memcpy_fromio() instead. - */ -void *(memcpy)(void *dest, const void *src, size_t count) -{ - char *tmp = (char *) dest, *s = (char *) src; - - while (count--) - *tmp++ = *s++; - - return dest; -} - -int vsnprintf(char* str, size_t size, const char* format, va_list args) -{ - size_t i = 0; /* Current position in the output string */ - size_t written = 0; /* Total number of characters written */ - char* dest = str; - - while ( format[i] != '\0' && written < size - 1 ) - { - if ( format[i] == '%' ) - { - i++; - - if ( format[i] == '\0' ) - break; - - if ( format[i] == '%' ) - { - if ( written < size - 1 ) - { - dest[written] = '%'; - written++; - } - i++; - continue; - } - - /* - * Handle format specifiers. - * For simplicity, only %s and %d are implemented here. - */ - - if ( format[i] == 's' ) - { - char* arg = va_arg(args, char*); - size_t arglen = strlen(arg); - - size_t remaining = size - written - 1; - - if ( arglen > remaining ) - arglen = remaining; - - memcpy(dest + written, arg, arglen); - - written += arglen; - i++; - } - else if ( format[i] == 'd' ) - { - int arg = va_arg(args, int); - - /* Convert the integer to string representation */ - char numstr[32]; /* Assumes a maximum of 32 digits */ - int numlen = 0; - int num = arg; - size_t remaining; - - if ( arg < 0 ) - { - if ( written < size - 1 ) - { - dest[written] = '-'; - written++; - } - - num = -arg; - } - - do - { - numstr[numlen] = '0' + num % 10; - num = num / 10; - numlen++; - } while ( num > 0 ); - - /* Reverse the string */ - for (int j = 0; j < numlen / 2; j++) - { - char tmp = numstr[j]; - numstr[j] = numstr[numlen - 1 - j]; - numstr[numlen - 1 - j] = tmp; - } - - remaining = size - written - 1; - - if ( numlen > remaining ) - numlen = remaining; - - memcpy(dest + written, numstr, numlen); - - written += numlen; - i++; - } - } - else - { - if ( written < size - 1 ) - { - dest[written] = format[i]; - written++; - } - i++; - } - } - - if ( size > 0 ) - dest[written] = '\0'; - - return written; -} - -void printk(const char *format, ...) -{ - static char buf[1024]; - - va_list args; - va_start(args, format); - - (void)vsnprintf(buf, sizeof(buf), format, args); - - early_printk(buf); - - va_end(args); -} - -#endif - diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index 8285bcffef..bda35fc347 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -24,12 +24,6 @@ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_mask); nodemask_t __read_mostly node_online_map = { { [0] = 1UL } }; -/* - * max_page is defined in page_alloc.c which isn't complied for now. - * definition of max_page will be remove as soon as page_alloc is built. - */ -unsigned long __read_mostly max_page; - /* time.c */ unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ @@ -419,21 +413,3 @@ void __cpu_die(unsigned int cpu) { BUG_ON("unimplemented"); } - -/* - * The following functions are defined in common/irq.c, but common/irq.c isn't - * built for now. These changes will be removed there when common/irq.c is - * ready. - */ - -void cf_check irq_actor_none(struct irq_desc *desc) -{ - BUG_ON("unimplemented"); -} - -unsigned int cf_check irq_startup_none(struct irq_desc *desc) -{ - BUG_ON("unimplemented"); - - return 0; -} From patchwork Fri May 17 13:55:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13667039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7CF4C25B79 for ; Fri, 17 May 2024 13:55:33 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.724193.1129474 (Exim 4.92) (envelope-from ) id 1s7y3R-00052t-Tm; Fri, 17 May 2024 13:55:25 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 724193.1129474; Fri, 17 May 2024 13:55:25 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3R-0004x6-9O; Fri, 17 May 2024 13:55:25 +0000 Received: by outflank-mailman (input) for mailman id 724193; Fri, 17 May 2024 13:55:22 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3N-0001cB-W4 for xen-devel@lists.xenproject.org; Fri, 17 May 2024 13:55:22 +0000 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [2a00:1450:4864:20::632]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 19807cb0-1455-11ef-909e-e314d9c70b13; Fri, 17 May 2024 15:55:20 +0200 (CEST) Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-a5a88339780so485649266b.0 for ; Fri, 17 May 2024 06:55:20 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a179c81b4sm1117456466b.113.2024.05.17.06.55.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 06:55:19 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 19807cb0-1455-11ef-909e-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715954120; x=1716558920; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mXA5k6NQLwnOQ/WhnpaidF2ChH86fmHaLKiU9LUuBe8=; b=Ny2NfuAP0b+VTowOJHcipcbTCVUJ61xXsSivrVxuKUTavxM7ysV4jHVRs6JvvwEKsc ME3oLmKCCV75UtBFm4NjtV6h9+N5jGMEvgnVCwsGh9DO5S8gX63bLm946V9c7dcfelOQ 0ZX27WqdANfuyLHp04z9dQy+bxGjoh3Fo9gXkfpH/eG/5M9fPo/F07wu7gTir07AAHxA rhyIFp5eoufHyjQAjTlUNThUWUtRA57Ycd06GLphJx2ntp67tRNBiiYsm7Uj5crCieUy 8XpeQNvb+wA/3eG76IHWMw68lt6DBbRiE7ePeBu61B8lE2TM4nb1dfmwBvOd2ntXIHPy d6dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715954120; x=1716558920; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mXA5k6NQLwnOQ/WhnpaidF2ChH86fmHaLKiU9LUuBe8=; b=l6f8XEMRO231x/Nfy2L66O1lRLFYO8W3C5i5hY/7j1znlIiXJnLBWU5kgohlrBB8Js DOER3eJJ5iVNQ2uMpIwKGdPW0x5OjVXFgyQTDVp6x0zcNidvW95O+HlJNBdm6haOD+Kz 3BcM1pony+aB52+uxz4sKsNrhbKLWR9faZWh7GIKKdVOmvDWdZNbNsVucZvnd9DIkkK3 QLZ3ZNxCNzWwkT7g09ArdfKqhrT9QpYXkxtUlkESRkuU7IsBlOGv2G21AyLG9y9aaaMd tKPXQeTMsHjJWBUlMtFAJI8qvR+4GiE/y5k74BoIQOvFpOb90eEpmkGPjZ73uwK43Xwj 1b4w== X-Gm-Message-State: AOJu0Yx5Xu9wpOKCbWchFQf5MIfpFDHvMH5g/LnLlxq/EeK6Bd4On/ZR EYlFSNtNCCdzx+Zn48+Hm+PqG4aRV02XRXcp+6QKNpGrit8MFdckagHUPnp7 X-Google-Smtp-Source: AGHT+IFlHn4riCAoAVLptslFcHSUF8D7d/Mhu9kIX5sx5rf7ZnlKWhXQQk9IqqGNWbsXrS264cWyuw== X-Received: by 2002:a17:906:57cf:b0:a59:c963:82b with SMTP id a640c23a62f3a-a5a2d5cffe2mr1330690966b.33.1715954119886; Fri, 17 May 2024 06:55:19 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v10 14/14] xen/README: add compiler and binutils versions for RISC-V64 Date: Fri, 17 May 2024 15:55:03 +0200 Message-ID: X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 This patch doesn't represent a strict lower bound for GCC and GNU Binutils; rather, these versions are specifically employed by the Xen RISC-V container and are anticipated to undergo continuous testing. Older GCC and GNU Binutils would work, but this is not a guarantee. While it is feasible to utilize Clang, it's important to note that, currently, there is no Xen RISC-V CI job in place to verify the seamless functioning of the build with Clang. Signed-off-by: Oleksii Kurochko --- Changes in V5-V10: - Nothing changed. Only rebase. --- Changes in V6: - update the message in README. --- Changes in V5: - update the commit message and README file with additional explanation about GCC and GNU Binutils version. Additionally, it was added information about Clang. --- Changes in V4: - Update version of GCC (12.2) and GNU Binutils (2.39) to the version which are in Xen's contrainter for RISC-V --- Changes in V3: - new patch --- README | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/README b/README index c8a108449e..30da5ff9c0 100644 --- a/README +++ b/README @@ -48,6 +48,10 @@ provided by your OS distributor: - For ARM 64-bit: - GCC 5.1 or later - GNU Binutils 2.24 or later + - For RISC-V 64-bit: + - GCC 12.2 or later + - GNU Binutils 2.39 or later + Older GCC and GNU Binutils would work, but this is not a guarantee. * POSIX compatible awk * Development install of zlib (e.g., zlib-dev) * Development install of Python 2.7 or later (e.g., python-dev)