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Mon, 20 May 2024 05:24:01 -0700 From: Sameer Pujar To: , , CC: , , , , , Subject: [PATCH 1/2] dt-bindings: dma: Add reg-names to nvidia,tegra210-adma Date: Mon, 20 May 2024 12:23:50 +0000 Message-ID: <20240520122351.1691058-2-spujar@nvidia.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240520122351.1691058-1-spujar@nvidia.com> References: <20240520122351.1691058-1-spujar@nvidia.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FA:EE_|DS0PR12MB8564:EE_ X-MS-Office365-Filtering-Correlation-Id: 62ce93a7-91b7-4546-6092-08dc78c7c33d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|82310400017|36860700004|376005; X-Microsoft-Antispam-Message-Info: HpGCMZzLzQ7xfY7O7QLps/loH9YKFOo7L3+WiBwrc6VEDX2cdv5ud0khOo3ejqoO+Y2duRH8lAwsUOK12w1CtZKfiW3MImgiHU0IHTmCFk4cWqU7JP8eRrAudQ+B7h5BgGeWLBrARofEVM/6Rb+D4ksING/bbPKe/8rvPGKXqG+HbmfVaWl3WlyJMETZI/kGmD1Ln5zTdSi6OXxSOgJjpNTpjchwiW1mJ8rFPXZVH/V3vaLuhDU8SFuFB5gzcKG3fZEXu81W9GAEL1lJAd3SKbrFXHYbNmUpYx9nvOnfEkKBR/oLNp/l40MgNyFwKQU0hYk+bnPRb3kedOyNYi3jRAQqpejL4VdAFYaOh52VpzU6E+fSAiyY4O7sh/f4XxbOmOCXMWEOEl2l3YNITCBCbvHqibDo3w9+8AMLMHca5pkZ46AkgDfTpLqpfLRfBxQ0gEljgAB74yuTU5n36Sb8sEaFw3l2jaUYKbBOdWFKHiHFYlrMC9j4co2vPbL3IEjywpquUqpyqgD1m0iKO2LzlSDxX5t/rJqod//yrg/AfONFbZvQs09qEkmed3jdufewq8Sa5CR+I0YgImSI0t2SGN5kjwrE2AbLeq8+9/akXdzTzFi9fl4cY0cN68OkCFlgSu20yKCKaqc+35PVBSRi/AOjeMp88m2AcQ3T41vkMiOsh3J+KrEIjyg9llH9ErolCJaFnjgalSljeVlKUgJ6hd67+NepX1y41x7kMg2I6ABxawCzDdXcoTePgXdfuHB9hzMhlcQhHCFKpXk4uLKq7k18+1n/VLZ6+o0CAlG6cQgaDLHwLTUcpQyFePcyOI+StX0nu3iRGEOITt1s9ro62fPZdFE4qylOGPl5WX7ahwrp9iVyFPGph5YlyY2xwGV9GAvLxfQ3tnVgTBWAgxSwm7b95mS3udIAxjWdGh8ajhDqfslOmmq+OUTa8Sjg3rlIRKyHx1z0UsNGErOSiKwK+tI5EuWOfxii3YP7VCa7FsFhYdmwPCx0aBSo++COSQ76kqz8ocJutJ0v1YVRtECBeGqUBGjmFwxtW6Pl1galfn+sCR/Od2hhgX7rcYC/F5vbHpTGFg3yUwCYvZLUKN4o6Gb0SLIIL/ujD4+S8WSZguNmWsITcr6Y0sjCZA6m/ZvZf1YWJxp+F1nF0VqDSyF5axFyutG01Sgl/CpyPQ0tueNXoeivWfUDoVi2bmDS5+kp/8EVThvxhUgVfvPJwJfaBs6n6+4CKuqLzRuPF+/wjx8MKcEToaqLHKcnyuVjQBGfSrkrLAm2hyQbcgUc0NMxnL0W692ybZTRcLB54fkavGDQwU9hnMzuBmyJxg8uMOXVt8P6EnzReyOM0G8g9o+R+UyIZpTQKzEZn1aXDFG5H00iak4p0tUzyFQWH27A9/us X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(1800799015)(82310400017)(36860700004)(376005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2024 12:24:14.7609 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 62ce93a7-91b7-4546-6092-08dc78c7c33d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FA.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8564 From: Mohan Kumar For Non-Hypervisor mode, Tegra ADMA driver requires the register resource range to include both global and channel page in the reg entry. For Hypervisor more, Tegra ADMA driver requires only the channel page and global page range is not allowed for access. Add reg-names DT binding for Hypervisor mode to help driver to differentiate the config between Hypervisor and Non-Hypervisor mode of execution. Signed-off-by: Mohan Kumar Signed-off-by: Sameer Pujar --- .../devicetree/bindings/dma/nvidia,tegra210-adma.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index 877147e95ecc..ede47f4a3eec 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -29,8 +29,18 @@ properties: - const: nvidia,tegra186-adma reg: + description: | + For hypervisor mode, the address range should include a + ADMA channel page address range, for non-hypervisor mode + it starts with ADMA base address covering Global and Channel + page address range. maxItems: 1 + reg-names: + description: only required for Hypervisor mode. + items: + - const: vm + interrupts: description: | Should contain all of the per-channel DMA interrupts in From patchwork Mon May 20 12:23:51 2024 Content-Type: text/plain; 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Mon, 20 May 2024 05:24:01 -0700 From: Sameer Pujar To: , , CC: , , , , , Subject: [PATCH 2/2] dmaengine: tegra210-adma: Add support for ADMA virtualization Date: Mon, 20 May 2024 12:23:51 +0000 Message-ID: <20240520122351.1691058-3-spujar@nvidia.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240520122351.1691058-1-spujar@nvidia.com> References: <20240520122351.1691058-1-spujar@nvidia.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE32:EE_|CH3PR12MB7665:EE_ X-MS-Office365-Filtering-Correlation-Id: 88672170-7a75-44ae-f4a2-08dc78c7c55b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|1800799015|376005|82310400017; X-Microsoft-Antispam-Message-Info: m7LGPa0a+lSc87BFV/wTNcfU44c990iS4dsM4TurJ1EbUY/eLpwhiLOiktiH/0gVvpgdfcSset0Y3I4/mceq0awK1UC0jKuAty4FtaZb+BbHhGPC6eFMksaqTQUu9Ei0Gy7vBbEqCzssHkpuniGecyx5MDFb/eOnW6KIxpY0R4rTaDEAAxS2eNBsZCDnbU9WT+Bx6iavBseWSRtB+59FaEjdTHE8tC6DOTm+V1qRCqcHv5wr53QiRyC1LmjCs0qe0c6rU71FMcVncIphwMziUgi3l/u0hcKnAoV8ZYtU2Cn44dbJ/Db3Y6QGLIf2s393yQnrtmbG4f5A9KQCoXA+Dq1GGVlKI8KD1o/vdKx1PXMPPeuKxNmcsZe8JKiNrYlWULS3kZ9tsvyLnhSjCcCW8IaJPTfny0dS2RHbVRbGNh6xqFUSxIHAJNNlGgLbvBalJKQqUkLzE2yMpREJMIx+qi8pMy6Whl41aW3EZq2wB3yvZ2dyz4xnj5wFWr9r4rzbyMRHn78gK5CYdhk4YaWON0+p5dedEDXMOGCvDFquaeoBN02mfWTZwvl6i6awV+N+YzEaTCtoIl+KVR6QY/n0ZRrlPtqFpFOgeEqiQZ+BEVnxTQDmVc6I3W8aWNUjBq3+uVjxuRGqg/P5co4MFEUcWo99mTWW4KzewEttvlq3e+fWOqgrQCAeq+xxjHgfAKgSz4RRQIUHzz1NYcxatyr2rs0s5CmsRNyoiTh9vCh1z2WtDWoIhuoFZzLZ3VZveyMKuqxFx+Ozq+2HhMHTLeFu+DcGyp5EDHkvkIWYm/KaGvor4MuIPQcxVxrHKbg7SLs9ZBJVXded/X3ORmamnqi7jXjlVEci5f1xsKhwWlIzFEZIh35uVZntoH89aO+nFj3kIY1puMVtrxXzJ7Pldsuj5j1yXSqyul2oBm319/pwdxy8TDAGkrDdviZoEl3WljvEx/N2OQrBGOlfor2TPP1NdpPUAIx/lW5/fbXiycL+/CqYGueyNrDjeLpd5DsmonHdHH7Bxm+vZ+RyT1Ol1Peo8rJ6333Y9QD7AHbT+YTNd4b568XpbzP8OHq8lofHYxAwQhNfrr0mNYi0FTBJmyco4OafU3oBmD5rqSEW/QBh1d1baD+X0A/hekkOaw/pDQJYA43Q7kCi7BFmrpdqxngNhm/Jdu6s7ef4ZnLXWNdBU87N6YTFBMBhd8Gj07dup+COiOtIzDGwFPtjoRKhXnzRFrTYxb+V/yRycIvMmC5nL1boYf7BQ2ccrelve7Aiqi5+MNHLb+mNmynIm1j3bzhtMqMs38JQCUyS0LmOB+VbUHMaAhDQEWwUb2B/m4BjxeEoMnEZM+N1hYBHETTQ/VVNcD0HzgNvaYl3MRECjV117lY= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(1800799015)(376005)(82310400017);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2024 12:24:18.3619 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 88672170-7a75-44ae-f4a2-08dc78c7c55b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE32.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7665 From: Mohan Kumar Tegra ADMA HW supports multiple PAGES for virtualization, to support virtualization support reg-names property has been added to DT binding to know the hypervisor mode. Also in hypervisor mode the ADMA global registers are not accessed by guest OS. Signed-off-by: Mohan Kumar Signed-off-by: Sameer Pujar --- drivers/dma/tegra210-adma.c | 44 ++++++++++++++++++++++++++++++------- 1 file changed, 36 insertions(+), 8 deletions(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index 24ad7077c53b..92f1c0c949dd 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -160,6 +160,8 @@ struct tegra_adma { /* Used to store global command register state when suspending */ unsigned int global_cmd; + bool is_virtualized; + const struct tegra_adma_chip_data *cdata; /* Last member of the structure */ @@ -222,8 +224,15 @@ static int tegra_adma_init(struct tegra_adma *tdma) u32 status; int ret; - /* Clear any interrupts */ - tdma_write(tdma, tdma->cdata->ch_base_offset + tdma->cdata->global_int_clear, 0x1); + if (!tdma->is_virtualized) { + /* Clear any interrupts */ + tdma_write(tdma, tdma->cdata->ch_base_offset + tdma->cdata->global_int_clear, 0x1); + } else { + /* For virtualized mode, ADMA global registers are not accessed */ + tdma_write(tdma, tdma->cdata->global_int_clear, 0x1); + tdma->global_cmd = 1; + return 0; + } /* Assert soft reset */ tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1); @@ -736,7 +745,9 @@ static int __maybe_unused tegra_adma_runtime_suspend(struct device *dev) struct tegra_adma_chan *tdc; int i; - tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD); + if (!tdma->is_virtualized) + tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD); + if (!tdma->global_cmd) goto clk_disable; @@ -777,7 +788,9 @@ static int __maybe_unused tegra_adma_runtime_resume(struct device *dev) dev_err(dev, "ahub clk_enable failed: %d\n", ret); return ret; } - tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); + + if (!tdma->is_virtualized) + tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); if (!tdma->global_cmd) return 0; @@ -846,6 +859,8 @@ static int tegra_adma_probe(struct platform_device *pdev) { const struct tegra_adma_chip_data *cdata; struct tegra_adma *tdma; + unsigned int ch_base_offset; + struct resource *res; int ret, i; cdata = of_device_get_match_data(&pdev->dev); @@ -865,9 +880,22 @@ static int tegra_adma_probe(struct platform_device *pdev) tdma->nr_channels = cdata->nr_channels; platform_set_drvdata(pdev, tdma); - tdma->base_addr = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(tdma->base_addr)) - return PTR_ERR(tdma->base_addr); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm"); + if (res) { + tdma->base_addr = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(tdma->base_addr)) + return PTR_ERR(tdma->base_addr); + + tdma->is_virtualized = true; + ch_base_offset = 0; + } else { + tdma->base_addr = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tdma->base_addr)) + return PTR_ERR(tdma->base_addr); + + tdma->is_virtualized = false; + ch_base_offset = cdata->ch_base_offset; + } tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio"); if (IS_ERR(tdma->ahub_clk)) { @@ -900,7 +928,7 @@ static int tegra_adma_probe(struct platform_device *pdev) if (!test_bit(i, tdma->dma_chan_mask)) continue; - tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset + tdc->chan_addr = tdma->base_addr + ch_base_offset + (cdata->ch_reg_size * i); tdc->irq = of_irq_get(pdev->dev.of_node, i);