From patchwork Mon May 20 18:57:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668580 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63C52C04FFE for ; Mon, 20 May 2024 18:58:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CAB0010E17B; Mon, 20 May 2024 18:58:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="RJJOLmyr"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9FD1010E31E for ; Mon, 20 May 2024 18:58:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716231500; x=1747767500; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=cueiYG9zerXsrx8PgoBTPCzMVz0ZP7NFU/vgx+Vn1uQ=; b=RJJOLmyr5R9guMyHiaFVNG/TQ8Rg2NckuLLx4tvDw+c/5xyM6jL2GJOy 2NklAymMEtO0z3DJlNJwvzP8dFJiTBSuol0XVzYNzw+gXFc4i9YJiNj1E 63XLXpbSeBcLwFHFrilX6m6TtRDrkHep8E+pVDKEhtGNaHWs5NRc4yt61 pV3MnotLYm8D94PIkfBwwqpqxs5k/tkO/FSlZ2T/k4hqsqpE3zDt9k/0/ s/Fp0+nuViA70HqFKumFfXW9TPZDKfpIV8HZfi0/b/b8QpH7C5L+Vy052 ASukHHCWjapqKP5IlBh+XFXl2gN0OhpJf85519PQpNTV1CTuhpUTGIKsB w==; X-CSE-ConnectionGUID: xKucSsieR9mjicY1pBMBmw== X-CSE-MsgGUID: e0IoYxkTQACY5vVA0NO6Hw== X-IronPort-AV: E=McAfee;i="6600,9927,11078"; a="16218506" X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="16218506" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:20 -0700 X-CSE-ConnectionGUID: tE5ep867TDmnlAl6Y4wGdQ== X-CSE-MsgGUID: pHoJyMSOSaKT8D55YVxijg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213829" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:19 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 01/21] drm/i915/dp_mst: Align TUs to avoid splitting symbols across MTPs Date: Mon, 20 May 2024 21:57:59 +0300 Message-ID: <20240520185822.3725844-2-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Symbols consisting of multiple (4) TU timeslots may get split across MTPs when using 2 or 1 link lanes. Avoid this, as required by Bspec by aligning the allocated TUs to 2 when using 2 lanes and 4 when using 1 lane. Atm, we also have to align the PBNs used to allocate BW along the MST path, since DRM core keeps track of its own TU value, derived from the PBN and that TU value must match what the driver calculates. On some platforms the alignment is only required on 8b/10b links, a follow-up patch will remove the limitation for those. Bspec: 49266, 68922 Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 27 ++++++++++++++++++--- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index c772ba19c5477..c9c5d235744ab 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -207,6 +207,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, int remote_bw_overhead; int link_bpp_x16; int remote_tu; + fixed20_12 pbn; drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); @@ -237,11 +238,29 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, * crtc_state->dp_m_n.tu), provided that the driver doesn't * enable SSC on the corresponding link. */ - crtc_state->pbn = intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock, - link_bpp_x16, - remote_bw_overhead); + pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock, + link_bpp_x16, + remote_bw_overhead)); + remote_tu = DIV_ROUND_UP(pbn.full, mst_state->pbn_div.full); - remote_tu = DIV_ROUND_UP(dfixed_const(crtc_state->pbn), mst_state->pbn_div.full); + /* + * Aligning the TUs ensures that symbols consisting of multiple + * (4) symbol cycles don't get split between two consecutive + * MTPs, as required by Bspec. + * TODO: remove the alignment restriction for 128b/132b links + * on some platforms, where Bspec allows this. + */ + remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count); + + /* + * Also align PBNs accordingly, since MST core will derive its + * own copy of TU from the PBN in drm_dp_atomic_find_time_slots(). + * The above comment about the difference between the PBN + * allocated for the whole path and the TUs allocated for the + * first branch device's link also applies here. + */ + pbn.full = remote_tu * mst_state->pbn_div.full; + crtc_state->pbn = dfixed_trunc(pbn); drm_WARN_ON(&i915->drm, remote_tu < crtc_state->dp_m_n.tu); crtc_state->dp_m_n.tu = remote_tu; From patchwork Mon May 20 18:58:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668589 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5C580C25B77 for ; Mon, 20 May 2024 18:58:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 17E6010E572; Mon, 20 May 2024 18:58:36 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="AQ7VYida"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4FA7310E17B for ; Mon, 20 May 2024 18:58:21 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="37213837" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:20 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Jani Nikula Subject: [PATCH v2 02/21] drm/i915/dp: Move link train params to a substruct in intel_dp Date: Mon, 20 May 2024 21:58:00 +0300 Message-ID: <20240520185822.3725844-3-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For clarity move the link training parameters updated during link training based on the pass/fail LT result under a substruct in intel_dp. This prepares for later patches in this patchset adding similar params here. Rename intel_dp_reset_max_link_params() to intel_dp_reset_link_params() to better reflect what state gets reset. v2: Add the parameters to a more generic link substruct. (Jani) Cc: Jani Nikula Signed-off-by: Imre Deak --- .../drm/i915/display/intel_display_types.h | 13 ++++---- drivers/gpu/drm/i915/display/intel_dp.c | 30 +++++++++---------- 2 files changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 9678c2b157f6f..1e44a23ca2125 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1739,7 +1739,6 @@ struct intel_dp { u8 lane_count; u8 sink_count; bool link_trained; - bool reset_link_params; bool use_max_params; u8 dpcd[DP_RECEIVER_CAP_SIZE]; u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; @@ -1760,10 +1759,14 @@ struct intel_dp { /* intersection of source and sink rates */ int num_common_rates; int common_rates[DP_MAX_SUPPORTED_RATES]; - /* Max lane count for the current link */ - int max_link_lane_count; - /* Max rate for the current link */ - int max_link_rate; + struct { + /* TODO: move the rest of link specific fields to here */ + /* Max lane count for the current link */ + int max_lane_count; + /* Max rate for the current link */ + int max_rate; + } link; + bool reset_link_params; int mso_link_count; int mso_pixel_overlap; /* sink or branch descriptor */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c0a3b6d506817..ceedd3ef41946 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -372,13 +372,13 @@ int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) int intel_dp_max_lane_count(struct intel_dp *intel_dp) { - switch (intel_dp->max_link_lane_count) { + switch (intel_dp->link.max_lane_count) { case 1: case 2: case 4: - return intel_dp->max_link_lane_count; + return intel_dp->link.max_lane_count; default: - MISSING_CASE(intel_dp->max_link_lane_count); + MISSING_CASE(intel_dp->link.max_lane_count); return 1; } } @@ -644,7 +644,7 @@ static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, * boot-up. */ if (link_rate == 0 || - link_rate > intel_dp->max_link_rate) + link_rate > intel_dp->link.max_rate) return false; if (lane_count == 0 || @@ -705,8 +705,8 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, "Retrying Link training for eDP with same parameters\n"); return 0; } - intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1); - intel_dp->max_link_lane_count = lane_count; + intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index - 1); + intel_dp->link.max_lane_count = lane_count; } else if (lane_count > 1) { if (intel_dp_is_edp(intel_dp) && !intel_dp_can_link_train_fallback_for_edp(intel_dp, @@ -716,8 +716,8 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, "Retrying Link training for eDP with same parameters\n"); return 0; } - intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); - intel_dp->max_link_lane_count = lane_count >> 1; + intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); + intel_dp->link.max_lane_count = lane_count >> 1; } else { drm_err(&i915->drm, "Link Training Unsuccessful\n"); return -1; @@ -1382,7 +1382,7 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp) { int len; - len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); + len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate); return intel_dp_common_rate(intel_dp, len - 1); } @@ -3017,10 +3017,10 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp, intel_dp->lane_count = lane_count; } -static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp) +static void intel_dp_reset_link_params(struct intel_dp *intel_dp) { - intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); - intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); + intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp); + intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); } /* Enable backlight PWM and backlight PP control. */ @@ -3355,7 +3355,7 @@ void intel_dp_sync_state(struct intel_encoder *encoder, intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated); if (crtc_state) - intel_dp_reset_max_link_params(intel_dp); + intel_dp_reset_link_params(intel_dp); } bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, @@ -5889,7 +5889,7 @@ intel_dp_detect(struct drm_connector *connector, * supports link training fallback params. */ if (intel_dp->reset_link_params || intel_dp->is_mst) { - intel_dp_reset_max_link_params(intel_dp); + intel_dp_reset_link_params(intel_dp); intel_dp->reset_link_params = false; } @@ -6741,7 +6741,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, intel_dp_set_source_rates(intel_dp); intel_dp_set_common_rates(intel_dp); - intel_dp_reset_max_link_params(intel_dp); + intel_dp_reset_link_params(intel_dp); /* init MST on ports that can support it */ intel_dp_mst_encoder_init(dig_port, From patchwork Mon May 20 18:58:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668582 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 08AC6C25B77 for ; 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X-CSE-ConnectionGUID: B04njp9sTsWDqkqWknHX5A== X-CSE-MsgGUID: pLXj8/ZWT1a8N5MWpkDC6g== X-IronPort-AV: E=McAfee;i="6600,9927,11078"; a="16218513" X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="16218513" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:22 -0700 X-CSE-ConnectionGUID: Wv2mT8SQQFuxWXVpgI7fRg== X-CSE-MsgGUID: wVp4P31DQU6kIWBDXaLl2Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213839" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:21 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 03/21] drm/i915/dp: Move link train fallback to intel_dp_link_training.c Date: Mon, 20 May 2024 21:58:01 +0300 Message-ID: <20240520185822.3725844-4-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Move the functions used to reduce the link parameters during link training to intel_dp_link_training.c . Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä Reviewed-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_dp.c | 76 +------------------ drivers/gpu/drm/i915/display/intel_dp.h | 4 +- .../drm/i915/display/intel_dp_link_training.c | 73 ++++++++++++++++++ 3 files changed, 77 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index ceedd3ef41946..81e620dd33bb7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -329,7 +329,7 @@ static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, intel_dp->num_common_rates, max_rate); } -static int intel_dp_common_rate(struct intel_dp *intel_dp, int index) +int intel_dp_common_rate(struct intel_dp *intel_dp, int index) { if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm, index < 0 || index >= intel_dp->num_common_rates)) @@ -604,7 +604,7 @@ static int intersect_rates(const int *source_rates, int source_len, } /* return index of rate in rates array, or -1 if not found */ -static int intel_dp_rate_index(const int *rates, int len, int rate) +int intel_dp_rate_index(const int *rates, int len, int rate) { int i; @@ -654,78 +654,6 @@ static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, return true; } -static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, - int link_rate, - u8 lane_count) -{ - /* FIXME figure out what we actually want here */ - const struct drm_display_mode *fixed_mode = - intel_panel_preferred_fixed_mode(intel_dp->attached_connector); - int mode_rate, max_rate; - - mode_rate = intel_dp_link_required(fixed_mode->clock, 18); - max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count); - if (mode_rate > max_rate) - return false; - - return true; -} - -int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, - int link_rate, u8 lane_count) -{ - struct drm_i915_private *i915 = dp_to_i915(intel_dp); - int index; - - /* - * TODO: Enable fallback on MST links once MST link compute can handle - * the fallback params. - */ - if (intel_dp->is_mst) { - drm_err(&i915->drm, "Link Training Unsuccessful\n"); - return -1; - } - - if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with max parameters\n"); - intel_dp->use_max_params = true; - return 0; - } - - index = intel_dp_rate_index(intel_dp->common_rates, - intel_dp->num_common_rates, - link_rate); - if (index > 0) { - if (intel_dp_is_edp(intel_dp) && - !intel_dp_can_link_train_fallback_for_edp(intel_dp, - intel_dp_common_rate(intel_dp, index - 1), - lane_count)) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with same parameters\n"); - return 0; - } - intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index - 1); - intel_dp->link.max_lane_count = lane_count; - } else if (lane_count > 1) { - if (intel_dp_is_edp(intel_dp) && - !intel_dp_can_link_train_fallback_for_edp(intel_dp, - intel_dp_max_common_rate(intel_dp), - lane_count >> 1)) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with same parameters\n"); - return 0; - } - intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); - intel_dp->link.max_lane_count = lane_count >> 1; - } else { - drm_err(&i915->drm, "Link Training Unsuccessful\n"); - return -1; - } - - return 0; -} - u32 intel_dp_mode_to_fec_clock(u32 mode_clock) { return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR), diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index aad2223df2a35..e7b47e7bcd98b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -55,8 +55,6 @@ void intel_dp_connector_sync_state(struct intel_connector *connector, const struct intel_crtc_state *crtc_state); void intel_dp_set_link_params(struct intel_dp *intel_dp, int link_rate, int lane_count); -int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, - int link_rate, u8 lane_count); int intel_dp_get_active_pipes(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask); @@ -107,6 +105,8 @@ int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state); int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); int intel_dp_max_common_rate(struct intel_dp *intel_dp); int intel_dp_max_common_lane_count(struct intel_dp *intel_dp); +int intel_dp_common_rate(struct intel_dp *intel_dp, int index); +int intel_dp_rate_index(const int *rates, int len, int rate); void intel_dp_update_sink_caps(struct intel_dp *intel_dp); void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 947575140059d..4db293f256896 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -25,6 +25,7 @@ #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_link_training.h" +#include "intel_panel.h" #define LT_MSG_PREFIX "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] " #define LT_MSG_ARGS(_intel_dp, _dp_phy) (_intel_dp)->attached_connector->base.base.id, \ @@ -1091,6 +1092,78 @@ intel_dp_link_train_phy(struct intel_dp *intel_dp, return ret; } +static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, + int link_rate, + u8 lane_count) +{ + /* FIXME figure out what we actually want here */ + const struct drm_display_mode *fixed_mode = + intel_panel_preferred_fixed_mode(intel_dp->attached_connector); + int mode_rate, max_rate; + + mode_rate = intel_dp_link_required(fixed_mode->clock, 18); + max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count); + if (mode_rate > max_rate) + return false; + + return true; +} + +static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, + int link_rate, u8 lane_count) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + int index; + + /* + * TODO: Enable fallback on MST links once MST link compute can handle + * the fallback params. + */ + if (intel_dp->is_mst) { + drm_err(&i915->drm, "Link Training Unsuccessful\n"); + return -1; + } + + if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { + drm_dbg_kms(&i915->drm, + "Retrying Link training for eDP with max parameters\n"); + intel_dp->use_max_params = true; + return 0; + } + + index = intel_dp_rate_index(intel_dp->common_rates, + intel_dp->num_common_rates, + link_rate); + if (index > 0) { + if (intel_dp_is_edp(intel_dp) && + !intel_dp_can_link_train_fallback_for_edp(intel_dp, + intel_dp_common_rate(intel_dp, index - 1), + lane_count)) { + drm_dbg_kms(&i915->drm, + "Retrying Link training for eDP with same parameters\n"); + return 0; + } + intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index - 1); + intel_dp->link.max_lane_count = lane_count; + } else if (lane_count > 1) { + if (intel_dp_is_edp(intel_dp) && + !intel_dp_can_link_train_fallback_for_edp(intel_dp, + intel_dp_max_common_rate(intel_dp), + lane_count >> 1)) { + drm_dbg_kms(&i915->drm, + "Retrying Link training for eDP with same parameters\n"); + return 0; + } + intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); + intel_dp->link.max_lane_count = lane_count >> 1; + } else { + drm_err(&i915->drm, "Link Training Unsuccessful\n"); + return -1; + } + + return 0; +} + static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { From patchwork Mon May 20 18:58:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668584 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40670C25B77 for ; Mon, 20 May 2024 18:58:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 71FDC10E728; Mon, 20 May 2024 18:58:33 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="M93cye34"; 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d="scan'208";a="16218516" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:23 -0700 X-CSE-ConnectionGUID: K+f7vb7HQn6EJuX23QePfA== X-CSE-MsgGUID: 4CqAbXXRS5+QgxSAiLs1lw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213843" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:22 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 04/21] drm/i915/dp: Sanitize intel_dp_get_link_train_fallback_values() Date: Mon, 20 May 2024 21:58:02 +0300 Message-ID: <20240520185822.3725844-5-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Reduce the indentation in intel_dp_get_link_train_fallback_values() by adding separate helpers to reduce the link rate and lane count. Also simplify things by passing crtc_state to the function. This also prepares for later patches in the patchset adding a limitation on how the link params are reduced. Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä --- .../drm/i915/display/intel_dp_link_training.c | 82 ++++++++++++------- 1 file changed, 51 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 4db293f256896..edc970036866a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1109,11 +1109,37 @@ static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, return true; } +static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) +{ + int rate_index; + int new_rate; + + rate_index = intel_dp_rate_index(intel_dp->common_rates, + intel_dp->num_common_rates, + current_rate); + + if (rate_index <= 0) + return -1; + + new_rate = intel_dp_common_rate(intel_dp, rate_index - 1); + + return new_rate; +} + +static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count) +{ + if (current_lane_count > 1) + return current_lane_count >> 1; + + return -1; +} + static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, - int link_rate, u8 lane_count) + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - int index; + int new_link_rate; + int new_lane_count; /* * TODO: Enable fallback on MST links once MST link compute can handle @@ -1131,36 +1157,32 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, return 0; } - index = intel_dp_rate_index(intel_dp->common_rates, - intel_dp->num_common_rates, - link_rate); - if (index > 0) { - if (intel_dp_is_edp(intel_dp) && - !intel_dp_can_link_train_fallback_for_edp(intel_dp, - intel_dp_common_rate(intel_dp, index - 1), - lane_count)) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with same parameters\n"); - return 0; - } - intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index - 1); - intel_dp->link.max_lane_count = lane_count; - } else if (lane_count > 1) { - if (intel_dp_is_edp(intel_dp) && - !intel_dp_can_link_train_fallback_for_edp(intel_dp, - intel_dp_max_common_rate(intel_dp), - lane_count >> 1)) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with same parameters\n"); - return 0; - } - intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); - intel_dp->link.max_lane_count = lane_count >> 1; - } else { + new_lane_count = crtc_state->lane_count; + new_link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock); + if (new_link_rate < 0) { + new_lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count); + new_link_rate = intel_dp_max_common_rate(intel_dp); + } + + if (new_lane_count < 0) { drm_err(&i915->drm, "Link Training Unsuccessful\n"); return -1; } + if (intel_dp_is_edp(intel_dp) && + !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) { + drm_dbg_kms(&i915->drm, + "Retrying Link training for eDP with same parameters\n"); + return 0; + } + + drm_dbg_kms(&i915->drm, "Reducing link parameters from %dx%d to %dx%d\n", + crtc_state->lane_count, crtc_state->port_clock, + new_lane_count, new_link_rate); + + intel_dp->link.max_rate = new_link_rate; + intel_dp->link.max_lane_count = new_lane_count; + return 0; } @@ -1178,9 +1200,7 @@ static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed with HOBL active, not enabling it from now on\n"); intel_dp->hobl_failed = true; - } else if (intel_dp_get_link_train_fallback_values(intel_dp, - crtc_state->port_clock, - crtc_state->lane_count)) { + } else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) { return; } From patchwork Mon May 20 18:58:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DCEDC04FFE for ; Mon, 20 May 2024 18:58:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C118B10E4F9; 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X-CSE-ConnectionGUID: qGbuQLftR7+XQ2kCXcKE4w== X-CSE-MsgGUID: pu0ufK+MR/az22APy36tag== X-IronPort-AV: E=McAfee;i="6600,9927,11078"; a="16218520" X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="16218520" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:24 -0700 X-CSE-ConnectionGUID: mTzJ+HEYQxmghLm0uhkp/Q== X-CSE-MsgGUID: RxHNm7KqS+i+nc5+nyhoAA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213845" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:23 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 05/21] drm/i915: Factor out function to modeset commit a set of pipes Date: Mon, 20 May 2024 21:58:03 +0300 Message-ID: <20240520185822.3725844-6-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Factor out a function to modeset commit a set of pipes, which a later patch will reuse for DP link retraining. Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 31 +----------------- drivers/gpu/drm/i915/display/intel_display.c | 34 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_display.h | 3 ++ 3 files changed, 38 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 3c3fc53376ce3..170ba01786cf8 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4441,35 +4441,6 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) return connector; } -static int modeset_pipe(struct drm_crtc *crtc, - struct drm_modeset_acquire_ctx *ctx) -{ - struct drm_atomic_state *state; - struct drm_crtc_state *crtc_state; - int ret; - - state = drm_atomic_state_alloc(crtc->dev); - if (!state) - return -ENOMEM; - - state->acquire_ctx = ctx; - to_intel_atomic_state(state)->internal = true; - - crtc_state = drm_atomic_get_crtc_state(state, crtc); - if (IS_ERR(crtc_state)) { - ret = PTR_ERR(crtc_state); - goto out; - } - - crtc_state->connectors_changed = true; - - ret = drm_atomic_commit(state); -out: - drm_atomic_state_put(state); - - return ret; -} - static int intel_hdmi_reset_link(struct intel_encoder *encoder, struct drm_modeset_acquire_ctx *ctx) { @@ -4539,7 +4510,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, * would be perfectly happy if were to just reconfigure * the SCDC settings on the fly. */ - return modeset_pipe(&crtc->base, ctx); + return intel_modeset_commit_pipes(dev_priv, BIT(crtc->pipe), ctx); } static enum intel_hotplug_state diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index cce1420fb5417..4edb1ede4a1b4 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5569,6 +5569,40 @@ int intel_modeset_all_pipes_late(struct intel_atomic_state *state, return 0; } +int intel_modeset_commit_pipes(struct drm_i915_private *i915, + u8 pipe_mask, + struct drm_modeset_acquire_ctx *ctx) +{ + struct drm_atomic_state *state; + struct intel_crtc *crtc; + int ret; + + state = drm_atomic_state_alloc(&i915->drm); + if (!state) + return -ENOMEM; + + state->acquire_ctx = ctx; + to_intel_atomic_state(state)->internal = true; + + for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) { + struct intel_crtc_state *crtc_state = + intel_atomic_get_crtc_state(state, crtc); + + if (IS_ERR(crtc_state)) { + ret = PTR_ERR(crtc_state); + goto out; + } + + crtc_state->uapi.connectors_changed = true; + } + + ret = drm_atomic_commit(state); +out: + drm_atomic_state_put(state); + + return ret; +} + /* * This implements the workaround described in the "notes" section of the mode * set sequence documentation. When going from no pipes or single pipe to diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 56d1c0e3e62cd..dfdc42cef8723 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -537,6 +537,9 @@ int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, const char *reason, u8 pipe_mask); int intel_modeset_all_pipes_late(struct intel_atomic_state *state, const char *reason); +int intel_modeset_commit_pipes(struct drm_i915_private *i915, + u8 pipe_mask, + struct drm_modeset_acquire_ctx *ctx); void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, struct intel_power_domain_mask *old_domains); void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, From patchwork Mon May 20 18:58:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668586 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 270A5C25B7A for ; Mon, 20 May 2024 18:58:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0A90210E751; Mon, 20 May 2024 18:58:34 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="OYdgqA+3"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3CE3610E572 for ; Mon, 20 May 2024 18:58:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716231505; x=1747767505; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ocZts2b03pi+cwATm6taC9FipPB+Jt6NEu9Uisy9P5U=; b=OYdgqA+3Cqik2bux7/oKph+RFhnaAdVuGrhxMNwM90Bwuzrt94Z6Dqjt KdApwM0nIRL9unTxkOnhAsZ4rfXuQAQLsRe/tR/vfsKwZlCQZ4loQ0vwH nx031hVBB4wIeyqWzFoNM2BJkyudq6SGmy4Dk5HuOwvyEreYBqY7F+mvx DqI9MR379hoou1Me2dMkFNsQOeNBWAVzDOYmupBFHMJJcpP09suOfUl7f Ql+HGwJWmzRfk05hZw29u6tEWOk41cqGd1/brOFhOW+X2oqPfcKhLm+RF gIRRB5C5bb8+WLUkYdaQ7ROXB1bBHKyuTVWFLnhItIMHLMsOl6trgnYS0 w==; X-CSE-ConnectionGUID: +8aQiJxIQJ65VGtOUIodAg== X-CSE-MsgGUID: QkKkro5yRkqf7slz9KEjmw== X-IronPort-AV: E=McAfee;i="6600,9927,11078"; a="16218522" X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="16218522" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:25 -0700 X-CSE-ConnectionGUID: FvhOTswoQrSC7arRVIqj4g== X-CSE-MsgGUID: kEYykyRwR0e3bjLwqZBJng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213847" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:24 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 06/21] drm/i915/dp: Use a commit modeset for link retraining MST links Date: Mon, 20 May 2024 21:58:04 +0300 Message-ID: <20240520185822.3725844-7-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Instead of direct calls to the link train functions, retrain the link via a commit modeset. The direct call means that the output port will be disabled/re-enabled while the rest of the pipeline (transcoder) is active, which doesn't seem to work on MST at least. It leads to underruns and black screen, presumedly because the transcoder is not disabled/re-enabled along the port. Leave switching to a commit modeset on SST for a later patchset, as that seems to work ok currently (though better to using a commit there too, due to the suppressed underruns). Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 81e620dd33bb7..120f7b420807b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5147,6 +5147,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_crtc *crtc; u8 pipe_mask; + bool mst_output = false; int ret; if (!intel_dp_is_connected(intel_dp)) @@ -5177,6 +5178,11 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { + mst_output = true; + break; + } + /* Suppress underruns caused by re-training */ intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); if (crtc_state->has_pch_encoder) @@ -5184,16 +5190,23 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, intel_crtc_pch_transcoder(crtc), false); } + /* TODO: use a modeset for SST as well. */ + if (mst_output) { + ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx); + + if (ret && ret != -EDEADLK) + drm_dbg_kms(&dev_priv->drm, + "[ENCODER:%d:%s] link retraining failed: %pe\n", + encoder->base.base.id, encoder->base.name, + ERR_PTR(ret)); + + return ret; + } + for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { const struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); - /* retrain on the MST master transcoder */ - if (DISPLAY_VER(dev_priv) >= 12 && - intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && - !intel_dp_mst_is_master_trans(crtc_state)) - continue; - intel_dp_check_frl_training(intel_dp); intel_dp_pcon_dsc_configure(intel_dp, crtc_state); intel_dp_start_link_train(intel_dp, crtc_state); From patchwork Mon May 20 18:58:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668590 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 15603C04FFE for ; Mon, 20 May 2024 18:58:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D53510E51E; Mon, 20 May 2024 18:58:38 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="AYFepQ2l"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3061510E5A5 for ; Mon, 20 May 2024 18:58:26 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="37213850" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:25 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 07/21] drm/i915/dp: Recheck link state after modeset Date: Mon, 20 May 2024 21:58:05 +0300 Message-ID: <20240520185822.3725844-8-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Recheck the link state after a passing link training, with a 2 sec delay to account for cases where the link goes bad following the link training and the sink doesn't report this via an HPD IRQ. The delayed work added here will be also used by a later patch after a failed link training to try to retrain the link with unchanged link params before reducing the link params. v2: Don't flush an uninitialized delayed work (on HDMI-only DDI ports). v3: Add the work to intel_digital_port instead of intel_dp. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/g4x_dp.c | 7 ++++ drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_ddi.h | 4 +++ .../drm/i915/display/intel_display_types.h | 3 ++ drivers/gpu/drm/i915/display/intel_dp.c | 1 + .../drm/i915/display/intel_dp_link_training.c | 12 +++++-- 6 files changed, 58 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 06ec04e667e32..4363e32a834df 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -20,6 +20,7 @@ #include "intel_dp_aux.h" #include "intel_dp_link_training.h" #include "intel_dpio_phy.h" +#include "intel_ddi.h" #include "intel_fifo_underrun.h" #include "intel_hdmi.h" #include "intel_hotplug.h" @@ -1241,6 +1242,10 @@ static bool ilk_digital_port_connected(struct intel_encoder *encoder) static void intel_dp_encoder_destroy(struct drm_encoder *encoder) { + struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); + + intel_ddi_flush_link_check_work(dig_port); + intel_dp_encoder_flush_work(encoder); drm_encoder_cleanup(encoder); @@ -1309,6 +1314,8 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, dig_port->aux_ch = AUX_CH_NONE; + intel_ddi_init_link_check_work(dig_port); + intel_connector = intel_connector_alloc(); if (!intel_connector) goto err_connector_alloc; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 170ba01786cf8..86358ec27e685 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4360,6 +4360,7 @@ static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) struct drm_i915_private *i915 = to_i915(encoder->dev); struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); + intel_ddi_flush_link_check_work(dig_port); intel_dp_encoder_flush_work(encoder); if (intel_encoder_is_tc(&dig_port->base)) intel_tc_port_cleanup(dig_port); @@ -4441,6 +4442,37 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) return connector; } +static void intel_ddi_link_check_work_fn(struct work_struct *work) +{ + struct intel_digital_port *dig_port = + container_of(work, typeof(*dig_port), check_link_work.work); + struct intel_encoder *encoder = &dig_port->base; + struct drm_modeset_acquire_ctx ctx; + int ret; + + intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) + if (dig_port->dp.attached_connector) + ret = intel_dp_retrain_link(encoder, &ctx); +} + +void intel_ddi_init_link_check_work(struct intel_digital_port *dig_port) +{ + INIT_DELAYED_WORK(&dig_port->check_link_work, intel_ddi_link_check_work_fn); +} + +void intel_ddi_flush_link_check_work(struct intel_digital_port *dig_port) +{ + cancel_delayed_work_sync(&dig_port->check_link_work); +} + +void intel_ddi_queue_link_check(struct intel_digital_port *dig_port, int delay_ms) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + + mod_delayed_work(i915->unordered_wq, + &dig_port->check_link_work, msecs_to_jiffies(delay_ms)); +} + static int intel_hdmi_reset_link(struct intel_encoder *encoder, struct drm_modeset_acquire_ctx *ctx) { @@ -4911,6 +4943,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, dig_port->aux_ch = AUX_CH_NONE; + intel_ddi_init_link_check_work(dig_port); + encoder = &dig_port->base; encoder->devdata = devdata; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index 434de7196875a..b67714483f3cc 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -15,6 +15,7 @@ struct intel_bios_encoder_data; struct intel_connector; struct intel_crtc; struct intel_crtc_state; +struct intel_digital_port; struct intel_dp; struct intel_dpll_hw_state; struct intel_encoder; @@ -53,6 +54,9 @@ void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, enum port port); +void intel_ddi_init_link_check_work(struct intel_digital_port *dig_port); +void intel_ddi_flush_link_check_work(struct intel_digital_port *dig_port); +void intel_ddi_queue_link_check(struct intel_digital_port *dig_port, int delay_ms); void intel_ddi_init(struct drm_i915_private *dev_priv, const struct intel_bios_encoder_data *devdata); bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 1e44a23ca2125..9317c1ae04efe 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1880,6 +1880,9 @@ struct intel_digital_port { struct intel_tc_port *tc; + /* Check and recover a bad link status on DP and HDMI ports. */ + struct delayed_work check_link_work; + /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */ struct mutex hdcp_mutex; /* the number of pipes using HDCP signalling out of this port */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 120f7b420807b..8da277f0c2735 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -75,6 +75,7 @@ #include "intel_hotplug_irq.h" #include "intel_lspcon.h" #include "intel_lvds.h" +#include "intel_modeset_lock.h" #include "intel_panel.h" #include "intel_pch_display.h" #include "intel_pps.h" diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index edc970036866a..ad1fbb150ff90 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -25,6 +25,7 @@ #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_link_training.h" +#include "intel_ddi.h" #include "intel_panel.h" #define LT_MSG_PREFIX "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] " @@ -1464,6 +1465,7 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); bool passed; /* @@ -1483,6 +1485,11 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, else passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); + if (passed) { + intel_ddi_queue_link_check(dig_port, 2000); + return; + } + /* * Ignore the link failure in CI * @@ -1495,13 +1502,12 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, * For test cases which rely on the link training or processing of HPDs * ignore_long_hpd flag can unset from the testcase. */ - if (!passed && i915->display.hotplug.ignore_long_hpd) { + if (i915->display.hotplug.ignore_long_hpd) { lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n"); return; } - if (!passed) - intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); + intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); } void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, From patchwork Mon May 20 18:58:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2823CC04FFE for ; Mon, 20 May 2024 18:58:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1724310E6D5; Mon, 20 May 2024 18:58:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="JI9t9fIz"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2845710E5CB for ; Mon, 20 May 2024 18:58:27 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="37213851" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:26 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 08/21] drm/i915/dp: Reduce link params only after retrying with unchanged params Date: Mon, 20 May 2024 21:58:06 +0300 Message-ID: <20240520185822.3725844-9-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Try to maintain the current link parameters by retrying the link training with unchanged link parameters before reducing these parameters (sending an uevent to userspace to retrain the link instead). Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_display_types.h | 2 ++ drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++ drivers/gpu/drm/i915/display/intel_dp_link_training.c | 8 ++++++++ 3 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 9317c1ae04efe..bde518c843468 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1765,6 +1765,8 @@ struct intel_dp { int max_lane_count; /* Max rate for the current link */ int max_rate; + /* Sequential link training failures after a passing LT */ + int seq_train_failures; } link; bool reset_link_params; int mso_link_count; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8da277f0c2735..7c824c5a13346 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2950,6 +2950,7 @@ static void intel_dp_reset_link_params(struct intel_dp *intel_dp) { intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp); intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); + intel_dp->link.seq_train_failures = 0; } /* Enable backlight PWM and backlight PP control. */ @@ -5056,6 +5057,9 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp) intel_dp->lane_count)) return false; + if (intel_dp->link.seq_train_failures) + return true; + /* Retrain if link not ok */ return !intel_dp_link_ok(intel_dp, link_status); } diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index ad1fbb150ff90..e804f0b801c02 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1486,10 +1486,13 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); if (passed) { + intel_dp->link.seq_train_failures = 0; intel_ddi_queue_link_check(dig_port, 2000); return; } + intel_dp->link.seq_train_failures++; + /* * Ignore the link failure in CI * @@ -1507,6 +1510,11 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, return; } + if (intel_dp->link.seq_train_failures < 2) { + intel_ddi_queue_link_check(dig_port, 0); + return; + } + intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); } From patchwork Mon May 20 18:58:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668597 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DCCBEC25B77 for ; Mon, 20 May 2024 18:58:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D6F3610E863; Mon, 20 May 2024 18:58:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="h22ZsXoi"; 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d="scan'208";a="16218533" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:28 -0700 X-CSE-ConnectionGUID: 3uYDKC1NT9m4yp5pD/WWaQ== X-CSE-MsgGUID: aRadFnmQQx6MdZuHYgE+mg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213855" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:27 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Imre Deak Subject: [PATCH v2 09/21] drm/i915/dp: Pass atomic state to link training function Date: Mon, 20 May 2024 21:58:07 +0300 Message-ID: <20240520185822.3725844-10-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Imre Deak The next patch adds sending a modeset-retry uevent after a link training failure to all MST connectors on link. This requires the atomic state, so pass it to intel_dp_start_link_train(). In case of SST where retraining still happens by calling this function directly instead of a modeset commit the atomic state is not available and NULL is passed instead. This is ok, since in this case the encoder's only DP connector is available from intel_dp->attached_connector not requiring the atomic state. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/g4x_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 4 +++- drivers/gpu/drm/i915/display/intel_dp_link_training.h | 4 +++- 5 files changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 4363e32a834df..0d7424a7581e6 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -707,7 +707,7 @@ static void intel_enable_dp(struct intel_atomic_state *state, intel_dp_configure_protocol_converter(intel_dp, pipe_config); intel_dp_check_frl_training(intel_dp); intel_dp_pcon_dsc_configure(intel_dp, pipe_config); - intel_dp_start_link_train(intel_dp, pipe_config); + intel_dp_start_link_train(state, intel_dp, pipe_config); intel_dp_stop_link_train(intel_dp, pipe_config); } diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 86358ec27e685..58e57a7704811 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2586,7 +2586,7 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) * (timeout after 800 us) */ - intel_dp_start_link_train(intel_dp, crtc_state); + intel_dp_start_link_train(state, intel_dp, crtc_state); /* 6.n Set DP_TP_CTL link training to Normal */ if (!is_trans_port_sync_mode(crtc_state)) @@ -2728,7 +2728,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) * (timeout after 800 us) */ - intel_dp_start_link_train(intel_dp, crtc_state); + intel_dp_start_link_train(state, intel_dp, crtc_state); /* 7.k Set DP_TP_CTL link training to Normal */ if (!is_trans_port_sync_mode(crtc_state)) @@ -2795,7 +2795,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, to_intel_connector(conn_state->connector), crtc_state); intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); - intel_dp_start_link_train(intel_dp, crtc_state); + intel_dp_start_link_train(state, intel_dp, crtc_state); if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && !is_trans_port_sync_mode(crtc_state)) intel_dp_stop_link_train(intel_dp, crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7c824c5a13346..1f0b7cceea2dc 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5214,7 +5214,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, intel_dp_check_frl_training(intel_dp); intel_dp_pcon_dsc_configure(intel_dp, crtc_state); - intel_dp_start_link_train(intel_dp, crtc_state); + intel_dp_start_link_train(NULL, intel_dp, crtc_state); intel_dp_stop_link_train(intel_dp, crtc_state); break; } diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index e804f0b801c02..4f60daa97407d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1453,6 +1453,7 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp, /** * intel_dp_start_link_train - start link training + * @state: Atomic state * @intel_dp: DP struct * @crtc_state: state for CRTC attached to the encoder * @@ -1461,7 +1462,8 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp, * fails. * After calling this function intel_dp_stop_link_train() must be called. */ -void intel_dp_start_link_train(struct intel_dp *intel_dp, +void intel_dp_start_link_train(struct intel_atomic_state *state, + struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h index 19836a8a4f904..f658230960333 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h @@ -8,6 +8,7 @@ #include +struct intel_atomic_state; struct intel_crtc_state; struct intel_dp; @@ -25,7 +26,8 @@ void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, void intel_dp_set_signal_levels(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy); -void intel_dp_start_link_train(struct intel_dp *intel_dp, +void intel_dp_start_link_train(struct intel_atomic_state *state, + struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); void intel_dp_stop_link_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); From patchwork Mon May 20 18:58:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668585 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0946C04FFE for ; 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X-CSE-ConnectionGUID: 2t/sgSbKTVOrUYtbm4KTvg== X-CSE-MsgGUID: uBs2pSFfTZe6CbKIIvohJw== X-IronPort-AV: E=McAfee;i="6600,9927,11078"; a="16218534" X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="16218534" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:29 -0700 X-CSE-ConnectionGUID: twU8fjw7TFe38e/sBREqkw== X-CSE-MsgGUID: /lbiinRlQt+snjhsWFnOtg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213859" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:28 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 10/21] drm/i915/dp: Send a link training modeset-retry uevent to all MST connectors Date: Mon, 20 May 2024 21:58:08 +0300 Message-ID: <20240520185822.3725844-11-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Send a modeset-retry uevent to all connectors in the same MST topology after a link training failure and reduction of the link parameters. This matches the way the same uevent is sent after a DP tunnel BW allocation failure. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dp.h | 1 - drivers/gpu/drm/i915/display/intel_dp_link_training.c | 9 +++++---- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 1f0b7cceea2dc..87f9f12814b93 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2791,7 +2791,7 @@ intel_dp_audio_compute_config(struct intel_encoder *encoder, intel_dp_is_uhbr(pipe_config); } -void intel_dp_queue_modeset_retry_work(struct intel_connector *connector) +static void intel_dp_queue_modeset_retry_work(struct intel_connector *connector) { struct drm_i915_private *i915 = to_i915(connector->base.dev); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index e7b47e7bcd98b..24777c035e2ad 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -44,7 +44,6 @@ bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state); int intel_dp_min_bpp(enum intel_output_format output_format); void intel_dp_init_modeset_retry_work(struct intel_connector *connector); -void intel_dp_queue_modeset_retry_work(struct intel_connector *connector); void intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 4f60daa97407d..97d499e4b6ef7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1187,10 +1187,11 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, return 0; } -static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, +static void intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state, + struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { - struct intel_connector *intel_connector = intel_dp->attached_connector; + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) { lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n"); @@ -1206,7 +1207,7 @@ static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, } /* Schedule a Hotplug Uevent to userspace to start modeset */ - intel_dp_queue_modeset_retry_work(intel_connector); + intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); } /* Perform the link training on all LTTPRs and the DPRX on a link. */ @@ -1517,7 +1518,7 @@ void intel_dp_start_link_train(struct intel_atomic_state *state, return; } - intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); + intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state); } void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, From patchwork Mon May 20 18:58:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668594 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4DA7C25B7B for ; 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X-CSE-ConnectionGUID: aV04ORIuQcmZneXtgGGynQ== X-CSE-MsgGUID: 0lsE14YOQQ+X7biULVkMPQ== X-IronPort-AV: E=McAfee;i="6600,9927,11078"; a="16218539" X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="16218539" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:30 -0700 X-CSE-ConnectionGUID: 0BzCdWoSQySAaBURfUqABg== X-CSE-MsgGUID: HDzFm2+xRbye6HtfEqa9Ww== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213861" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:29 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 11/21] drm/i915/dp: Use check link state work in the hotplug handler Date: Mon, 20 May 2024 21:58:09 +0300 Message-ID: <20240520185822.3725844-12-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Simplify things by retraining a DP link if a bad link is detected in the hotplug handler from the encoder's check link state work, similarly to how this is done after a modeset link training failure. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/g4x_dp.c | 20 +------------------- drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++++------ drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 1 + 4 files changed, 15 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 0d7424a7581e6..1f3b6b3956a1c 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -1160,9 +1160,7 @@ intel_dp_hotplug(struct intel_encoder *encoder, struct intel_connector *connector) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct drm_modeset_acquire_ctx ctx; enum intel_hotplug_state state; - int ret; if (intel_dp->compliance.test_active && intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { @@ -1173,23 +1171,7 @@ intel_dp_hotplug(struct intel_encoder *encoder, state = intel_encoder_hotplug(encoder, connector); - drm_modeset_acquire_init(&ctx, 0); - - for (;;) { - ret = intel_dp_retrain_link(encoder, &ctx); - - if (ret == -EDEADLK) { - drm_modeset_backoff(&ctx); - continue; - } - - break; - } - - drm_modeset_drop_locks(&ctx); - drm_modeset_acquire_fini(&ctx); - drm_WARN(encoder->base.dev, ret, - "Acquiring modeset locks failed with %i\n", ret); + intel_dp_check_link_state(intel_dp); /* * Keeping it consistent with intel_ddi_hotplug() and diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 58e57a7704811..ea24404724075 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4566,14 +4566,13 @@ intel_ddi_hotplug(struct intel_encoder *encoder, state = intel_encoder_hotplug(encoder, connector); if (!intel_tc_port_link_reset(dig_port)) { - intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) { - if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) + if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { + intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) ret = intel_hdmi_reset_link(encoder, &ctx); - else - ret = intel_dp_retrain_link(encoder, &ctx); + drm_WARN_ON(encoder->base.dev, ret); + } else { + intel_dp_check_link_state(intel_dp); } - - drm_WARN_ON(encoder->base.dev, ret); } /* diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 87f9f12814b93..ff4ed6bb520d8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5064,6 +5064,14 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp) return !intel_dp_link_ok(intel_dp, link_status); } +void intel_dp_check_link_state(struct intel_dp *intel_dp) +{ + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + + if (intel_dp_needs_link_retrain(intel_dp)) + intel_ddi_queue_link_check(dig_port, 0); +} + static bool intel_dp_has_connector(struct intel_dp *intel_dp, const struct drm_connector_state *conn_state) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 24777c035e2ad..3fa53ac601d58 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -57,6 +57,7 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp, int intel_dp_get_active_pipes(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask); +void intel_dp_check_link_state(struct intel_dp *intel_dp); int intel_dp_retrain_link(struct intel_encoder *encoder, struct drm_modeset_acquire_ctx *ctx); void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode); From patchwork Mon May 20 18:58:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668588 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 796A8C25B7B for ; Mon, 20 May 2024 18:58:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1AC2610E82E; Mon, 20 May 2024 18:58:36 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="16218541" X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="16218541" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:31 -0700 X-CSE-ConnectionGUID: WS4SIOqGTpmxGuL2CVdOPg== X-CSE-MsgGUID: YnY2JmGQRuCwEeYo/5MNrQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213864" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:30 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 12/21] drm/i915/dp: Use check link state work in the detect handler Date: Mon, 20 May 2024 21:58:10 +0300 Message-ID: <20240520185822.3725844-13-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Simplify things by retraining a DP link if a bad link is detected in the connector detect handler from the encoder's check link state work, similarly to how this is done after a modeset link training failure. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index ff4ed6bb520d8..70b00e5ae7ad7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5863,11 +5863,8 @@ intel_dp_detect(struct drm_connector *connector, * Some external monitors do not signal loss of link synchronization * with an IRQ_HPD, so force a link status check. */ - if (!intel_dp_is_edp(intel_dp)) { - ret = intel_dp_retrain_link(encoder, ctx); - if (ret) - return ret; - } + if (!intel_dp_is_edp(intel_dp)) + intel_dp_check_link_state(intel_dp); /* * Clearing NACK and defer counts to get their exact values From patchwork Mon May 20 18:58:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668592 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 89744C25B7A for ; Mon, 20 May 2024 18:58:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 82EBF10E894; Mon, 20 May 2024 18:58:39 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="QEzT2ag/"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 03CE410E572 for ; Mon, 20 May 2024 18:58:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716231512; x=1747767512; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=mIZuqHdMCoLYo4iyVRboxmbY3mSKHVSrEmFo29PhqCU=; b=QEzT2ag/hl7O0UcUtlrMgGWGYy93jAqt/QxBBu3bAOhjsIQSIxD/udk9 8fw52jnhFERS5igp5U3D3Q2Q5t7LVjJWp3+BLb7onM6aZNbEx+x9/Eg6N lgKw3EGCTwdU1x0PR0vy1SEPIBla63lkSybRwY6pmuJK/rqonu0xjqOx4 N3t6o9pa9CeCryY6rFGLiEzHcOIsRc1UFRSBa4Jl/l1nlNUkJXFyIonWj SK93jkH9nP64hjaLjbFmEdpkM+SGs5qwW8/MzgWHjGHzgDQITlDpiYyHR CTH6VKRy/1NlLmOg1105IY5IduXXOCB75U90GAJj03a9saXKFCW8hJUVO A==; X-CSE-ConnectionGUID: z0PP9EneSKC5P79vT1BWKw== X-CSE-MsgGUID: aA7GVUI8T0qaliXGHQlq/w== X-IronPort-AV: E=McAfee;i="6600,9927,11078"; a="16218543" X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="16218543" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:32 -0700 X-CSE-ConnectionGUID: CmwCdQZ8QnKLrr0wUEsfQw== X-CSE-MsgGUID: s7uA/LypQOGEsQ/GrqUxPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213871" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:31 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 13/21] drm/i915/dp: Use check link state work in the HPD IRQ handler Date: Mon, 20 May 2024 21:58:11 +0300 Message-ID: <20240520185822.3725844-14-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Simplify things by retraining a DP link if a bad link is detected in the HPD IRQ handler from the encoder's check link state work, similarly to how this is done after a modeset link training failure. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 70b00e5ae7ad7..b72dbd7becb74 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4950,6 +4950,7 @@ static bool intel_dp_check_mst_status(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); bool link_ok = true; bool reprobe_needed = false; @@ -4995,7 +4996,10 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr); } - return link_ok && !reprobe_needed; + if (!link_ok) + intel_ddi_queue_link_check(dig_port, 0); + + return !reprobe_needed; } static void @@ -5453,9 +5457,7 @@ intel_dp_short_pulse(struct intel_dp *intel_dp) /* Handle CEC interrupts, if any */ drm_dp_cec_irq(&intel_dp->aux); - /* defer to the hotplug work for link retraining if needed */ - if (intel_dp_needs_link_retrain(intel_dp)) - return false; + intel_dp_check_link_state(intel_dp); intel_psr_short_pulse(intel_dp); From patchwork Mon May 20 18:58:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668593 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4CDD1C25B77 for ; Mon, 20 May 2024 18:58:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A3A710E89E; Mon, 20 May 2024 18:58:39 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Oxc/Oo3/"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 032E310E572 for ; Mon, 20 May 2024 18:58:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716231513; x=1747767513; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=XcCt4oRxeVdAxRFZL43I3czJuh/gzjRiBwmlQ7BBBUM=; b=Oxc/Oo3/dpoHWiC0WsxfFW1vaNn7TyH9ChP0yyQ2ynBE18SPcbxZwpf3 VMU6n/6R18TXfVtPSihw39PXDSbC/hxrD5n7KamvxnVh992caqhSNnHA8 nAoWO6dzvKvQieGcOrZTCzY2jthL8uVvogqgHuDGTPB2CUFO/jUtLWN4S eZRTz88xU9sglYtWVTPvyWaK4okPq3lhj2jy/Wmy5dT97mN3rWkBxfKjt Ix5wA6OnavNUu+IQ7fvSpXZdQPL2xYCJn/hzS+5BOC+eH7TYz/m7sSSWT sKWebFYqxGc7SKW5Znypdu94FrXIj9HgOYAeF0/j+uOmrkwVT46HmMSgs A==; X-CSE-ConnectionGUID: 2dNBLU2oQR+uE2+o5PWRUQ== X-CSE-MsgGUID: ZhugzzeGQXCECZuz3DpArA== X-IronPort-AV: E=McAfee;i="6600,9927,11078"; a="16218545" X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="16218545" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:33 -0700 X-CSE-ConnectionGUID: oTVvY9FxSeifoaZAwp0zsQ== X-CSE-MsgGUID: VkvHwyGtSA24D5iFonm0Nw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213873" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:32 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 14/21] drm/i915/dp: Disable link retraining after the last fallback step Date: Mon, 20 May 2024 21:58:12 +0300 Message-ID: <20240520185822.3725844-15-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" After a link training failure if the link parameters can't be further reduced, there is no point in trying to retrain the link in the driver. This avoids excessive retrain attempts after detecting a bad link, for instance while handling MST HPD IRQs, which is likely redundant as the link training failed already twice with the same minimum link parameters. Userspace can still try to retrain the link with these parameters via a modeset. While at it make the error message more accurate and emit instead a debug message if the link training failure was only forced for testing purposes. Signed-off-by: Imre Deak --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++ .../drm/i915/display/intel_dp_link_training.c | 22 +++++++++++++------ 3 files changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index bde518c843468..eb0cac3e27acf 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1765,6 +1765,7 @@ struct intel_dp { int max_lane_count; /* Max rate for the current link */ int max_rate; + bool retrain_disabled; /* Sequential link training failures after a passing LT */ int seq_train_failures; } link; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b72dbd7becb74..34d64fe3302ef 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2950,6 +2950,7 @@ static void intel_dp_reset_link_params(struct intel_dp *intel_dp) { intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp); intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); + intel_dp->link.retrain_disabled = false; intel_dp->link.seq_train_failures = 0; } @@ -5061,6 +5062,9 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp) intel_dp->lane_count)) return false; + if (intel_dp->link.retrain_disabled) + return false; + if (intel_dp->link.seq_train_failures) return true; diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 97d499e4b6ef7..375f59afd4dec 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1165,10 +1165,8 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, new_link_rate = intel_dp_max_common_rate(intel_dp); } - if (new_lane_count < 0) { - drm_err(&i915->drm, "Link Training Unsuccessful\n"); + if (new_lane_count < 0) return -1; - } if (intel_dp_is_edp(intel_dp) && !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) { @@ -1187,7 +1185,7 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, return 0; } -static void intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state, +static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state, struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { @@ -1195,7 +1193,7 @@ static void intel_dp_schedule_fallback_link_training(struct intel_atomic_state * if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) { lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n"); - return; + return true; } if (intel_dp->hobl_active) { @@ -1203,11 +1201,13 @@ static void intel_dp_schedule_fallback_link_training(struct intel_atomic_state * "Link Training failed with HOBL active, not enabling it from now on\n"); intel_dp->hobl_failed = true; } else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) { - return; + return false; } /* Schedule a Hotplug Uevent to userspace to start modeset */ intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); + + return true; } /* Perform the link training on all LTTPRs and the DPRX on a link. */ @@ -1518,7 +1518,15 @@ void intel_dp_start_link_train(struct intel_atomic_state *state, return; } - intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state); + if (intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state)) + return; + + intel_dp->link.retrain_disabled = true; + + if (!passed) + lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n"); + else + lt_dbg(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after forced failure\n"); } void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, From patchwork Mon May 20 18:58:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668596 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B75CC04FFE for ; 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X-CSE-ConnectionGUID: ZM0YHqxZQfWbDQ6Nmuhv8A== X-CSE-MsgGUID: 6+/H83B9RbmfmfyCCGhucw== X-IronPort-AV: E=McAfee;i="6600,9927,11078"; a="16218550" X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="16218550" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:34 -0700 X-CSE-ConnectionGUID: hbm6JE0bQ9eOc0uLZurpRA== X-CSE-MsgGUID: 7YNbLNukQdWm9nddPueSGg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213881" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:33 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 15/21] drm/i915/dp_mst: Reset intel_dp->link_trained during disabling Date: Mon, 20 May 2024 21:58:13 +0300 Message-ID: <20240520185822.3725844-16-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Reset the flag indicating an active link after disabling an MST link, similarly to how this is done for SST outputs. This avoids trying to retrain an MST link while its disabled. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index c9c5d235744ab..66c1c59268167 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -981,6 +981,9 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state, drm_dbg_kms(&i915->drm, "active links %d\n", intel_dp->active_mst_links); + if (intel_dp->active_mst_links == 1) + intel_dp->link_trained = false; + intel_hdcp_disable(intel_mst->connector); intel_dp_sink_disable_decompression(state, connector, old_crtc_state); From patchwork Mon May 20 18:58:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668601 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1155C25B77 for ; Mon, 20 May 2024 18:59:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7668B10E8EC; Mon, 20 May 2024 18:59:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="erOlFv14"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id EAC9F10E572 for ; Mon, 20 May 2024 18:58:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716231515; x=1747767515; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=Kld5cQz/Tz1ZdJ1mijOtI3vNE0gsreq/zl0gsSM2mA8=; b=erOlFv14om7EeZzRiXNBpus7wN3vH3NW5suSmrh5tfhX8bFFrnyEJnsX KI69NqU8+uf7DCSZ9VHxFsReam1Vx++mEaKbFjYXe4c7Lrnfx4FgzbLKj WmPkck5t5Ft5XC+jJrljmkIvAZBt2uEIpqFZe56hxso/U7p4E5ZfvBtAc EfA6g6y7yBz2f1Mddt1zqLKcfmVIBD1YSfWIb2nLlwN+A3Gb3G9y7wTd1 9Q25t6fTwLrzWnEaqfVyfCTuXEbY2xfGK0LOk7JyEeF7dP+2VSY6CZCx5 /p8iPz58ziGv+JpeWm3EgF0WRZQFSn8mUgykRJffkmdMzshw2er4unx37 A==; X-CSE-ConnectionGUID: C922/W8fRTipPCRldk2qKw== X-CSE-MsgGUID: okw0oHVRTqOq9RkbORMC/A== X-IronPort-AV: E=McAfee;i="6600,9927,11078"; a="16218551" X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="16218551" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:34 -0700 X-CSE-ConnectionGUID: o5rRKvUiTXeqGYfpdcCztg== X-CSE-MsgGUID: rX1Q2mGMRUqM9y0b3NwREw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213886" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:34 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 16/21] drm/i915/dp_mst: Enable link training fallback for MST Date: Mon, 20 May 2024 21:58:14 +0300 Message-ID: <20240520185822.3725844-17-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Reduce the link parameters after a link training failure for MST outputs, similarly to how this is done for SST. For now allow the reduction only by staying in the 8b/10b vs. 128b/132b mode. Enabling the mode switch is left for a follow-up patchset, after taking measures ensuring that the mode switch happens properly. In particular a rediscovery of the whole MST topology may be required for such a switch, see the References below. Link: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10970 Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 6 +----- .../gpu/drm/i915/display/intel_dp_link_training.c | 13 ++++--------- 2 files changed, 5 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 34d64fe3302ef..c8d940a2ef7af 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5844,11 +5844,7 @@ intel_dp_detect(struct drm_connector *connector, intel_dp_mst_configure(intel_dp); - /* - * TODO: Reset link params when switching to MST mode, until MST - * supports link training fallback params. - */ - if (intel_dp->reset_link_params || intel_dp->is_mst) { + if (intel_dp->reset_link_params) { intel_dp_reset_link_params(intel_dp); intel_dp->reset_link_params = false; } diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 375f59afd4dec..9a59a28ca36d2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1124,6 +1124,10 @@ static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) new_rate = intel_dp_common_rate(intel_dp, rate_index - 1); + /* TODO: Make switching from UHBR to non-UHBR rates work. */ + if (drm_dp_is_uhbr_rate(current_rate) != drm_dp_is_uhbr_rate(new_rate)) + return -1; + return new_rate; } @@ -1142,15 +1146,6 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, int new_link_rate; int new_lane_count; - /* - * TODO: Enable fallback on MST links once MST link compute can handle - * the fallback params. - */ - if (intel_dp->is_mst) { - drm_err(&i915->drm, "Link Training Unsuccessful\n"); - return -1; - } - if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { drm_dbg_kms(&i915->drm, "Retrying Link training for eDP with max parameters\n"); From patchwork Mon May 20 18:58:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668598 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76155C25B7B for ; Mon, 20 May 2024 18:58:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E2A5B10E8AC; Mon, 20 May 2024 18:58:43 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="UkiwxgPV"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4D3D210E863 for ; Mon, 20 May 2024 18:58:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716231516; x=1747767516; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8yvJk7ZgPVuak9IOYlayX8FTEczVQ6jI4zzI4MSAtDQ=; b=UkiwxgPVwNXdMU0MbY1gu6vMM3blOOjG8booWk9SgkS944nqYM0C6Km5 XYhbSQlHwf8vnfY0DLKLGPn9yxoZ2uvVkee0eUykIiAp7Pz79k15Jk7j8 7ZWPcbwwOydsrkhWu/K2jSslRNtW53swX37B61y7syKO/MGD0Ce3iBVlt 5IZHnKuSW3L8TlzVn0gVpoJUX4/oqPSOmxxb1aj1KPoWUUkgPBwlmlJpL cv8ENBmZBCiee7D6HMn2xB5oVtTCoeyMAScF/oSvsg0zEQBe6WQnZv6Y2 KiDK4qM6pVEPaN0Vm76esq4yBxK4b8Mw4PSDmTwtszkGMngM/UZEYLge6 g==; X-CSE-ConnectionGUID: M1D7HuJOQriJ246JAIkG6w== X-CSE-MsgGUID: Zygu2YrHQIGbYFeFvRLJ8w== X-IronPort-AV: E=McAfee;i="6600,9927,11078"; a="16218552" X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="16218552" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:36 -0700 X-CSE-ConnectionGUID: AGdnRQVVSsyy7JfJ2u+Bmg== X-CSE-MsgGUID: q8cXyhR5TnW0ACGskQlWhA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213892" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:35 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Jani Nikula Subject: [PATCH v2 17/21] drm/i915/dp: Add debugfs entries to set a target link rate/lane count Date: Mon, 20 May 2024 21:58:15 +0300 Message-ID: <20240520185822.3725844-18-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add connector debugfs entries to set a target link rate/lane count to be used by a link training afterwards. After setting a target link rate/lane count reset the link training parameters and for a non-auto target disable reducing the link parameters via the fallback logic. The former one can be used after testing link training failure scenarios - via debugfs entries added later - to reset the reduced link parameters after the test. v2: - Add the entries from intel_dp_link_training.c (Jani) - Rename the entries to i915_dp_set_link_rate/lane_count. Cc: Jani Nikula Signed-off-by: Imre Deak --- .../drm/i915/display/intel_display_debugfs.c | 2 + .../drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/display/intel_dp.c | 63 ++++- drivers/gpu/drm/i915/display/intel_dp.h | 2 + .../drm/i915/display/intel_dp_link_training.c | 230 ++++++++++++++++++ .../drm/i915/display/intel_dp_link_training.h | 4 + 6 files changed, 294 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 35f9f86ef70f4..f83ffa2534925 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -23,6 +23,7 @@ #include "intel_display_types.h" #include "intel_dmc.h" #include "intel_dp.h" +#include "intel_dp_link_training.h" #include "intel_dp_mst.h" #include "intel_drrs.h" #include "intel_fbc.h" @@ -1515,6 +1516,7 @@ void intel_connector_debugfs_add(struct intel_connector *connector) intel_drrs_connector_debugfs_add(connector); intel_pps_connector_debugfs_add(connector); intel_psr_connector_debugfs_add(connector); + intel_dp_link_training_debugfs_add(connector); if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || connector_type == DRM_MODE_CONNECTOR_HDMIA || diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index eb0cac3e27acf..e1c41cece249d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1765,6 +1765,8 @@ struct intel_dp { int max_lane_count; /* Max rate for the current link */ int max_rate; + int requested_lane_count; + int requested_rate; bool retrain_disabled; /* Sequential link training failures after a passing LT */ int seq_train_failures; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c8d940a2ef7af..cf4a768fccd15 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -345,7 +345,7 @@ int intel_dp_max_common_rate(struct intel_dp *intel_dp) return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1); } -static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port) +int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port) { int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata); int max_lanes = dig_port->max_lanes; @@ -371,19 +371,39 @@ int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) return min3(source_max, sink_max, lane_max); } +static int requested_lane_count(struct intel_dp *intel_dp) +{ + return clamp(intel_dp->link.requested_lane_count, 1, intel_dp_max_common_lane_count(intel_dp)); +} + int intel_dp_max_lane_count(struct intel_dp *intel_dp) { - switch (intel_dp->link.max_lane_count) { + int lane_count; + + if (intel_dp->link.requested_lane_count) + lane_count = requested_lane_count(intel_dp); + else + lane_count = intel_dp->link.max_lane_count; + + switch (lane_count) { case 1: case 2: case 4: - return intel_dp->link.max_lane_count; + return lane_count; default: - MISSING_CASE(intel_dp->link.max_lane_count); + MISSING_CASE(lane_count); return 1; } } +static int intel_dp_min_lane_count(struct intel_dp *intel_dp) +{ + if (intel_dp->link.requested_lane_count) + return requested_lane_count(intel_dp); + + return 1; +} + /* * The required data bandwidth for a mode with given pixel clock and bpp. This * is the required net bandwidth independent of the data bandwidth efficiency. @@ -1306,16 +1326,38 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp) drm_dbg_kms(&i915->drm, "common rates: %s\n", str); } +static int requested_rate(struct intel_dp *intel_dp) +{ + int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.requested_rate); + + if (len == 0) + return intel_dp_common_rate(intel_dp, 0); + + return intel_dp_common_rate(intel_dp, len - 1); +} + int intel_dp_max_link_rate(struct intel_dp *intel_dp) { int len; + if (intel_dp->link.requested_rate) + return requested_rate(intel_dp); + len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate); return intel_dp_common_rate(intel_dp, len - 1); } +static int +intel_dp_min_link_rate(struct intel_dp *intel_dp) +{ + if (intel_dp->link.requested_rate) + return requested_rate(intel_dp); + + return intel_dp_common_rate(intel_dp, 0); +} + int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -2285,13 +2327,14 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp, bool dsc, struct link_config_limits *limits) { - limits->min_rate = intel_dp_common_rate(intel_dp, 0); + limits->min_rate = intel_dp_min_link_rate(intel_dp); limits->max_rate = intel_dp_max_link_rate(intel_dp); /* FIXME 128b/132b SST support missing */ limits->max_rate = min(limits->max_rate, 810000); + limits->min_rate = min(limits->min_rate, limits->max_rate); - limits->min_lane_count = 1; + limits->min_lane_count = intel_dp_min_lane_count(intel_dp); limits->max_lane_count = intel_dp_max_lane_count(intel_dp); limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format); @@ -2307,8 +2350,10 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp, * configuration, and typically on older panels these * values correspond to the native resolution of the panel. */ - limits->min_lane_count = limits->max_lane_count; - limits->min_rate = limits->max_rate; + if (intel_dp->link.requested_lane_count == 0) + limits->min_lane_count = limits->max_lane_count; + if (intel_dp->link.requested_rate == 0) + limits->min_rate = limits->max_rate; } intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits); @@ -2946,7 +2991,7 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp, intel_dp->lane_count = lane_count; } -static void intel_dp_reset_link_params(struct intel_dp *intel_dp) +void intel_dp_reset_link_params(struct intel_dp *intel_dp) { intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp); intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 3fa53ac601d58..79914e5080251 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -99,6 +99,7 @@ void intel_edp_backlight_off(const struct drm_connector_state *conn_state); void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp); void intel_dp_mst_suspend(struct drm_i915_private *dev_priv); void intel_dp_mst_resume(struct drm_i915_private *dev_priv); +int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port); int intel_dp_max_link_rate(struct intel_dp *intel_dp); int intel_dp_max_lane_count(struct intel_dp *intel_dp); int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state); @@ -108,6 +109,7 @@ int intel_dp_max_common_lane_count(struct intel_dp *intel_dp); int intel_dp_common_rate(struct intel_dp *intel_dp, int index); int intel_dp_rate_index(const int *rates, int len, int rate); void intel_dp_update_sink_caps(struct intel_dp *intel_dp); +void intel_dp_reset_link_params(struct intel_dp *intel_dp); void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, u8 *link_bw, u8 *rate_select); diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 9a59a28ca36d2..a6021e17cc1ef 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1115,6 +1115,9 @@ static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) int rate_index; int new_rate; + if (intel_dp->link.requested_rate) + return -1; + rate_index = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates, current_rate); @@ -1133,6 +1136,9 @@ static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count) { + if (intel_dp->link.requested_lane_count) + return -1; + if (current_lane_count > 1) return current_lane_count >> 1; @@ -1543,3 +1549,227 @@ void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n"); } + +static struct intel_dp *intel_connector_to_intel_dp(struct intel_connector *connector) +{ + if (connector->mst_port) + return connector->mst_port; + else + return enc_to_intel_dp(intel_attached_encoder(connector)); +} + +static int i915_dp_set_link_rate_show(struct seq_file *m, void *data) +{ + struct intel_connector *connector = to_intel_connector(m->private); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int ret; + int i; + + ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (ret) + return ret; + + intel_dp = intel_connector_to_intel_dp(connector); + + seq_printf(m, "%sauto%s", + intel_dp->link.requested_rate == 0 ? "[" : "", + intel_dp->link.requested_rate == 0 ? "]" : ""); + + for (i = 0; i < intel_dp->num_source_rates; i++) + seq_printf(m, " %s%d%s%s", + intel_dp->source_rates[i] == intel_dp->link.requested_rate ? "[" : "", + intel_dp->source_rates[i], + intel_dp->link_trained && + intel_dp->source_rates[i] == intel_dp->link_rate ? "*" : "", + intel_dp->source_rates[i] == intel_dp->link.requested_rate ? "]" : ""); + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + seq_putc(m, '\n'); + + return 0; +} + +static int parse_link_rate(struct intel_dp *intel_dp, const char __user *ubuf, size_t len) +{ + char *kbuf; + const char *p; + int rate; + int ret = 0; + + kbuf = memdup_user_nul(ubuf, len); + if (IS_ERR(kbuf)) + return PTR_ERR(kbuf); + + p = strim(kbuf); + + if (!strcmp(p, "auto")) { + rate = 0; + } else { + ret = kstrtoint(p, 0, &rate); + if (ret < 0) + goto out_free; + + if (intel_dp_rate_index(intel_dp->source_rates, + intel_dp->num_source_rates, + rate) < 0) + ret = -EINVAL; + } + +out_free: + kfree(kbuf); + + return ret < 0 ? ret : rate; +} + +static ssize_t i915_dp_set_link_rate_write(struct file *file, + const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct intel_connector *connector = to_intel_connector(m->private); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); + int rate; + int ret; + + ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (ret) + return ret; + + intel_dp = intel_connector_to_intel_dp(connector); + + rate = parse_link_rate(intel_dp, ubuf, len); + if (rate < 0) { + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return rate; + } + + intel_dp_reset_link_params(intel_dp); + intel_dp->link.requested_rate = rate; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + *offp += len; + + return len; +} +DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_set_link_rate); + +static int i915_dp_set_lane_count_show(struct seq_file *m, void *data) +{ + struct intel_connector *connector = to_intel_connector(m->private); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int ret; + int i; + + ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (ret) + return ret; + + intel_dp = intel_connector_to_intel_dp(connector); + + seq_printf(m, "%sauto%s", + intel_dp->link.requested_lane_count == 0 ? "[" : "", + intel_dp->link.requested_lane_count == 0 ? "]" : ""); + + for (i = 1; i <= 4; i <<= 1) + seq_printf(m, " %s%d%s%s", + i == intel_dp->link.requested_lane_count ? "[" : "", + i, + intel_dp->link_trained && + i == intel_dp->lane_count ? "*" : "", + i == intel_dp->link.requested_lane_count ? "]" : ""); + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + seq_putc(m, '\n'); + + return 0; +} + +static int parse_lane_count(const char __user *ubuf, size_t len) +{ + char *kbuf; + const char *p; + int lane_count; + int ret = 0; + + kbuf = memdup_user_nul(ubuf, len); + if (IS_ERR(kbuf)) + return PTR_ERR(kbuf); + + p = strim(kbuf); + + if (!strcmp(p, "auto")) { + lane_count = 0; + } else { + ret = kstrtoint(p, 0, &lane_count); + if (ret < 0) + goto out_free; + + switch (lane_count) { + case 1: + case 2: + case 4: + break; + default: + ret = -EINVAL; + } + } + +out_free: + kfree(kbuf); + + return ret < 0 ? ret : lane_count; +} + +static ssize_t i915_dp_set_lane_count_write(struct file *file, + const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct intel_connector *connector = to_intel_connector(m->private); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int lane_count; + int ret; + + lane_count = parse_lane_count(ubuf, len); + if (lane_count < 0) + return lane_count; + + ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (ret) + return ret; + + intel_dp = intel_connector_to_intel_dp(connector); + + intel_dp_reset_link_params(intel_dp); + intel_dp->link.requested_lane_count = lane_count; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + *offp += len; + + return len; +} +DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_set_lane_count); + +void intel_dp_link_training_debugfs_add(struct intel_connector *connector) +{ + struct dentry *root = connector->base.debugfs_entry; + + if (connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort && + connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) + return; + + debugfs_create_file("i915_dp_set_link_rate", 0644, root, + connector, &i915_dp_set_link_rate_fops); + + debugfs_create_file("i915_dp_set_lane_count", 0644, root, + connector, &i915_dp_set_lane_count_fops); +} diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h index f658230960333..42e7fc6cb171a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h @@ -9,6 +9,7 @@ #include struct intel_atomic_state; +struct intel_connector; struct intel_crtc_state; struct intel_dp; @@ -44,4 +45,7 @@ static inline u8 intel_dp_training_pattern_symbol(u8 pattern) void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); + +void intel_dp_link_training_debugfs_add(struct intel_connector *connector); + #endif /* __INTEL_DP_LINK_TRAINING_H__ */ From patchwork Mon May 20 18:58:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668591 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DBEF8C25B7C for ; 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X-CSE-ConnectionGUID: 95t9Fl3uQQOicjadXjutZQ== X-CSE-MsgGUID: auHDGmQURwazRqpOKaomZA== X-IronPort-AV: E=McAfee;i="6600,9927,11078"; a="16218553" X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="16218553" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:37 -0700 X-CSE-ConnectionGUID: cr5d8zGWTiSEHhvymvLpVA== X-CSE-MsgGUID: /pEzXvlzQqK/KF0p+/qjew== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213893" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:36 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 18/21] drm/i915/dp: Add debugfs entries to get the max link rate/lane count Date: Mon, 20 May 2024 21:58:16 +0300 Message-ID: <20240520185822.3725844-19-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add connector debugfs entries to get the maximum link rate and lane count. Signed-off-by: Imre Deak --- .../drm/i915/display/intel_dp_link_training.c | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index a6021e17cc1ef..764187bc42ff9 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1759,6 +1759,46 @@ static ssize_t i915_dp_set_lane_count_write(struct file *file, } DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_set_lane_count); +static int i915_dp_max_link_rate_show(void *data, u64 *val) +{ + struct intel_connector *connector = to_intel_connector(data); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int err; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + intel_dp = intel_connector_to_intel_dp(connector); + *val = intel_dp->link.max_rate; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_link_rate_fops, i915_dp_max_link_rate_show, NULL, "%llu\n"); + +static int i915_dp_max_lane_count_show(void *data, u64 *val) +{ + struct intel_connector *connector = to_intel_connector(data); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int err; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + intel_dp = intel_connector_to_intel_dp(connector); + *val = intel_dp->link.max_lane_count; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops, i915_dp_max_lane_count_show, NULL, "%llu\n"); + void intel_dp_link_training_debugfs_add(struct intel_connector *connector) { struct dentry *root = connector->base.debugfs_entry; @@ -1772,4 +1812,10 @@ void intel_dp_link_training_debugfs_add(struct intel_connector *connector) debugfs_create_file("i915_dp_set_lane_count", 0644, root, connector, &i915_dp_set_lane_count_fops); + + debugfs_create_file("i915_dp_max_link_rate", 0444, root, + connector, &i915_dp_max_link_rate_fops); + + debugfs_create_file("i915_dp_max_lane_count", 0444, root, + connector, &i915_dp_max_lane_count_fops); } From patchwork Mon May 20 18:58:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668595 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BB56C25B7C for ; Mon, 20 May 2024 18:58:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9F0CE10E31E; Mon, 20 May 2024 18:58:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="16218558" X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="16218558" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:38 -0700 X-CSE-ConnectionGUID: aeRbihK8RLecHLTv3prTXg== X-CSE-MsgGUID: CMjhhoOlQhq/aW/29xpKsg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213901" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:37 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Jani Nikula Subject: [PATCH v2 19/21] drm/i915/dp: Add debugfs entry to force link training failure Date: Mon, 20 May 2024 21:58:17 +0300 Message-ID: <20240520185822.3725844-20-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a connector debugfs entry to force a failure during the following 1-2 link training. The entry will auto-reset after the specified link training events are complete. v2: Add the entry from intel_dp_link_training.c (Jani) Cc: Jani Nikula Signed-off-by: Imre Deak --- .../drm/i915/display/intel_display_types.h | 1 + .../drm/i915/display/intel_dp_link_training.c | 52 ++++++++++++++++++- 2 files changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index e1c41cece249d..dbe1468fe471d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1770,6 +1770,7 @@ struct intel_dp { bool retrain_disabled; /* Sequential link training failures after a passing LT */ int seq_train_failures; + int force_train_failure; } link; bool reset_link_params; int mso_link_count; diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 764187bc42ff9..b40148a42f442 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1489,7 +1489,10 @@ void intel_dp_start_link_train(struct intel_atomic_state *state, else passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); - if (passed) { + if (intel_dp->link.force_train_failure) { + intel_dp->link.force_train_failure--; + lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n"); + } else if (passed) { intel_dp->link.seq_train_failures = 0; intel_ddi_queue_link_check(dig_port, 2000); return; @@ -1799,6 +1802,50 @@ static int i915_dp_max_lane_count_show(void *data, u64 *val) } DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops, i915_dp_max_lane_count_show, NULL, "%llu\n"); +static int i915_dp_force_link_training_failure_show(void *data, u64 *val) +{ + struct intel_connector *connector = to_intel_connector(data); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int err; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + intel_dp = intel_connector_to_intel_dp(connector); + *val = intel_dp->link.force_train_failure; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} + +static int i915_dp_force_link_training_failure_write(void *data, u64 val) +{ + struct intel_connector *connector = to_intel_connector(data); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int err; + + if (val > 2) + return -EINVAL; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + intel_dp = intel_connector_to_intel_dp(connector); + intel_dp->link.force_train_failure = val; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops, + i915_dp_force_link_training_failure_show, + i915_dp_force_link_training_failure_write, "%llu\n"); + void intel_dp_link_training_debugfs_add(struct intel_connector *connector) { struct dentry *root = connector->base.debugfs_entry; @@ -1818,4 +1865,7 @@ void intel_dp_link_training_debugfs_add(struct intel_connector *connector) debugfs_create_file("i915_dp_max_lane_count", 0444, root, connector, &i915_dp_max_lane_count_fops); + + debugfs_create_file("i915_dp_force_link_training_failure", 0644, root, + connector, &i915_dp_force_link_training_failure_fops); } From patchwork Mon May 20 18:58:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668600 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DF5ECC04FFE for ; Mon, 20 May 2024 18:59:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A0F4F10E873; Mon, 20 May 2024 18:59:12 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="PfeRsmEj"; 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d="scan'208";a="16218561" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:39 -0700 X-CSE-ConnectionGUID: /BPK+NWcSaSB0UoID8F4ow== X-CSE-MsgGUID: 3ARhuo3uRR2b3YbcgXfveg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213909" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:38 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Jani Nikula Subject: [PATCH v2 20/21] drm/i915/dp: Add debugfs entry to force link retrain Date: Mon, 20 May 2024 21:58:18 +0300 Message-ID: <20240520185822.3725844-21-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a connector debugfs entry to force retrain an active link. This can be used to test both custom link parameters (previously set via the target link lane count/rate entries) or link train failure scenarios (previously forced via the force-failure entry). The entry will autoreset after the link-retrain is complete. v2: Add the entry from intel_dp_link_training.c (Jani) Cc: Jani Nikula Signed-off-by: Imre Deak --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 18 +++++-- .../drm/i915/display/intel_dp_link_training.c | 47 +++++++++++++++++++ 3 files changed, 61 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index dbe1468fe471d..52c69c7eb52f5 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1771,6 +1771,7 @@ struct intel_dp { /* Sequential link training failures after a passing LT */ int seq_train_failures; int force_train_failure; + bool force_retrain; } link; bool reset_link_params; int mso_link_count; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index cf4a768fccd15..895074d548671 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5042,7 +5042,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr); } - if (!link_ok) + if (!link_ok || intel_dp->link.force_retrain) intel_ddi_queue_link_check(dig_port, 0); return !reprobe_needed; @@ -5091,6 +5091,9 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp) if (intel_psr_enabled(intel_dp)) return false; + if (intel_dp->link.force_retrain) + return true; + if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, link_status) < 0) return false; @@ -5237,8 +5240,9 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, if (!intel_dp_needs_link_retrain(intel_dp)) return 0; - drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n", - encoder->base.base.id, encoder->base.name); + drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link (forced %s)\n", + encoder->base.base.id, encoder->base.name, + str_yes_no(intel_dp->link.force_retrain)); for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { const struct intel_crtc_state *crtc_state = @@ -5266,7 +5270,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, encoder->base.base.id, encoder->base.name, ERR_PTR(ret)); - return ret; + goto out; } for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { @@ -5293,7 +5297,11 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, intel_crtc_pch_transcoder(crtc), true); } - return 0; +out: + if (ret != -EDEADLK) + intel_dp->link.force_retrain = false; + + return ret; } static int intel_dp_prep_phy_test(struct intel_dp *intel_dp, diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index b40148a42f442..6fac8421a6918 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -26,6 +26,7 @@ #include "intel_dp.h" #include "intel_dp_link_training.h" #include "intel_ddi.h" +#include "intel_hotplug.h" #include "intel_panel.h" #define LT_MSG_PREFIX "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] " @@ -1846,6 +1847,49 @@ DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops, i915_dp_force_link_training_failure_show, i915_dp_force_link_training_failure_write, "%llu\n"); +static int i915_dp_force_link_retrain_show(void *data, u64 *val) +{ + struct intel_connector *connector = to_intel_connector(data); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int err; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + intel_dp = intel_connector_to_intel_dp(connector); + *val = intel_dp->link.force_retrain; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} + +static int i915_dp_force_link_retrain_write(void *data, u64 val) +{ + struct intel_connector *connector = to_intel_connector(data); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int err; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + intel_dp = intel_connector_to_intel_dp(connector); + + intel_dp->link.force_retrain = val; + intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_retrain_fops, + i915_dp_force_link_retrain_show, + i915_dp_force_link_retrain_write, "%llu\n"); + void intel_dp_link_training_debugfs_add(struct intel_connector *connector) { struct dentry *root = connector->base.debugfs_entry; @@ -1868,4 +1912,7 @@ void intel_dp_link_training_debugfs_add(struct intel_connector *connector) debugfs_create_file("i915_dp_force_link_training_failure", 0644, root, connector, &i915_dp_force_link_training_failure_fops); + + debugfs_create_file("i915_dp_force_link_retrain", 0644, root, + connector, &i915_dp_force_link_retrain_fops); } From patchwork Mon May 20 18:58:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13668599 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EB6BBC04FFE for ; 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X-CSE-ConnectionGUID: fZEym7huTgOboaHesxxTBw== X-CSE-MsgGUID: wuJ+XpYyTM+xufVoOPNeuw== X-IronPort-AV: E=McAfee;i="6600,9927,11078"; a="16218562" X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="16218562" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:40 -0700 X-CSE-ConnectionGUID: h51ixuBFRQqjrJytdG8BNQ== X-CSE-MsgGUID: gU0vZX5jTduyonM26fNPqQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,175,1712646000"; d="scan'208";a="37213915" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2024 11:58:39 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: Jani Nikula Subject: [PATCH v2 21/21] drm/i915/dp: Add debugfs entry for link training info Date: Mon, 20 May 2024 21:58:19 +0300 Message-ID: <20240520185822.3725844-22-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240520185822.3725844-1-imre.deak@intel.com> References: <20240520185822.3725844-1-imre.deak@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add counters for link training pass/failure events and a connector debugfs entry showing these and relevant link training information. This is meant to be used by automated testing of the driver's link retraining and link parameter fallback functionality. v2: - Add the entry from intel_dp_link_training.c (Jani) - Add separate entries for the max link rate/lane count. Cc: Jani Nikula Signed-off-by: Imre Deak --- .../drm/i915/display/intel_display_types.h | 3 ++ drivers/gpu/drm/i915/display/intel_dp.c | 7 +++- .../drm/i915/display/intel_dp_link_training.c | 37 +++++++++++++++++++ 3 files changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 52c69c7eb52f5..6f37f2cca2e99 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1768,6 +1768,9 @@ struct intel_dp { int requested_lane_count; int requested_rate; bool retrain_disabled; + int train_count; + int retrain_count; + int all_train_failures; /* Sequential link training failures after a passing LT */ int seq_train_failures; int force_train_failure; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 895074d548671..0337be8416082 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2996,6 +2996,9 @@ void intel_dp_reset_link_params(struct intel_dp *intel_dp) intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp); intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); intel_dp->link.retrain_disabled = false; + intel_dp->link.train_count = 0; + intel_dp->link.retrain_count = 0; + intel_dp->link.all_train_failures = 0; intel_dp->link.seq_train_failures = 0; } @@ -5298,8 +5301,10 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, } out: - if (ret != -EDEADLK) + if (ret != -EDEADLK) { + intel_dp->link.retrain_count++; intel_dp->link.force_retrain = false; + } return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 6fac8421a6918..969a5fc4c7b2e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1490,6 +1490,8 @@ void intel_dp_start_link_train(struct intel_atomic_state *state, else passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); + intel_dp->link.train_count++; + if (intel_dp->link.force_train_failure) { intel_dp->link.force_train_failure--; lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n"); @@ -1499,6 +1501,7 @@ void intel_dp_start_link_train(struct intel_atomic_state *state, return; } + intel_dp->link.all_train_failures++; intel_dp->link.seq_train_failures++; /* @@ -1890,6 +1893,37 @@ DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_retrain_fops, i915_dp_force_link_retrain_show, i915_dp_force_link_retrain_write, "%llu\n"); +static int i915_dp_link_training_info_show(struct seq_file *m, void *data) +{ + struct intel_connector *connector = to_intel_connector(m->private); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp; + int ret; + + ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (ret) + return ret; + + intel_dp = intel_connector_to_intel_dp(connector); + + seq_printf(m, + "retrain_disabled: %s\n" + "train_count: %d\n" + "retrain_count: %d\n" + "all_train_failures: %d\n" + "seq_train_failures: %d\n", + str_yes_no(intel_dp->link.retrain_disabled), + intel_dp->link.train_count, + intel_dp->link.retrain_count, + intel_dp->link.all_train_failures, + intel_dp->link.seq_train_failures); + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(i915_dp_link_training_info); + void intel_dp_link_training_debugfs_add(struct intel_connector *connector) { struct dentry *root = connector->base.debugfs_entry; @@ -1915,4 +1949,7 @@ void intel_dp_link_training_debugfs_add(struct intel_connector *connector) debugfs_create_file("i915_dp_force_link_retrain", 0644, root, connector, &i915_dp_force_link_retrain_fops); + + debugfs_create_file("i915_dp_link_training_info", 0444, root, + connector, &i915_dp_link_training_info_fops); }