From patchwork Tue May 21 08:35:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea della Porta X-Patchwork-Id: 13669013 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 949DF6DCF5 for ; Tue, 21 May 2024 08:35:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716280512; cv=none; b=fgWkG5buvwqgBIKRbV7jPHcXp6IEHLiZWElzEMyEhou2ge+SNsE2Pnbc3Xy5eo/BLhiX2iKzOswt4dIlFQK6Hqj0wRjpDsr30IgQWTyqbBVfjNaHmZXO5UTaMn5LEkbW2FB8xLRzFxvfZPZIH4OYfPiu01M0HgPuVo6F09U57TY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716280512; c=relaxed/simple; bh=9k25ZsPTf+WrTiK8qVLkskl+r232la4YhtO+5MWY/Sk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=vGBY3ZAEFJLV+cjubz+G3FzoGKAviU+YH0/i5MWeEtnws7OpawyNXe2WJO01+ffYGKkLm3ce1kdEh2W8ZzgXR+n03dxjpUJoDgn682F9oZOMq9EwE8HyXYKlr1/q8IbyX2snWr+UnSkx2D8J7ADZwytDq08IFIBl39kB39+wI0E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b=Pw0ZRPHA; arc=none smtp.client-ip=209.85.218.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b="Pw0ZRPHA" Received: by mail-ej1-f41.google.com with SMTP id a640c23a62f3a-a5a0013d551so455590566b.2 for ; Tue, 21 May 2024 01:35:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1716280509; x=1716885309; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sE1zrpU4sY3RHfj/RfOgVZHYb52D/eP6ho+94PIl9YU=; b=Pw0ZRPHAzzYC6/ONfa/PFJAWG0VTChASjdFU7viYyzKJFfXJ7ZZILcW3K6/Fn9Duy7 v9Lz8RjRhe9B4t2P1PNnScM/xgTszJnxy4QRqiujEcc8rJcA6wyW/rb7TXOhDmNVhHCS CjEhYD23i+9G64QHuCNZFzXE4vOxC0s6iyYxjgWFnDciOTq/lkGMPFBbrCHUaCuWOzo3 w+n9MQltA00m38xLboWecFJzaIH7OFSdKl9lrxk6IxBVwJ1qhLc7bWXmNGfU+aImaYn7 OaXUY6yT8GEZfys2Rld6QIUEPBUDpIz1q4j4tzrCu2uehlUerS8FAqeNbdozRuX3+D02 voJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716280509; x=1716885309; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sE1zrpU4sY3RHfj/RfOgVZHYb52D/eP6ho+94PIl9YU=; b=pgOXX2fPVYzntuXHHsNSBNQQMkd45/Ef+Hw4v+iJpfIlzMHs6oKT8PNGgl5jQxX84+ al9Hpwrpd9nJmTw/8sxjq2IeIGhZjd7E807dxNa/dHfC7AydZJf5Q787o7ygXA7OosZK qfO8i/hYO+wzKyJUN542z8+wW8qev2fQ/5jRWrVrZryuqqBkf43Nnf3Kr0tzQFQ16bZs IA6xSK6RG4qc7arc60QT14k3eB9J3IHNGm21pSeKSGUB9TpFqbpwadDjzKjgtA0r2b4Z BvAQyIrt7xvlklzYw+tohojZmsPMOrQtiKa+ur7bE6HTaf8zZSse2Eiwo5OUDosv6K66 H+Cg== X-Forwarded-Encrypted: i=1; AJvYcCV1mOLUPgUt4lKQw/ejlaW/Vx8yKbOlvqIm0511YDpzIZ0SxaAgDOPbaa/fLioJdfy2tsUCVZpcRRYapYPm806GaZwQ7Zs/+cUV X-Gm-Message-State: AOJu0YzKsbhxfM0Pk5dASkKdcgLNJ6WZmlRhWKdmDBDF3R4O3FMKG3cy UOI0BpiZMa/tzbobw5Shkfe6aKqA1JwpaIkbMZK0I5oM2BPqrNNUjItMEp+UYs0= X-Google-Smtp-Source: AGHT+IFdOJDaXxwt3G/XzqPJASfDE2cQLEMIY3fQlL8rVbF4b17JPtcvYhCbyKk+sH7uacDvaHu6OQ== X-Received: by 2002:a50:d518:0:b0:575:2ccc:13c1 with SMTP id 4fb4d7f45d1cf-5752ccc14damr6751138a12.9.1716280508952; Tue, 21 May 2024 01:35:08 -0700 (PDT) Received: from localhost (host-87-18-209-253.retail.telecomitalia.it. [87.18.209.253]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a1787c63bsm1577804466b.51.2024.05.21.01.35.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 May 2024 01:35:08 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Marc Zyngier , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta , Conor Dooley , Krzysztof Kozlowski Subject: [PATCH v3 1/4] dt-bindings: arm: bcm: Add BCM2712 SoC support Date: Tue, 21 May 2024 10:35:13 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The BCM2712 SoC is found on Raspberry Pi 5. Add compatible string to acknowledge its new chipset. Signed-off-by: Andrea della Porta Reviewed-by: Stefan Wahren Acked-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml index 162a39dab218..e4ff71f006b8 100644 --- a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml @@ -23,6 +23,12 @@ properties: - raspberrypi,4-model-b - const: brcm,bcm2711 + - description: BCM2712 based Boards + items: + - enum: + - raspberrypi,5-model-b + - const: brcm,bcm2712 + - description: BCM2835 based Boards items: - enum: From patchwork Tue May 21 08:35:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea della Porta X-Patchwork-Id: 13669015 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D19454F89 for ; Tue, 21 May 2024 08:35:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716280513; cv=none; b=EGTH26EA4DM4Y8S8v2wZgXSewimB5UDaOWqnYtJ6GoeeZlBlymZYTRvdUWgKMOubNiLJtZiNRMnyrrysj5A1uf/PISXhmYFdG2WZJVDwDgUAlC1ToL3bRzoo4eV8TwvZqkbZFhNV5xhhQrCSEBxseGtUSb0j4+pzkAohN+oYYTQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716280513; c=relaxed/simple; bh=kNZI+tfNPBQt9dkkmteDOfG96JtFEZcf2Sv6/JIELrA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PfPodqD7Z20AHHZs8qVBDOiSmvnm7m4/t78thniDYJERVcX9G21O4kp6RS/H6K2HwtJzJi4JLLJN76Dz7BnCdQO0d2a+zFKaaBySKEqB8DAUPUHeHBMBOOA/49a8LvtyEkPl/W+88FQZaN4LZVrioLb/RjJCwi6YX/3JLqL8eg0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b=Cgwxp9Fu; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b="Cgwxp9Fu" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-a599c55055dso789754166b.0 for ; Tue, 21 May 2024 01:35:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1716280510; x=1716885310; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xeUzaJgucCPR+zY9E+AvBWEfJ2LsXQToej63r5VWGuY=; b=Cgwxp9Fue7rRSDVSezsi0r80JzLqSafgcM3l0o4GwUPhE8aJ3o4tad6KyyEW0d6x7L 1Sbxl6r53uMkhO3NTKHkfHGt4OP/ewFHWPkBky57fNedKmDAfdGGkb72zSwQI3yTXu0G t9TGQSqWuhFyf+Pjm1uv9X6QwK7iUSFGNyae7pW4oM0upm0GTsl4oYU+WhIGfRCrJSKP adnVFle45ktAqtwXy+P31wdRQM18uZqC7ra0AFntZUBTA9D62JQGqUG6AjgH9bTLaSnC 103Q0COs+iosXWPLkAuQav5TBjRdIg0Chl9Zsft2U40qoQLLDcTVWMNJoRQifmpHIfhU 4tVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716280510; x=1716885310; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xeUzaJgucCPR+zY9E+AvBWEfJ2LsXQToej63r5VWGuY=; b=KgaFw9wwjVLiqZ1a73vTZZe4DmJPDyBhz1XahorF0CHZ05sIcwogDc/poxxdhe4aPc FhdJRMnjimAkmIB3FIgblBAw0Wvn+q59QA9nEevG/jtWplwF8FyaJ15oigUaqqJ6TEjc wG3CUs/0c9+WeD0fK+EoOjVnNbsRoHhqBTS02AHUkYfbjKtBu0GBM9jblnlHPXU1yF52 dGt5bZncL9r5CM6bHbNVS+jNQ1WM3WrNN0XpiY5NWqEWv5NOBDUSvtzRa9NBLDFyt1a3 r/WH8o215tEeCRmtDZ0kSjw7R0Ji4LTX4g15RK0fFBGtiM5qnji6vQZD+3fskVIJDiFS taIw== X-Forwarded-Encrypted: i=1; AJvYcCWiPm4l2e3KI7T0M8zVFV7iSKTIavXJXeXDcW68Gn4EM1qBlDQj24ffGzAyF3Y69FGpi+GrHag5YdkcXD/R3NiGLIZD/8E8KcqV X-Gm-Message-State: AOJu0YyotFEC5mCjVCtStJ9ZQlQhUKVQZ6NMRnvSIK7grMm9XYJWpuk4 O0MXdZ9XWWuBoSXfGyO2IqdtFlHK64Sm51PPDFrJTejKO+dtY5lr2tSwCz08BHU= X-Google-Smtp-Source: AGHT+IFGVFbO+Vvt/HLW1ts2sBvZryzev6bkeYdTBdUsoUpVu04fdJMUBuNaBT0ihT7+qGIBU1QAIA== X-Received: by 2002:a17:906:6415:b0:a59:adf8:a6d5 with SMTP id a640c23a62f3a-a5a2d6786fbmr2042739566b.72.1716280509907; Tue, 21 May 2024 01:35:09 -0700 (PDT) Received: from localhost (host-87-18-209-253.retail.telecomitalia.it. [87.18.209.253]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a179c7f49sm1572664766b.101.2024.05.21.01.35.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 May 2024 01:35:09 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Marc Zyngier , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta Subject: [PATCH v3 2/4] dt-bindings: mmc: Add support for BCM2712 SD host controller Date: Tue, 21 May 2024 10:35:14 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The BCM2712 has an SDHCI capable host interface similar to the one found in other STB chipsets. Add the relevant compatible string. Signed-off-by: Andrea della Porta --- Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml index cbd3d6c6c77f..d584a7ea707a 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml @@ -13,6 +13,10 @@ maintainers: properties: compatible: oneOf: + - items: + - enum: + - brcm,bcm2712-sdhci + - const: brcm,sdhci-brcmstb - items: - enum: - brcm,bcm7216-sdhci From patchwork Tue May 21 08:35:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea della Porta X-Patchwork-Id: 13669016 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D6CA56448 for ; Tue, 21 May 2024 08:35:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716280515; cv=none; b=X2P+Qzy7q+JCG7YJCVeVtl33rj+0P2s8440E/hVzQi7seI5b/NBv3vEM4llbpV+zZG/gvvvOPxTK+IL/svYILaD06sDenBj8Er4pPq6nabKrnO+ZeMfJUg2YgGrxZJOJdenA55mF/wPeU/8LwlDd93NRumn1RTy3HY/t+S2Htfc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716280515; c=relaxed/simple; bh=y5QaR0C7PpeJzmsQ9dDbD7B8GvNZlMj9O7OXHSq0r6o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nEwynVSQlhPwjK5QLw1quT9dE3ldDfEvbGDMqDNW8Vi6i2ArtXtAncw9ts1U8FNVPOYQ0WjoUH5bjfeHPzoHQ6VALta4gH/PhSZZ7P1T8HNgwVUtixHNt5aLOxjTNhk2VBUhteMi1sWaj77DYKyiljMxw0IE6MrWQdzbzYxNJZA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b=GGrm8FTu; arc=none smtp.client-ip=209.85.218.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b="GGrm8FTu" Received: by mail-ej1-f45.google.com with SMTP id a640c23a62f3a-a61b70394c0so199248666b.1 for ; Tue, 21 May 2024 01:35:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1716280511; x=1716885311; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D2fOQltsojx/EfK7u7I+TssNN5t4CrMscEHwUz7PdS4=; b=GGrm8FTu7m9CxZw9AcltcugEzu3enmPkwFmjcZ/BHbJLM7GchV7K0iccW6t8Vh0sbG N3CZShY0vu78WFMhWFgSQyFLAxl4hi3hM8OxP/0nz903Mi2rS77YuSyjCEU1ttrZEhp2 0Z6/rCVLM67T3YQ4QIaT1hRoaBRja9mEY6zrsbJcAu+shkjFY7NyfS+8Yg7zI7iK9Gjp k6DrdSy5/sUqAO0yoF6U2/kmqjKzGKGA8gmXzzIXbXCwRzjWqLYANKC+e60Ui6r6GbML OM+dp/jYJ4EZ+ffokDb/jKByoK4x052DmLWlT6z1FDEDSnTfDz7KKrWitnoteg0ev1+x Bcbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716280511; x=1716885311; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D2fOQltsojx/EfK7u7I+TssNN5t4CrMscEHwUz7PdS4=; b=qybbbbFVMyfxcm3lG2+gas3c/D2SHkKVeq5hNp7bdMag4v7YlwqetfEsfC3kvONR3l LMla0Eo88yQHurH1MyT9QuIlOx0iBsxjgGg93/veMt1mA9W7B4z4QTMmtECGRVr+LFjA YsgKuDDirGh2yHd82UNRK59V1jHjHoNMcpAGlFL4vbDAF3dJ1+3n9pfa/s0RtU0/X22S S5vNlk/0/M8CPjTqd5yWXxPfgPCjDS/6pl4Dpiz+jbL89lk2el7DUrkDGLwJA6nz9aJ+ RpKdkFYyBXKDVYu6lMb7Fp7Avi/UbhzJlL9+XL1FD3bihiGBee0c8r4OWXxSS385vCE7 MIUA== X-Forwarded-Encrypted: i=1; AJvYcCXWR6hMe11ag4Yxgpvon6RAxQGxqimfPpjYrxvVKWwLZuZg4j0Qjlmk/jvaGpw0sgPHCigGi4+2+8s/q7lEPxa5jsx38Aqxg+tU X-Gm-Message-State: AOJu0YyfUWw23myKixD/FfCBQ9Ha3OnhUTI6tADSxaNik+azJsQCF4wc FcmGllj1BpPUBSO/CrQhfF7eYEFgkbFf9eZxYb9inU2Ax7UTEIPD4xYeaz2I4qU= X-Google-Smtp-Source: AGHT+IEvkv22JFzUjiKZ/QCHeIdDQIX0EZHONqalNwfZwbu9gG6VO37bmkSctPmgWFlMfN25yeFZrQ== X-Received: by 2002:a17:906:37d6:b0:a55:9dec:355f with SMTP id a640c23a62f3a-a5a2d676774mr1842300566b.70.1716280510921; Tue, 21 May 2024 01:35:10 -0700 (PDT) Received: from localhost (host-87-18-209-253.retail.telecomitalia.it. [87.18.209.253]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a17b01932sm1570871666b.168.2024.05.21.01.35.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 May 2024 01:35:10 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Marc Zyngier , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta Subject: [PATCH v3 3/4] mmc: sdhci-brcmstb: Add BCM2712 support Date: Tue, 21 May 2024 10:35:15 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Broadcom BCM2712 SoC has an SDHCI card controller using the SDIO CFG register block present on other STB chips. Add support for BCM2712 SD capabilities of this chipset. The silicon is SD Express capable but this driver port does not currently include that feature yet. Based on downstream driver by raspberry foundation maintained kernel. Signed-off-by: Andrea della Porta --- drivers/mmc/host/sdhci-brcmstb.c | 65 ++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index 9053526fa212..b349262da36e 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -30,6 +30,21 @@ #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 +#define SDIO_CFG_CQ_CAPABILITY 0x4c +#define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) + +#define SDIO_CFG_CTRL 0x0 +#define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31) +#define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30) + +#define SDIO_CFG_MAX_50MHZ_MODE 0x1ac +#define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31) +#define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0) + +#define MMC_CAP_HSE_MASK (MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V) +/* Select all SD UHS type I SDR speed above 50MB/s */ +#define MMC_CAP_UHS_I_SDR_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104) + struct sdhci_brcmstb_priv { void __iomem *cfg_regs; unsigned int flags; @@ -38,6 +53,7 @@ struct sdhci_brcmstb_priv { }; struct brcmstb_match_priv { + void (*cfginit)(struct sdhci_host *host); void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); struct sdhci_ops *ops; const unsigned int flags; @@ -168,6 +184,38 @@ static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); } +static void sdhci_brcmstb_cfginit_2712(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host); + u32 reg, base_clk_mhz; + + /* + * If we support a speed that requires tuning, + * then select the delay line PHY as the clock source. + */ + if ((host->mmc->caps & MMC_CAP_UHS_I_SDR_MASK) || (host->mmc->caps2 & MMC_CAP_HSE_MASK)) { + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); + reg &= ~SDIO_CFG_MAX_50MHZ_MODE_ENABLE; + reg |= SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE; + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); + } + + if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || + (host->mmc->caps & MMC_CAP_NEEDS_POLL)) { + /* Force presence */ + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); + reg &= ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV; + reg |= SDIO_CFG_CTRL_SDCD_N_TEST_EN; + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); + } + + /* Guesstimate the timer frequency (controller base clock) */ + base_clk_mhz = max_t(u32, clk_get_rate(pltfm_host->clk) / (1000 * 1000), 1); + reg = SDIO_CFG_CQ_CAPABILITY_FMUL | base_clk_mhz; + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CQ_CAPABILITY); +} + static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) { sdhci_dumpregs(mmc_priv(mmc)); @@ -200,6 +248,14 @@ static struct sdhci_ops sdhci_brcmstb_ops = { .set_uhs_signaling = sdhci_set_uhs_signaling, }; +static struct sdhci_ops sdhci_brcmstb_ops_2712 = { + .set_clock = sdhci_set_clock, + .set_power = sdhci_set_power_and_bus_voltage, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, +}; + static struct sdhci_ops sdhci_brcmstb_ops_7216 = { .set_clock = sdhci_brcmstb_set_clock, .set_bus_width = sdhci_set_bus_width, @@ -214,6 +270,11 @@ static struct sdhci_ops sdhci_brcmstb_ops_74165b0 = { .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling, }; +static const struct brcmstb_match_priv match_priv_2712 = { + .cfginit = sdhci_brcmstb_cfginit_2712, + .ops = &sdhci_brcmstb_ops_2712, +}; + static struct brcmstb_match_priv match_priv_7425 = { .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT | BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, @@ -238,6 +299,7 @@ static struct brcmstb_match_priv match_priv_74165b0 = { }; static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = { + { .compatible = "brcm,bcm2712-sdhci", .data = &match_priv_2712 }, { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 }, @@ -370,6 +432,9 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) (host->mmc->caps2 & MMC_CAP2_HS400_ES)) host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es; + if (match_priv->cfginit) + match_priv->cfginit(host); + /* * Supply the existing CAPS, but clear the UHS modes. This * will allow these modes to be specified by device tree From patchwork Tue May 21 08:35:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea della Porta X-Patchwork-Id: 13669017 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A05C5B69E for ; Tue, 21 May 2024 08:35:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716280516; cv=none; b=M+E4QzWxXm1kDQGosOvFQWGSWJ3IOohhb7HGWEyB9J8byVJfEkx5qNWuFNMaoC6tDos/0ie1brLMCQw1ZDTiQElsvsYhXl5Thb7RNFwFhODzdCUhNpuJQq3oBiedM8ASItbhZvPKa8waW4v5hDakwaXgv8HmOStPtqdCxB4GojY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716280516; c=relaxed/simple; bh=uXU5QfaH5qlqXoA4DPbAYFEaIVRvOPrHJFlST/zPwXU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jtjjKcgZXk+Q/WrvH0BrAbr2TDGDb2VqdI0QKTmyFjg/o2T+4eV93/X7EJQkK4RicZiZLzpucncVNavgQDeB2IKyPyi7YfwIpCNZWjeWac1Soh63v7vhAxK8U3YRvVmMm0cmYHyniPTIjFtfdZcNZb5K22i++BCZM0vFXtbmXYg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b=L3hCpjwy; arc=none smtp.client-ip=209.85.208.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b="L3hCpjwy" Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-57822392a0dso692297a12.0 for ; Tue, 21 May 2024 01:35:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1716280513; x=1716885313; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P80V1HVAEHdvXLPhNcgfiUJ7gY/EImR+9FLANrvqAlM=; b=L3hCpjwyzSmKYFQdh4zdoTwgNdCPQoP0VvHut6NC8vFehTQEYQbcrLtAlh1WAWOXby djFoMX7EHYXER2dSMuW7SogbFCwq4v5rgqLTngkyfwAvu6J+MeFLYddgCi+I3DWIb/ef sLwzPEUUVnBe9Dp6PXFp5+Iz9VLfVwhPvyOCQSdVn3ju8jIryuBWT3U1SKG6zv/gAgYQ ryoSiPDyEm4NiqX1yYrdw7Ng2yPNgaoWIcbR5HhAyNFtEd9AEPRIG5uQgGkSHTcF5qeE 1MH3YFBqV114kZMGQef8IymUOrA2BTdUs39NemMn6ADslblrMjh30pdn7KWShAH5rc/J nT/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716280513; x=1716885313; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P80V1HVAEHdvXLPhNcgfiUJ7gY/EImR+9FLANrvqAlM=; b=D9xNcec5bS+XX7Ee6v0M+OiT69Sv9I6TbUBNhz6UMlyohUUWNtj1I4t2Pq2cdahgFx xisMsikLeq4lFpbxX4wngkiMuKlasIY2b08znnh19uMWGrg09/yRl4SrmpJqeamXx+Xd EFC4ziveUHNxkjBz4pl7GwuTPWRsX4Xea/joHvDWYpSh/xMBR98SgWT1InTgHbn5X+t/ FjoPERFvFvs2v4L5R6Tzf5cWf7mQ2A5DHm/uPk7nIuoxA5L9pieUVpGpHFRw7p/qAY6y 6W7+iMm+uVH7nmeFO5hCZiDHD57HT2QNEiPZrlQswkYtSy4YuGxYeNI0am33q6CMT8+Y SQ5g== X-Forwarded-Encrypted: i=1; AJvYcCXsSXkbzKJgFJ8f934stfVTOwd56v2HMUSH4cnn7KnaBFx16D+ytvmCaryZs9Q5ucM4ZBpHi4lTQRf/ijv5ym9hpTuB/hL6Zt48 X-Gm-Message-State: AOJu0Yx+inZBcBKgCsE1DKZi2YLIScGTy2VQjQzhJuGLcVil5MqknTzf 4HcoHYOH5GdHsoL7lkfHTY4NPB09UaXiyQdn44+6db+h3PULXgM4qFx7zwkw98A= X-Google-Smtp-Source: AGHT+IHz9p5OTO55wUBRLM61KvuJyO1Ga+w2762Be3+GlQAj9VUKOINFTaXF5ZLfnK8vzmTXiTKfeA== X-Received: by 2002:a50:9fc9:0:b0:572:ad86:d317 with SMTP id 4fb4d7f45d1cf-5734d5b90e3mr22304712a12.11.1716280512646; Tue, 21 May 2024 01:35:12 -0700 (PDT) Received: from localhost (host-87-18-209-253.retail.telecomitalia.it. [87.18.209.253]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5733c2c7e0dsm16388546a12.71.2024.05.21.01.35.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 May 2024 01:35:12 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Marc Zyngier , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta Subject: [PATCH v3 4/4] arm64: dts: broadcom: Add support for BCM2712 Date: Tue, 21 May 2024 10:35:16 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The BCM2712 SoC family can be found on Raspberry Pi 5. Add minimal SoC and board (Rpi5 specific) dts file to be able to boot from SD card and use console on debug UART. Signed-off-by: Andrea della Porta --- arch/arm64/boot/dts/broadcom/Makefile | 1 + .../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 64 ++++ arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 292 ++++++++++++++++++ 3 files changed, 357 insertions(+) create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712.dtsi diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index 8b4591ddd27c..92565e9781ad 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -6,6 +6,7 @@ DTC_FLAGS := -@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \ bcm2711-rpi-4-b.dtb \ bcm2711-rpi-cm4-io.dtb \ + bcm2712-rpi-5-b.dtb \ bcm2837-rpi-3-a-plus.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts new file mode 100644 index 000000000000..2bdbb6780242 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/dts-v1/; + +#include +#include "bcm2712.dtsi" + +/ { + compatible = "raspberrypi,5-model-b", "brcm,bcm2712"; + model = "Raspberry Pi 5"; + + aliases { + serial10 = &uart10; + }; + + chosen: chosen { + stdout-path = "serial10:115200n8"; + }; + + /* Will be filled by the bootloader */ + memory@0 { + device_type = "memory"; + reg = <0 0 0 0x28000000>; + }; + + sd_io_1v8_reg: sd-io-1v8-reg { + compatible = "regulator-gpio"; + regulator-name = "vdd-sd-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-settling-time-us = <5000>; + gpios = <&gio_aon 3 GPIO_ACTIVE_HIGH>; + states = <1800000 1>, + <3300000 0>; + }; + + sd_vcc_reg: sd-vcc-reg { + compatible = "regulator-fixed"; + regulator-name = "vcc-sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>; + }; +}; + +/* The Debug UART, on Rpi5 it's on JST-SH 1.0mm 3-pin connector + * labeled "UART", i.e. the interface with the system console. + */ +&uart10 { + status = "okay"; +}; + +/* SDIO1 is used to drive the SD card */ +&sdio1 { + vqmmc-supply = <&sd_io_1v8_reg>; + vmmc-supply = <&sd_vcc_reg>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi new file mode 100644 index 000000000000..71b0fa6c9594 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +#include + +/ { + compatible = "brcm,bcm2712"; + + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gicv2>; + + axi: axi@1000000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>; + + sdio1: mmc@1000fff000 { + compatible = "brcm,bcm2712-sdhci", + "brcm,sdhci-brcmstb"; + reg = <0x10 0x00fff000 0x0 0x260>, + <0x10 0x00fff400 0x0 0x200>; + reg-names = "host", "cfg"; + interrupts = ; + clocks = <&clk_emmc2>; + clock-names = "sw_sdio"; + mmc-ddr-3_3v; + }; + + gicv2: interrupt-controller@107fff9000 { + interrupt-controller; + #interrupt-cells = <3>; + compatible = "arm,gic-400"; + reg = <0x10 0x7fff9000 0x0 0x1000>, + <0x10 0x7fffa000 0x0 0x2000>, + <0x10 0x7fffc000 0x0 0x2000>, + <0x10 0x7fffe000 0x0 0x2000>; + }; + }; + + clocks { + /* The oscillator is the root of the clock tree. */ + clk_osc: clk-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "osc"; + clock-frequency = <54000000>; + }; + + clk_vpu: clk-vpu { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <750000000>; + clock-output-names = "vpu-clock"; + }; + + clk_uart: clk-uart { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <9216000>; + clock-output-names = "uart-clock"; + }; + + clk_emmc2: clk-emmc2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + clock-output-names = "emmc2-clock"; + }; + }; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* Source for L1 d/i cache-line-size, cache-sets, cache-size + * https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en + * Source for L2 cache-line-size and cache-sets: + * https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en + * and for cache-size: + * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 + */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x000>; + enable-method = "psci"; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + next-level-cache = <&l2_cache_l0>; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <128>; + cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x100>; + enable-method = "psci"; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + next-level-cache = <&l2_cache_l1>; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <128>; + cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x200>; + enable-method = "psci"; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + next-level-cache = <&l2_cache_l2>; + + l2_cache_l2: l2-cache-l2 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <128>; + cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x300>; + enable-method = "psci"; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + next-level-cache = <&l2_cache_l3>; + + l2_cache_l3: l2-cache-l3 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <128>; + cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + }; + + /* Source for cache-line-size and cache-sets: + * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en + * Source for cache-size: + * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 + */ + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set + cache-level = <3>; + cache-unified; + }; + }; + + psci { + method = "smc"; + compatible = "arm,psci-1.0", "arm,psci-0.2"; + }; + + rmem: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + atf@0 { + reg = <0x0 0x0 0x0 0x80000>; + no-map; + }; + + cma: linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x4000000>; /* 64MB */ + reusable; + linux,cma-default; + alloc-ranges = <0x0 0x00000000 0x0 0x40000000>; + }; + }; + + soc: soc@107c000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x7c000000 0x10 0x7c000000 0x04000000>; + /* Emulate a contiguous 30-bit address range for DMA */ + dma-ranges = <0xc0000000 0x00 0x00000000 0x40000000>, + <0x7c000000 0x10 0x7c000000 0x04000000>; + + system_timer: timer@7c003000 { + compatible = "brcm,bcm2835-system-timer"; + reg = <0x7c003000 0x1000>; + interrupts = , + , + , + ; + clock-frequency = <1000000>; + }; + + mailbox: mailbox@7c013880 { + compatible = "brcm,bcm2835-mbox"; + reg = <0x7c013880 0x40>; + interrupts = ; + #mbox-cells = <0>; + }; + + local_intc: local-intc@7cd00000 { + compatible = "brcm,bcm2836-l1-intc"; + reg = <0x7cd00000 0x100>; + }; + + uart10: serial@7d001000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7d001000 0x200>; + interrupts = ; + clocks = <&clk_uart>, <&clk_vpu>; + clock-names = "uartclk", "apb_pclk"; + arm,primecell-periphid = <0x00241011>; + status = "disabled"; + }; + + interrupt-controller@7d517000 { + compatible = "brcm,bcm7271-l2-intc"; + reg = <0x7d517000 0x10>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gio_aon: gpio@7d517c00 { + compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + reg = <0x7d517c00 0x40>; + gpio-controller; + #gpio-cells = <2>; + // Don't use GIO_AON as an interrupt controller because it will + // clash with the firmware monitoring the PMIC interrupt via the VPU. + brcm,gpio-bank-widths = <17 6>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + }; +};