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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EE3E.mail.protection.outlook.com (10.167.242.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7611.14 via Frontend Transport; Tue, 21 May 2024 12:54:46 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 21 May 2024 07:54:44 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH 1/3] x86/mce: Rename mce_setup() to mce_prep_record() Date: Tue, 21 May 2024 07:54:32 -0500 Message-ID: <20240521125434.1555845-2-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240521125434.1555845-1-yazen.ghannam@amd.com> References: <20240521125434.1555845-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3E:EE_|SA3PR12MB7976:EE_ X-MS-Office365-Filtering-Correlation-Id: 7346d79b-4664-4432-4c64-08dc7995316e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|82310400017|376005|36860700004; X-Microsoft-Antispam-Message-Info: xz5SoPvSwHGq0vEpqhplr23DoIoG1m/5riQh+9CnstBQ701UF4WeEE3bZZL2JiLUi+5FCIlJRqWk7ifsai5PFquqoKGBxetoKRo7/SBggH5j9KJ92mmK64sFmn3cAO25+D/qpqXqKbeRIz1QqzXDy1SACZdhaKHwhHh5grPoB9T6r5SZWDO0RrROtW9WlwCZItvYonJXRO0gmi4yYkiCgzQ4qOjNNKOzAyJlFt8eKvId5UZc3QyQUxKzerDKEp2WKd5mYnhdlsIn5KtjdgzH59xAZHJ88+M5tYeAzuHNi/wvKyhqJ1WwC0XpfU4TkFycwWFLfchvKay+X4bgBu5CgeaDI19upbnkYhTh7y6fw45IJGPyv75Q2RNVzip7pwSV5isMU1utbanc0Iko73u2GieDuQf4NAYrvyMDq/dyXeo9btaX4cuQ7LpBoAKpdaRatdvGOnZekwRTdW45ZRDT1cmE57GK7t1y8w4r0RdWuoJfhLh9LzFUNhXX6BdChgygYApp4dUnauhC0JqsDPaGFUroJuQPv//TYZArii25ztB8hL3Q63QwESnlZ9tcR70UiC79dx08ZY4qDzDMyDSoLNNgyYzgfzlYpE2ljcE1t7Ih7CX2MLFbVxqkPVSEiZI9SAiw40l62pH45vUMcP1Vj+/JWRAp6wHCLr+BdO/bGjZo+T6JHGTnPTIpvIlk7SXECCc+FNxFnECUE+/Mf3di2U6sJ22M7lz0Ej73s9HgVIQeBlBk+VKTUZ6pYuX8xfTUyMROTV55NvsvfRtOUdCWuLYxVCe5DYFb+omLpx/w0P2mYt0wBh/vt5umMRkkxrzJWAIbGzBBxdwaQbjUQdtiPTvk9/zq3oOeisJgYCGJnlCp9LdOevA+zsN1ON51Wqslx37LOb1h+DlpiImwi0v1ieXXTRIszGJWoraOfMP8bDN5Dz0N1wwGqGJeSGGYNcWDyvcFYjBwvEf1QJcMH4vqejbwHlSJl+CdFjKiXIAETi99YfvqHvIUmSMIlrgq5or2UGNs+98ru+0mwYw7sCyEgh5TeEQn+VqvNT6cmX+LQpd7Z39nNT7p7+aXhMSOARnb+tOu+71F23GNXqlWjTxQOZNigijz0DKGnrYBXzgs+A3mnZCNXjQ9hWcBoQoohpkevatba3Nu71FTNamaeUoDqzAPv0EzrmegO2qXB7mYPWW8e4NiS+nb6YDrkg1tl9KPuGItRjBtAlpNKr39GKqlVn9Zu039r3+pcBObRueoWnnJUUXsPBkrbB3Uid0Mxw8HktQn9hdERLUFYfktqV9+2ZFHA9jR9z5KL0/kBBiWuuqWsCvQMQi9wMrDr98C8k2G3OoZC02ylmFplHDGRjdTPdUxaykeGMIokKumMrCdq4Q= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(1800799015)(82310400017)(376005)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2024 12:54:46.5074 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7346d79b-4664-4432-4c64-08dc7995316e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7976 There is no MCE "setup" done in mce_setup(). Rather this function initializes and prepares an MCE record. Rename the function to highlight what it does. No functional change is intended. Suggested-by: Borislav Petkov Signed-off-by: Yazen Ghannam --- arch/x86/include/asm/mce.h | 2 +- arch/x86/kernel/cpu/mce/amd.c | 2 +- arch/x86/kernel/cpu/mce/apei.c | 4 ++-- arch/x86/kernel/cpu/mce/core.c | 6 +++--- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index de3118305838..c3722b84d9cf 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -219,7 +219,7 @@ static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) { return -EINVAL; } #endif -void mce_setup(struct mce *m); +void mce_prep_record(struct mce *m); void mce_log(struct mce *m); DECLARE_PER_CPU(struct device *, mce_device); diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 9a0133ef7e20..14bf8c232e45 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -780,7 +780,7 @@ static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) { struct mce m; - mce_setup(&m); + mce_prep_record(&m); m.status = status; m.misc = misc; diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c index 7f7309ff67d0..8f509c8a4e98 100644 --- a/arch/x86/kernel/cpu/mce/apei.c +++ b/arch/x86/kernel/cpu/mce/apei.c @@ -44,7 +44,7 @@ void apei_mce_report_mem_error(int severity, struct cper_sec_mem_err *mem_err) else lsb = PAGE_SHIFT; - mce_setup(&m); + mce_prep_record(&m); m.bank = -1; /* Fake a memory read error with unknown channel */ m.status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_ADDRV | MCI_STATUS_MISCV | 0x9f; @@ -97,7 +97,7 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) if (ctx_info->reg_arr_size < 48) return -EINVAL; - mce_setup(&m); + mce_prep_record(&m); m.extcpu = -1; m.socketid = -1; diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index b5cc557cfc37..9dfa80084054 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -118,7 +118,7 @@ static struct irq_work mce_irq_work; BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); /* Do initial initialization of a struct mce */ -void mce_setup(struct mce *m) +void mce_prep_record(struct mce *m) { memset(m, 0, sizeof(struct mce)); m->cpu = m->extcpu = smp_processor_id(); @@ -436,11 +436,11 @@ static noinstr void mce_wrmsrl(u32 msr, u64 v) static noinstr void mce_gather_info(struct mce *m, struct pt_regs *regs) { /* - * Enable instrumentation around mce_setup() which calls external + * Enable instrumentation around mce_prep_record() which calls external * facilities. */ instrumentation_begin(); - mce_setup(m); + mce_prep_record(m); instrumentation_end(); m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); From patchwork Tue May 21 12:54:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13669411 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2077.outbound.protection.outlook.com [40.107.243.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 212667710C; 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Tue, 21 May 2024 07:54:45 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH 2/3] x86/mce: Define mce_prep_record() helpers for common and per-CPU fields Date: Tue, 21 May 2024 07:54:33 -0500 Message-ID: <20240521125434.1555845-3-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240521125434.1555845-1-yazen.ghannam@amd.com> References: <20240521125434.1555845-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3E:EE_|CY5PR12MB9054:EE_ X-MS-Office365-Filtering-Correlation-Id: bb65989b-808b-4886-46ee-08dc799531ea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|376005|1800799015|82310400017; X-Microsoft-Antispam-Message-Info: VtYVgMtuotHq2yGSM0JwhrOl5FW54MWS4KclO9jPghQCn3h/XCM3NbkbWIJUK4rDhJggcMNgwRCAXG96JqHgpoGLdRHoc1kj96/PgLOuWpkOgNOg53T/qZrHVPtVKxT+WBN8HFxuOgcEBpirC6F4NvZRO26uV/tr9fCVElcuGGKUyMft9PHvxgy8wfEb/8kdfMhR/bLhr7ZkJ49sTywkCZLAzsZgLzuNoHn2oBfI8xrUvyN+6rjAiwggIs7Otbu6hZ1Vkza9sYUJ7/QwiEFdw6CfiHwlwMTvGgbLoAXjMA0P9J4F2GfqUIwJI+Q2Z7msthVKyWn0V75upne5kbgOK1W7SBakg7/JMw7U+KNkiVfdjtTfso/xXWTiW5SrjnBaMqKKPmIk9TPDkjHPMiVfTriVNWyvFhu00Ggiza4PnX9LGWLkwaKjHJZb8KEpfaIo3scSL1Y9oVd7uLoogsi6PyxJlTv3pGgFfle+zY5eqv6A2EGwBomcGBIoQeTsxAWxV5MKE3qtMr2J0F24Ur3/12XrEqejL7JB7bSJSdocAID2RRli1BO+/ZMRRm02myaNk5TeTBZj7ElbSrnk7z5wmHHnW9K9l8kkRwdtrK3QM76qTvABaNDdMaTaE9mjlB0Gbct+Mlx6WTs5rfPAOP8AAH0GLpDHWyleVRVd7p1M7z0zgHr7/5if9xZ06hZzR0s6DzF9ml9rm6tWoGrygOUCO+7Z/97bFau6YmOzrIJpgUdez4HjUaKdxQZ4XEBcqc9vqUwmSqMe1MArGrboRO1tFDZjOM+4/EdV56r/pSo75uvxrhrEIXEN8e103Cne5UcvZxkbdKbl8AKn2QpFIBkRZ/HlJKxGw2Kjpc+MRlIipixZ7W3T7x2qrZM5tp+thviYEwMm9UxKotJrqBg9tu/zldF8cHJqjJxxdmQef7ucm3MGf9eFOhSGDkXuqZgbxhwh8bljasKp3GNGNpC4nztt9wIrxEqVp3mJKY3GNl9E9i4lM0Di8O4STZO3/gEPMmgTg6/glRiXhaWh3xXUVFPmRmme0xRBxA27W+/kJkOAscc3IdNMVNe0Hc+KcY8NFIbcdwMvnJtBz54EnDNfhAA4OuLhdhMlMeUwZ9dntuyL4ZaVZrdNRFtLbwYvbm2o8X0mMvAFu6NtMpJfJaW8VMQBntJRVPxkxE/JyWalwaKR+YC0quQCbXjrFxdH2uidytQ76GI8yit0Jmw5qPSggble8tckKNUVDAUGWxQmusjXNoMILh40fkCRCOLoK1dQuT/Wu/OFHbdVXDXBOhv+IEF9lc9M785BPFLKWBkQhmGhwBDnhOUu+ICRBFe7W1bJPZkqHF03NwR9DNI3Cm8bty3iB9F+O1IhyNgIGECj3w1f/z80X8myJP9XXVh4RZt4mVvQ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(36860700004)(376005)(1800799015)(82310400017);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2024 12:54:47.3199 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb65989b-808b-4886-46ee-08dc799531ea X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB9054 Generally, MCA information for an error is gathered on the CPU that reported the error. In this case, CPU-specific information from the running CPU will be correct. However, this will be incorrect if the MCA information is gathered while running on a CPU that didn't report the error. One example is creating an MCA record using mce_prep_record() for errors reported from ACPI. Split mce_prep_record() so that there is a helper function to gather common, i.e. not CPU-specific, information and another helper for CPU-specific information. Leave mce_prep_record() defined as-is for the common case when running on the reporting CPU. Get MCG_CAP in the global helper even though the register is per-CPU. This value is not already cached per-CPU like other values. And it does not assist with any per-CPU decoding or handling. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/core.c | 34 ++++++++++++++++++++---------- arch/x86/kernel/cpu/mce/internal.h | 2 ++ 2 files changed, 25 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 9dfa80084054..dacca82d45de 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -117,20 +117,32 @@ static struct irq_work mce_irq_work; */ BLOCKING_NOTIFIER_HEAD(x86_mce_decoder_chain); -/* Do initial initialization of a struct mce */ -void mce_prep_record(struct mce *m) +void mce_prep_record_common(struct mce *m) { memset(m, 0, sizeof(struct mce)); - m->cpu = m->extcpu = smp_processor_id(); + + m->cpuid = cpuid_eax(1); + m->cpuvendor = boot_cpu_data.x86_vendor; + m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); /* need the internal __ version to avoid deadlocks */ - m->time = __ktime_get_real_seconds(); - m->cpuvendor = boot_cpu_data.x86_vendor; - m->cpuid = cpuid_eax(1); - m->socketid = cpu_data(m->extcpu).topo.pkg_id; - m->apicid = cpu_data(m->extcpu).topo.initial_apicid; - m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); - m->ppin = cpu_data(m->extcpu).ppin; - m->microcode = boot_cpu_data.microcode; + m->time = __ktime_get_real_seconds(); +} + +void mce_prep_record_per_cpu(unsigned int cpu, struct mce *m) +{ + m->cpu = cpu; + m->extcpu = cpu; + m->apicid = cpu_data(m->extcpu).topo.initial_apicid; + m->microcode = cpu_data(m->extcpu).microcode; + m->ppin = cpu_data(m->extcpu).ppin; + m->socketid = cpu_data(m->extcpu).topo.pkg_id; +} + +/* Do initial initialization of a struct mce */ +void mce_prep_record(struct mce *m) +{ + mce_prep_record_common(m); + mce_prep_record_per_cpu(smp_processor_id(), m); } DEFINE_PER_CPU(struct mce, injectm); diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 01f8f03969e6..43c7f3b71df5 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -261,6 +261,8 @@ enum mca_msr { /* Decide whether to add MCE record to MCE event pool or filter it out. */ extern bool filter_mce(struct mce *m); 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Tue, 21 May 2024 12:54:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EE3E.mail.protection.outlook.com (10.167.242.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7611.14 via Frontend Transport; Tue, 21 May 2024 12:54:49 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 21 May 2024 07:54:45 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH 3/3] x86/mce: Use mce_prep_record() helpers for apei_smca_report_x86_error() Date: Tue, 21 May 2024 07:54:34 -0500 Message-ID: <20240521125434.1555845-4-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240521125434.1555845-1-yazen.ghannam@amd.com> References: <20240521125434.1555845-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3E:EE_|SA1PR12MB8162:EE_ X-MS-Office365-Filtering-Correlation-Id: d5db1949-e4fc-4d12-7104-08dc79953359 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|1800799015|376005|82310400017; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2024 12:54:49.7261 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d5db1949-e4fc-4d12-7104-08dc79953359 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8162 Current AMD systems can report MCA errors using the ACPI Boot Error Record Table (BERT). The BERT entries for MCA errors will be an x86 Common Platform Error Record (CPER) with an MSR register context that matches the MCAX/SMCA register space. However, the BERT will not necessarily be processed on the CPU that reported the MCA errors. Therefore, the correct CPU number needs to be determined and the information saved in struct mce. The CPU number is determined by searching all possible CPUs for a Local APIC ID matching the value in the x86 CPER. Use the newly defined mce_prep_record_*() helpers to get the correct data. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/apei.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c index 8f509c8a4e98..0cbadfaf2400 100644 --- a/arch/x86/kernel/cpu/mce/apei.c +++ b/arch/x86/kernel/cpu/mce/apei.c @@ -97,20 +97,17 @@ int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id) if (ctx_info->reg_arr_size < 48) return -EINVAL; - mce_prep_record(&m); - - m.extcpu = -1; - m.socketid = -1; - for_each_possible_cpu(cpu) { - if (cpu_data(cpu).topo.initial_apicid == lapic_id) { - m.extcpu = cpu; - m.socketid = cpu_data(m.extcpu).topo.pkg_id; + if (cpu_data(cpu).topo.initial_apicid == lapic_id) break; - } } - m.apicid = lapic_id; + if (!cpu_possible(cpu)) + return -EINVAL; + + mce_prep_record_common(&m); + mce_prep_record_per_cpu(cpu, &m); + m.bank = (ctx_info->msr_addr >> 4) & 0xFF; m.status = *i_mce; m.addr = *(i_mce + 1);