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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Maher Sanalla , Tariq Toukan Subject: [PATCH net 1/8] net/mlx5: Lag, do bond only if slaves agree on roce state Date: Wed, 22 May 2024 22:26:52 +0300 Message-ID: <20240522192659.840796-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240522192659.840796-1-tariqt@nvidia.com> References: <20240522192659.840796-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001508:EE_|PH7PR12MB8794:EE_ X-MS-Office365-Filtering-Correlation-Id: e0fc4bcf-b952-4afd-7d23-08dc7a954e3c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|1800799015|82310400017|36860700004; X-Microsoft-Antispam-Message-Info: =?utf-8?q?bj1aZF6nWIjsjpBv24dtukcwCAu0SD+?= =?utf-8?q?hD1wms7w9hYSaH21jSARo4axPecPzHTPrMfq7QycghPjRAUnD6uWZ83X9A8amryHG?= =?utf-8?q?EO2NS1EcjvnW41mC8wcOFkNT6tEz+q/vrQfa33bsLL78WwbJdmuCcvhTsSEmc+CvV?= =?utf-8?q?i+vgA8/i5UAfmp4EtOgwA2DCYIo5w8C8Z5LYS0zCGsR7oSrAvrCD/Z4zQJIroCe22?= =?utf-8?q?DoMkiPGz7nBzHeQBQ1TSwWLDnr4Zeqv3wlQajacUJjjEkQAzsIxdvQ7O0mAqgcLsq?= =?utf-8?q?dxjWKwCZDtDPS2TmVGf+IIoDEThdy5fX/AXimxmArC7U0y2iRn2klDHgmHEAY9xOy?= =?utf-8?q?htKlkZr4p95pBVUvExDbGJvGfCIrH3P/b9NPDWCcsFYMxmt2oQ/FjrxCVo1rJ5Tgo?= =?utf-8?q?9KHdWhDrvSCTx2cP3pSwjYq7N9MfkxsEtlZjUEp+HV8hFVPu3aDuPv6Guw0sB9Y5y?= =?utf-8?q?VSff60U3RSZkp1NLu+rZaRgkL6zZGSNS8TBTqNXqE2IzAqv7ok4rV9lxGykqZAir4?= =?utf-8?q?2vgM/MI5zsRRTata+hB0v3vguWKoFUI4tmvVhzdHQYjl+zgpBq9zHl7SadEWVZaxo?= =?utf-8?q?EWluBFuqH4dwfw3dCuEKtEV7ZdNjefEQUnq3hFxyWh3ugRZGkkiatcbt8iYTjERmw?= =?utf-8?q?Zulw3EBT/8p7l44Sm68cXp/2WKkbus4KR0AMuoTewZ2JUARQpEr6HYOSVJfWOhq9/?= =?utf-8?q?odLtqBGxvlnMoS89vTFEqCJOwjSm6yIqqPFmPtUda6Wdb4Q5Sc7SMUDelJOXGUM9W?= =?utf-8?q?VfgG02Qr+W5Bchx8YXW71QBnvpCgkKWZfC/UPthNgvLWM7XG8/vhEse2tj1aMwaMD?= =?utf-8?q?p6lgp9DePkNkyFYFRyrFt2ujI1tfxWYMXy5Ng8Z/n3kfIr/ZyEoE3OojsBpiZItSQ?= =?utf-8?q?BkmS0X1pQwtUym4T0qoL9WPpLYZMJBY6FePaw7QmslxVQ6/vaRgTnCXUOPE2X3XQh?= =?utf-8?q?jrYyWu+W1iolkVzoQFTUe6zbacjAP0xthklP6JYS5z30QswzpjM1wJ500WxP+R9pp?= =?utf-8?q?DIPKxTw4wzLbTxiSICeRd+xwojHn9LkwIv/0xUWeP4ZMjiUwQEApzMuNrGkroVJZB?= =?utf-8?q?jIDhlqWi2z1LK6DZJ41J6JHpQTevdOU/O/8tpOhyhkP3RM7dzZWHXgGfRxuOR1DHo?= =?utf-8?q?chpHdNBs5unM5WUdPbDOOTDNOquT9n7zxJxdkrOfLlVmd8LVGky48yEI2YZ5hkZd3?= =?utf-8?q?/p+f7GmxWc4VRWDIpJdvV3D8o+a8f2bCrkvIP9gpfuUAHZCDFfzIonoc386OpcNaq?= =?utf-8?q?iu8fZW7KMK5RcY6AZdd7YkNTBaVmEDKkj87Hrs9gBUOpV6i6Da/e49m6hVZ++6wFX?= =?utf-8?q?dNXZPtd7UrBY?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(376005)(1800799015)(82310400017)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2024 19:28:05.9820 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e0fc4bcf-b952-4afd-7d23-08dc7a954e3c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001508.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8794 X-Patchwork-Delegate: kuba@kernel.org From: Maher Sanalla Currently, the driver does not enforce that lag bond slaves must have matching roce capabilities. Yet, in mlx5_do_bond(), the driver attempts to enable roce on all vports of the bond slaves, causing the following syndrome when one slave has no roce fw support: mlx5_cmd_out_err:809:(pid 25427): MODIFY_NIC_VPORT_CONTEXT(0×755) op_mod(0×0) failed, status bad parameter(0×3), syndrome (0xc1f678), err(-22) Thus, create HW lag only if bond's slaves agree on roce state, either all slaves have roce support resulting in a roce lag bond, or none do, resulting in a raw eth bond. Fixes: 7907f23adc18 ("net/mlx5: Implement RoCE LAG feature") Signed-off-by: Maher Sanalla Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c index f7f0476a4a58..d0871c46b8c5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -719,6 +719,7 @@ bool mlx5_lag_check_prereq(struct mlx5_lag *ldev) struct mlx5_core_dev *dev; u8 mode; #endif + bool roce_support; int i; for (i = 0; i < ldev->ports; i++) @@ -743,6 +744,11 @@ bool mlx5_lag_check_prereq(struct mlx5_lag *ldev) if (mlx5_sriov_is_enabled(ldev->pf[i].dev)) return false; #endif + roce_support = mlx5_get_roce_state(ldev->pf[MLX5_LAG_P1].dev); + for (i = 1; i < ldev->ports; i++) + if (mlx5_get_roce_state(ldev->pf[i].dev) != roce_support) + return false; + return true; } @@ -910,8 +916,10 @@ static void mlx5_do_bond(struct mlx5_lag *ldev) } else if (roce_lag) { dev0->priv.flags &= ~MLX5_PRIV_FLAGS_DISABLE_IB_ADEV; mlx5_rescan_drivers_locked(dev0); - for (i = 1; i < ldev->ports; i++) - mlx5_nic_vport_enable_roce(ldev->pf[i].dev); + for (i = 1; i < ldev->ports; i++) { + if (mlx5_get_roce_state(ldev->pf[i].dev)) + mlx5_nic_vport_enable_roce(ldev->pf[i].dev); + } } else if (shared_fdb) { int i; From patchwork Wed May 22 19:26:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13671033 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2068.outbound.protection.outlook.com [40.107.220.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F16B1474A8 for ; Wed, 22 May 2024 19:28:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Tariq Toukan Subject: [PATCH net 2/8] net/mlx5: Do not query MPIR on embedded CPU function Date: Wed, 22 May 2024 22:26:53 +0300 Message-ID: <20240522192659.840796-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240522192659.840796-1-tariqt@nvidia.com> References: <20240522192659.840796-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A2:EE_|MN2PR12MB4439:EE_ X-MS-Office365-Filtering-Correlation-Id: 485633ea-56a7-4ea3-ecf0-08dc7a955327 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|376005|36860700004|82310400017; X-Microsoft-Antispam-Message-Info: 23y9Zry1VKOn9pFyIXa2Qe0ygO66nTVsEFQe8Qeva/pfkR6AnN/kML9LeI561k+MHczok/VLYTjghccxtoW4fFCEQJ44P39WsdvFov8XhVop4TdM023TyQkye3mwBYH//aN7DfnPz5ODrHqAuRbujcSHCc0cRR5ftX6qazny+7MCMsMFBY+PocqWDPdQQHu0rCNFduMeizQ/1tAASaCAPFq+PaqNS99fNQc2F+UIP9ByoiHu4A/15egfFVNjqqls+B6k346Y8NcLphbDd0NeHcjnHgP92YUerdH6N5rAiy5WynLcV0w0zfKPPxnLmJATeb2BNdAHWSLukMVdlTKP4o4Ndb40ptJhBwEkONittKKDI2enrlWMEHaFEw2lqGwb4xRtJRCmmNYxkQnfYuWIyAaLo1WuU0a4tFILssEDY9VOoOzY+juclP8TSTbdkMHko5kfk1HOoUJgaYZrWK2/hzOvQzgBeg4kW+I8gY7iA9Ed+eMt1q7SzvoeD+EPoo9F2Ht//icBWm93830/5BfGFlrkX2rCIUBoYEKrsmBdYcbZdM12VikrjB8bj79cN5KtIWnSHeJhkIaOF4OC6Xjh17W2TneYhqw3BHZjS8wBcHgnIUnv0pHAXGVlxKg8pXD4EcsRXvMQ4+l/Q3dENz8yBW6LCcmEu4h7oLTeq95EfYuHsPqRPF15bAj2nukD2iiMWl0a0FNc5pQXpTc+TNqC/QTljrH7A4ICd086NgsYkoHbH3C7iARvf8LfHVg6BHItTssWpUvwcwGPkrodMeTYNxo1JIQi/yi2yu0p0R/6VnDoWhdmwChDT4oY3VojrQCkpf82sst8U61qt7UcLteYl9FeWv2mwsCyiPoLoZcJbnHjcP2oqFz0kAK8pAM9fqou2LK+itr3On3sE0b6WW6r33eYSHdwD0pVZrlr2nQ/vjjkDe6Z5XWhTYAIZXVy3IPDMjtdjn9f7E+Fb8+TFkZBTeRuyzVMhPk9nQLI/qZcekHrLHR52ryPDOCZkgw0oDlCDS1Fa9MzuP1NJKAiND/vPFne/fsyV0Z43k4op9NMxyeex0VF1g4Iw1GE8vG+C5gz0trPxgEmNrS+0j8+aw8Wob7N/hBp0TW/SDEhmYEyIHti/RWnShCSRoWXI6URnjwKAB4dvHDg+tHN2GVR7lp9H1x+JUITj9sVnYMf5JPBAQ2tiQh7hV7Jf7gv5+SliNB0zDEVmSr6ZojJ00fdLkgAuQF8ENjEBYv3BpDgJzPTSefngNoom0HsKC+4Q3Ox0keMRN8qesPEgX3ae5hy2jQUMRwBgXxqDBSdN1VdE0LP3DVrA6WQzMM+9ZbqocltZ0lM41Xdq19MkCXkPKrKniJX2qYiJOQp1GibZylMGwCWxCM= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(1800799015)(376005)(36860700004)(82310400017);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2024 19:28:14.1577 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 485633ea-56a7-4ea3-ecf0-08dc7a955327 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4439 X-Patchwork-Delegate: kuba@kernel.org A proper query to MPIR needs to set the correct value in the depth field. On embedded CPU this value is not necessarily zero. As there is no real use case for multi-PF netdev on the embedded CPU of the smart NIC, block this option. This fixes the following failure: ACCESS_REG(0x805) op_mod(0x1) failed, status bad system state(0x4), syndrome (0x685f19), err(-5) Fixes: 678eb448055a ("net/mlx5: SD, Implement basic query and instantiation") Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c index dd5d186dc614..f6deb5a3f820 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/sd.c @@ -100,10 +100,6 @@ static bool ft_create_alias_supported(struct mlx5_core_dev *dev) static bool mlx5_sd_is_supported(struct mlx5_core_dev *dev, u8 host_buses) { - /* Feature is currently implemented for PFs only */ - if (!mlx5_core_is_pf(dev)) - return false; - /* Honor the SW implementation limit */ if (host_buses > MLX5_SD_MAX_GROUP_SZ) return false; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net 3/8] net/mlx5: Fix MTMP register capability offset in MCAM register Date: Wed, 22 May 2024 22:26:54 +0300 Message-ID: <20240522192659.840796-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240522192659.840796-1-tariqt@nvidia.com> References: <20240522192659.840796-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001508:EE_|LV8PR12MB9334:EE_ X-MS-Office365-Filtering-Correlation-Id: 2398008b-651c-44e7-7089-08dc7a955483 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|376005|82310400017|36860700004; X-Microsoft-Antispam-Message-Info: iDMNd5t1ss7WO4ulg+8v+hW5l2OQYTz2O1dwac7VXhl4VvO1idfvvq0HyYZWuX5E/h9ckQEsI9kNofAD7LqjHyY/EJOyMiyn1dxIjqS9nWzvlTlkJqr1SDKDeCw8anPHfAJSxHPlebP8kiVttoKGkZBRM6XmxQbXsG8zoUIa789DGj4vezPcEV93QZJhyVBMDUQZQE1xz2KDYrHqY4N/fRSXytMGInWCm49dlKItoC5tqIpNZw+m0C+HfGuXUGX4MIokYPttE1MIKDo3DsJ9nprc57hW0JJnzCeXLhgj5n8yJdGg2msRpg3RQ1ExBgyktNhjF2Dj5UWrXfwV8HWhjIC9zG8vU4DXq2sL7DK4gro/XRFa2ch79pY1wJl/EyDo8i9OiUIFnQv0AYfbCFYajMyZLvasze+ABBQ/5YjjOxh8/hy5athyk2uCPWwE1XDxSk54fsgY1SCzYO1l1kN7mFwHZESduS44U4ly8G9hrPN7tJluCsqWSzB+kmpxOstoEtetd0SUJRSm4GDB6YNpoCbRt0voDqtR8rONv/QqnB44rI/rpgcWzCI3arnBlSdsUnC4BpYiyp/5HaZwf90BhxDmRQVg6PeHnGCG/Si8FP7mLtwOLSo2NabAfEonsCGmB4VyAMOjWH5NcfEytZpiLQn2whDTbSxhqPth8bzmaoaH663YQH1jENKL59IJdHbIKgVKCPDsVxk3RISb7kkLo6WxGQj4RkwM0vRgqdTG+MM1Yh6lpJJRqGEZlWwzeSaWUuRGEXAnNxkfgque3c2sAJYLbBMGsaZCnt1j1tEXbD9i0++U3Rlgs5u+clUNDk/3kHmPzw2oPN6q8cbvgNPlVh7bCzyvuAllW67q8qjmu+JGO/Pmm8fGGP/QQPqMiMXpnWY0P09ZcL94wqiJ/6PX2ItUCxCYCm9k+kkzUWGNseVoVyJ+XMtHxpiWmxt04fkYOhSOsQbNvJqs42V+Cwv2Pnq5SCzhOUMJVtiFCdtdgpY0l451ndw14HILEyTBprYD1JptDge3Rgw4s0HrmT+OdMeTrbcrhvs7iI7GI5adgUtS/HdB1ONuHihfd+aMwZTQS1fvZBD7TVZtlji+a5voygQfKKIHOcobzO8ek5HRhEBpSN2OgRQEGLSzRlw0+ALDbQ+LxoNf8SUPrv4/2RwddWUrWTvxvCob9Xug3VLKX8ButAD7rtKoNSFEnO3SmFsvFyaOeHrdhB4S9fqiPcjfxo51I/UTIv4bfi3qKiGQ0lHGvFqdq0irrgIbAJUTRw63baFiAVV9AiYH8trUxqE2wIMshba5tlGL3WmsNLOeX4WIDkMEg2YLqnHNiRi2bwoNRx7aaL88jK4TsVIJV6KCs+AcpXa8MxAhwDT1RJzb+ctoX0Iuzq3jk4AlASVGe/GR X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(1800799015)(376005)(82310400017)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2024 19:28:16.5133 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2398008b-651c-44e7-7089-08dc7a955483 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001508.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9334 X-Patchwork-Delegate: kuba@kernel.org From: Gal Pressman The MTMP register (0x900a) capability offset is off-by-one, move it to the right place. Fixes: 1f507e80c700 ("net/mlx5: Expose NIC temperature via hardware monitoring kernel API") Signed-off-by: Gal Pressman Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- include/linux/mlx5/mlx5_ifc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index f468763478ae..5df52e15f7d6 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -10308,9 +10308,9 @@ struct mlx5_ifc_mcam_access_reg_bits { u8 mfrl[0x1]; u8 regs_39_to_32[0x8]; - u8 regs_31_to_10[0x16]; + u8 regs_31_to_11[0x15]; u8 mtmp[0x1]; - u8 regs_8_to_0[0x9]; + u8 regs_9_to_0[0xa]; }; struct mlx5_ifc_mcam_access_reg_bits1 { From patchwork Wed May 22 19:26:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13671036 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2066.outbound.protection.outlook.com [40.107.94.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 511771474A8 for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Rahul Rameshbabu , Tariq Toukan Subject: [PATCH net 4/8] net/mlx5: Use mlx5_ipsec_rx_status_destroy to correctly delete status rules Date: Wed, 22 May 2024 22:26:55 +0300 Message-ID: <20240522192659.840796-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240522192659.840796-1-tariqt@nvidia.com> References: <20240522192659.840796-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A0:EE_|MW5PR12MB5651:EE_ X-MS-Office365-Filtering-Correlation-Id: 01ec9fd8-d136-4c3f-c5cf-08dc7a955656 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|1800799015|36860700004|376005; X-Microsoft-Antispam-Message-Info: birNZFjy/93Dc3++jBFXjX2jIuPejIBwlsX0JMOo+xpY0Nz98vq9p8y6A3BuMYiYJiCMMz3XsMmFucD6B6kq/E7YI0DtrpNiKlW5QQCZwq1tyM8xg6CijUzVOtXvQUkU6aDzyFvHlMLtMJDqG+Os+5ciHULBB5+SEP0s6ZObAKclTzpgjjh69at1Pm56nalCrX2N4BUB37hVf4soRMj3cVItxM+fDX/A4P2t7/l4V3GAmJbCrEgiw6wEAB4THONvD3mkntkebOxlptRozc6W7aITv5929Uvy/3VAcSFwUbmyWGdI217cD3eENJzyDj14nHycQCrj5K770lDGblGVWYY425+7BAk0LpcFwdR6Lu+6Vf8inSxAmHyMuU0sSho2PdGvGzi3NMU25st0lOCiJo5GXWQj6cHppP0F9YJAcrMqb94kkrup6rseDhVgVnFiKJpaVpHrJUBrV0LmDG7eA3PZAHniLAeHek8loUl9rfpN7arHWFxogKr9c+fcEgn0sZcny4C6AtuSI3bPakBWInEUFBk3CtxfJpl4jCTvrmzkhn4VIJDbzrbEB6TBL+zCyLGan4ykCmJ/MUl+waSr+xxxt354RQHk7ypgzcDcoWhTSANXf+WbTh8PGiXFT4/RPgPtg718VIXnIePv00O9iovkdA24o56PpLzHBesPJ+fieCg3p7T+0OTGXYA+hKGVD6sYG4/yQdSq3/XB1rQI+6nT842M8NAywq/bl02p5hhA5PriqjCsiFHHsoDzVYGrgsLlJB36Zr/Ey/P8hIxLW3zn40hLDcHXirYp+fxyHMo+lufOMdN6MszjogYzDNcaSxv/z3P0SormsTt1JP3BRMNy5nNGPTrn8QXOXwp+bHTptqiNtpCqpRIbMAOePZy6f/p8CA+nMndatgIgnikJO9ZwJITL0UUhBE2/2lEl+Ed3IBVF05fTAxtm/RdbW/K+hhj3ZvfdKSx9llyCK9QriDQJCc49GWpnKSAqkQpqD6jDxoPRKZZhdryO0QIu7jMcK/6WE0mm8AChzx0LcawCd9RLxLy+s7Egc409Dj93+4Eqg/V2IkHNvmM8dpKArmV533mDq/3qI+9hYKtazoehpr6MszdvbfsDYpy3iMVAr7n3HWphl9qqA/nTwd/OnHrOoGlSnSVt88J9Loo79A3oUxe2H8tDYZrRFv2pdknWGoL38YkxEBTPVD8+D0FTH1ECL59GHh0JTWQZ60n8vF8ljekf7sAo8VQ5+cDFE+kGSxAooPO7E5vVbVxfwvMTRHYmQNpDETG18u9Ppx9tjmxmnTIs+URrFKO+S59zx6N6FqJGcMnmlhJr+DPpwZeYm6+LpGZUYsll9e1VPQLeTRYuoeqBMqMoxqx3aakIDOWcSTrNQjJv2A6aFibfk5zKvg8r X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(82310400017)(1800799015)(36860700004)(376005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2024 19:28:19.4979 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 01ec9fd8-d136-4c3f-c5cf-08dc7a955656 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR12MB5651 X-Patchwork-Delegate: kuba@kernel.org From: Rahul Rameshbabu rx_create no longer allocates a modify_hdr instance that needs to be cleaned up. The mlx5_modify_header_dealloc call will lead to a NULL pointer dereference. A leak in the rules also previously occurred since there are now two rules populated related to status. BUG: kernel NULL pointer dereference, address: 0000000000000000 #PF: supervisor read access in kernel mode #PF: error_code(0x0000) - not-present page PGD 109907067 P4D 109907067 PUD 116890067 PMD 0 Oops: 0000 [#1] SMP CPU: 1 PID: 484 Comm: ip Not tainted 6.9.0-rc2-rrameshbabu+ #254 Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS Arch Linux 1.16.3-1-1 04/01/2014 RIP: 0010:mlx5_modify_header_dealloc+0xd/0x70 Call Trace: ? show_regs+0x60/0x70 ? __die+0x24/0x70 ? page_fault_oops+0x15f/0x430 ? free_to_partial_list.constprop.0+0x79/0x150 ? do_user_addr_fault+0x2c9/0x5c0 ? exc_page_fault+0x63/0x110 ? asm_exc_page_fault+0x27/0x30 ? mlx5_modify_header_dealloc+0xd/0x70 rx_create+0x374/0x590 rx_add_rule+0x3ad/0x500 ? rx_add_rule+0x3ad/0x500 ? mlx5_cmd_exec+0x2c/0x40 ? mlx5_create_ipsec_obj+0xd6/0x200 mlx5e_accel_ipsec_fs_add_rule+0x31/0xf0 mlx5e_xfrm_add_state+0x426/0xc00 Fixes: 94af50c0a9bb ("net/mlx5e: Unify esw and normal IPsec status table creation/destruction") Signed-off-by: Rahul Rameshbabu Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c index 41a2543a52cd..e51b03d4c717 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c @@ -750,8 +750,7 @@ static int rx_create(struct mlx5_core_dev *mdev, struct mlx5e_ipsec *ipsec, err_fs_ft: if (rx->allow_tunnel_mode) mlx5_eswitch_unblock_encap(mdev); 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Rahul Rameshbabu , Tariq Toukan Subject: [PATCH net 5/8] net/mlx5e: Fix IPsec tunnel mode offload feature check Date: Wed, 22 May 2024 22:26:56 +0300 Message-ID: <20240522192659.840796-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240522192659.840796-1-tariqt@nvidia.com> References: <20240522192659.840796-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A3:EE_|SJ0PR12MB6944:EE_ X-MS-Office365-Filtering-Correlation-Id: a9dfd6e3-0b6d-493d-68d3-08dc7a955977 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|1800799015|36860700004|376005; X-Microsoft-Antispam-Message-Info: zlqb2weBSOHAR27WsYMs8kEsthj0XmWj3uZ2w6sKaWu0uP6/b1YzPsvICHCw8ngqMjd993gY1Z1iDTgByAWJEKElNGNRhnkF+tfpoJBAkEVek31IqADl7ZsjVtzWmrRg8h314ed9cTftUsfbiZ+yWjHfN8qCtRxFN+Rwo7gJADra+l+n00Wa9+Ddqc7YfuQLECs8OWIpm+gbO6q6/2O9aHbfU4Semzzo6p669dRlsseDEzdS2WYRD+42SK0KCeDCdcgsPn21MueQV0ukcb/PMg0vUcz1Ut3sxC+K12IYH1QKbKHacKh9dX4A/R2a8L9IKc2EMpeqNYc7bARKzcK03vwB/Yh2KpR3r9sXF5pCuIlqqAZpzMLBxmLvteJXoZtA1MmZg0ou0LQIH9gZPZsNClheZk1KpCZNaUzaSRkTqsVz1DiwNBHG+op1okuiJjF1NDli5zcbspqffoXjKsgKDp4+8JogLkRPJBSNdWZ1Ntvn22pCPERsV2a4UfccE+pdWR9mJlrh/KCDGs3sUm+vyNiwLp5pklSV4z3cmT++q0QnZLyihVPhIGIiZ1TspyJQoLsF1mOvV+5ZaA7XNdxoTiR1kjl2D2BF0NJag99TOih+vpoCoVjAeO3hQ90ivQSeG71DxBF7h55ZJK0U2iEZJvtFySU8SkKRylxjJtnbewvxxqWFHfb3SmlR5UsU5Jt9ipYxu2leKHGMjIE34wwBtdftFeAVwcniiFu5C6rinceJIUoKEc1jHnVho26QYOguJyqcqYIxczkFJlI7D/evlgQ8VO0/8uB+anzQECCOfuoyCLhLWgZuPxwrcYEWBHF1W9XibvgWb1c6YEHj0nE/FjvC65zI5DZoTtCOZ/jwZDop2NqQ0aSqpvfDTsO/5nCi4A4nZXtEzNq4lo4BGFSL6pZh3vAQyHWnYJ0Ii3zyVswpesCzLwKP9nP41q0PXfZv2BDJ4gryp7U18MwtgVJRq4ccnM4+GAFM7o5c+dCDFnJovuS6fG8O5HPidcpgnJcXQe0zkjKVSiJ9kP7TreiCgbGWQThVl9W2FJIqBYXh5ce7r7d6tBHhP0nunxDtqrNobFFELHw9kbIzbgWljgU9mYiQHErgbLES5QoQ0HNywDg3omCwWH8NWVsp666kGTclCQn9YtTLifKzn7NNxH+PZpR59czgjz2dNAX0g4GFhTLjNI499Ba3692KCoyBSvmOB/Z5NE6Ktp/yUwhyM1BY2ErIqZuo8dWQ3VWiZRGKxXwXBSwYThgnFDm1+ShcPGiBwxlOWurFDEfcYT79F1tl9d+qLHzQ8qJSYvlg4p0AFtHuLvviiLQpor9E0t9yqwyI06qcBSyIwT4Tsj6yvExpwpYkgkeU1u6+mggfnN56zfIjaUw+BH0jgvh5hDXDL4Ll X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(82310400017)(1800799015)(36860700004)(376005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2024 19:28:24.7450 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a9dfd6e3-0b6d-493d-68d3-08dc7a955977 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A3.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6944 X-Patchwork-Delegate: kuba@kernel.org From: Rahul Rameshbabu Remove faulty check disabling checksum offload and GSO for offload of simple IPsec tunnel L4 traffic. Comment previously describing the deleted code incorrectly claimed the check prevented double tunnel (or three layers of ip headers). Fixes: f1267798c980 ("net/mlx5: Fix checksum issue of VXLAN and IPsec crypto offload") Signed-off-by: Rahul Rameshbabu Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- .../mellanox/mlx5/core/en_accel/ipsec_rxtx.h | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h index 82064614846f..359050f0b54d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h @@ -97,18 +97,11 @@ mlx5e_ipsec_feature_check(struct sk_buff *skb, netdev_features_t features) if (!x || !x->xso.offload_handle) goto out_disable; - if (xo->inner_ipproto) { - /* Cannot support tunnel packet over IPsec tunnel mode - * because we cannot offload three IP header csum - */ - if (x->props.mode == XFRM_MODE_TUNNEL) - goto out_disable; - - /* Only support UDP or TCP L4 checksum */ - if (xo->inner_ipproto != IPPROTO_UDP && - xo->inner_ipproto != IPPROTO_TCP) - goto out_disable; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Rahul Rameshbabu , Tariq Toukan Subject: [PATCH net 6/8] net/mlx5e: Do not use ptp structure for tx ts stats when not initialized Date: Wed, 22 May 2024 22:26:57 +0300 Message-ID: <20240522192659.840796-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240522192659.840796-1-tariqt@nvidia.com> References: <20240522192659.840796-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001508:EE_|CY8PR12MB8362:EE_ X-MS-Office365-Filtering-Correlation-Id: 6ac62246-bbd2-4ceb-8bd7-08dc7a95590c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|376005|1800799015|36860700004; X-Microsoft-Antispam-Message-Info: 7G70XtI3y/Pmo85a6Y11WMVIPHIGl1Le/NXOmt3khyilpI9sW1W1CbtJp9fzfyVBrUniYdOK0JsW8GMaqbMhjG883bOBhCosPCQj7ewVxli3EXJbylRx/jMbznimrbADbRXn4Ozqk/zrWtuHuu+de2k7YQ31/wRstmI/xEhdS+YzzwIwf3DoUOk5SuoaQv7EhwMTiy7lsQtxVXP9dB4CRZUezZKt14AWQf1rtLE4gEFH+7ssYImvvPgSrQOMBq2b9QvhciNrfIxTFsdKWeZ/HJZ7la0cge9uVfwhY5Nr6edxj2ZQMgemr4liR6H5lRygl46f/PjrbyFoMt5pX7LCXlTm2MmAzWXAqCEfzcPxRu6Dpjk4tquMglqMZeXPFEkbNN3QUmw5zjqZH6TJwh0MkBoQ5jswtqwKuhHw3n7LV5NkJe//kiXabuCMOjAKYrOOSuohggQ2O/Vfc+V2baerd4Pj2a12Yq1AyzMgaaRmC2ieQ37bJooFmCB7yPq52iPUQSj4XpWmTFk4sWYUs6T0vJb6BgrRI3AQYvbRAYf7VCGrauqZYpMqFnGXevVRxTR0nT38fNRaTXuYEH+6TP3Bb6/UiEvpDsa6HRVfPXQmReRjor5phVU8rj+ETzsTdv98ClgP7GABhU7ZeSANx4CWcPA1StcSm1HS9mjAKVVS2lO4lsAcH0+6aag7WWHQmW308wI4vaonaK8BK1SUN1tNQVjTd2KCI0eSeCuckmcDP4VPdIt/bPbNxZIlPJfVOQiZ2MsEZ7ruBf10kgtMAUSB+i/vJjPHZc39eImdPj5SP59xMd5A7eBdZk7ydG3PrvFzpBU2Mpam9/dQpzeSZiupR6kw1Vko3TtV+gBNnthWCmRyuEHf9fobS7CMJKjHseCEChtw0SrRcY3INBdZNkUuDdcgHxhIvTvxHg4hddH/3Hl0gJHBUQ6Qc9dzoEFd2DXKUqWHcfwBbKB1Ij8BekR4Pb4CAC9VnSBmmzNOui6YhPj2idrD+UENQjbvbKSnsCVj2ChzBbRGO0UtAbQTD9BQestVyNYipvX5RyITkCDtNMCA5KcwnUMk6rjfqPF+I2il/mBrufPX9LerA6+UhFY18ruFRgwY+PsSO8UUg2P6StJMjLJCQTcH4D1ersQyRWXL57T8TUZswm+IZtdXO67Ywh4YJMNZEF39hUQi+C8/mAF1uotNSqusGWwLHNgXXbrYgxABPHTdwmYovZ4jS6qgIBuuIgLSBrdgwICwi3Kv8SPCOoKqc60vK/PHRr9D09ptHimiCNPbh4Qhft7BmQSx5pTLZBX6HwHRboIpznIKoYQ2yeTn7/Y60ydh1ZLPEru2TXXNyJa/RqAvS7w21PgdaKSBFSYASE2n4E7n5Ck3Sdg= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(82310400017)(376005)(1800799015)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2024 19:28:24.1071 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ac62246-bbd2-4ceb-8bd7-08dc7a95590c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001508.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8362 X-Patchwork-Delegate: kuba@kernel.org From: Rahul Rameshbabu The ptp channel instance is only initialized when ptp traffic is first processed by the driver. This means that there is a window in between when port timestamping is enabled and ptp traffic is sent where the ptp channel instance is not initialized. Accessing statistics during this window will lead to an access violation (NULL + member offset). Check the validity of the instance before attempting to query statistics. BUG: unable to handle page fault for address: 0000000000003524 #PF: supervisor read access in kernel mode #PF: error_code(0x0000) - not-present page PGD 109dfc067 P4D 109dfc067 PUD 1064ef067 PMD 0 Oops: 0000 [#1] SMP CPU: 0 PID: 420 Comm: ethtool Not tainted 6.9.0-rc2-rrameshbabu+ #245 Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS Arch Linux 1.16.3-1-1 04/01/204 RIP: 0010:mlx5e_stats_ts_get+0x4c/0x130 Call Trace: ? show_regs+0x60/0x70 ? __die+0x24/0x70 ? page_fault_oops+0x15f/0x430 ? do_user_addr_fault+0x2c9/0x5c0 ? exc_page_fault+0x63/0x110 ? asm_exc_page_fault+0x27/0x30 ? mlx5e_stats_ts_get+0x4c/0x130 ? mlx5e_stats_ts_get+0x20/0x130 mlx5e_get_ts_stats+0x15/0x20 Fixes: 3579032c08c1 ("net/mlx5e: Implement ethtool hardware timestamping statistics") Signed-off-by: Rahul Rameshbabu Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/en_stats.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c index e211c41cec06..e1ed214e8651 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_stats.c @@ -1186,6 +1186,9 @@ void mlx5e_stats_ts_get(struct mlx5e_priv *priv, ts_stats->err = 0; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Carolina Jubran , Tariq Toukan Subject: [PATCH net 7/8] net/mlx5e: Use rx_missed_errors instead of rx_dropped for reporting buffer exhaustion Date: Wed, 22 May 2024 22:26:58 +0300 Message-ID: <20240522192659.840796-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240522192659.840796-1-tariqt@nvidia.com> References: <20240522192659.840796-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001509:EE_|CH3PR12MB9252:EE_ X-MS-Office365-Filtering-Correlation-Id: d42a6fe7-a218-4a5f-7352-08dc7a955b5d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|1800799015|82310400017|36860700004; X-Microsoft-Antispam-Message-Info: KudAWJyoAbd2RkZ4aD8h3Ob8K/9wDbZ0CtytSJa2C97DGjTX41U3A9N1M3i40Bz+A9ALPKMIZrGiybQX4DFFu4vP3epnI5H7CMTb2Ef9xHKSlAiou4/ZAHW5umVrK4qzgkN7mFnxF/WMRXoO1UI4vsds8+iyaArauMDTjFTeJKl1j7J0tkFLPiGEYwB6uyvCY8/GuzZLTHy1bwKkXhq1VsuLAD2FVWx8IYA3n3HPftYbFBw04Tzp1USVO2mKCjggJa96zMHT7+rLNh0TSs0fswpZhqVg59nQ3oAtEEh3wHxHaaIyYRkDHX2bSylkrUHy/U8snAQHQgEFUzzGDmJ38Nx/s6BHZl7Cesjj+mIJhAsjoDsIPLMwB00r8ulJKIwFlx9SECuHH9DXSwS0UfYzkIRd9c5vcMCz6LzqWpuSNU0FLrcWbSU4mtPU8fikKtlA0c7vZSsVrIce8rwCc/Jya1Vu+2yRwv8jzZHpI0TtW33kQlKT6yeliqTTV+EgXPE2JkxM3Gy3FzsUpB/HmPR/SzGVq2QceVycNrbDzQc58zUvJyv5oe6wcLt2eNIyYeGL29bFqsgpg/tUoR8Fvc7HaGVFQMmapgrv0pOLRKntU2cLOroaAWpcPKIMir8SJttEL7f4DeDNNK4/DdXjY5ZwoKqkedviO2gnGgE+2Ox3evtjRSgVJ3W+y3uYhj2b/phAPSlUpwGK5fYoxOp2pRiwPzR0WUhtbRxebiljd0Y5LLJnIbmNgqD9r5brSft4tKRJh4+TDAEUtDMgDMxElOWouIYnyCvXYgFU8g0UDdF6H04Ty9jn0y1YtrSB8IcFOuHysGL2UTSPzKUHRbkiZJkfi+N4I7Boc1MCkXL+rndQZIANY1kJzlMqNovXV+txUxzDdZ66+Iy9erxuvWCRP/QYfLY1oIM0HG9Z+bZSXqA3rfwDCu2YtshJfk6JRNqTOS5rJY1UyGS07yn/7frbHiP7cNs8IcoL/kBAQF2UCh1/F4wL0PpeT9qiTIS9n2RigFZriV8Tpwgv8lXYuQARGuj1rUJl4ZRHEOMIooFZ2X3dfqTXIdfRY/osfJjVdHVuCMU+SV3u/tWojF6KyTTTpiP8YIccNeHtntCiJ89qAIjtCGE8frtRiA/EEcladNrL2mnA1yUsExUjGkNDJK78tw7hmCnrczcodMPI/2X+8MjfNDv8eFga3GsmnzL7v6RLDk+RcS9YKkW3E0M1XxjCGDHAncl4bUOEozApQW82mefbfC6GTscZt/VICDfsxVn5//MMigHTqXwFQScmNmD6vtvskyulXkEQl2ehSUdOw1h1NRJRM0MyzRkWWj1KNBnXw+xBlgU7U4OTZYbn5j0ewuE0PAgK25sD+WTWAypQtaxqng6x+8I8FwduIxDFVevKIXQL X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(376005)(1800799015)(82310400017)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2024 19:28:27.9303 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d42a6fe7-a218-4a5f-7352-08dc7a955b5d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001509.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9252 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Previously, the driver incorrectly used rx_dropped to report device buffer exhaustion. According to the documentation, rx_dropped should not be used to count packets dropped due to buffer exhaustion, which is the purpose of rx_missed_errors. Use rx_missed_errors as intended for counting packets dropped due to buffer exhaustion. Fixes: 269e6b3af3bf ("net/mlx5e: Report additional error statistics in get stats ndo") Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index b758bc72ac36..c53c99dde558 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -3886,7 +3886,7 @@ mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) mlx5e_fold_sw_stats64(priv, stats); } - stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer; + stats->rx_missed_errors = priv->stats.qcnt.rx_out_of_buffer; stats->rx_length_errors = PPORT_802_3_GET(pstats, a_in_range_length_errors) + From patchwork Wed May 22 19:26:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tariq Toukan X-Patchwork-Id: 13671040 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2080.outbound.protection.outlook.com [40.107.93.80]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DED2148314 for ; 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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Jason Baron , Dragos Tatulea , Boris Pismenny , Tariq Toukan Subject: [PATCH net 8/8] net/mlx5e: Fix UDP GSO for encapsulated packets Date: Wed, 22 May 2024 22:26:59 +0300 Message-ID: <20240522192659.840796-9-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240522192659.840796-1-tariqt@nvidia.com> References: <20240522192659.840796-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A3:EE_|MN2PR12MB4406:EE_ X-MS-Office365-Filtering-Correlation-Id: d509382a-d119-4c69-11e3-08dc7a955dcc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|36860700004|1800799015|82310400017; X-Microsoft-Antispam-Message-Info: 7XZ4fDj0At5fpNj5l0MF6BfGeAov13m+3tQgSDQr2rAVEbmTb59tOn7LiMrHjLMleu1AZTy/1Mg6GKRn3FsqtUlu9Wp4FcjVddqpAjrbiv9j3z9fDwsVTvX7bZpoApAZDxQpROYOPtgdl7D1EJSHzYZcexZWdDZQjZXLTzpMsxgviHBu+OKQTHI6Y5hw2vE48FJ3/o7vKj5aTLZzgI8tH1Y5VZjpZQM6hfA8t4wdsrELQHotarRdlIvbvY9ZpyxsL5Qd3wmnT1jV0CzuF36uRStRcUw3pjywkLiUVS/yeDdgj4g2xssN8by8cBdVNMYp3xl9R62TUKosc33oFq3r1uiiCpCxE6uRFumHBf5Koxy48+rVk4S/PDBDBqbdpXaO+k2vZWXZDsWqQOKL27/JWmppTOUkobYebKJpPW+SZ3vcKHV7qI7gB92rj4XvWcC9QPAu8KVeNQFqsEktUl0Z16RY/jtF2/iVdE7t0QN8imGyRQQHkQROJ/wFIsbxmUy6KI/4AvFYG6ZfOdARJwaxQo2eE9IgU8mmu7ZI0DsGoYY2uTzA82g7oTpp977dfBbe9bR01VNEfk6HXVad+gHvMcPVkmGybsu/pcknSY8Pg6pVadkdhgDiTKmB/mJ4PNAwijK+jIaUITbgFXhuIIoPX5ZjXKOuaJnnxdyK3SXfOu0BiaHdc/AKNuXLyZMVxA4lSH6TVW+AyZojs4X1dFCeKFJ++6NQWj21h3oUIYtXifnUjoC6YdYBtl4CRyLkfmFiJ31QkdSdNx3uf+XjAGhEAP+1ZoVU7saBy4RsypftkgYrDZDN46rsvh6mr0igd/qKZfEzRRlNp6zlyRJIgFjhPMUX1stjiIPIEBap3tTCFgN6hfvULtHL6cIS2V3/Ug9qncC0t9OE3xScPiH78FYobL2VORxv91cu2+liEkUSq8p0LMTdFh2SAs6N7TRVQAcNGpjvAsi47qhmJvNhNh3/4HXp3Zfw/nJteLzsc+R8rPfqr77NXfWbyNVzeYNLG7KcB3+v/ljlWxca+he6qZLw/5SodP1uvhGsM1iQPIHzRqe7/jOnfL1kb0npsMX+jGV6QujEoDQEpCGocsj3HsxVfKAeejKFOzmT6n3HnnEU+4j9bPU4qNwSmpdXvwgznHiJBeWRnp7vgLprAe78sMxRxP7lD7I3xtE6e8Eq6AaHOZ0spWO+a8+9i3ImRsq3ld+hOgiAWSynwBhZ/+eTlZe3qMo6G9f9JH554WcUjCKyGomczYehZZ5KvGtGomzlccyqSNSaMNxYUn2aoCyiGiGwwoI3QBsC0HKRGBM//Me2g7AVLLf6qjswPhgEmWDlACKXdZB8xnGTE00qQ6GuocDBNg6uy61SkdjtdZyMwf/4B0niO493gj2ONiMaTsl6rO6M X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(376005)(36860700004)(1800799015)(82310400017);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2024 19:28:32.0107 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d509382a-d119-4c69-11e3-08dc7a955dcc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A3.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4406 X-Patchwork-Delegate: kuba@kernel.org From: Gal Pressman When the skb is encapsulated, adjust the inner UDP header instead of the outer one, and account for UDP header (instead of TCP) in the inline header size calculation. Fixes: 689adf0d4892 ("net/mlx5e: Add UDP GSO support") Reported-by: Jason Baron Closes: https://lore.kernel.org/netdev/c42961cb-50b9-4a9a-bd43-87fe48d88d29@akamai.com/ Signed-off-by: Gal Pressman Reviewed-by: Dragos Tatulea Reviewed-by: Boris Pismenny Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- .../net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h | 8 +++++++- drivers/net/ethernet/mellanox/mlx5/core/en_tx.c | 6 +++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h index caa34b9c161e..33e32584b07f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h @@ -102,8 +102,14 @@ static inline void mlx5e_udp_gso_handle_tx_skb(struct sk_buff *skb) { int payload_len = skb_shinfo(skb)->gso_size + sizeof(struct udphdr); + struct udphdr *udphdr; - udp_hdr(skb)->len = htons(payload_len); + if (skb->encapsulation) + udphdr = (struct udphdr *)skb_inner_transport_header(skb); + else + udphdr = udp_hdr(skb); + + udphdr->len = htons(payload_len); } struct mlx5e_accel_tx_state { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c index 099bf1078889..b09e9abd39f3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c @@ -153,7 +153,11 @@ mlx5e_tx_get_gso_ihs(struct mlx5e_txqsq *sq, struct sk_buff *skb, int *hopbyhop) *hopbyhop = 0; if (skb->encapsulation) { - ihs = skb_inner_tcp_all_headers(skb); + if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) + ihs = skb_inner_transport_offset(skb) + + sizeof(struct udphdr); + else + ihs = skb_inner_tcp_all_headers(skb); stats->tso_inner_packets++; stats->tso_inner_bytes += skb->len - ihs; } else {