From patchwork Thu May 23 12:59:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671797 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B0D6C25B75 for ; Thu, 23 May 2024 12:59:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C780A10E4E2; Thu, 23 May 2024 12:59:55 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="dOc3RQbH"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id BA23910E4E2 for ; Thu, 23 May 2024 12:59:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716469192; x=1748005192; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rs3z9HzdRBzbBCkQW5guuWz+ROPpqO5uAFFVkKdV55c=; b=dOc3RQbHtuPFo8TxFcFfAPVGpxvC9G1XQkfyNvX8JO2XISh6wDei6z9o F3rfdBnQpKSDckCC78Y+A/3JYibWKKF2s3F5D/CuVO13AQbwuOOp8/pA5 RpjZEy7X1cJZIHEo/X02r0UKEvIdG9SHbwqqVfUiJFzyKpahApP9Hhn0d PfjHgbR0+DXbKq23PTy1SLIR/UerdIPZM9a6MO80dLWmCSHdtG1bbF7aw QQ88j9kiDUZfSIOPQza+BmhqMcBdY6uUXg7CAmO5+e+fp/RNmdGhC8KNK lqVm9tl7JSf+UJTFA47kS1ke4cuOgxUMQNVftcCvwBo0VU++ZMfZxfHpZ A==; X-CSE-ConnectionGUID: ixOwJBnwS0iz/VJYbgMRww== X-CSE-MsgGUID: tllykwjZTQmBaYzq1N5xjQ== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="38164655" X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="38164655" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 05:59:52 -0700 X-CSE-ConnectionGUID: wO8v6RT4RQORPTmn9Zxx/w== X-CSE-MsgGUID: iMP9njP2ROuW2jHlVzab6w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="33731553" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 05:59:51 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 01/16] drm/i915: pass dev_priv explicitly to DSPADDR_VLV Date: Thu, 23 May 2024 15:59:29 +0300 Message-Id: <1d9be6b1eedd9240468a89cd3a10e8513caa33b1.1716469091.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPADDR_VLV register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 1f05f9184cb2..4636523d7948 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -577,7 +577,7 @@ vlv_primary_async_flip(struct intel_plane *plane, u32 dspaddr_offset = plane_state->view.color_plane[0].offset; enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; - intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane), + intel_de_write_fw(dev_priv, DSPADDR_VLV(dev_priv, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index d74a74d1f29a..926da106f1a2 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -9,7 +9,7 @@ #include "intel_display_reg_defs.h" #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ -#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) +#define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) #define _DSPACNTR 0x70180 #define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) From patchwork Thu May 23 12:59:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671798 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F9F5C25B75 for ; Thu, 23 May 2024 13:00:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C06CB10E387; Thu, 23 May 2024 13:00:00 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="QOUVEVOI"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0057F10E564 for ; Thu, 23 May 2024 12:59:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716469197; x=1748005197; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kf5W2AcUFWcxML+CHA11oZKKSFrVeTjoL/iufV9OKyg=; b=QOUVEVOIAij2rrdW8j9HfaAZd0GkTahLxrNawzHj/lzjjn2KcmvYZuqF c+GgantBXKKhKh+tivLVOpMf0ObqtUT4HnsLjrhQR+GymsP1Q0YWoglhh Pwee9niW5MZwls4m71yEFZxQCokpgK7ZBzcW3wgWvZILorNhX4PsJu0hX 4rmUE/i4fgd/nRlqFgT9rSOjZ3Rp8kJDtdAuQ8npYHWqE6XfgrqyKocuQ VUjECGlFH1EJq2IvMTfBb5P9TGjX84hjiw6kPyRk8KcbRuXIJKOpn2j1C llPHp10h7j//EeK2Je3chBJorNS8y/uhzYfV252piA/HY35ppj9KeX+nS Q==; X-CSE-ConnectionGUID: 3RCBN2ENSoeps3G0QqyOlw== X-CSE-MsgGUID: KZ9TUj5NRByOz63BEI16CQ== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="38164661" X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="38164661" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 05:59:56 -0700 X-CSE-ConnectionGUID: 9lRPR+UpRFORmP6XSE5MDQ== X-CSE-MsgGUID: ER1nCfIYStq9Esu9Xg2RXA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="33731564" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 05:59:55 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 02/16] drm/i915: pass dev_priv explicitly to DSPCNTR Date: Thu, 23 May 2024 15:59:30 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPCNTR register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 10 +++++----- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/display/intel_color.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 6 +++--- drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 ++-- drivers/gpu/drm/i915/gvt/display.c | 4 ++-- drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 2 +- drivers/gpu/drm/i915/intel_clock_gating.c | 3 ++- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 10 files changed, 21 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 4636523d7948..ceb0a969357f 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -496,7 +496,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); + intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); if (DISPLAY_VER(dev_priv) >= 4) intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), @@ -539,7 +539,7 @@ static void i9xx_plane_disable_arm(struct intel_plane *plane, */ dspcntr = i9xx_plane_ctl_crtc(crtc_state); - intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); + intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); if (DISPLAY_VER(dev_priv) >= 4) intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); @@ -561,7 +561,7 @@ g4x_primary_async_flip(struct intel_plane *plane, if (async_flip) dspcntr |= DISP_ASYNC_FLIP; - intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); + intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); @@ -685,7 +685,7 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); + val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane)); ret = val & DISP_ENABLE; @@ -1012,7 +1012,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, fb->dev = dev; - val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); + val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane)); if (DISPLAY_VER(dev_priv) >= 4) { if (val & DISP_TILED) { diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 926da106f1a2..d483569e4147 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -12,7 +12,7 @@ #define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) #define _DSPACNTR 0x70180 -#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) +#define DSPCNTR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) #define DISP_ENABLE REG_BIT(31) #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) #define DISP_FORMAT_MASK REG_GENMASK(29, 26) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 82b155708422..a83f41ee6834 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1038,7 +1038,7 @@ static void i9xx_get_config(struct intel_crtc_state *crtc_state) enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; u32 tmp; - tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); + tmp = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane)); if (tmp & DISP_PIPE_GAMMA_ENABLE) crtc_state->gamma_enable = true; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 1e8e2fd52cf6..58a4060f90b4 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -8233,11 +8233,11 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) pipe_name(pipe)); drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); + intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_A)) & DISP_ENABLE); drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); + intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_B)) & DISP_ENABLE); drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); + intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_C)) & DISP_ENABLE); drm_WARN_ON(&dev_priv->drm, intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & MCURSOR_MODE_MASK); drm_WARN_ON(&dev_priv->drm, diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 2c315caf2414..3b6529a6501b 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1315,7 +1315,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s, info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); if (info->plane == PLANE_A) { - info->ctrl_reg = DSPCNTR(info->pipe); + info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); info->stride_reg = DSPSTRIDE(info->pipe); info->surf_reg = DSPSURF(info->pipe); } else if (info->plane == PLANE_B) { @@ -1381,7 +1381,7 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s, info->surf_val = (dword2 & GENMASK(31, 12)) >> 12; info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); - info->ctrl_reg = DSPCNTR(info->pipe); + info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); info->stride_reg = DSPSTRIDE(info->pipe); info->surf_reg = DSPSURF(info->pipe); diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index dafa13ac826b..eaa92d392189 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -193,7 +193,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) for_each_pipe(dev_priv, pipe) { vgpu_vreg_t(vgpu, TRANSCONF(pipe)) &= ~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE); - vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; + vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE; vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) &= ~MCURSOR_MODE_MASK; vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE; @@ -504,7 +504,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) /* Disable Primary/Sprite/Cursor plane */ for_each_pipe(dev_priv, pipe) { - vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; + vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE; vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) &= ~MCURSOR_MODE_MASK; vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE; diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index 521dee39e5fb..48e3b6d8ed98 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -217,7 +217,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, if (pipe >= I915_MAX_PIPES) return -ENODEV; - val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); + val = vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)); plane->enabled = !!(val & DISP_ENABLE); if (!plane->enabled) return -ENODEV; diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 27ef6dfee641..56fb606b4a3d 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1022,7 +1022,7 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; - if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) + if (vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) & PLANE_CTL_ASYNC_FLIP) intel_vgpu_trigger_virtual_event(vgpu, event); else set_bit(event, vgpu->irq.flip_done_event[pipe]); diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index 5c5685ebd49e..59d50195c144 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -138,7 +138,8 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv) enum pipe pipe; for_each_pipe(dev_priv, pipe) { - intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(pipe), 0, DISP_TRICKLE_FEED_DISABLE); + intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(dev_priv, pipe), + 0, DISP_TRICKLE_FEED_DISABLE); intel_uncore_rmw(&dev_priv->uncore, DSPSURF(pipe), 0, 0); intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe)); diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 2375292292b6..909823d7ed1b 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -165,7 +165,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(_MMIO(0x70094)); MMIO_D(_MMIO(0x70098)); MMIO_D(_MMIO(0x7009c)); - MMIO_D(DSPCNTR(PIPE_A)); + MMIO_D(DSPCNTR(dev_priv, PIPE_A)); MMIO_D(DSPADDR(PIPE_A)); MMIO_D(DSPSTRIDE(PIPE_A)); MMIO_D(DSPPOS(PIPE_A)); @@ -174,7 +174,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPOFFSET(PIPE_A)); MMIO_D(DSPSURFLIVE(PIPE_A)); MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY)); - MMIO_D(DSPCNTR(PIPE_B)); + MMIO_D(DSPCNTR(dev_priv, PIPE_B)); MMIO_D(DSPADDR(PIPE_B)); MMIO_D(DSPSTRIDE(PIPE_B)); MMIO_D(DSPPOS(PIPE_B)); @@ -183,7 +183,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPOFFSET(PIPE_B)); MMIO_D(DSPSURFLIVE(PIPE_B)); MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY)); - MMIO_D(DSPCNTR(PIPE_C)); + MMIO_D(DSPCNTR(dev_priv, PIPE_C)); MMIO_D(DSPADDR(PIPE_C)); MMIO_D(DSPSTRIDE(PIPE_C)); MMIO_D(DSPPOS(PIPE_C)); From patchwork Thu May 23 12:59:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E290C25B79 for ; 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X-CSE-ConnectionGUID: l8ayJPR9Ssm2Mg7JNKZ4QQ== X-CSE-MsgGUID: EOFelE7KQcWSVGdDFC3IEw== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="38164668" X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="38164668" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:00 -0700 X-CSE-ConnectionGUID: z6epAkPGTOekpCS+iSlinw== X-CSE-MsgGUID: YNXvp9hgTLqIsAKRVhSM0g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="33731585" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 05:59:59 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 03/16] drm/i915: pass dev_priv explicitly to DSPADDR Date: Thu, 23 May 2024 15:59:31 +0300 Message-Id: <777d4189c18c16392015dd2770f5c56d94bb88a9.1716469091.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPADDR register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 8 ++++---- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++-- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index ceb0a969357f..79280fe2662d 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -502,7 +502,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); else - intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), + intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); } @@ -544,7 +544,7 @@ static void i9xx_plane_disable_arm(struct intel_plane *plane, if (DISPLAY_VER(dev_priv) >= 4) intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); else - intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0); + intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), 0); } static void @@ -1045,7 +1045,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; } else { offset = 0; - base = intel_de_read(dev_priv, DSPADDR(i9xx_plane)); + base = intel_de_read(dev_priv, DSPADDR(dev_priv, i9xx_plane)); } plane_config->base = base; @@ -1096,7 +1096,7 @@ bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc, if (DISPLAY_VER(dev_priv) >= 4) intel_de_write(dev_priv, DSPSURF(i9xx_plane), base); else - intel_de_write(dev_priv, DSPADDR(i9xx_plane), base); + intel_de_write(dev_priv, DSPADDR(dev_priv, i9xx_plane), base); return true; } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index d483569e4147..a68d7b228187 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -44,7 +44,7 @@ #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ #define _DSPAADDR 0x70184 /* pre-i965 */ -#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) +#define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) #define _DSPALINOFF 0x70184 /* i965+ */ #define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 680d7fc39503..f46e01cad053 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -327,8 +327,8 @@ static void i8xx_fbc_nuke(struct intel_fbc *fbc) enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; struct drm_i915_private *dev_priv = fbc->i915; - intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), - intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane))); + intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), + intel_de_read_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane))); } static void i8xx_fbc_program_cfb(struct intel_fbc *fbc) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 909823d7ed1b..944765fe22e7 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -166,7 +166,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(_MMIO(0x70098)); MMIO_D(_MMIO(0x7009c)); MMIO_D(DSPCNTR(dev_priv, PIPE_A)); - MMIO_D(DSPADDR(PIPE_A)); + MMIO_D(DSPADDR(dev_priv, PIPE_A)); MMIO_D(DSPSTRIDE(PIPE_A)); MMIO_D(DSPPOS(PIPE_A)); MMIO_D(DSPSIZE(PIPE_A)); @@ -175,7 +175,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPSURFLIVE(PIPE_A)); MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY)); MMIO_D(DSPCNTR(dev_priv, PIPE_B)); - MMIO_D(DSPADDR(PIPE_B)); + MMIO_D(DSPADDR(dev_priv, PIPE_B)); MMIO_D(DSPSTRIDE(PIPE_B)); MMIO_D(DSPPOS(PIPE_B)); MMIO_D(DSPSIZE(PIPE_B)); @@ -184,7 +184,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPSURFLIVE(PIPE_B)); MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY)); MMIO_D(DSPCNTR(dev_priv, PIPE_C)); - MMIO_D(DSPADDR(PIPE_C)); + MMIO_D(DSPADDR(dev_priv, PIPE_C)); MMIO_D(DSPSTRIDE(PIPE_C)); MMIO_D(DSPPOS(PIPE_C)); MMIO_D(DSPSIZE(PIPE_C)); From patchwork Thu May 23 12:59:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671800 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AF48FC25B75 for ; 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X-CSE-ConnectionGUID: Z1z+cGHgQR2HxQ/kAwHnhw== X-CSE-MsgGUID: /Ren5cWHRVGmWqm8YdcI9A== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="38164695" X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="38164695" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:05 -0700 X-CSE-ConnectionGUID: 4Ybi/0JuSLK61zU9rgXOLQ== X-CSE-MsgGUID: 4p+5SyVySwq7x3xYFlBM9A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="33731698" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:04 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 04/16] drm/i915: pass dev_priv explicitly to DSPLINOFF Date: Thu, 23 May 2024 15:59:32 +0300 Message-Id: <922b6b0795787b335bd3d5b0541bd30dc2c19dd5.1716469091.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPLINOFF register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++-- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 79280fe2662d..ba76c952a656 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -485,7 +485,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); } else if (DISPLAY_VER(dev_priv) >= 4) { - intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), + intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane), linear_offset); intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); @@ -1041,7 +1041,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, DSPTILEOFF(i9xx_plane)); else offset = intel_de_read(dev_priv, - DSPLINOFF(i9xx_plane)); + DSPLINOFF(dev_priv, i9xx_plane)); base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; } else { offset = 0; diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index a68d7b228187..e222c0333d19 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -47,7 +47,7 @@ #define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) #define _DSPALINOFF 0x70184 /* i965+ */ -#define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) +#define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) #define _DSPASTRIDE 0x70188 #define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) From patchwork Thu May 23 12:59:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671801 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F32E2C25B79 for ; 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X-CSE-ConnectionGUID: WUMGt/KeQeyuAczqpXuRcQ== X-CSE-MsgGUID: iYD0JxsRQ0GYIKovUMUifg== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="38164698" X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="38164698" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:09 -0700 X-CSE-ConnectionGUID: Yta1NiPTQUKKT7BNYv/98Q== X-CSE-MsgGUID: Wv1LraC5SV2FfeORJ0SKmw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="33731731" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:08 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 05/16] drm/i915: pass dev_priv explicitly to DSPSTRIDE Date: Thu, 23 May 2024 15:59:33 +0300 Message-Id: <4067b3009076492d05e80ae994f9a7bd29b56b2e.1716469091.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPSTRIDE register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++-- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 ++-- drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index ba76c952a656..34760ecd5d34 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -423,7 +423,7 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane, struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; - intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), + intel_de_write_fw(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane), plane_state->view.color_plane[0].mapping_stride); if (DISPLAY_VER(dev_priv) < 4) { @@ -1055,7 +1055,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1; fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1; - val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane)); + val = intel_de_read(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane)); fb->pitches[0] = val & 0xffffffc0; aligned_height = intel_fb_align_height(fb, 0, fb->height); diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index e222c0333d19..049114620d93 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -50,7 +50,7 @@ #define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) #define _DSPASTRIDE 0x70188 -#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) +#define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) #define _DSPAPOS 0x7018C /* pre-g4x */ #define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 3b6529a6501b..7072d14d86cf 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1316,7 +1316,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s, if (info->plane == PLANE_A) { info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); - info->stride_reg = DSPSTRIDE(info->pipe); + info->stride_reg = DSPSTRIDE(dev_priv, info->pipe); info->surf_reg = DSPSURF(info->pipe); } else if (info->plane == PLANE_B) { info->ctrl_reg = SPRCTL(info->pipe); @@ -1382,7 +1382,7 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s, info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); - info->stride_reg = DSPSTRIDE(info->pipe); + info->stride_reg = DSPSTRIDE(dev_priv, info->pipe); info->surf_reg = DSPSURF(info->pipe); return 0; diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index 48e3b6d8ed98..cf1cff3d1c4f 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -155,7 +155,7 @@ static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe, { struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; - u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask; + u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(dev_priv, pipe)) & stride_mask; u32 stride = stride_reg; if (GRAPHICS_VER(dev_priv) >= 9) { diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 944765fe22e7..02c5dafc0c93 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -167,7 +167,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(_MMIO(0x7009c)); MMIO_D(DSPCNTR(dev_priv, PIPE_A)); MMIO_D(DSPADDR(dev_priv, PIPE_A)); - MMIO_D(DSPSTRIDE(PIPE_A)); + MMIO_D(DSPSTRIDE(dev_priv, PIPE_A)); MMIO_D(DSPPOS(PIPE_A)); MMIO_D(DSPSIZE(PIPE_A)); MMIO_D(DSPSURF(PIPE_A)); @@ -176,7 +176,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY)); MMIO_D(DSPCNTR(dev_priv, PIPE_B)); MMIO_D(DSPADDR(dev_priv, PIPE_B)); - MMIO_D(DSPSTRIDE(PIPE_B)); + MMIO_D(DSPSTRIDE(dev_priv, PIPE_B)); MMIO_D(DSPPOS(PIPE_B)); MMIO_D(DSPSIZE(PIPE_B)); MMIO_D(DSPSURF(PIPE_B)); @@ -185,7 +185,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY)); MMIO_D(DSPCNTR(dev_priv, PIPE_C)); MMIO_D(DSPADDR(dev_priv, PIPE_C)); - MMIO_D(DSPSTRIDE(PIPE_C)); + MMIO_D(DSPSTRIDE(dev_priv, PIPE_C)); MMIO_D(DSPPOS(PIPE_C)); MMIO_D(DSPSIZE(PIPE_C)); MMIO_D(DSPSURF(PIPE_C)); From patchwork Thu May 23 12:59:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671802 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9190FC25B75 for ; Thu, 23 May 2024 13:00:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B7EDE10E594; Thu, 23 May 2024 13:00:45 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="38164702" X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="38164702" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:13 -0700 X-CSE-ConnectionGUID: CqGHSsd7SBqxwzc++lXCOw== X-CSE-MsgGUID: fHbmDsHpQAugORwESNopUg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="33731775" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:12 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 06/16] drm/i915: pass dev_priv explicitly to DSPPOS Date: Thu, 23 May 2024 15:59:34 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPPOS register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 34760ecd5d34..b23135ed1a38 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -437,7 +437,7 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane, * generator but let's assume we still need to * program whatever is there. */ - intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), + intel_de_write_fw(dev_priv, DSPPOS(dev_priv, i9xx_plane), DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x)); intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1)); diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 049114620d93..13a49550c456 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -53,7 +53,7 @@ #define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) #define _DSPAPOS 0x7018C /* pre-g4x */ -#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) +#define DSPPOS(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) #define DISP_POS_Y_MASK REG_GENMASK(31, 16) #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) #define DISP_POS_X_MASK REG_GENMASK(15, 0) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 02c5dafc0c93..00dd2b647c83 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -168,7 +168,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPCNTR(dev_priv, PIPE_A)); MMIO_D(DSPADDR(dev_priv, PIPE_A)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_A)); - MMIO_D(DSPPOS(PIPE_A)); + MMIO_D(DSPPOS(dev_priv, PIPE_A)); MMIO_D(DSPSIZE(PIPE_A)); MMIO_D(DSPSURF(PIPE_A)); MMIO_D(DSPOFFSET(PIPE_A)); @@ -177,7 +177,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPCNTR(dev_priv, PIPE_B)); MMIO_D(DSPADDR(dev_priv, PIPE_B)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_B)); - MMIO_D(DSPPOS(PIPE_B)); + MMIO_D(DSPPOS(dev_priv, PIPE_B)); MMIO_D(DSPSIZE(PIPE_B)); MMIO_D(DSPSURF(PIPE_B)); MMIO_D(DSPOFFSET(PIPE_B)); @@ -186,7 +186,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPCNTR(dev_priv, PIPE_C)); MMIO_D(DSPADDR(dev_priv, PIPE_C)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_C)); - MMIO_D(DSPPOS(PIPE_C)); + MMIO_D(DSPPOS(dev_priv, PIPE_C)); MMIO_D(DSPSIZE(PIPE_C)); MMIO_D(DSPSURF(PIPE_C)); MMIO_D(DSPOFFSET(PIPE_C)); From patchwork Thu May 23 12:59:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671809 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 942D6C25B75 for ; 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X-CSE-ConnectionGUID: MCKBW3LcQVyQdDrfDMGXKA== X-CSE-MsgGUID: T9ZJ05LxRxm0CezqmX5mgg== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="38164709" X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="38164709" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:17 -0700 X-CSE-ConnectionGUID: yBgO3RAxRLql3tdl0bKttQ== X-CSE-MsgGUID: L6sMuDGFQMOX3e+YfqHo4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="33731797" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:15 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 07/16] drm/i915: pass dev_priv explicitly to DSPSIZE Date: Thu, 23 May 2024 15:59:35 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPSIZE register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index b23135ed1a38..42175cb74d5d 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -439,7 +439,7 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane, */ intel_de_write_fw(dev_priv, DSPPOS(dev_priv, i9xx_plane), DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x)); - intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), + intel_de_write_fw(dev_priv, DSPSIZE(dev_priv, i9xx_plane), DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1)); } } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 13a49550c456..5a1f45eceed4 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -60,7 +60,7 @@ #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) #define _DSPASIZE 0x70190 /* pre-g4x */ -#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) +#define DSPSIZE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) #define DISP_WIDTH_MASK REG_GENMASK(15, 0) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 00dd2b647c83..e047928c3ea0 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -169,7 +169,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPADDR(dev_priv, PIPE_A)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_A)); MMIO_D(DSPPOS(dev_priv, PIPE_A)); - MMIO_D(DSPSIZE(PIPE_A)); + MMIO_D(DSPSIZE(dev_priv, PIPE_A)); MMIO_D(DSPSURF(PIPE_A)); MMIO_D(DSPOFFSET(PIPE_A)); MMIO_D(DSPSURFLIVE(PIPE_A)); @@ -178,7 +178,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPADDR(dev_priv, PIPE_B)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_B)); MMIO_D(DSPPOS(dev_priv, PIPE_B)); - MMIO_D(DSPSIZE(PIPE_B)); + MMIO_D(DSPSIZE(dev_priv, PIPE_B)); MMIO_D(DSPSURF(PIPE_B)); MMIO_D(DSPOFFSET(PIPE_B)); MMIO_D(DSPSURFLIVE(PIPE_B)); @@ -187,7 +187,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPADDR(dev_priv, PIPE_C)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_C)); MMIO_D(DSPPOS(dev_priv, PIPE_C)); - MMIO_D(DSPSIZE(PIPE_C)); + MMIO_D(DSPSIZE(dev_priv, PIPE_C)); MMIO_D(DSPSURF(PIPE_C)); MMIO_D(DSPOFFSET(PIPE_C)); MMIO_D(DSPSURFLIVE(PIPE_C)); From patchwork Thu May 23 12:59:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671806 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30870C25B75 for ; Thu, 23 May 2024 13:00:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 99E9310E5BE; Thu, 23 May 2024 13:00:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="WSLfByEN"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id DFFF310E68B for ; Thu, 23 May 2024 13:00:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716469222; x=1748005222; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=O99t5C9A1LG1n/+akVb8iPrCW0QxpBf5WatNprVYIKw=; b=WSLfByENhbi85+gRY5fmn86E66ch4WFOjdnj1BEwe3aue9lcwnyhTpki yWndgEuGXaTt2D2qkV/DE+Bqmp6dwj61TQrBkebbfub6HaV6SLgJz4jc3 OXzphhXOZlFTwtL0F59pE9M92h9aLTMARQwh5A66IFV6V7IO+h6ifNIKA p/inQmKAKn+//hCJq5W33QkdiiEEQi7aFFG/2zBBHhdPMrPw91U0mUE/Z CorcFPEt1wYa5jolkUpFKK4vC6p7ua/idkPeaX0dn0p6N/Fk2v5QjF9EX 8vlpkahCPnGqNwChbGrEX11omc8dVJZCgS9WFlFe2JHet0en8SsLdf1ZH Q==; X-CSE-ConnectionGUID: Ka+ezO+JSN+2rUZt9LAeYQ== X-CSE-MsgGUID: jRSJBxY/QUmRTYVD4F+g7Q== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="16610011" X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="16610011" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:21 -0700 X-CSE-ConnectionGUID: wvPEXROXQYOQpNgGcF16sA== X-CSE-MsgGUID: O0bZz41jQleksS9yO/QkFw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="33672271" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:18 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 08/16] drm/i915: pass dev_priv explicitly to DSPSURF Date: Thu, 23 May 2024 15:59:36 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPSURF register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 12 ++++++------ drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++-- drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 ++-- drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 8 ++++---- drivers/gpu/drm/i915/intel_clock_gating.c | 6 ++++-- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 8 files changed, 23 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 42175cb74d5d..7adaf8cbd945 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -499,7 +499,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); if (DISPLAY_VER(dev_priv) >= 4) - intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), + intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); else intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), @@ -542,7 +542,7 @@ static void i9xx_plane_disable_arm(struct intel_plane *plane, intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); if (DISPLAY_VER(dev_priv) >= 4) - intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); + intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), 0); else intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), 0); } @@ -563,7 +563,7 @@ g4x_primary_async_flip(struct intel_plane *plane, intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); - intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), + intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); } @@ -1034,7 +1034,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane)); - base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; + base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK; } else if (DISPLAY_VER(dev_priv) >= 4) { if (plane_config->tiling) offset = intel_de_read(dev_priv, @@ -1042,7 +1042,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, else offset = intel_de_read(dev_priv, DSPLINOFF(dev_priv, i9xx_plane)); - base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; + base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK; } else { offset = 0; base = intel_de_read(dev_priv, DSPADDR(dev_priv, i9xx_plane)); @@ -1094,7 +1094,7 @@ bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc, return false; if (DISPLAY_VER(dev_priv) >= 4) - intel_de_write(dev_priv, DSPSURF(i9xx_plane), base); + intel_de_write(dev_priv, DSPSURF(dev_priv, i9xx_plane), base); else intel_de_write(dev_priv, DSPADDR(dev_priv, i9xx_plane), base); diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 5a1f45eceed4..2771f2a7645b 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -67,7 +67,7 @@ #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) #define _DSPASURF 0x7019C /* i965+ */ -#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) +#define DSPSURF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) #define DISP_ADDR_MASK REG_GENMASK(31, 12) #define _DSPATILEOFF 0x701A4 /* i965+ */ diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index f46e01cad053..e9189a864f69 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -364,8 +364,8 @@ static void i965_fbc_nuke(struct intel_fbc *fbc) enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; struct drm_i915_private *dev_priv = fbc->i915; - intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), - intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane))); + intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), + intel_de_read_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane))); } static const struct intel_fbc_funcs i965_fbc_funcs = { diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 7072d14d86cf..9cdb53015d16 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1317,7 +1317,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s, if (info->plane == PLANE_A) { info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); info->stride_reg = DSPSTRIDE(dev_priv, info->pipe); - info->surf_reg = DSPSURF(info->pipe); + info->surf_reg = DSPSURF(dev_priv, info->pipe); } else if (info->plane == PLANE_B) { info->ctrl_reg = SPRCTL(info->pipe); info->stride_reg = SPRSTRIDE(info->pipe); @@ -1383,7 +1383,7 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s, info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); info->stride_reg = DSPSTRIDE(dev_priv, info->pipe); - info->surf_reg = DSPSURF(info->pipe); + info->surf_reg = DSPSURF(dev_priv, info->pipe); return 0; } diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index cf1cff3d1c4f..6c3a0f160bea 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -251,7 +251,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, plane->hw_format = fmt; - plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; + plane->base = vgpu_vreg_t(vgpu, DSPSURF(dev_priv, pipe)) & I915_GTT_PAGE_MASK; if (!vgpu_gmadr_is_valid(vgpu, plane->base)) return -EINVAL; diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 56fb606b4a3d..abcb8f0825e0 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1008,7 +1008,7 @@ static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, } #define DSPSURF_TO_PIPE(offset) \ - calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) + calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(dev_priv, PIPE_C)) static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) @@ -2276,13 +2276,13 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_DH(TRANSCONF(TRANSCODER_B), D_ALL, NULL, pipeconf_mmio_write); MMIO_DH(TRANSCONF(TRANSCODER_C), D_ALL, NULL, pipeconf_mmio_write); MMIO_DH(TRANSCONF(TRANSCODER_EDP), D_ALL, NULL, pipeconf_mmio_write); - MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); + MMIO_DH(DSPSURF(dev_priv, PIPE_A), D_ALL, NULL, pri_surf_mmio_write); MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, reg50080_mmio_write); - MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); + MMIO_DH(DSPSURF(dev_priv, PIPE_B), D_ALL, NULL, pri_surf_mmio_write); MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, reg50080_mmio_write); - MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); + MMIO_DH(DSPSURF(dev_priv, PIPE_C), D_ALL, NULL, pri_surf_mmio_write); MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, reg50080_mmio_write); MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index 59d50195c144..db4fbb6a803d 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -141,8 +141,10 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv) intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(dev_priv, pipe), 0, DISP_TRICKLE_FEED_DISABLE); - intel_uncore_rmw(&dev_priv->uncore, DSPSURF(pipe), 0, 0); - intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe)); + intel_uncore_rmw(&dev_priv->uncore, DSPSURF(dev_priv, pipe), + 0, 0); + intel_uncore_posting_read(&dev_priv->uncore, + DSPSURF(dev_priv, pipe)); } } diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index e047928c3ea0..a8be80bde2e7 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -170,7 +170,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPSTRIDE(dev_priv, PIPE_A)); MMIO_D(DSPPOS(dev_priv, PIPE_A)); MMIO_D(DSPSIZE(dev_priv, PIPE_A)); - MMIO_D(DSPSURF(PIPE_A)); + MMIO_D(DSPSURF(dev_priv, PIPE_A)); MMIO_D(DSPOFFSET(PIPE_A)); MMIO_D(DSPSURFLIVE(PIPE_A)); MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY)); @@ -179,7 +179,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPSTRIDE(dev_priv, PIPE_B)); MMIO_D(DSPPOS(dev_priv, PIPE_B)); MMIO_D(DSPSIZE(dev_priv, PIPE_B)); - MMIO_D(DSPSURF(PIPE_B)); + MMIO_D(DSPSURF(dev_priv, PIPE_B)); MMIO_D(DSPOFFSET(PIPE_B)); MMIO_D(DSPSURFLIVE(PIPE_B)); MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY)); @@ -188,7 +188,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPSTRIDE(dev_priv, PIPE_C)); MMIO_D(DSPPOS(dev_priv, PIPE_C)); MMIO_D(DSPSIZE(dev_priv, PIPE_C)); - MMIO_D(DSPSURF(PIPE_C)); + MMIO_D(DSPSURF(dev_priv, PIPE_C)); MMIO_D(DSPOFFSET(PIPE_C)); MMIO_D(DSPSURFLIVE(PIPE_C)); MMIO_D(REG_50080(PIPE_C, PLANE_PRIMARY)); From patchwork Thu May 23 12:59:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671803 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CC934C25B7C for ; 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X-CSE-ConnectionGUID: t0zAI1mYRiyUh8Lbowkb9A== X-CSE-MsgGUID: J3Qq6El3SmCh8hXgJFmyTg== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="16610014" X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="16610014" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:25 -0700 X-CSE-ConnectionGUID: Q6x0VaRrTU+o3vCbLmjNUg== X-CSE-MsgGUID: yJZsIapXTteJ+JwTnFmPxw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="33672301" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:22 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 09/16] drm/i915: pass dev_priv explicitly to DSPTILEOFF Date: Thu, 23 May 2024 15:59:37 +0300 Message-Id: <4736b2d65ca3be3e9eb5a835ddac801ba99e1e6b.1716469091.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPTILEOFF register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++-- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 7adaf8cbd945..36225c2aa1c8 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -487,7 +487,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, } else if (DISPLAY_VER(dev_priv) >= 4) { intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane), linear_offset); - intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), + intel_de_write_fw(dev_priv, DSPTILEOFF(dev_priv, i9xx_plane), DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); } @@ -1038,7 +1038,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, } else if (DISPLAY_VER(dev_priv) >= 4) { if (plane_config->tiling) offset = intel_de_read(dev_priv, - DSPTILEOFF(i9xx_plane)); + DSPTILEOFF(dev_priv, i9xx_plane)); else offset = intel_de_read(dev_priv, DSPLINOFF(dev_priv, i9xx_plane)); diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 2771f2a7645b..baa3d348c77e 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -71,7 +71,7 @@ #define DISP_ADDR_MASK REG_GENMASK(31, 12) #define _DSPATILEOFF 0x701A4 /* i965+ */ -#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) +#define DSPTILEOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index 6c3a0f160bea..0afde865a7de 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -274,7 +274,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT; plane->height += 1; /* raw height is one minus the real value */ - val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe)); + val = vgpu_vreg_t(vgpu, DSPTILEOFF(dev_priv, pipe)); plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >> _PRI_PLANE_X_OFF_SHIFT; plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >> From patchwork Thu May 23 12:59:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671811 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38AACC25B7F for ; Thu, 23 May 2024 13:00:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1424410E685; 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X-CSE-ConnectionGUID: Q0Zuy4VSSTys4hWUYvK1mw== X-CSE-MsgGUID: 2GTxV006T46oo9x7jOwJTg== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="23451196" X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="23451196" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:29 -0700 X-CSE-ConnectionGUID: jXIOpvr2Rk6n6fEzik34EA== X-CSE-MsgGUID: xkg4tgQfRh+TwTfhZ3YBkw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="34128841" Received: from unknown (HELO localhost) ([10.237.66.160]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:27 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 10/16] drm/i915: pass dev_priv explicitly to DSPOFFSET Date: Thu, 23 May 2024 15:59:38 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPOFFSET register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 5 +++-- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 36225c2aa1c8..2026323d88ac 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -482,7 +482,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, } if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), + intel_de_write_fw(dev_priv, DSPOFFSET(dev_priv, i9xx_plane), DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); } else if (DISPLAY_VER(dev_priv) >= 4) { intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane), @@ -1033,7 +1033,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, fb->format = drm_format_info(fourcc); if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane)); + offset = intel_de_read(dev_priv, + DSPOFFSET(dev_priv, i9xx_plane)); base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK; } else if (DISPLAY_VER(dev_priv) >= 4) { if (plane_config->tiling) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index baa3d348c77e..0930a76ccf3c 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -78,7 +78,7 @@ #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) #define _DSPAOFFSET 0x701A4 /* hsw+ */ -#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) +#define DSPOFFSET(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) #define _DSPASURFLIVE 0x701AC /* g4x+ */ #define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index a8be80bde2e7..50dfe1f81b99 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -171,7 +171,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPPOS(dev_priv, PIPE_A)); MMIO_D(DSPSIZE(dev_priv, PIPE_A)); MMIO_D(DSPSURF(dev_priv, PIPE_A)); - MMIO_D(DSPOFFSET(PIPE_A)); + MMIO_D(DSPOFFSET(dev_priv, PIPE_A)); MMIO_D(DSPSURFLIVE(PIPE_A)); MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY)); MMIO_D(DSPCNTR(dev_priv, PIPE_B)); @@ -180,7 +180,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPPOS(dev_priv, PIPE_B)); MMIO_D(DSPSIZE(dev_priv, PIPE_B)); MMIO_D(DSPSURF(dev_priv, PIPE_B)); - MMIO_D(DSPOFFSET(PIPE_B)); + MMIO_D(DSPOFFSET(dev_priv, PIPE_B)); MMIO_D(DSPSURFLIVE(PIPE_B)); MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY)); MMIO_D(DSPCNTR(dev_priv, PIPE_C)); @@ -189,7 +189,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPPOS(dev_priv, PIPE_C)); MMIO_D(DSPSIZE(dev_priv, PIPE_C)); MMIO_D(DSPSURF(dev_priv, PIPE_C)); - MMIO_D(DSPOFFSET(PIPE_C)); + MMIO_D(DSPOFFSET(dev_priv, PIPE_C)); MMIO_D(DSPSURFLIVE(PIPE_C)); MMIO_D(REG_50080(PIPE_C, PLANE_PRIMARY)); MMIO_D(SPRCTL(PIPE_A)); From patchwork Thu May 23 12:59:39 2024 Content-Type: text/plain; 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d="scan'208";a="33672347" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:30 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 11/16] drm/i915: pass dev_priv explicitly to DSPSURFLIVE Date: Thu, 23 May 2024 15:59:39 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPSURFLIVE register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 4 ++-- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 0930a76ccf3c..22a550c8b41a 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -81,7 +81,7 @@ #define DSPOFFSET(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) #define _DSPASURFLIVE 0x701AC /* g4x+ */ -#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) +#define DSPSURFLIVE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) #define _DSPAGAMC 0x701E0 /* pre-g4x */ #define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index abcb8f0825e0..840fea160aa6 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1018,7 +1018,7 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY); write_vreg(vgpu, offset, p_data, bytes); - vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); + vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset); vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; @@ -1061,7 +1061,7 @@ static int reg50080_mmio_write(struct intel_vgpu *vgpu, write_vreg(vgpu, offset, p_data, bytes); if (plane == PLANE_PRIMARY) { - vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); + vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset); vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; } else { vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 50dfe1f81b99..b4d5592b18df 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -172,7 +172,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPSIZE(dev_priv, PIPE_A)); MMIO_D(DSPSURF(dev_priv, PIPE_A)); MMIO_D(DSPOFFSET(dev_priv, PIPE_A)); - MMIO_D(DSPSURFLIVE(PIPE_A)); + MMIO_D(DSPSURFLIVE(dev_priv, PIPE_A)); MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY)); MMIO_D(DSPCNTR(dev_priv, PIPE_B)); MMIO_D(DSPADDR(dev_priv, PIPE_B)); @@ -181,7 +181,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPSIZE(dev_priv, PIPE_B)); MMIO_D(DSPSURF(dev_priv, PIPE_B)); MMIO_D(DSPOFFSET(dev_priv, PIPE_B)); - MMIO_D(DSPSURFLIVE(PIPE_B)); + MMIO_D(DSPSURFLIVE(dev_priv, PIPE_B)); MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY)); MMIO_D(DSPCNTR(dev_priv, PIPE_C)); MMIO_D(DSPADDR(dev_priv, PIPE_C)); @@ -190,7 +190,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPSIZE(dev_priv, PIPE_C)); MMIO_D(DSPSURF(dev_priv, PIPE_C)); MMIO_D(DSPOFFSET(dev_priv, PIPE_C)); - MMIO_D(DSPSURFLIVE(PIPE_C)); + MMIO_D(DSPSURFLIVE(dev_priv, PIPE_C)); MMIO_D(REG_50080(PIPE_C, PLANE_PRIMARY)); MMIO_D(SPRCTL(PIPE_A)); MMIO_D(SPRLINOFF(PIPE_A)); From patchwork Thu May 23 12:59:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671808 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AF7BBC25B7C for ; Thu, 23 May 2024 13:00:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2DA0510E5DC; Thu, 23 May 2024 13:00:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="eI/UJNWW"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2060110E539 for ; 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23 May 2024 06:00:37 -0700 X-CSE-ConnectionGUID: h+A0iyk1SaeivB8sjzfxqQ== X-CSE-MsgGUID: jvnQix6FSwaIZHhsH66Bmw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="33672370" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:34 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 12/16] drm/i915: pass dev_priv explicitly to DSPGAMC Date: Thu, 23 May 2024 15:59:40 +0300 Message-Id: <542455204f62182a46fa2cb16ad6b0648c72f612.1716469091.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPGAMC register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 22a550c8b41a..f67c5a2bb6b9 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -84,7 +84,7 @@ #define DSPSURFLIVE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) #define _DSPAGAMC 0x701E0 /* pre-g4x */ -#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ +#define DSPGAMC(dev_priv, plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ /* CHV pipe B primary plane */ #define _PRIMPOS_A 0x60a08 From patchwork Thu May 23 12:59:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671805 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB881C25B7D for ; Thu, 23 May 2024 13:00:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EBCB710E5A0; Thu, 23 May 2024 13:00:46 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="evvepqzc"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id C8C3510E539 for ; Thu, 23 May 2024 13:00:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716469241; x=1748005241; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IDws+VOfARKOF1bagQ9sxP0Mwnn6UDtk37iWymy2NxA=; b=evvepqzcQM/ucCEogIdXoghrDcGXScsO9XZ7ipchCvu7iTPPl8wnE+kk HFFN1IYGwH8lE7MXI1de3GerqmEmEOoJevrveNm+qNNnoLbuvPlZ4oSzL PPTligWXOSKxvCOP1nuVa/22KOh+c3g/CjAIk6fVWU3VsizAU98wYhwha ujZnDzYSoEk3wnUwNJaytPaM5rs+W4G275k+rtzkH2koN1IuOnaMWUdMI K3cwxDiDd7BV2r6mJXNPBxgUUImo7f+iHqIx8GjLUaOh+Q81bnbkh7Vs+ D+yMKtxNFT/7kYeu4BkwVhKBDdmdX7BXH9pA+hJFxBuqQWqkQpLjBuklP w==; X-CSE-ConnectionGUID: gVEddlQYTMiJZ5hm0IX6DA== X-CSE-MsgGUID: rOhDeVRDQhuxQbY3Hw7Agw== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="16610037" X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="16610037" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:40 -0700 X-CSE-ConnectionGUID: 5DAKPalcRWeeNMuG/vNyOg== X-CSE-MsgGUID: 3V8k0rqKQKStusOrwbcd8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="33672398" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:38 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 13/16] drm/i915: pass dev_priv explicitly to PRIMPOS Date: Thu, 23 May 2024 15:59:41 +0300 Message-Id: <4bbb3218ac25b292bea46dcba3df8ec474d578e2.1716469091.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PRIMPOS register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 2026323d88ac..1cefcdd4f26a 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -474,7 +474,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, int crtc_w = drm_rect_width(&plane_state->uapi.dst); int crtc_h = drm_rect_height(&plane_state->uapi.dst); - intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), + intel_de_write_fw(dev_priv, PRIMPOS(dev_priv, i9xx_plane), PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x)); intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1)); diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index f67c5a2bb6b9..7f291b34f10a 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -87,8 +87,8 @@ #define DSPGAMC(dev_priv, plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ /* CHV pipe B primary plane */ -#define _PRIMPOS_A 0x60a08 -#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) +#define _PRIMPOS_A 0x60a08 +#define PRIMPOS(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) #define PRIM_POS_X_MASK REG_GENMASK(15, 0) From patchwork Thu May 23 12:59:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D418C25B79 for ; Thu, 23 May 2024 13:00:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2310A10E5D6; Thu, 23 May 2024 13:00:50 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="CO731yoC"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 81A2A10E539 for ; Thu, 23 May 2024 13:00:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716469245; x=1748005245; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9rhCKD56IVyikgw7pt6l/v5Uf4yYscenCJR7e/kQeow=; b=CO731yoCgvgN8u6RoUnU60FKAfvzrR5SF8GoNx+hD1No4EHVmPF6CgLx q4Hjk2UK7r6aNIW7HU7VFcSeXQ6OMJqOWSmHF9lvxHQtwh2QTpY/qvFrA z4tHSsev5sFbBtMENxZtlqBsx87lug1n1phsQGIq+YsNY3M1B4p0rL/zA mx9jePtBN4KgQuUFaOPECT6NoIae0rPJo7mD3r4SEwW9b3zgi5yipxAx7 sloav0YeBswoGU+TfX1ol00LEoXDBUcnGdj9L5LyGciP22emYYEZeUtVY /ZowTJFD7zF0ffkObdFQ5FXoAUus1xA1lCC+YNgURq125hGIa4TCnAeXi A==; X-CSE-ConnectionGUID: 1yrEdiVHQGONXiQtTGuK5g== X-CSE-MsgGUID: YRlt9TCxTGi5BhTEAi847w== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="16610046" X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="16610046" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:44 -0700 X-CSE-ConnectionGUID: w2i8y0MFRP+e3OUuPAtrZg== X-CSE-MsgGUID: OYKSr/GIRL6ZvrdXk+jiRA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="33672419" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:42 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 14/16] drm/i915: pass dev_priv explicitly to PRIMSIZE Date: Thu, 23 May 2024 15:59:42 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PRIMSIZE register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 1cefcdd4f26a..82cb393a0a22 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -476,7 +476,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, intel_de_write_fw(dev_priv, PRIMPOS(dev_priv, i9xx_plane), PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x)); - intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), + intel_de_write_fw(dev_priv, PRIMSIZE(dev_priv, i9xx_plane), PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1)); intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 7f291b34f10a..8d45c879e74a 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -94,8 +94,8 @@ #define PRIM_POS_X_MASK REG_GENMASK(15, 0) #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) -#define _PRIMSIZE_A 0x60a0c -#define PRIMSIZE(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A) +#define _PRIMSIZE_A 0x60a0c +#define PRIMSIZE(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A) #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) From patchwork Thu May 23 12:59:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671812 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 099BEC25B7C for ; Thu, 23 May 2024 13:00:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E939A10E64B; Thu, 23 May 2024 13:00:56 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="X6Io4Me9"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2157D10E5A9 for ; Thu, 23 May 2024 13:00:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716469248; x=1748005248; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=P3khCOKzFVaNKXEZxyL120c2xPRrfbUchSwkyGEk0qo=; b=X6Io4Me9cDiaKdlnuRn3mD2HVj4ZOXABsg8EHGQMIStXRhR1d5cEfSME zy4PY7Q6zWX46MQL7UlGMyGAOjtBJgwLVglSOOJuzjvUVZxeKvOoutWOG skyuF+g8ZpH7t0SkXmigw0t+CGSS6AzsJccBnaDFAlt2srHoB0eRJ2W57 1XnYowkHMzhO5fkeJKrgu/MlJqXjYBwc4oLVFnsItTRSTN7FWeaaO4JEj xqXX/g/SESPSk+xxGrzOUIVIHWLgc9Fnem1Sv8dwZ+NeBXzdEJjtkk6t8 8p/zUBbFksEBAaElFcwi/IqSewZEXCI0Hk8pgjByocFhclY0OFb0+z8Us A==; X-CSE-ConnectionGUID: 3IVvIt8BQvur4BB1JYJKgA== X-CSE-MsgGUID: wn0Am0HnSm+arHcbKZyi0A== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="16610052" X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="16610052" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:48 -0700 X-CSE-ConnectionGUID: jPA6H8oBSPS5/WgTNwlhFQ== X-CSE-MsgGUID: 8tRa/rJmTlyzRlkNf6DGZg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="33672442" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:45 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 15/16] drm/i915: pass dev_priv explicitly to PRIMCNSTALPHA Date: Thu, 23 May 2024 15:59:43 +0300 Message-Id: <783477b86f4d53849775cbf690bb8b9042792a66.1716469091.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PRIMCNSTALPHA register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 3 ++- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 82cb393a0a22..5c8778865156 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -478,7 +478,8 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x)); intel_de_write_fw(dev_priv, PRIMSIZE(dev_priv, i9xx_plane), PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1)); - intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); + intel_de_write_fw(dev_priv, + PRIMCNSTALPHA(dev_priv, i9xx_plane), 0); } if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 8d45c879e74a..a2ba55fa2b30 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -101,8 +101,8 @@ #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w)) -#define _PRIMCNSTALPHA_A 0x60a10 -#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A) +#define _PRIMCNSTALPHA_A 0x60a10 +#define PRIMCNSTALPHA(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A) #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31) #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) From patchwork Thu May 23 12:59:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13671810 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6ACDFC25B79 for ; Thu, 23 May 2024 13:00:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9FA4410E649; Thu, 23 May 2024 13:00:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="ChAUWcJ+"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id B782D10E643 for ; Thu, 23 May 2024 13:00:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716469252; x=1748005252; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AtaRa5oL4CyU1VHlswWJ9FkQro1Bw24n1zxADvUUdJ0=; b=ChAUWcJ+SN6SffOPQanct6lRbjT1HM2XJSxsnMx1OArPTzCHetRL0ErA CTgIxNrIMYbooAu2D1C2jYUwkprtJnzUD793oxbZnn1gJokFnu2lkEudu 0JzQOR6MxbkInVOgLoCYRLMo6jC6xNlrlbArT10Vy3sBEKFdUesbB+v8X 357WeToohVZiSHrb8dbQxEYubU5fz6ZnojYUPM/0XBvRWeNqWuWwhbskD +9b9fu3kn0Mdl4fe56/wvnENwA9YoiEmIpdAH7v3rwpjwoc0Hdb9gztlD dtL4puPk6eL+feo44XeTPclWdGqOlHXiwAUdF8YMC1J3X6I3WA1S9zK85 Q==; X-CSE-ConnectionGUID: 5E6JydwnSCabkwRkVZokWg== X-CSE-MsgGUID: Agj1bgG6Qz+00I+1u7tYsg== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="12966419" X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="12966419" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:52 -0700 X-CSE-ConnectionGUID: 5BogjUnPQkmn3MUYrOXDcg== X-CSE-MsgGUID: MmWlsyupQMSHT0/Qiaj7xA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,182,1712646000"; d="scan'208";a="64874885" Received: from unknown (HELO localhost) ([10.237.66.160]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2024 06:00:50 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com Subject: [PATCH 16/16] drm/i915: pass dev_priv explicitly to PIPEGCMAX Date: Thu, 23 May 2024 15:59:44 +0300 Message-Id: <5fdc8562fe7b8d26e1ec1bb8f9a221348246bbe1.1716469091.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPEGCMAX register macro. Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 13 +++++++------ drivers/gpu/drm/i915/display/intel_color_regs.h | 6 +++--- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index a83f41ee6834..da56d24eb933 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1284,9 +1284,10 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc, i965_lut_10p6_udw(&lut[i])); } - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red); - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green); - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue); + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 0), lut[i].red); + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 1), + lut[i].green); + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 2), lut[i].blue); } static void i965_load_luts(const struct intel_crtc_state *crtc_state) @@ -3239,9 +3240,9 @@ static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc) i965_lut_10p6_pack(&lut[i], ldw, udw); } - lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 0))); - lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 1))); - lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 2))); + lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 0))); + lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 1))); + lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 2))); return blob; } diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h index 61c18b4a7fa5..8eb643cfead7 100644 --- a/drivers/gpu/drm/i915/display/intel_color_regs.h +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h @@ -37,9 +37,9 @@ (i) * 4) /* i965/g4x/vlv/chv */ -#define _PIPEAGCMAX 0x70010 -#define _PIPEBGCMAX 0x71010 -#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ +#define _PIPEAGCMAX 0x70010 +#define _PIPEBGCMAX 0x71010 +#define PIPEGCMAX(dev_priv, pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ /* ilk+ palette */ #define _LGC_PALETTE_A 0x4a000