From patchwork Fri May 24 10:24:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13673037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AF2B6C25B79 for ; Fri, 24 May 2024 10:30:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BFAC310E8A0; Fri, 24 May 2024 10:30:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="G1lYnqUO"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 001CD10E882 for ; Fri, 24 May 2024 10:30:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716546617; x=1748082617; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ssZ2vZkjKzfq4nqw4eAiACZ8SZwjtRY5ng2i4iZh1Wc=; b=G1lYnqUOpzhC6vX+sUdNcRRoLW7MUcu5DUAq5HVxy9Y+W9MgUXUZkWQ2 Ibb1PT8Ju3M2RUtY/NQs3ryph1YfKDd+8t7ckooCduoYML5OAOqYf++fB EUDTXJr/J/Sc6+4Tg/E+cHH5JatbP1uJSwhvrzrhbUoE/N0ZYY1/cYriT kZQjKRG6p5veIc2iDb7AYC1i+Ns/pQnKppXQCS0i4MNUzXbye85put7ej tUZyajTy6Pk6N2cC0447VOUCdZqiTl6E0p9Q5MBvOc23BgQre2z8uiKS2 yJ+bHCNbrITN6AeH8rgZEpeRazLKbTViAvzPMvIXDF6d1D8Ms0bDOXEf+ A==; X-CSE-ConnectionGUID: ZQLwqNOcTEyTEbHKYylLkw== X-CSE-MsgGUID: cSNi2toJQ5aKU64XPQi1BQ== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="15862709" X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="15862709" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2024 03:30:17 -0700 X-CSE-ConnectionGUID: 1SGWHZt/SqiYaxoVWND+qw== X-CSE-MsgGUID: Qg1ufYUNQWOkth+OPhwUzA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="71385645" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa001.jf.intel.com with ESMTP; 24 May 2024 03:30:13 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com Subject: [PATCH v9 1/8] drm/i915: Define and compute Transcoder CMRR registers Date: Fri, 24 May 2024 15:54:25 +0530 Message-Id: <20240524102432.2499104-2-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add register definitions for Transcoder Fixed Average Vtotal mode/CMRR function, with the necessary bitfields. Compute these registers when CMRR is enabled, extending Adaptive refresh rate capabilities. --v2: - Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani] - Fix indent and order based on register offset. [Jani] --v3: - Removing RFC tag. --v4: - Update place holder for CMRR register definition. (Jani) --v5: - Add CMRR register definitions to a separate file intel_vrr_reg.h. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_display.c | 23 ++++++++++++++++++- .../drm/i915/display/intel_display_types.h | 6 +++++ drivers/gpu/drm/i915/display/intel_vrr.c | 23 +++++++++++++++++++ drivers/gpu/drm/i915/intel_vrr_reg.h | 21 +++++++++++++++++ 4 files changed, 72 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/intel_vrr_reg.h diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 1e8e2fd52cf6..803360fcb0cc 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1004,6 +1004,13 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state, old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full; } +static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m || + old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n; +} + static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -5054,6 +5061,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, } \ } while (0) +#define PIPE_CONF_CHECK_LLI(name) do { \ + if (current_config->name != pipe_config->name) { \ + pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ + "(expected %lli, found %lli)", \ + current_config->name, \ + pipe_config->name); \ + ret = false; \ + } \ +} while (0) + #define PIPE_CONF_CHECK_BOOL(name) do { \ if (current_config->name != pipe_config->name) { \ BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \ @@ -5418,10 +5435,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.guardband); PIPE_CONF_CHECK_I(vrr.vsync_start); PIPE_CONF_CHECK_I(vrr.vsync_end); + PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); + PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); } #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I +#undef PIPE_CONF_CHECK_LLI #undef PIPE_CONF_CHECK_BOOL #undef PIPE_CONF_CHECK_P #undef PIPE_CONF_CHECK_FLAGS @@ -6810,7 +6830,8 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, intel_crtc_needs_fastset(new_crtc_state)) icl_set_pipe_chicken(new_crtc_state); - if (vrr_params_changed(old_crtc_state, new_crtc_state)) + if (vrr_params_changed(old_crtc_state, new_crtc_state) || + cmrr_params_changed(old_crtc_state, new_crtc_state)) intel_vrr_set_transcoder_timings(new_crtc_state); } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 9678c2b157f6..ee0323422c7d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1401,6 +1401,12 @@ struct intel_crtc_state { u32 vsync_end, vsync_start; } vrr; + /* Content Match Refresh Rate state */ + struct { + bool enable; + u64 cmrr_n, cmrr_m; + } cmrr; + /* Stream Splitter for eDP MSO */ struct { bool enable; diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 5f3657aa8313..b96a8b2e7083 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -9,6 +9,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_vrr.h" +#include "intel_vrr_reg.h" #include "intel_dp.h" bool intel_vrr_is_capable(struct intel_connector *connector) @@ -218,6 +219,19 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) return; } + if (crtc_state->cmrr.enable) { + intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), + VRR_CTL_CMRR_ENABLE | trans_vrr_ctl(crtc_state)); + intel_de_write(dev_priv, TRANS_CMRR_M_HI(dev_priv, cpu_transcoder), + upper_32_bits(crtc_state->cmrr.cmrr_m)); + intel_de_write(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder), + lower_32_bits(crtc_state->cmrr.cmrr_m)); + intel_de_write(dev_priv, TRANS_CMRR_N_HI(dev_priv, cpu_transcoder), + upper_32_bits(crtc_state->cmrr.cmrr_n)); + intel_de_write(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder), + lower_32_bits(crtc_state->cmrr.cmrr_n)); + } + intel_de_write(dev_priv, TRANS_VRR_VMIN(dev_priv, cpu_transcoder), crtc_state->vrr.vmin - 1); intel_de_write(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder), @@ -306,6 +320,15 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + if (crtc_state->cmrr.enable) { + crtc_state->cmrr.cmrr_n = + intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder), + TRANS_CMRR_N_HI(dev_priv, cpu_transcoder)); + crtc_state->cmrr.cmrr_m = + intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder), + TRANS_CMRR_M_HI(dev_priv, cpu_transcoder)); + } + if (DISPLAY_VER(dev_priv) >= 13) crtc_state->vrr.guardband = REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl); diff --git a/drivers/gpu/drm/i915/intel_vrr_reg.h b/drivers/gpu/drm/i915/intel_vrr_reg.h new file mode 100644 index 000000000000..e1273b4e1b9b --- /dev/null +++ b/drivers/gpu/drm/i915/intel_vrr_reg.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_VRR_REG_H__ +#define __INTEL_VRR_REG_H__ + +#define VRR_CTL_CMRR_ENABLE REG_BIT(27) + +#define _TRANS_CMRR_M_LO_A 0x604F0 +#define _TRANS_CMRR_M_HI_A 0x604F4 +#define _TRANS_CMRR_N_LO_A 0x604F8 +#define _TRANS_CMRR_N_HI_A 0x604FC +#define TRANS_CMRR_M_LO(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_LO_A) +#define TRANS_CMRR_M_HI(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_HI_A) +#define TRANS_CMRR_N_LO(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_LO_A) +#define TRANS_CMRR_N_HI(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A) + +#endif /* __INTEL_VRR_REGS__ */ + From patchwork Fri May 24 10:24:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13673038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22A6AC25B74 for ; Fri, 24 May 2024 10:30:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C27BB10E8F2; Fri, 24 May 2024 10:30:32 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="kvF/5YSr"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id B817C10E8A0 for ; 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24 May 2024 03:30:17 -0700 X-CSE-ConnectionGUID: 5DV0JTDNQwGrenFN+nNmpA== X-CSE-MsgGUID: SyPENktNQi2e8+9WGsb+8g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="71385656" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa001.jf.intel.com with ESMTP; 24 May 2024 03:30:15 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com Subject: [PATCH v9 2/8] drm/i915: Update trans_vrr_ctl flag when cmrr is computed Date: Fri, 24 May 2024 15:54:26 +0530 Message-Id: <20240524102432.2499104-3-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable is set, With this commit setting the stage for subsequent CMRR enablement. --v2: - Check pipe active state in cmrr enabling. [Jani] - Remove usage of bitwise OR on booleans. [Jani] - Revert unrelated changes. [Jani] - Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani] - Simplify whole if-ladder in intel_vrr_enable. [Jani] - Revert patch restructuring mistakes in intel_vrr_get_config. [Jani] --v3: - Check pipe active state in cmrr disabling.[Jani] - Correct messed up condition in intel_vrr_enable. [Jani] --v4: - Removing RFC tag. --v5: - CMRR handling in co-existatnce of LRR and DRRS. --v7: - Rebase on top of AS SDP merge. --v8: - Remove cmrr_enabling/disabling and update commit message. (Ankit) Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_vrr.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index b96a8b2e7083..3b250e92af98 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -277,15 +277,20 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), TRANS_PUSH_EN); - if (HAS_AS_SDP(dev_priv)) intel_de_write(dev_priv, TRANS_VRR_VSYNC(dev_priv, cpu_transcoder), VRR_VSYNC_END(crtc_state->vrr.vsync_end) | VRR_VSYNC_START(crtc_state->vrr.vsync_start)); - intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + if (crtc_state->cmrr.enable) { + intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), + VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | + trans_vrr_ctl(crtc_state)); + } else { + intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + } } void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) From patchwork Fri May 24 10:24:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13673036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7AB15C25B74 for ; Fri, 24 May 2024 10:30:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4FF3C10E882; Fri, 24 May 2024 10:30:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="CO9297SO"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7FD6510E8F2 for ; Fri, 24 May 2024 10:30:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716546626; x=1748082626; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TXB0mRuVTBGEKbrfsPIkXBNtNMdqTjq2l3azdj/Wxag=; b=CO9297SOEGZlJGGd4Q1EFtIaWHVNLXIGVU1YOX1NeLyfxFjxJ3/Hg+11 fyTN6bWID2bA3XkqdZgH8W9Z5DSDvUc8xsUg23ASV53zbifMlxdvNlDNf apf04p1mHYP5Sg81UUlly0zB4Ns6b0LmZ6cXPSNLjPhSvHcesJEMc3R3i yC7Mwccke0z0RnCKvAXqN68ZYCTksgHd89jymu1vCH6ENJVHy/4x5+bg9 /WvpLx1zpEOIYV3zjEOwogLCidTwgQmD5Ty2m3j2BxpI+7oy4XDHKWc3T kTEi7Z34FscMxgp2Z3XX2cZWiinExUFCtahcburd0nhapOxjhiPX/BdX/ Q==; X-CSE-ConnectionGUID: JxcOO7IzSbO3IJFvQsnYmA== X-CSE-MsgGUID: 2bHjXiR+QC2LuFIOMsZcGw== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="15862720" X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="15862720" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2024 03:30:18 -0700 X-CSE-ConnectionGUID: WjWrUTCHREeNEcg0CQ/uUA== X-CSE-MsgGUID: XF0UmneeQx6QRU0wktVhZA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="71385665" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa001.jf.intel.com with ESMTP; 24 May 2024 03:30:17 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com Subject: [PATCH v9 3/8] drm/i915: Compute CMRR and calculate vtotal Date: Fri, 24 May 2024 15:54:27 +0530 Message-Id: <20240524102432.2499104-4-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Compute Fixed Average Vtotal/CMRR with resepect to userspace VRR enablement. Also calculate required parameters in case of CMRR is enabled. During intel_vrr_compute_config, CMRR is getting enabled based on userspace has enabled Variable refresh mode with VRR timing generator or not. Make CMRR as small subset of FAVT mode, when Panel is running on Fixed refresh rate and on VRR framework then only enable CMRR to match with actual refresh rate. --v2: - Update is_cmrr_frac_required function return as bool, not int. [Jani] - Use signed int math instead of unsigned in cmrr_get_vtotal2. [Jani] - Fix typo and usage of camel case in cmrr_get_vtotal. [Jani] - Use do_div in cmrr_get_vtotalwhile calculating cmrr_m. [ Jani] - Simplify cmrr and vrr compute config in intel_vrr_compute_config. [Jani] - Correct valiable name usage in is_cmrr_frac_required. [Ville] --v3: - Removing RFC tag. --v4: - Added edp check to address edp usecase for now. (ville) - Updated is_cmrr_fraction_required to more simplified calculation. - on longterm goal to be worked upon uapi as suggestion from ville. --v5: - Correct vtotal paramas accuracy and add 2 digit precision. - Avoid using DIV_ROUND_UP and improve scanline precision. --v6: - Make CMRR a small subset of FAVT mode. --v7: - Update commit message to avoid confusion with Legacy VRR (Ankit). - Add cmrr.enable in last, so remove from this patch. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_display.c | 1 + .../drm/i915/display/intel_display_device.h | 1 + drivers/gpu/drm/i915/display/intel_vrr.c | 99 ++++++++++++++++--- 3 files changed, 89 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 803360fcb0cc..f7e82d1e2bf9 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5437,6 +5437,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.vsync_end); PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); + PIPE_CONF_CHECK_BOOL(cmrr.enable); } #undef PIPE_CONF_CHECK_X diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 17ddf82f0b6e..b372b1acc19b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -71,6 +71,7 @@ struct drm_printer; BIT(trans)) != 0) #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) #define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13) +#define HAS_CMRR(i915) (DISPLAY_VER(i915) >= 20) #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask)) #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug) #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 3b250e92af98..3fbedd7366bb 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -12,6 +12,9 @@ #include "intel_vrr_reg.h" #include "intel_dp.h" +#define FIXED_POINT_PRECISION 100 +#define CMRR_PRECISION_TOLERANCE 10 + bool intel_vrr_is_capable(struct intel_connector *connector) { const struct drm_display_info *info = &connector->base.display_info; @@ -107,6 +110,59 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state) return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state); } +static bool +is_cmrr_frac_required(struct intel_crtc_state *crtc_state, bool is_edp) +{ + int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line; + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + + if (!(HAS_CMRR(i915) && is_edp)) + return false; + + actual_refresh_k = + drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION; + pixel_clock_per_line = + adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal; + calculated_refresh_k = + pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal; + + if ((actual_refresh_k - calculated_refresh_k) < CMRR_PRECISION_TOLERANCE) + return false; + + return true; +} + +static unsigned int +cmrr_get_vtotal(struct intel_crtc_state *crtc_state) +{ + int multiplier_m = 1, multiplier_n = 1, vtotal; + int actual_refresh_rate, desired_refresh_rate; + long long actual_pixel_rate, adjusted_pixel_rate, pixel_clock_per_line; + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + + pixel_clock_per_line = + adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal; + actual_refresh_rate = + pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal; + desired_refresh_rate = drm_mode_vrefresh(adjusted_mode); + actual_pixel_rate = actual_refresh_rate * adjusted_mode->crtc_vtotal; + actual_pixel_rate = + (actual_pixel_rate * adjusted_mode->crtc_htotal) / FIXED_POINT_PRECISION; + + multiplier_m = 1001; + multiplier_n = 1000; + + crtc_state->cmrr.cmrr_n = + ((desired_refresh_rate * adjusted_mode->crtc_htotal * multiplier_n) / multiplier_m); + crtc_state->cmrr.cmrr_n *= multiplier_n; + vtotal = (actual_pixel_rate * multiplier_n) / crtc_state->cmrr.cmrr_n; + adjusted_pixel_rate = actual_pixel_rate * multiplier_m; + crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n); + + return vtotal; +} + void intel_vrr_compute_config(struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -116,6 +172,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, struct intel_connector *connector = to_intel_connector(conn_state->connector); struct intel_dp *intel_dp = intel_attached_dp(connector); + bool is_edp = intel_dp_is_edp(intel_dp); struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; const struct drm_display_info *info = &connector->base.display_info; int vmin, vmax; @@ -160,18 +217,10 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; /* - * For XE_LPD+, we use guardband and pipeline override - * is deprecated. + * When panel is VRR capable and userspace has + * not enabled adaptive sync mode then Fixed Average + * Vtotal mode should be enabled. */ - if (DISPLAY_VER(i915) >= 13) { - crtc_state->vrr.guardband = - crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start; - } else { - crtc_state->vrr.pipeline_full = - min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start - - crtc_state->framestart_delay - 1); - } - if (crtc_state->uapi.vrr_enabled) { crtc_state->vrr.enable = true; crtc_state->mode_flags |= I915_MODE_FLAG_VRR; @@ -183,6 +232,25 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, (crtc_state->hw.adjusted_mode.crtc_vtotal - crtc_state->hw.adjusted_mode.vsync_end); } + } else if (is_cmrr_frac_required(crtc_state, is_edp)) { + crtc_state->vrr.enable = true; + crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state); + crtc_state->vrr.vmin = crtc_state->vrr.vmax; + crtc_state->vrr.flipline = crtc_state->vrr.vmin; + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; + } + + /* + * For XE_LPD+, we use guardband and pipeline override + * is deprecated. + */ + if (DISPLAY_VER(i915) >= 13) { + crtc_state->vrr.guardband = + crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start; + } else { + crtc_state->vrr.pipeline_full = + min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start - + crtc_state->framestart_delay - 1); } } @@ -323,7 +391,14 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder)); - crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + if (HAS_CMRR(dev_priv)) { + crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE) && + (trans_vrr_ctl & VRR_CTL_VRR_ENABLE); + crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE && + !(trans_vrr_ctl & VRR_CTL_CMRR_ENABLE); + } else { + crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + } if (crtc_state->cmrr.enable) { crtc_state->cmrr.cmrr_n = From patchwork Fri May 24 10:24:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13673035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9C9DCC25B74 for ; Fri, 24 May 2024 10:30:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EAA1A10E471; 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X-CSE-ConnectionGUID: 6AOijD4WQMupXhYX0fDRUw== X-CSE-MsgGUID: lK9yl0rhQymz9lZyXRe2Tw== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="15862727" X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="15862727" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2024 03:30:19 -0700 X-CSE-ConnectionGUID: MrgQSzubTkOO0LQKFWZtbQ== X-CSE-MsgGUID: uRXBitbrRaOeMflO7xS7zg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="71385678" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa001.jf.intel.com with ESMTP; 24 May 2024 03:30:18 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com Subject: [PATCH v9 4/8] Add refresh rate divider to struct representing AS SDP Date: Fri, 24 May 2024 15:54:28 +0530 Message-Id: <20240524102432.2499104-5-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add target_rr_divider to structure representing AS SDP. It is valid only in FAVT mode, sink device ignores the bit in AVT mode. Signed-off-by: Mitul Golani Reviewed-by: Arun R Murthy --- include/drm/display/drm_dp_helper.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h index 8bed890eec2c..393dbf8cf6ab 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -122,6 +122,7 @@ struct drm_dp_as_sdp { int target_rr; int duration_incr_ms; int duration_decr_ms; + bool target_rr_divider; enum operation_mode mode; }; From patchwork Fri May 24 10:24:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13673040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6EE1BC25B74 for ; Fri, 24 May 2024 10:30:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C818D10E906; Fri, 24 May 2024 10:30:33 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="OBTM7jAV"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7572F10E906 for ; Fri, 24 May 2024 10:30:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716546626; x=1748082626; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sUo1sxcg0LXJNmYXKF4IJJSqO9DNrhg6ikktmWnYeqw=; b=OBTM7jAVs3eYG7AF1bAddqoOwZxtCss0V1/CQfsvxQJVvbq1C0DOX0SW ZQpiVKsVbO8w/tBHk6nU+fKf6qwtWaDxhXjZaK3619m6mPgGqZqV6sJCO WjCZQ17zaY95Ue9TV1ynfcBZsiqPAzYgLYu+EgvtSFDcQ+/A7z3yWwKlg +J2HVkkgX0+y8pHomUhD2c5u+fukrAjoB0s5JCMD/dl4tmQ+Oex1HDg/J 4u3EdEbDm//ydTV5rXo/jLuIm8kJEiPMw4YaN9GaQObHsa6HhfmV5mblb NjqdiM3eE+4XNb4EPksqO4g4WXcCpPJ//V8/H+ijxCQj68rdxLA6ktVnL A==; X-CSE-ConnectionGUID: DQsNs5HCQzCQQvcnUzGilQ== X-CSE-MsgGUID: Z7cKmK0lRQKCssFslh0Ztw== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="15862731" X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="15862731" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2024 03:30:20 -0700 X-CSE-ConnectionGUID: CSEK5kZ3SHOeGN51E3H6Yw== X-CSE-MsgGUID: C4NpnR2sS5q2pUpWV2I/HA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="71385688" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa001.jf.intel.com with ESMTP; 24 May 2024 03:30:19 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com Subject: [PATCH v9 5/8] drm/i915/display: Add support for pack and unpack Date: Fri, 24 May 2024 15:54:29 +0530 Message-Id: <20240524102432.2499104-6-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add support of pack and unpack for target_rr_divider. --v2: - Set Target Refresh Rate Divider bit when related AS SDP bit is set (Ankit). Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c0a3b6d50681..15aab14c4206 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4230,6 +4230,9 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, sdp->db[3] = as_sdp->target_rr & 0xFF; sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3; + if (as_sdp->target_rr_divider) + sdp->db[4] |= 0x20; + return length; } @@ -4410,6 +4413,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE; as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1]; as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3); + as_sdp->target_rr_divider = sdp->db[4] & 0x20; return 0; } From patchwork Fri May 24 10:24:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13673042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47B44C25B7C for ; Fri, 24 May 2024 10:30:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7E95510E967; Fri, 24 May 2024 10:30:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="CmAAOO3y"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 98E1010E961 for ; Fri, 24 May 2024 10:30:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716546627; x=1748082627; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=t3Q/K/OlJOU7XNwZLaYsmcrCncSdYnGifq9zN6ZcGkg=; b=CmAAOO3yLzJWj8Ae0S5bisfh05XhIUVKl3SdNmoo3nzyDYvJRWTxNThB OkreA1+MM2YmNnydzUoZwSdQAd0d5h88sIgwihZdTzTcGjS9aAX0zeqL4 HGcQDLdTTksFGUB7o+1jvB3NGNybJhm26rUb93ZNv4vlx80uFVP6jBkSb 9NlBQXMkn1q6VEBC06jx4iR3TSH8vm7osClPGpP0fpLfB/sg+bLst6/g8 TMoH3sZ+HuKMm8/u0HVRIYH4Bbs/LMAu5FbjTSc1A6576I5PXlAUjR9t1 kloYzmbWA27iFD8VlEUzoBrqEmlF8p7KjjcS36Muk10GlMrzbRnVK0JFO g==; X-CSE-ConnectionGUID: 2WQHg3MHQ3q4rZjT2xjlxQ== X-CSE-MsgGUID: VisrtGMYTTODa/VaBPxdxQ== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="15862733" X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="15862733" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2024 03:30:21 -0700 X-CSE-ConnectionGUID: 1btX3VAaS72xFSvCG/+J4g== X-CSE-MsgGUID: BSRQmoG3SBGmb80NGqnl0A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="71385701" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa001.jf.intel.com with ESMTP; 24 May 2024 03:30:20 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com Subject: [PATCH v9 6/8] drm/i915/display: Compute Adaptive sync SDP params Date: Fri, 24 May 2024 15:54:30 +0530 Message-Id: <20240524102432.2499104-7-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Compute params for Adaptive Sync SDP when Fixed Average Vtotal mode is enabled. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_dp.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 15aab14c4206..7edc517b7859 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2627,7 +2627,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - if (!crtc_state->vrr.enable || + if (!(crtc_state->vrr.enable || crtc_state->cmrr.enable) || !intel_dp_as_sdp_supported(intel_dp)) return; @@ -2636,11 +2636,20 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, /* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */ as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; as_sdp->length = 0x9; - as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL; - as_sdp->vtotal = adjusted_mode->vtotal; - as_sdp->target_rr = 0; as_sdp->duration_incr_ms = 0; as_sdp->duration_incr_ms = 0; + + if (crtc_state->vrr.enable) { + as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL; + as_sdp->vtotal = adjusted_mode->vtotal; + as_sdp->target_rr = 0; + } else { + as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED; + as_sdp->vtotal = adjusted_mode->vtotal; + as_sdp->target_rr = DIV_ROUND_UP(adjusted_mode->clock * 1000, + adjusted_mode->htotal * adjusted_mode->vtotal); + as_sdp->target_rr_divider = true; + } } static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, From patchwork Fri May 24 10:24:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13673043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D0792C25B74 for ; Fri, 24 May 2024 10:30:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 30B7510E97D; Fri, 24 May 2024 10:30:38 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="KTscsZqf"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id DBC4910E97D for ; Fri, 24 May 2024 10:30:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716546627; x=1748082627; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nVWM4vyxp0Wknorm/wK+BdMLZp2Uv4HGhTN48rj3vWE=; b=KTscsZqfO4Jyb1+4W+qjw0wCbQaAG2IHqtsnYSJccs9VRfJzfUBwP7Qy Uk80mO6Yu2OYtP859G+AzMLqvv6ysdSfIUnZciUuIn83RozndDTv0a1Kg 48VZsGQmKrlGnRPVRBGqV0NGBInN9hd+N/iqmutgsCgWgAUfyO+OI0UUl PVLQmJxiaIGiDjEF9ms62P9fNgDZuBWnrZTw8UAcD11mB5eRJmB/OQhz2 Hq9Aydqf0LjX6/h2B/Kl8Cm6Dn8nF7e/2eXu0l17SCxArGYcZAKbdByK1 po+3Y30K/lmxsVfGcO+xV4zPrTDLiAV+egdUH4bLbBqC6/Y2eyxdQ1qjn Q==; X-CSE-ConnectionGUID: 2VwT/wQmTLysi1/l1rYM8A== X-CSE-MsgGUID: TJBIhmNmSKSpANlEPrjBcw== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="15862739" X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="15862739" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2024 03:30:23 -0700 X-CSE-ConnectionGUID: aAUcmUY3RO2YhGY2PbHX/w== X-CSE-MsgGUID: AePmKdIhQpygpg/rUQU7ig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="71385708" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa001.jf.intel.com with ESMTP; 24 May 2024 03:30:22 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com Subject: [PATCH v9 7/8] drm/i915/display: Compute vrr vsync params Date: Fri, 24 May 2024 15:54:31 +0530 Message-Id: <20240524102432.2499104-8-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Compute vrr vsync params in case of FAVT as well instead of only to AVT mode of operation. --v2: - Remove redundant computation for vrr_vsync_start and vrr_vsync_end(Ankit). Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_vrr.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 3fbedd7366bb..07be70f7c536 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -224,14 +224,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, if (crtc_state->uapi.vrr_enabled) { crtc_state->vrr.enable = true; crtc_state->mode_flags |= I915_MODE_FLAG_VRR; - if (intel_dp_as_sdp_supported(intel_dp)) { - crtc_state->vrr.vsync_start = - (crtc_state->hw.adjusted_mode.crtc_vtotal - - crtc_state->hw.adjusted_mode.vsync_start); - crtc_state->vrr.vsync_end = - (crtc_state->hw.adjusted_mode.crtc_vtotal - - crtc_state->hw.adjusted_mode.vsync_end); - } } else if (is_cmrr_frac_required(crtc_state, is_edp)) { crtc_state->vrr.enable = true; crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state); @@ -240,6 +232,15 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } + if (intel_dp_as_sdp_supported(intel_dp)) { + crtc_state->vrr.vsync_start = + (crtc_state->hw.adjusted_mode.crtc_vtotal - + crtc_state->hw.adjusted_mode.vsync_start); + crtc_state->vrr.vsync_end = + (crtc_state->hw.adjusted_mode.crtc_vtotal - + crtc_state->hw.adjusted_mode.vsync_end); + } + /* * For XE_LPD+, we use guardband and pipeline override * is deprecated. From patchwork Fri May 24 10:24:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13673041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10376C25B79 for ; Fri, 24 May 2024 10:30:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2B13010E9AD; Fri, 24 May 2024 10:30:37 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="SODL2IUT"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id D89A310E967 for ; Fri, 24 May 2024 10:30:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1716546627; x=1748082627; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mABwUKog6wI/OIG1iFlFckqcCCcMqs7RlaHVQpOkjNU=; b=SODL2IUTalgsbj+Xi1CPZ435DoF0tdek8f5V4GQEWB31RTobHeuxMCgD AvHLYsWNDrKcLPnmfbPK7SeGVI2FuIFHJhJVO9yXQVAVx1vRWwk1Q+TUd LFUvktqKuKOmbCk+q5d62CSMVA6Mp8+R3rXYHJ4HUOX+zIfncYUMOuW/t 869nKR95hhIB0wo6qm6hYRcJVCf1UOOC/kOIz+MCGujbwuEtkvDZ4xZyy O7S13zRXUgjxEU9/VdOf3T5PaW7NPqyPIju7FLy23/N9La5R3Y3nlyPJK fwL0K3pLfrqIC2sEecwUv/4g0DP9kFAJyltjiPt5I0VMni2uO5f6Er0ae w==; X-CSE-ConnectionGUID: HzBXHDPdSAGOYP548N6pgA== X-CSE-MsgGUID: J0+N6q9fSbuP3UWAE+oBNw== X-IronPort-AV: E=McAfee;i="6600,9927,11081"; a="15862744" X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="15862744" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2024 03:30:24 -0700 X-CSE-ConnectionGUID: 59faEmqJTpOBdNwZ3I6e9Q== X-CSE-MsgGUID: 7xw3UtOlSyalza0ZMKcfmg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,185,1712646000"; d="scan'208";a="71385720" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa001.jf.intel.com with ESMTP; 24 May 2024 03:30:23 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com Subject: [PATCH v9 8/8] drm/i915/display: Compute cmrr.enable flag Date: Fri, 24 May 2024 15:54:32 +0530 Message-Id: <20240524102432.2499104-9-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> References: <20240524102432.2499104-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Set cmrr.enable flag during intel_vrr_compute_config. Signed-off-by: Mitul Golani --- drivers/gpu/drm/i915/display/intel_vrr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 07be70f7c536..a981c8384f91 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -226,6 +226,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } else if (is_cmrr_frac_required(crtc_state, is_edp)) { crtc_state->vrr.enable = true; + crtc_state->cmrr.enable = true; crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state); crtc_state->vrr.vmin = crtc_state->vrr.vmax; crtc_state->vrr.flipline = crtc_state->vrr.vmin;