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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c756996sm10936625ad.8.2024.05.24.03.33.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 03:33:21 -0700 (PDT) From: Yong-Xuan Wang To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, cleger@rivosinc.com, alex@ghiti.fr, Yong-Xuan Wang , Jinyu Tang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Jones , Anup Patel , Conor Dooley , Mayuresh Chitale , Samuel Holland , Samuel Ortiz , Evan Green , Xiao Wang , Alexandre Ghiti , Andrew Morton , Kemeng Shi , "Mike Rapoport (IBM)" , Jisheng Zhang , "Matthew Wilcox (Oracle)" , Charlie Jenkins , Leonardo Bras , linux-kernel@vger.kernel.org Subject: [RFC PATCH v4 1/5] RISC-V: Detect and Enable Svadu Extension Support Date: Fri, 24 May 2024 18:33:01 +0800 Message-Id: <20240524103307.2684-2-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240524103307.2684-1-yongxuan.wang@sifive.com> References: <20240524103307.2684-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Svadu is a RISC-V extension for hardware updating of PTE A/D bits. In this patch we detect Svadu extension support from DTB and enable it with SBI FWFT extension. Also we add arch_has_hw_pte_young() to enable optimization in MGLRU and __wp_page_copy_user() if Svadu extension is available. Co-developed-by: Jinyu Tang Signed-off-by: Jinyu Tang Signed-off-by: Yong-Xuan Wang Reviewed-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/pgtable.h | 8 +++++++- arch/riscv/kernel/cpufeature.c | 11 +++++++++++ 5 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index be09c8836d56..30fa558ee284 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -34,6 +34,7 @@ config RISCV select ARCH_HAS_PMEM_API select ARCH_HAS_PREPARE_SYNC_CORE_CMD select ARCH_HAS_PTE_SPECIAL + select ARCH_HAS_HW_PTE_YOUNG select ARCH_HAS_SET_DIRECT_MAP if MMU select ARCH_HAS_SET_MEMORY if MMU select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2468c55933cd..2ac270ad4acd 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -194,6 +194,7 @@ /* xENVCFG flags */ #define ENVCFG_STCE (_AC(1, ULL) << 63) #define ENVCFG_PBMTE (_AC(1, ULL) << 62) +#define ENVCFG_ADUE (_AC(1, ULL) << 61) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) #define ENVCFG_CBIE_SHIFT 4 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e17d0078a651..8d539e3f4e11 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,7 @@ #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 +#define RISCV_ISA_EXT_SVADU 75 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 9f8ea0e33eb1..1f1b326ccf63 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -117,6 +117,7 @@ #include #include #include +#include #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT) @@ -285,7 +286,6 @@ static inline pte_t pud_pte(pud_t pud) } #ifdef CONFIG_RISCV_ISA_SVNAPOT -#include static __always_inline bool has_svnapot(void) { @@ -621,6 +621,12 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot) return __pgprot(prot); } +#define arch_has_hw_pte_young arch_has_hw_pte_young +static inline bool arch_has_hw_pte_young(void) +{ + return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU); +} + /* * THP functions */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3ed2359eae35..b023908c5932 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -93,6 +93,16 @@ static bool riscv_isa_extension_check(int id) return false; } return true; + case RISCV_ISA_EXT_SVADU: + if (sbi_probe_extension(SBI_EXT_FWFT) > 0) { + struct sbiret ret; + + ret = sbi_ecall(SBI_EXT_FWFT, SBI_EXT_FWFT_SET, SBI_FWFT_PTE_AD_HW_UPDATING, + 1, 0, 0, 0, 0); + + return ret.error == SBI_SUCCESS; + } + return false; case RISCV_ISA_EXT_INVALID: return false; } @@ -301,6 +311,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), + __RISCV_ISA_EXT_SUPERSET(svadu, RISCV_ISA_EXT_SVADU, riscv_xlinuxenvcfg_exts), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), From patchwork Fri May 24 10:33:02 2024 Content-Type: text/plain; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c756996sm10936625ad.8.2024.05.24.03.33.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 03:33:26 -0700 (PDT) From: Yong-Xuan Wang To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, cleger@rivosinc.com, alex@ghiti.fr, Yong-Xuan Wang , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v4 2/5] dt-bindings: riscv: Add Svadu Entry Date: Fri, 24 May 2024 18:33:02 +0800 Message-Id: <20240524103307.2684-3-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240524103307.2684-1-yongxuan.wang@sifive.com> References: <20240524103307.2684-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add an entry for the Svadu extension to the riscv,isa-extensions property. Signed-off-by: Yong-Xuan Wang Acked-by: Conor Dooley Reviewed-by: Andrew Jones --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 468c646247aa..598a5841920f 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -153,6 +153,12 @@ properties: ratified at commit 3f9ed34 ("Add ability to manually trigger workflow. (#2)") of riscv-time-compare. + - const: svadu + description: | + The standard Svadu supervisor-level extension for hardware updating + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request + #25 from ved-rivos/ratified") of riscv-svadu. + - const: svinval description: The standard Svinval supervisor-level extension for fine-grained From patchwork Fri May 24 10:33:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13673049 Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1187C8627C for ; Fri, 24 May 2024 10:33:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716546813; cv=none; b=rcEBSRu4CkaRqJDb98G0hACi6ay9H3xi6SO8rJhxV5I1reTRyOZ9kMECzpZ/HDk7SX1wWoi7MdKwWpi5g8cvFSgsYHAsatIPdEcP/5qgmMma/aItS9BwUPpYpuR06HKgSMPm0bLbIoK+vg2DFpuqLewl14l+NFXcXM76PDmzqzQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716546813; c=relaxed/simple; bh=ebtVeCnssg8Ja7qxL27lGhEYvxpCJBglPrv0beQGGHs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=frDvbnNezMepYU4zxwekOd3EVNE5ZhIP2RlVjmWwoMtebYUIMuOYSyblM/vu14qo5d2h8FSqoeD1YAzdLYXxCi1HejWTF75L5t4xXvd2DJqKnt3nPC7m709Cs6zQbKb81QJfuoyVm7jZCg6d3O3NKk6kaHHauOetZ7+pO9BHP5o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=HEYO/aHD; arc=none smtp.client-ip=209.85.216.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="HEYO/aHD" Received: by mail-pj1-f53.google.com with SMTP id 98e67ed59e1d1-2bd816ecaf5so2707433a91.2 for ; Fri, 24 May 2024 03:33:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1716546811; x=1717151611; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=jd1Ys62vbvg6Kc0O0Y86nMWaJ5oNcjAjjfmW/HddUAI=; b=HEYO/aHDDBm//TSFfLUIP0CayPLRVN+54SUQb0KlwHmM9tfw5MZv9MUyc/hVi+wn3Z h9uGrHsQ16nxbBqL4qpCG3ywRzdZLGHXxrm3O9FpLENIhY9gGfVW1flyXvI+LPJdnZUZ n2MFh9UyNhwWHfW6dCgoZ8K3XU9trCgZOjEzoHzNImq4PsC1EjR23aVb3pJK+G6BaX0x OXr0TAqKKuuz/qF6svZofpZKGx5MtW2K/42VgDwqK450De9G2Zeov12e5oS7Lch9/t2v NWYvzLZg5mtgKRcbyhc7S6FwPzZEY7qT4NK5wKcsNj459fYXUIlqlVDVfk8GRF4wuy/t hTJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716546811; x=1717151611; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=jd1Ys62vbvg6Kc0O0Y86nMWaJ5oNcjAjjfmW/HddUAI=; b=G32vSxp3AzyOfecC+sGa1wYJwi+cDzt/yd3QXudvNCHdKjpAiqw+uKK8LYzgwu0Gr7 +qAgcjVb8Oj0MrSc96C8DOokBKZhidT7adUFO8QY2gRzgnK+10ynpLaBdEz5YYrjMN0W RYQ07cw3FGmXdxRQ3Y1lR5zUFV1D+M9kHOnRkl0VUhf9JS8bSlGvGkzCF4skZ3x8xDb8 fAIQycuwlmiXie+/echuhcCrS/jrXfbdYkKUiuK49ejxe1wjofPSiHab34xihOUTPZ79 0Rwvq5o8qSap/qT89wPOOh1BB9zhwkojC6WCJZEn4PVlOj/i11nU62vjqYsi39GCpG7v g7dw== X-Forwarded-Encrypted: i=1; AJvYcCVIFGDmi12nNfdIQkthjjvVvaQfH0mADsTjU4zdzuG9GMyqw/dKiUnqL51DUb51vdV8rlcF7Z+SGE2hBidEks8Tp9Jc X-Gm-Message-State: AOJu0YxFkosaT1IYtkevJs/T+csRZN8mwzv9mCmYP7frlbYmxt7q77WM I3d9rnSp6B2VQbEsvcdqlf4ij3PBKw5cTRl9+mR0GscbMS2jFNRMdhAtapbmABQ= X-Google-Smtp-Source: AGHT+IEqHFEgIIblN+tGvoPCOSPByLGwZDHSVVvoF8yH7h0Gq/GADB1ishTF2VIIM9YemQrEgoARmQ== X-Received: by 2002:a17:90a:db54:b0:2be:d1:e7e1 with SMTP id 98e67ed59e1d1-2bf5e173c71mr1678283a91.10.1716546811417; Fri, 24 May 2024 03:33:31 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c756996sm10936625ad.8.2024.05.24.03.33.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 03:33:31 -0700 (PDT) From: Yong-Xuan Wang To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, cleger@rivosinc.com, alex@ghiti.fr, Yong-Xuan Wang , Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kernel@vger.kernel.org Subject: [RFC PATCH v4 3/5] RISC-V: KVM: Add Svadu Extension Support for Guest/VM Date: Fri, 24 May 2024 18:33:03 +0800 Message-Id: <20240524103307.2684-4-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240524103307.2684-1-yongxuan.wang@sifive.com> References: <20240524103307.2684-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: We extend the KVM ISA extension ONE_REG interface to allow VMM tools to detect and enable Svadu extension for Guest/VM. The ADUE bit in henvcfg is cleared by default for backward-compatibility. Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_onereg.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index a59a8448deea..bcf99264560d 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -167,6 +167,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZFA, KVM_RISCV_ISA_EXT_ZTSO, KVM_RISCV_ISA_EXT_ZACAS, + KVM_RISCV_ISA_EXT_SVADU, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 994adc26db4b..4166665e215d 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -37,6 +37,7 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVADU), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), From patchwork Fri May 24 10:33:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13673050 Received: from mail-pg1-f170.google.com (mail-pg1-f170.google.com [209.85.215.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6998086AFC for ; Fri, 24 May 2024 10:33:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716546817; cv=none; b=M9m/fvm0iEEvmUgzgQfHDAQjOCQc17VJ7wm8L3il0Zvmr36T9x0hZqIseFqFdX1g2V0hZJPOVyjBRm9cFZ/4hus7IMcLqffiU4tGbGQ26f/Lx3ezw0XCJ0kUXLKHXi4btVvTa+CK0M9hHl5Slzy1uxw2K0ZGdn4AQyFvqAxZbBo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716546817; c=relaxed/simple; bh=8o+/jM3VuqOdvK334SVVAiO8sfT3FG+iNmrY1VGDMO8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=RATZwNSv4oTqrja0/r9VJeDRQwNGv8K/ufjPAmnqWxo8WYPLhr8WIlFcLY56WJQa3DYPxo1hs46kbR2Q+c13/Eo2PSu/OawrjrN8m3jd+QoRP3OMqe7S7aJIGzPBZv5+MUhkaI9pOCl/+9/Zvb7roZVRXV0dr9on94KkIn+fyJI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=PSBg/bvq; arc=none smtp.client-ip=209.85.215.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="PSBg/bvq" Received: by mail-pg1-f170.google.com with SMTP id 41be03b00d2f7-681ad26f277so567410a12.3 for ; Fri, 24 May 2024 03:33:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1716546816; x=1717151616; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=WZ6BYwn5mOMy3jrtkhWqLvXB1lQ/8oP4LPFGWsTQioU=; b=PSBg/bvqruGiCClL8p5vUf2yjQWC7mCCG4Bdt2IK6I3EBBlKN2o96374zmbJFIfAja K0HMw26C+2thxDaD6QAIckuOoyzVvGD3Rw8i6jtQ8Q057NXorOVYhJ66Wv83c3+6n2vP YKmIJJif0Ud6I8C5/UpLdrZVJgGlLg1au/S0HQz01h1P4rkrIM6IBBeuu21DIksBHjCz WDzvXrQc9SzbDPQ3A5RqCd4CQExu/B+/cX2yMxVob0eUIptzPrIXEaF/j3EoxKyuHTGC I9CfVVnyh53FVzXWlg0A2fL9dGbA3g0uOuePFPJtvpiJ/VE6ick/tjmPlaeDDZ+K1inF 7wCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716546816; x=1717151616; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=WZ6BYwn5mOMy3jrtkhWqLvXB1lQ/8oP4LPFGWsTQioU=; b=vMYG8PChWH1nEgHlWo1HZqe0n+NsysAfePRb56SmV+OGDeNHqYXOyEvgAdz57clorJ SWrTbHb+iZuvPHM05xdGBcRKXTDAabaupEJNUgqNdekqn6uR8tGscK+VR6Mb07FppOTN X8LvkI7MuANvA6SqHi7nslH709+uwaJIBGUMYe81eAXKXNBKIZIPN3iAgaxHlzfQ9B+m bEXpsUiiLEkzMCb2lYn0up9/kzC9kKRBXJYSws62TH22rJedHw1BHRM1yl9gZFANV3J/ TGuwuka1JPH/NnbeYDP0CzWB27ELu2TELuhkRSRpSjK27tOQeSNIPYe17SrL/hsDIhtK 7u2g== X-Forwarded-Encrypted: i=1; AJvYcCVBH7dauNA2OcfIWEt46JLPKqziM9II5G0vR313wbQPNUjrRzvg8xVQ7YFb9+UxQJKhwqOQrlhRpk9me45GcyCeNNKu X-Gm-Message-State: AOJu0YzitXakYWb5zlt9epUHYBjL8EmtY2hS2J+ZjjxvNf5MMAeYrLwF HTuVwLoQrzAjoIKNXq4emfnktNOuWm112SqpyxO2sUcb++311ggp7Lcwy3p3MsQ= X-Google-Smtp-Source: AGHT+IHwYRl01Pr85mA3t2HEOvg+sKlaLLf3SKTeqlscw+r+oqPR6B2j0Lab23cBYZRY16JbGWy4mw== X-Received: by 2002:a05:6a20:6a2c:b0:1af:f23c:804a with SMTP id adf61e73a8af0-1b212e20716mr2197510637.38.1716546815854; Fri, 24 May 2024 03:33:35 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c756996sm10936625ad.8.2024.05.24.03.33.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 03:33:35 -0700 (PDT) From: Yong-Xuan Wang To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, cleger@rivosinc.com, alex@ghiti.fr, Yong-Xuan Wang , Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kernel@vger.kernel.org Subject: [RFC PATCH v4 4/5] RISC-V: KVM: add support for SBI_FWFT_PTE_AD_HW_UPDATING Date: Fri, 24 May 2024 18:33:04 +0800 Message-Id: <20240524103307.2684-5-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240524103307.2684-1-yongxuan.wang@sifive.com> References: <20240524103307.2684-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add support for SBI_FWFT_PTE_AD_HW_UPDATING to set the PTE A/D bits updating behavior for Guest/VM. Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h | 2 +- arch/riscv/kvm/vcpu_sbi_fwft.c | 38 +++++++++++++++++++++- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h b/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h index 7b7bcc5c8fee..3614a44e0a4a 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h @@ -11,7 +11,7 @@ #include -#define KVM_SBI_FWFT_FEATURE_COUNT 1 +#define KVM_SBI_FWFT_FEATURE_COUNT 2 struct kvm_sbi_fwft_config; struct kvm_vcpu; diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index 89ec263c250d..14ef74023340 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -71,6 +71,36 @@ static int kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu, return SBI_SUCCESS; } +static int kvm_sbi_fwft_adue_supported(struct kvm_vcpu *vcpu) +{ + if (!riscv_isa_extension_available(vcpu->arch.isa, SVADU)) + return SBI_ERR_NOT_SUPPORTED; + + return 0; +} + +static int kvm_sbi_fwft_set_adue(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, + unsigned long value) +{ + if (value) + vcpu->arch.cfg.henvcfg |= ENVCFG_ADUE; + else + vcpu->arch.cfg.henvcfg &= ~ENVCFG_ADUE; + + return SBI_SUCCESS; +} + +static int kvm_sbi_fwft_get_adue(struct kvm_vcpu *vcpu, struct kvm_sbi_fwft_config *conf, + unsigned long *value) +{ + if (!riscv_isa_extension_available(vcpu->arch.isa, SVADU)) + return SBI_ERR_NOT_SUPPORTED; + + *value = !!(vcpu->arch.cfg.henvcfg & ENVCFG_ADUE); + + return SBI_SUCCESS; +} + static struct kvm_sbi_fwft_config * kvm_sbi_fwft_get_config(struct kvm_vcpu *vcpu, enum sbi_fwft_feature_t feature) { @@ -177,7 +207,13 @@ static const struct kvm_sbi_fwft_feature features[] = { .supported = kvm_sbi_fwft_misaligned_delegation_supported, .set = kvm_sbi_fwft_set_misaligned_delegation, .get = kvm_sbi_fwft_get_misaligned_delegation, - } + }, + { + .id = SBI_FWFT_PTE_AD_HW_UPDATING, + .supported = kvm_sbi_fwft_adue_supported, + .set = kvm_sbi_fwft_set_adue, + .get = kvm_sbi_fwft_get_adue, + }, }; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f44c756996sm10936625ad.8.2024.05.24.03.33.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 03:33:40 -0700 (PDT) From: Yong-Xuan Wang To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, cleger@rivosinc.com, alex@ghiti.fr, Yong-Xuan Wang , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v4 5/5] KVM: riscv: selftests: Add Svadu Extension to get-reg-list testt Date: Fri, 24 May 2024 18:33:05 +0800 Message-Id: <20240524103307.2684-6-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240524103307.2684-1-yongxuan.wang@sifive.com> References: <20240524103307.2684-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Update the get-reg-list test to test the Svadu Extension is available for guest OS. Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index b882b7b9b785..3e71b7e40dbf 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -44,6 +44,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADU: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT: @@ -409,6 +410,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVADU), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), @@ -932,6 +934,7 @@ KVM_ISA_EXT_SUBLIST_CONFIG(fp_d, FP_D); KVM_ISA_EXT_SIMPLE_CONFIG(h, H); KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN); KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC); +KVM_ISA_EXT_SIMPLE_CONFIG(svadu, SVADU); KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL); KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT); KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT); @@ -987,6 +990,7 @@ struct vcpu_reg_list *vcpu_configs[] = { &config_h, &config_smstateen, &config_sstc, + &config_svadu, &config_svinval, &config_svnapot, &config_svpbmt,