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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a626c817c81sm116051366b.28.2024.05.24.04.08.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 04:08:57 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 05423ceb-19be-11ef-90a1-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716548939; x=1717153739; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VObOJh3vdjUSCat91cLLs4dKVo8jpzpt3RbhRwfCXX4=; b=BT3hrZH+0zQcsy8aojUBE1iXiTjgohradSxzFr0lWS1lZZMWajmn6cKfM87ISrd3dJ JXNF6VPwBYzhaOwluaDWtx65Yd08KRwANoqgL8UClRqmrJzIobLIG1glN3jTZtfRQCJF cv3bxEQJqwZXvEZYTVpmgLRMnO85pTSIshZ2OE9HQQjhUqpbwAKBjLFWcyWYTf5NKqce LJPdYwa9FW4LdR2vxe9b9LkCetmMTSPjXITFTAElX64LH9RaBF9UlmtwY+XdYCuDSODb PhaguEL3wybPi2Lw1BFRakJMT3HgxDOeXaJQu5IkXCCJNqCYcu6fVxgXSeJnsNCPVDeV du+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716548939; x=1717153739; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VObOJh3vdjUSCat91cLLs4dKVo8jpzpt3RbhRwfCXX4=; b=oSJH6jYMwnMfjs/mUFdu5dQie0nF5xnSJua3T3hn0WARxH2l/GnFyEvJ6X7X+mKHUn lzYgsEl96+Kk6qhy6z1ud7ECXCacISDwaTK2i8tWOEiocn4KUKNCjjIbGuGOv4FKCNRz 7gGngY8XSmeHXdjpbqE0KuO1RrICpW8PfTvmV41b6iQXap5aQplIb16DByBa26J3yqs4 txML7UBEK/MKZoXkF0Z2n+U+5tLA0eJuq0lWzHrbjU8RmR32cfHG3VyjOAVSOPXlzd9h nB8H+0PSmj5RG1WsqM5hyhQQRk3OeaArRyGrAb9rh8Ed6affHtD+EToj/3bjuY+rGswl xQlg== X-Gm-Message-State: AOJu0Yw6ipFMikCMmnNSbMTAVp3BX2TA8eLO4kQ/S6A5vcHY/H+0O3uS vddq+r9XpykaToHu4VnDf526039azoJXeCzhxF1os6f97RUlfrktKCXtfvjg X-Google-Smtp-Source: AGHT+IEnfRajkGsXOcdDFf+N0NCog0aw4WP70ktRaE8iDhxiyttE5UG/CVauN9Avk8uaqYIdE5AXJA== X-Received: by 2002:a17:906:2dd7:b0:a59:ccbb:595b with SMTP id a640c23a62f3a-a62642e937amr189197966b.25.1716548938644; Fri, 24 May 2024 04:08:58 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Doug Goldstein , Stefano Stabellini , Alistair Francis , Bob Eshleman , Connor Davis , "Daniel P. Smith" Subject: [PATCH v11 1/9] xen/riscv: disable unnecessary configs Date: Fri, 24 May 2024 13:08:47 +0200 Message-ID: <77cfff76ddcad4e41efce46c1e68d504e376bd32.1716547693.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Disables unnecessary configs for two cases: 1. By utilizing EXTRA_FIXED_RANDCONFIG for randconfig builds (GitLab CI jobs). 2. By using tiny64_defconfig for non-randconfig builds. Only configs which lead to compilation issues were disabled. Remove lines related to disablement of configs which aren't affected compilation: -# CONFIG_SCHED_CREDIT is not set -# CONFIG_SCHED_RTDS is not set -# CONFIG_SCHED_NULL is not set -# CONFIG_SCHED_ARINC653 is not set -# CONFIG_TRACEBUFFER is not set -# CONFIG_HYPFS is not set -# CONFIG_SPECULATIVE_HARDEN_ARRAY is not set To allow CONFIG_ARGO build happy it was included to as ARGO requires p2m_type_t ( p2m_ram_rw ) and declaration of check_get_page_from_gfn() from xen/p2m-common.h. Also, it was included to asm/p2m.h as after the latter was included to the compilation error that EINVAL, EOPNOTSUPP aren't declared started to occur. CONFIG_XSM=n as it requires an introduction of: * boot_module_find_by_kind() * BOOTMOD_XSM * struct bootmodule * copy_from_paddr() The mentioned things aren't introduced now. CPU_BOOT_TIME_CPUPOOLS requires an introduction of cpu_physical_id() and acpi_disabled, so it is disabled for now. PERF_COUNTERS requires asm/perf.h and asm/perfc-defn.h, so it is also disabled for now, as RISC-V hasn't introduced this headers yet. LIVEPATCH isn't ready for RISC-V too and it can be overriden by randconfig, so to avoid compilation errors for randconfig it is disabled for now. Signed-off-by: Oleksii Kurochko --- Changes in V10-V11: - Nothing changed. Only rebase. --- Changes in V9: - update the commit message: add info about LIVEPATCH and PERF_COUNTERS. --- Changes in V8: - disabled CPU_BOOT_TIME_CPUPOOLS as it requires an introduction of cpu_physical_id() and acpi_disabled. - leave XSM disabled, add explanation in the commit message. - drop HYPFS as the patch was provided to resolve compilation issue when this condif is enabled for RISC-V. - include asm/p2m.h to asm/domain.h, and xen/errno.h to asm/p2m.h to drop ARGO config from tiny64_defconfing and build.yaml. - update the commit message. --- Changes in V7: - Disable only configs which cause compilation issues. - Update the commit message. --- Changes in V6: - Nothing changed. Only rebase. --- Changes in V5: - Rebase and drop duplicated configs in EXTRA_FIXED_RANDCONFIG list - Update the commit message --- Changes in V4: - Nothing changed. Only rebase --- Changes in V3: - Remove EXTRA_FIXED_RANDCONFIG for non-randconfig jobs. For non-randconfig jobs, it is sufficient to disable configs by using the defconfig. - Remove double blank lines in build.yaml file before archlinux-current-gcc-riscv64-debug --- Changes in V2: - update the commit message. - remove xen/arch/riscv/Kconfig changes. --- automation/gitlab-ci/build.yaml | 4 ++++ xen/arch/riscv/configs/tiny64_defconfig | 12 +++++------- xen/arch/riscv/include/asm/domain.h | 2 ++ xen/arch/riscv/include/asm/p2m.h | 2 ++ 4 files changed, 13 insertions(+), 7 deletions(-) diff --git a/automation/gitlab-ci/build.yaml b/automation/gitlab-ci/build.yaml index 49d6265ad5..ff5c9055d1 100644 --- a/automation/gitlab-ci/build.yaml +++ b/automation/gitlab-ci/build.yaml @@ -494,10 +494,14 @@ alpine-3.18-gcc-debug-arm64-earlyprintk: .riscv-fixed-randconfig: variables: &riscv-fixed-randconfig EXTRA_FIXED_RANDCONFIG: | + CONFIG_BOOT_TIME_CPUPOOLS=n CONFIG_COVERAGE=n CONFIG_EXPERT=y CONFIG_GRANT_TABLE=n CONFIG_MEM_ACCESS=n + CONFIG_PERF_COUNTERS=n + CONFIG_LIVEPATCH=n + CONFIG_XSM=n archlinux-current-gcc-riscv64: extends: .gcc-riscv64-cross-build diff --git a/xen/arch/riscv/configs/tiny64_defconfig b/xen/arch/riscv/configs/tiny64_defconfig index 09defe236b..fc7a04872f 100644 --- a/xen/arch/riscv/configs/tiny64_defconfig +++ b/xen/arch/riscv/configs/tiny64_defconfig @@ -1,12 +1,10 @@ -# CONFIG_SCHED_CREDIT is not set -# CONFIG_SCHED_RTDS is not set -# CONFIG_SCHED_NULL is not set -# CONFIG_SCHED_ARINC653 is not set -# CONFIG_TRACEBUFFER is not set -# CONFIG_HYPFS is not set +# CONFIG_BOOT_TIME_CPUPOOLS is not set # CONFIG_GRANT_TABLE is not set -# CONFIG_SPECULATIVE_HARDEN_ARRAY is not set # CONFIG_MEM_ACCESS is not set +# CONFIG_PERF_COUNTERS is not set +# CONFIG_COVERAGE is not set +# CONFIG_LIVEPATCH is not set +# CONFIG_XSM is not set CONFIG_RISCV_64=y CONFIG_DEBUG=y diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/asm/domain.h index 027bfa8a93..16a9dd57aa 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -5,6 +5,8 @@ #include #include +#include + struct hvm_domain { uint64_t params[HVM_NR_PARAMS]; diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/p2m.h index 387f372b5d..26860c0ae7 100644 --- a/xen/arch/riscv/include/asm/p2m.h +++ b/xen/arch/riscv/include/asm/p2m.h @@ -2,6 +2,8 @@ #ifndef __ASM_RISCV_P2M_H__ #define __ASM_RISCV_P2M_H__ +#include + #include #define paddr_bits PADDR_BITS From patchwork Fri May 24 11:08:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13673090 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5022FC25B7D for ; Fri, 24 May 2024 11:09:15 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.729357.1134507 (Exim 4.92) (envelope-from ) id 1sASnJ-0003gx-5l; Fri, 24 May 2024 11:09:05 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 729357.1134507; Fri, 24 May 2024 11:09:05 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sASnJ-0003gq-2c; Fri, 24 May 2024 11:09:05 +0000 Received: by outflank-mailman (input) for mailman id 729357; Fri, 24 May 2024 11:09:03 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sASnH-0003Cz-8A for xen-devel@lists.xenproject.org; Fri, 24 May 2024 11:09:03 +0000 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [2a00:1450:4864:20::634]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 060dc183-19be-11ef-b4bb-af5377834399; Fri, 24 May 2024 13:09:00 +0200 (CEST) Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-a62769075adso51716266b.3 for ; Fri, 24 May 2024 04:09:00 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a626c817c81sm116051366b.28.2024.05.24.04.08.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 04:08:59 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 060dc183-19be-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716548940; x=1717153740; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+VAAhE05amsEXGMuoLHu119Hm7q5hqdBYgzStrwEHgM=; b=LkIuXS6VBuwouDn3Z+NJ8C2lM4gnQtJpQmcDf5tEr+N8bKfn3yILOH2cueNm0n3aXU En6ZIhTeoOYP7xi3KB0v2/v0Pape3R7J+5WrN+vFjeLsMd9ECF8uOge5xHgjIYq2O8fo kFNHdN6liySXBTlU3dBud7oVC3vwZwoHZbVflR7+KKCREQZlPSeAUmUUDxEnunXC8ni5 BnHB3yoKg96zg4iWWqOy0DEv29gF5aH0e2ZYfQRRGu2B+0PrLF4qU81tDBEaHsZRq4Jt ufvCaXRa0gzpUEac01riNtASPxAclfus/UN/D0jaPvM05n3SmZCKpwLQ0eKQZtSVxzB2 At7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716548940; x=1717153740; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+VAAhE05amsEXGMuoLHu119Hm7q5hqdBYgzStrwEHgM=; b=qDu2/aRMkxnXSS+M/T1/FpQgvbQM0vss0Csquu3X49csH3fJNxziuX7BYQ/o3dVNUn Ulq+UCjKi1dnBYGvr/oC44Z3deJq0+5tUd8uPZPmpTFM3H9lzvtn/Ie4Qq8DSnSaimSk I22EsoMGEhNVrqCG1Fpus48vXaaqN7YNo3Pxc9G3tO6+EbbRvV0n4hnhDvue46yZTJMZ 5LbhAOrdPz6L+2tuzk5Pe5JgV/u4uELzVmW/+2oIJjdRUn7nXvJB/ZeoxyrnlRce+krP drW/o5imnWdpQ/53dPdi3AR7awPu6lwZ4v9kukcB6NQmlvm4TB3/DNuca6PGyJAIYcx5 WVzA== X-Gm-Message-State: AOJu0YzGChUoevLEX/6dVSF9Xzg+vT/8JwYj0KLtrvIJUA5yMnddscQ6 A8xIn7GAV9Ia1wFotG3IGWkZMrWSStW/MsN4SwvCVogmdox9VmQLMytFhYz8 X-Google-Smtp-Source: AGHT+IH8Xhcb1dv8lZUHDI5J6yAYaAcBV72erzycFafIGTAk/CxjjZTaBtujwXSoOE/FwfWwC9cqVA== X-Received: by 2002:a17:907:3f29:b0:a5a:6122:d64b with SMTP id a640c23a62f3a-a62641a33e7mr165738766b.5.1716548939777; Fri, 24 May 2024 04:08:59 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , George Dunlap , Jan Beulich , Shawn Anastasio , =?utf-8?q?Roger_Pau_Mon?= =?utf-8?q?n=C3=A9?= Subject: [PATCH v11 2/9] xen: introduce generic non-atomic test_*bit() Date: Fri, 24 May 2024 13:08:48 +0200 Message-ID: <79c3c31f0032a79c25d0a458b6091904457c8939.1716547693.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 The following generic functions were introduced: * test_bit * generic__test_and_set_bit * generic__test_and_clear_bit * generic__test_and_change_bit These functions and macros can be useful for architectures that don't have corresponding arch-specific instructions. Also, the patch introduces the following generics which are used by the functions mentioned above: * BITOP_BITS_PER_WORD * BITOP_MASK * BITOP_WORD * BITOP_TYPE BITS_PER_BYTE was moved to xen/bitops.h as BITS_PER_BYTE is the same across architectures. The following approach was chosen for generic*() and arch*() bit operation functions: If the bit operation function that is going to be generic starts with the prefix "__", then the corresponding generic/arch function will also contain the "__" prefix. For example: * test_bit() will be defined using arch_test_bit() and generic_test_bit(). * __test_and_set_bit() will be defined using arch__test_and_set_bit() and generic__test_and_set_bit(). Signed-off-by: Oleksii Kurochko --- Reviewed-by: Jan Beulich jbeulich@suse.com? Jan gave his R-by for the previous version of the patch, but some changes were done, so I wasn't sure if I could use the R-by in this patch version. The current patch can be merged without waiting for Andrew's patch series as it was rebased on top of staging. --- Changes in V11: - fix identation in generic_test_bit() function. - move definition of BITS_PER_BYTE from /bitops.h to xen/bitops.h - drop the changes in arm64/livepatch.c. - update the the comments on top of functions: generic__test_and_set_bit(), generic__test_and_clear_bit(), generic__test_and_change_bit(), generic_test_bit(). - Update footer after Signed-off section. - Rebase the patch on top of staging branch, so it can be merged when necessary approves will be given. - Update the commit message. --- Changes in V10: - update the commit message. ( re-order paragraphs and add explanation usage of prefix "__" in bit operation function names ) - add parentheses around the whole expression of bitop_bad_size() macros. - move macros bitop_bad_size() above asm/bitops.h as it is not arch-specific anymore and there is no need for overriding it. - drop macros check_bitop_size() and use "if ( bitop_bad_size(addr) ) __bitop_bad_size();" implictly where it is needed. - in use 'int' as a first parameter for __test_and_*(), generic__test_and_*() to be consistent with how the mentioned functions were declared in the original per-arch functions. - add 'const' to p variable in generic_test_bit(). - move definition of BITOP_BITS_PER_WORD and bitop_uint_t to xen/bitops.h as we don't allow for arch overrides these definitions anymore. --- Changes in V9: - move up xen/bitops.h in ppc/asm/page.h. - update defintion of arch_check_bitop_size. And drop correspondent macros from x86/asm/bitops.h - drop parentheses in generic__test_and_set_bit() for definition of local variable p. - fix indentation inside #ifndef BITOP_TYPE...#endif - update the commit message. --- Changes in V8: - drop __pure for function which uses volatile. - drop unnessary () in generic__test_and_change_bit() for addr casting. - update prototype of generic_test_bit() and test_bit(): now it returns bool instead of int. - update generic_test_bit() to use BITOP_MASK(). - Deal with fls{l} changes: it should be in the patch with introduced generic fls{l}. - add a footer with explanation of dependency on an uncommitted patch after Signed-off. - abstract bitop_size(). - move BITOP_TYPE define to . --- Changes in V7: - move everything to xen/bitops.h to follow the same approach for all generic bit ops. - put together BITOP_BITS_PER_WORD and bitops_uint_t. - make BITOP_MASK more generic. - drop #ifdef ... #endif around BITOP_MASK, BITOP_WORD as they are generic enough. - drop "_" for generic__{test_and_set_bit,...}(). - drop " != 0" for functions which return bool. - add volatile during the cast for generic__{...}(). - update the commit message. - update arch related code to follow the proposed generic approach. --- Changes in V6: - Nothing changed ( only rebase ) --- Changes in V5: - new patch --- xen/arch/arm/include/asm/bitops.h | 69 ----------- xen/arch/ppc/include/asm/bitops.h | 54 --------- xen/arch/ppc/include/asm/page.h | 2 +- xen/arch/ppc/mm-radix.c | 2 +- xen/arch/x86/include/asm/bitops.h | 31 ++--- xen/include/xen/bitops.h | 185 ++++++++++++++++++++++++++++++ 6 files changed, 196 insertions(+), 147 deletions(-) diff --git a/xen/arch/arm/include/asm/bitops.h b/xen/arch/arm/include/asm/bitops.h index ab030b6cb0..af38fbffdd 100644 --- a/xen/arch/arm/include/asm/bitops.h +++ b/xen/arch/arm/include/asm/bitops.h @@ -22,11 +22,6 @@ #define __set_bit(n,p) set_bit(n,p) #define __clear_bit(n,p) clear_bit(n,p) -#define BITOP_BITS_PER_WORD 32 -#define BITOP_MASK(nr) (1UL << ((nr) % BITOP_BITS_PER_WORD)) -#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) -#define BITS_PER_BYTE 8 - #define ADDR (*(volatile int *) addr) #define CONST_ADDR (*(const volatile int *) addr) @@ -76,70 +71,6 @@ bool test_and_change_bit_timeout(int nr, volatile void *p, bool clear_mask16_timeout(uint16_t mask, volatile void *p, unsigned int max_try); -/** - * __test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_set_bit(int nr, volatile void *addr) -{ - unsigned int mask = BITOP_MASK(nr); - volatile unsigned int *p = - ((volatile unsigned int *)addr) + BITOP_WORD(nr); - unsigned int old = *p; - - *p = old | mask; - return (old & mask) != 0; -} - -/** - * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned int mask = BITOP_MASK(nr); - volatile unsigned int *p = - ((volatile unsigned int *)addr) + BITOP_WORD(nr); - unsigned int old = *p; - - *p = old & ~mask; - return (old & mask) != 0; -} - -/* WARNING: non atomic and it can be reordered! */ -static inline int __test_and_change_bit(int nr, - volatile void *addr) -{ - unsigned int mask = BITOP_MASK(nr); - volatile unsigned int *p = - ((volatile unsigned int *)addr) + BITOP_WORD(nr); - unsigned int old = *p; - - *p = old ^ mask; - return (old & mask) != 0; -} - -/** - * test_bit - Determine whether a bit is set - * @nr: bit number to test - * @addr: Address to start counting from - */ -static inline int test_bit(int nr, const volatile void *addr) -{ - const volatile unsigned int *p = (const volatile unsigned int *)addr; - return 1UL & (p[BITOP_WORD(nr)] >> (nr & (BITOP_BITS_PER_WORD-1))); -} - /* * On ARMv5 and above those functions can be implemented around * the clz instruction for much better code efficiency. diff --git a/xen/arch/ppc/include/asm/bitops.h b/xen/arch/ppc/include/asm/bitops.h index bea655796d..71bbb5f16a 100644 --- a/xen/arch/ppc/include/asm/bitops.h +++ b/xen/arch/ppc/include/asm/bitops.h @@ -15,11 +15,6 @@ #define __set_bit(n, p) set_bit(n, p) #define __clear_bit(n, p) clear_bit(n, p) -#define BITOP_BITS_PER_WORD 32 -#define BITOP_MASK(nr) (1U << ((nr) % BITOP_BITS_PER_WORD)) -#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) -#define BITS_PER_BYTE 8 - /* PPC bit number conversion */ #define PPC_BITLSHIFT(be) (BITS_PER_LONG - 1 - (be)) #define PPC_BIT(bit) (1UL << PPC_BITLSHIFT(bit)) @@ -69,17 +64,6 @@ static inline void clear_bit(int nr, volatile void *addr) clear_bits(BITOP_MASK(nr), (volatile unsigned int *)addr + BITOP_WORD(nr)); } -/** - * test_bit - Determine whether a bit is set - * @nr: bit number to test - * @addr: Address to start counting from - */ -static inline int test_bit(int nr, const volatile void *addr) -{ - const volatile unsigned int *p = addr; - return 1 & (p[BITOP_WORD(nr)] >> (nr & (BITOP_BITS_PER_WORD - 1))); -} - static inline unsigned int test_and_clear_bits( unsigned int mask, volatile unsigned int *p) @@ -133,44 +117,6 @@ static inline int test_and_set_bit(unsigned int nr, volatile void *addr) (volatile unsigned int *)addr + BITOP_WORD(nr)) != 0; } -/** - * __test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_set_bit(int nr, volatile void *addr) -{ - unsigned int mask = BITOP_MASK(nr); - volatile unsigned int *p = (volatile unsigned int *)addr + BITOP_WORD(nr); - unsigned int old = *p; - - *p = old | mask; - return (old & mask) != 0; -} - -/** - * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned int mask = BITOP_MASK(nr); - volatile unsigned int *p = (volatile unsigned int *)addr + BITOP_WORD(nr); - unsigned int old = *p; - - *p = old & ~mask; - return (old & mask) != 0; -} - #define flsl(x) generic_flsl(x) #define fls(x) generic_fls(x) #define ffs(x) ({ unsigned int t_ = (x); fls(t_ & -t_); }) diff --git a/xen/arch/ppc/include/asm/page.h b/xen/arch/ppc/include/asm/page.h index 890e285051..6d4cd2611c 100644 --- a/xen/arch/ppc/include/asm/page.h +++ b/xen/arch/ppc/include/asm/page.h @@ -2,9 +2,9 @@ #ifndef _ASM_PPC_PAGE_H #define _ASM_PPC_PAGE_H +#include #include -#include #include #define PDE_VALID PPC_BIT(0) diff --git a/xen/arch/ppc/mm-radix.c b/xen/arch/ppc/mm-radix.c index ab5a10695c..9055730997 100644 --- a/xen/arch/ppc/mm-radix.c +++ b/xen/arch/ppc/mm-radix.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include #include #include #include #include -#include #include #include #include diff --git a/xen/arch/x86/include/asm/bitops.h b/xen/arch/x86/include/asm/bitops.h index 5a71afbc89..c4e7a06155 100644 --- a/xen/arch/x86/include/asm/bitops.h +++ b/xen/arch/x86/include/asm/bitops.h @@ -19,9 +19,6 @@ #define ADDR (*(volatile int *) addr) #define CONST_ADDR (*(const volatile int *) addr) -extern void __bitop_bad_size(void); -#define bitop_bad_size(addr) (sizeof(*(addr)) < 4) - /** * set_bit - Atomically set a bit in memory * @nr: the bit to set @@ -175,7 +172,7 @@ static inline int test_and_set_bit(int nr, volatile void *addr) }) /** - * __test_and_set_bit - Set a bit and return its old value + * arch__test_and_set_bit - Set a bit and return its old value * @nr: Bit to set * @addr: Address to count from * @@ -183,7 +180,7 @@ static inline int test_and_set_bit(int nr, volatile void *addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static inline int __test_and_set_bit(int nr, void *addr) +static inline int arch__test_and_set_bit(int nr, volatile void *addr) { int oldbit; @@ -194,10 +191,7 @@ static inline int __test_and_set_bit(int nr, void *addr) return oldbit; } -#define __test_and_set_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ - __test_and_set_bit(nr, addr); \ -}) +#define arch__test_and_set_bit arch__test_and_set_bit /** * test_and_clear_bit - Clear a bit and return its old value @@ -224,7 +218,7 @@ static inline int test_and_clear_bit(int nr, volatile void *addr) }) /** - * __test_and_clear_bit - Clear a bit and return its old value + * arch__test_and_clear_bit - Clear a bit and return its old value * @nr: Bit to set * @addr: Address to count from * @@ -232,7 +226,7 @@ static inline int test_and_clear_bit(int nr, volatile void *addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static inline int __test_and_clear_bit(int nr, void *addr) +static inline int arch__test_and_clear_bit(int nr, volatile void *addr) { int oldbit; @@ -243,13 +237,10 @@ static inline int __test_and_clear_bit(int nr, void *addr) return oldbit; } -#define __test_and_clear_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ - __test_and_clear_bit(nr, addr); \ -}) +#define arch__test_and_clear_bit arch__test_and_clear_bit /* WARNING: non atomic and it can be reordered! */ -static inline int __test_and_change_bit(int nr, void *addr) +static inline int arch__test_and_change_bit(int nr, volatile void *addr) { int oldbit; @@ -260,10 +251,7 @@ static inline int __test_and_change_bit(int nr, void *addr) return oldbit; } -#define __test_and_change_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ - __test_and_change_bit(nr, addr); \ -}) +#define arch__test_and_change_bit arch__test_and_change_bit /** * test_and_change_bit - Change a bit and return its new value @@ -307,8 +295,7 @@ static inline int variable_test_bit(int nr, const volatile void *addr) return oldbit; } -#define test_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ +#define arch_test_bit(nr, addr) ({ \ __builtin_constant_p(nr) ? \ constant_test_bit(nr, addr) : \ variable_test_bit(nr, addr); \ diff --git a/xen/include/xen/bitops.h b/xen/include/xen/bitops.h index e3c5a4ccf3..9f89232ba6 100644 --- a/xen/include/xen/bitops.h +++ b/xen/include/xen/bitops.h @@ -103,8 +103,193 @@ static inline int generic_flsl(unsigned long x) * Include this here because some architectures need generic_ffs/fls in * scope */ + +#define BITOP_BITS_PER_WORD 32 +typedef uint32_t bitop_uint_t; + +#define BITOP_MASK(nr) ((bitop_uint_t)1 << ((nr) % BITOP_BITS_PER_WORD)) + +#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) + +#define BITS_PER_BYTE 8 + +extern void __bitop_bad_size(void); + +#define bitop_bad_size(addr) (sizeof(*(addr)) < sizeof(bitop_uint_t)) + +/* --------------------- Please tidy above here --------------------- */ + #include +/** + * generic__test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +generic__test_and_set_bit(int nr, volatile void *addr) +{ + bitop_uint_t mask = BITOP_MASK(nr); + volatile bitop_uint_t *p = (volatile bitop_uint_t *)addr + BITOP_WORD(nr); + bitop_uint_t old = *p; + + *p = old | mask; + return (old & mask); +} + +/** + * generic__test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +generic__test_and_clear_bit(int nr, volatile void *addr) +{ + bitop_uint_t mask = BITOP_MASK(nr); + volatile bitop_uint_t *p = (volatile bitop_uint_t *)addr + BITOP_WORD(nr); + bitop_uint_t old = *p; + + *p = old & ~mask; + return (old & mask); +} + +/** + * generic__test_and_change_bit - Change a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +generic__test_and_change_bit(int nr, volatile void *addr) +{ + bitop_uint_t mask = BITOP_MASK(nr); + volatile bitop_uint_t *p = (volatile bitop_uint_t *)addr + BITOP_WORD(nr); + bitop_uint_t old = *p; + + *p = old ^ mask; + return (old & mask); +} + +/** + * generic_test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool generic_test_bit(int nr, const volatile void *addr) +{ + bitop_uint_t mask = BITOP_MASK(nr); + const volatile bitop_uint_t *p = + (const volatile bitop_uint_t *)addr + BITOP_WORD(nr); + + return (*p & mask); +} + +/** + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +__test_and_set_bit(int nr, volatile void *addr) +{ +#ifndef arch__test_and_set_bit +#define arch__test_and_set_bit generic__test_and_set_bit +#endif + + return arch__test_and_set_bit(nr, addr); +} +#define __test_and_set_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + __test_and_set_bit(nr, addr); \ +}) + +/** + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +__test_and_clear_bit(int nr, volatile void *addr) +{ +#ifndef arch__test_and_clear_bit +#define arch__test_and_clear_bit generic__test_and_clear_bit +#endif + + return arch__test_and_clear_bit(nr, addr); +} +#define __test_and_clear_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + __test_and_clear_bit(nr, addr); \ +}) + +/** + * __test_and_change_bit - Change a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +__test_and_change_bit(int nr, volatile void *addr) +{ +#ifndef arch__test_and_change_bit +#define arch__test_and_change_bit generic__test_and_change_bit +#endif + + return arch__test_and_change_bit(nr, addr); +} +#define __test_and_change_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + __test_and_change_bit(nr, addr); \ +}) + +/** + * test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool test_bit(int nr, const volatile void *addr) +{ +#ifndef arch_test_bit +#define arch_test_bit generic_test_bit +#endif + + return arch_test_bit(nr, addr); +} +#define test_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + test_bit(nr, addr); \ +}) + #ifndef find_next_bit /** * find_next_bit - find the next set bit in a memory region From patchwork Fri May 24 11:08:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13673086 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1F094C25B74 for ; Fri, 24 May 2024 11:09:15 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.729359.1134517 (Exim 4.92) (envelope-from ) id 1sASnJ-0003nF-MW; Fri, 24 May 2024 11:09:05 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 729359.1134517; Fri, 24 May 2024 11:09:05 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sASnJ-0003li-Gw; Fri, 24 May 2024 11:09:05 +0000 Received: by outflank-mailman (input) for mailman id 729359; Fri, 24 May 2024 11:09:03 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sASnH-0003Cz-RW for xen-devel@lists.xenproject.org; Fri, 24 May 2024 11:09:03 +0000 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [2a00:1450:4864:20::636]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 06b269ad-19be-11ef-b4bb-af5377834399; Fri, 24 May 2024 13:09:02 +0200 (CEST) Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-a62769075adso51717966b.3 for ; Fri, 24 May 2024 04:09:02 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a626c817c81sm116051366b.28.2024.05.24.04.08.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 04:09:00 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 06b269ad-19be-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716548941; x=1717153741; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yd/DGVLnKJ3GtywGuSmeUy0gbzAiv6eqVrDkcFb+xAQ=; b=LmQszo4JSC5P2geKR+tI6RLKfJcUH3JqyXSvybyZh1EF5p3ayn0krV9eSpZ78A3rw+ lPQtx9TyhhtY9h2VVv7zEOMGz2cXkBKqfBbPsTGoHUj3DriyyEjZwfFVyYWrok+6bRMz ryRsfw2LJ9qcE07vipfZaIkJMcoMBJJOXjweDS5oUciUqLwDF1fEY0C5oOxprBqf1mp2 GQSxpllKaRxEU3DusEP02oW/yb8y6PdctUAZO05w0K1XKhaPtd8jAK+9UEw+xKbRIrId c7mMCzXwiCywzzwd5S5BjVFpqLKZJOmCyJwnee138Qk3D/B05B62tzAv5hLr/VUhjHCV lYKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716548941; x=1717153741; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yd/DGVLnKJ3GtywGuSmeUy0gbzAiv6eqVrDkcFb+xAQ=; b=DldyTDxGlYw5qYAbaaYaOqWyWNAsJuTL+5a/zVDOYp/MeTPXB3inIcyAA1ekHE+RwF xU0WSQWLviXfKusgv6Kh/BIgFzJGaj97TlUbFUK2+WHgr1wTKk49PySEZTtiyNZliEAU lltPaVJ64yEXeyA2RqPi6IsCyd+d60P8Aij4/Gq2es3W+awkSv/7V0uwqMQ2XzZ9FXtM G5GhBM3/F0fkZ/DCPrdoakA6Yh3+YQZu2UqDpTMtVPRXLSE+trP7aaboPF6eGcbYkDk4 b4AK7e86hvrGSFvIdU8Ba2J5KmkGTD1JODC0Zk5T4t4kzM031WZ/Kee8I5n5JviSJmkK 4xWw== X-Gm-Message-State: AOJu0YxXanfNmUc6gKQWmPhdFcPFOMDzDzUpbPFTgIXVLYm7cF6tTU70 kNy7eDY+vnOAE2ZmHt1Jy8P58w9Y9/5bVu+WhljhdATV+Ye70m7Fzy+ngnVH X-Google-Smtp-Source: AGHT+IHhqAZDjBHBhgoru8Yb8g2qsIBr02+0uTRek59eZRvOMQ4xA+qVHiPyAFEp4ebYGzazT1zCCg== X-Received: by 2002:a17:906:4f01:b0:a59:b784:ced4 with SMTP id a640c23a62f3a-a6265118800mr123826166b.75.1716548940991; Fri, 24 May 2024 04:09:00 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , George Dunlap , Jan Beulich , Shawn Anastasio , =?utf-8?q?Roger_Pau_Mon?= =?utf-8?q?n=C3=A9?= Subject: [PATCH v11 3/9] xen/bitops: implement fls{l}() in common logic Date: Fri, 24 May 2024 13:08:49 +0200 Message-ID: X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 To avoid the compilation error below, it is needed to update to places in common/page_alloc.c where flsl() is used as now flsl() returns unsigned int: ./include/xen/kernel.h:18:21: error: comparison of distinct pointer types lacks a cast [-Werror] 18 | (void) (&_x == &_y); \ | ^~ common/page_alloc.c:1843:34: note: in expansion of macro 'min' 1843 | unsigned int inc_order = min(MAX_ORDER, flsl(e - s) - 1); generic_fls{l} was used instead of __builtin_clz{l}(x) as if x is 0, the result in undefined. The prototype of the per-architecture fls{l}() functions was changed to return 'unsigned int' to align with the generic implementation of these functions and avoid introducing signed/unsigned mismatches. Signed-off-by: Oleksii Kurochko --- The current one patch can be merged w/o waiting of Andrew's patch series. Andrew C. could you please consider the following patch to be as a part of your bit operation patch series if your patch series will be in staging before mine: https://gitlab.com/xen-project/people/olkur/xen/-/commit/24a346c7aa4f51ba34eacb7bfee2808e431daf00 Thanks in advance. --- Changes in V11: - drop unnessary case and fix code style for x86's arch_flsl() - rebase on top of staging, so it can be merged to staging if necessary apporves will be given - move changes related to fls related function to separate patch on top of Andrew's patch series as the C file with tests is introduced in his patch series. The patch is mentioned in footer. --- Changes in V10: - update return type of arch_flsl() across arcitectures to 'unsigned int' to be aligned with return type of generic flsl() in xen/bitops.h. - switch inline to always_inline for arch_flsl() across architectures to be in sync with other similar changes. - define arch_flsl as arch_fls not just only fls. - update the commit message ( add information that per-arch fls{l)() protypes were changed ). --- Changes in V9: - update return type of fls and flsl() to unsigned int to be aligned with other bit ops. - update places where return value of fls() and flsl() is compared with int. - update the commit message. --- Changes in V8: - do proper rebase: back definition of fls{l} to the current patch. - drop the changes which removed ffz() in PPC. it should be done not in this patch. - add a message after Signed-off. --- Changes in V7: - Code style fixes --- Changes in V6: - new patch for the patch series. --- xen/arch/arm/include/asm/arm32/bitops.h | 2 +- xen/arch/arm/include/asm/arm64/bitops.h | 6 ++---- xen/arch/arm/include/asm/bitops.h | 9 +++------ xen/arch/ppc/include/asm/bitops.h | 2 -- xen/arch/x86/include/asm/bitops.h | 12 +++++++----- xen/common/page_alloc.c | 4 ++-- xen/include/xen/bitops.h | 24 ++++++++++++++++++++++++ 7 files changed, 39 insertions(+), 20 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/bitops.h b/xen/arch/arm/include/asm/arm32/bitops.h index d0309d47c1..9ee96f568b 100644 --- a/xen/arch/arm/include/asm/arm32/bitops.h +++ b/xen/arch/arm/include/asm/arm32/bitops.h @@ -1,7 +1,7 @@ #ifndef _ARM_ARM32_BITOPS_H #define _ARM_ARM32_BITOPS_H -#define flsl fls +#define arch_flsl arch_fls /* * Little endian assembly bitops. nr = 0 -> byte 0 bit 0. diff --git a/xen/arch/arm/include/asm/arm64/bitops.h b/xen/arch/arm/include/asm/arm64/bitops.h index 906d84e5f2..d942077392 100644 --- a/xen/arch/arm/include/asm/arm64/bitops.h +++ b/xen/arch/arm/include/asm/arm64/bitops.h @@ -1,17 +1,15 @@ #ifndef _ARM_ARM64_BITOPS_H #define _ARM_ARM64_BITOPS_H -static inline int flsl(unsigned long x) +static always_inline unsigned int arch_flsl(unsigned long x) { uint64_t ret; - if (__builtin_constant_p(x)) - return generic_flsl(x); - asm("clz\t%0, %1" : "=r" (ret) : "r" (x)); return BITS_PER_LONG - ret; } +#define arch_flsl arch_flsl /* Based on linux/include/asm-generic/bitops/find.h */ diff --git a/xen/arch/arm/include/asm/bitops.h b/xen/arch/arm/include/asm/bitops.h index af38fbffdd..52fd33a797 100644 --- a/xen/arch/arm/include/asm/bitops.h +++ b/xen/arch/arm/include/asm/bitops.h @@ -76,17 +76,14 @@ bool clear_mask16_timeout(uint16_t mask, volatile void *p, * the clz instruction for much better code efficiency. */ -static inline int fls(unsigned int x) +static always_inline unsigned int arch_fls(unsigned int x) { - int ret; - - if (__builtin_constant_p(x)) - return generic_fls(x); + unsigned int ret; asm("clz\t%"__OP32"0, %"__OP32"1" : "=r" (ret) : "r" (x)); return 32 - ret; } - +#define arch_fls arch_fls #define ffs(x) ({ unsigned int __t = (x); fls(ISOLATE_LSB(__t)); }) #define ffsl(x) ({ unsigned long __t = (x); flsl(ISOLATE_LSB(__t)); }) diff --git a/xen/arch/ppc/include/asm/bitops.h b/xen/arch/ppc/include/asm/bitops.h index 71bbb5f16a..82f9d92c7a 100644 --- a/xen/arch/ppc/include/asm/bitops.h +++ b/xen/arch/ppc/include/asm/bitops.h @@ -117,8 +117,6 @@ static inline int test_and_set_bit(unsigned int nr, volatile void *addr) (volatile unsigned int *)addr + BITOP_WORD(nr)) != 0; } -#define flsl(x) generic_flsl(x) -#define fls(x) generic_fls(x) #define ffs(x) ({ unsigned int t_ = (x); fls(t_ & -t_); }) #define ffsl(x) ({ unsigned long t_ = (x); flsl(t_ & -t_); }) diff --git a/xen/arch/x86/include/asm/bitops.h b/xen/arch/x86/include/asm/bitops.h index c4e7a06155..e488b39728 100644 --- a/xen/arch/x86/include/asm/bitops.h +++ b/xen/arch/x86/include/asm/bitops.h @@ -434,20 +434,21 @@ static inline int ffs(unsigned int x) * * This is defined the same way as ffs. */ -static inline int flsl(unsigned long x) +static always_inline unsigned int arch_flsl(unsigned long x) { - long r; + unsigned long r; asm ( "bsr %1,%0\n\t" "jnz 1f\n\t" "mov $-1,%0\n" "1:" : "=r" (r) : "rm" (x)); - return (int)r+1; + return r + 1; } +#define arch_flsl arch_flsl -static inline int fls(unsigned int x) +static always_inline unsigned int arch_fls(unsigned int x) { - int r; + unsigned int r; asm ( "bsr %1,%0\n\t" "jnz 1f\n\t" @@ -455,6 +456,7 @@ static inline int fls(unsigned int x) "1:" : "=r" (r) : "rm" (x)); return r + 1; } +#define arch_fls arch_fls /** * hweightN - returns the hamming weight of a N-bit word diff --git a/xen/common/page_alloc.c b/xen/common/page_alloc.c index 7c1bdfc046..d4d05d02b7 100644 --- a/xen/common/page_alloc.c +++ b/xen/common/page_alloc.c @@ -1842,7 +1842,7 @@ static void _init_heap_pages(const struct page_info *pg, * Note that the value of ffsl() and flsl() starts from 1 so we need * to decrement it by 1. */ - unsigned int inc_order = min(MAX_ORDER, flsl(e - s) - 1); + unsigned int inc_order = min(MAX_ORDER + 0U, flsl(e - s) - 1); if ( s ) inc_order = min(inc_order, ffsl(s) - 1U); @@ -2266,7 +2266,7 @@ void __init xenheap_max_mfn(unsigned long mfn) ASSERT(!first_node_initialised); ASSERT(!xenheap_bits); BUILD_BUG_ON((PADDR_BITS - PAGE_SHIFT) >= BITS_PER_LONG); - xenheap_bits = min(flsl(mfn + 1) - 1 + PAGE_SHIFT, PADDR_BITS); + xenheap_bits = min(flsl(mfn + 1) - 1 + PAGE_SHIFT, PADDR_BITS + 0U); printk(XENLOG_INFO "Xen heap: %u bits\n", xenheap_bits); } diff --git a/xen/include/xen/bitops.h b/xen/include/xen/bitops.h index 9f89232ba6..c98eb827e3 100644 --- a/xen/include/xen/bitops.h +++ b/xen/include/xen/bitops.h @@ -290,6 +290,30 @@ static always_inline bool test_bit(int nr, const volatile void *addr) test_bit(nr, addr); \ }) +static always_inline __pure unsigned int fls(unsigned int x) +{ + if ( __builtin_constant_p(x) ) + return generic_fls(x); + +#ifndef arch_fls +#define arch_fls generic_fls +#endif + + return arch_fls(x); +} + +static always_inline __pure unsigned int flsl(unsigned long x) +{ + if ( __builtin_constant_p(x) ) + return generic_flsl(x); + +#ifndef arch_flsl +#define arch_flsl generic_flsl +#endif + + return arch_flsl(x); +} + #ifndef find_next_bit /** * find_next_bit - find the next set bit in a memory region From patchwork Fri May 24 11:08:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13673085 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B55C6C25B79 for ; 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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a626c817c81sm116051366b.28.2024.05.24.04.09.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 04:09:01 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 07469569-19be-11ef-90a1-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716548942; x=1717153742; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7d2EqxK4VlcyZgrHG2d9Y7mDD/1pyOMs5CW5hdSjjiU=; b=glSE4kwn5qEQxFFXIbJUWaxkiOqug39gdIUW8yMlimFqG3+LV/oQpGWW8hiYLWDyML 6WR/nGySJF9CL3DxNQ8/ZItewsk0kXchapcovvLn/DW8dU8g/AcHM08YIkaIuDIS+0ki MHHHnuPJhpImhlak8fSvs3eZfV4cTLIhneclhLiJ6ATsLRwdl9B7yRjzbWc6vPRa616J XoZjLsZFF0o5HAsyhOtKWeqagTQba1Kx2JpmEgS01v7f6VD3kLA1/ZimP9P2ccMuzXRr +QqAteghF0QwramrAzEmftS47GeP8arRFp71hu3gk6ZN2NLeiqzNsUr+ax/0ddoeaFq1 mlzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716548942; x=1717153742; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7d2EqxK4VlcyZgrHG2d9Y7mDD/1pyOMs5CW5hdSjjiU=; b=QxKWkHbyqon0e/46TRhm6mkp3BAQeMlpGURe3KbhO5V4WJmxWuEcspsblJo3gevmMe zNjtPXttimcjQqeAKUchLsPh0cE1KSCNFopy51msM0eIdbezIoypXMQtTI717dP5q7Xz suXotDRFIEzqhFv77w1VFLgk+PX+aGnbFLDiBWvOpiOKZgo8m+aZ1ZTYge11bU6I1mLP B80QBHAt3bDUivLxiVuQhx+w6wnP7hTPmg57oJukm7mMaWFZ94iciTYyy9tTRGQDEFRK xjr1lqKGbPRGqQH98wHkG3enhDgHOygQxvjLMI3rwcCrpjPi+lE/wtUvCoZW0njqJRjL ZTPA== X-Gm-Message-State: AOJu0YzABATIiHnYNFPFvl7UFUUwOGQLRVw0LiMfrSTZJm9NI3NFpAF4 5z5k2eE4F6EKkpPdHFBDU6OcKadM4OSSA3kQk1TmEvqR0Do/JecVYoVDri2p X-Google-Smtp-Source: AGHT+IFYmUG+cdFWEbzCaV2+43OdHFBaS5Oay+qaniUbOIU4fOv63gV5vPi3OV9HxRioNeHsSaDeCw== X-Received: by 2002:a17:906:19cf:b0:a59:b342:3ed5 with SMTP id a640c23a62f3a-a62641b5482mr128417666b.15.1716548942063; Fri, 24 May 2024 04:09:02 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v11 4/9] xen/riscv: introduce bitops.h Date: Fri, 24 May 2024 13:08:50 +0200 Message-ID: <154d59893ac84668f73690fbf94898b2ce0710a4.1716547693.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Taken from Linux-6.4.0-rc1 Xen's bitops.h consists of several Linux's headers: * linux/arch/include/asm/bitops.h: * The following function were removed as they aren't used in Xen: * test_and_set_bit_lock * clear_bit_unlock * __clear_bit_unlock * The following functions were renamed in the way how they are used by common code: * __test_and_set_bit * __test_and_clear_bit * The declaration and implementation of the following functios were updated to make Xen build happy: * clear_bit * set_bit * __test_and_clear_bit * __test_and_set_bit Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V11: - Nothing changed. Only rebase was done. --- Changes in V10: - update the error message BITS_PER_LONG -> BITOP_BITS_PER_WORD --- Changes in V9: - add Acked-by: Jan Beulich - drop redefinition of bitop_uint_t in asm/types.h as some operation in Xen common code expects to work with 32-bit quantities. - s/BITS_PER_LONG/BITOP_BITS_PER_WORD in asm/bitops.h around __AMO() macros. --- Changes in V8: - define bitop_uint_t in after the changes in patch related to introduction of "introduce generic non-atomic test_*bit()". - drop duplicated __set_bit() and __clear_bit(). - drop duplicated comment: /* Based on linux/arch/include/asm/bitops.h */. - update type of res and mask in test_and_op_bit_ord(): unsigned long -> bitop_uint_t. - drop 1 padding blank in test_and_op_bit_ord(). - update definition of test_and_set_bit(),test_and_clear_bit(),test_and_change_bit: change return type to bool. - change addr argument type of test_and_change_bit(): unsigned long * -> void *. - move test_and_change_bit() closer to other test_and-s function. - Code style fixes: tabs -> space. - s/#undef __op_bit/#undef op_bit. - update the commit message: delete information about generic-non-atomic.h changes as now it is a separate patch. --- Changes in V7: - Update the commit message. - Drop "__" for __op_bit and __op_bit_ord as they are atomic. - add comment above __set_bit and __clear_bit about why they are defined as atomic. - align bitops_uint_t with __AMO(). - make changes after generic non-atomic test_*bit() were changed. - s/__asm__ __volatile__/asm volatile --- Changes in V6: - rebase clean ups were done: drop unused asm-generic includes --- Changes in V5: - new patch --- xen/arch/riscv/include/asm/bitops.h | 137 ++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) create mode 100644 xen/arch/riscv/include/asm/bitops.h diff --git a/xen/arch/riscv/include/asm/bitops.h b/xen/arch/riscv/include/asm/bitops.h new file mode 100644 index 0000000000..7f7af3fda1 --- /dev/null +++ b/xen/arch/riscv/include/asm/bitops.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2012 Regents of the University of California */ + +#ifndef _ASM_RISCV_BITOPS_H +#define _ASM_RISCV_BITOPS_H + +#include + +#if BITOP_BITS_PER_WORD == 64 +#define __AMO(op) "amo" #op ".d" +#elif BITOP_BITS_PER_WORD == 32 +#define __AMO(op) "amo" #op ".w" +#else +#error "Unexpected BITOP_BITS_PER_WORD" +#endif + +/* Based on linux/arch/include/asm/bitops.h */ + +/* + * Non-atomic bit manipulation. + * + * Implemented using atomics to be interrupt safe. Could alternatively + * implement with local interrupt masking. + */ +#define __set_bit(n, p) set_bit(n, p) +#define __clear_bit(n, p) clear_bit(n, p) + +#define test_and_op_bit_ord(op, mod, nr, addr, ord) \ +({ \ + bitop_uint_t res, mask; \ + mask = BITOP_MASK(nr); \ + asm volatile ( \ + __AMO(op) #ord " %0, %2, %1" \ + : "=r" (res), "+A" (addr[BITOP_WORD(nr)]) \ + : "r" (mod(mask)) \ + : "memory"); \ + ((res & mask) != 0); \ +}) + +#define op_bit_ord(op, mod, nr, addr, ord) \ + asm volatile ( \ + __AMO(op) #ord " zero, %1, %0" \ + : "+A" (addr[BITOP_WORD(nr)]) \ + : "r" (mod(BITOP_MASK(nr))) \ + : "memory"); + +#define test_and_op_bit(op, mod, nr, addr) \ + test_and_op_bit_ord(op, mod, nr, addr, .aqrl) +#define op_bit(op, mod, nr, addr) \ + op_bit_ord(op, mod, nr, addr, ) + +/* Bitmask modifiers */ +#define NOP(x) (x) +#define NOT(x) (~(x)) + +/** + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + */ +static inline bool test_and_set_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr = p; + + return test_and_op_bit(or, NOP, nr, addr); +} + +/** + * test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + */ +static inline bool test_and_clear_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr = p; + + return test_and_op_bit(and, NOT, nr, addr); +} + +/** + * test_and_change_bit - Toggle (change) a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +static inline bool test_and_change_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr = p; + + return test_and_op_bit(xor, NOP, nr, addr); +} + +/** + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void set_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr = p; + + op_bit(or, NOP, nr, addr); +} + +/** + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + */ +static inline void clear_bit(int nr, volatile void *p) +{ + volatile bitop_uint_t *addr = p; + + op_bit(and, NOT, nr, addr); +} + +#undef test_and_op_bit +#undef op_bit +#undef NOP +#undef NOT +#undef __AMO + +#endif /* _ASM_RISCV_BITOPS_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Fri May 24 11:08:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13673087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 317DCC25B7C for ; Fri, 24 May 2024 11:09:15 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.729360.1134524 (Exim 4.92) (envelope-from ) id 1sASnK-0003wU-69; Fri, 24 May 2024 11:09:06 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 729360.1134524; Fri, 24 May 2024 11:09:06 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sASnJ-0003vl-UV; Fri, 24 May 2024 11:09:05 +0000 Received: by outflank-mailman (input) for mailman id 729360; Fri, 24 May 2024 11:09:04 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sASnI-0003D0-Nx for xen-devel@lists.xenproject.org; Fri, 24 May 2024 11:09:04 +0000 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [2a00:1450:4864:20::632]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 07e29255-19be-11ef-90a1-e314d9c70b13; Fri, 24 May 2024 13:09:04 +0200 (CEST) Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-a62614b9ae1so102337066b.0 for ; Fri, 24 May 2024 04:09:04 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a626c817c81sm116051366b.28.2024.05.24.04.09.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 04:09:02 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 07e29255-19be-11ef-90a1-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716548943; x=1717153743; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GUAxAxl17Un/j2tMvIXlYjzldu2txD+7ziiQaQEA83I=; b=hYJP88TGNRM52W25def6gIE/lefzt0O6evaSDhD9VMT2hsWtzKrUtJUn4ttvFEyBx1 pc5U98BYIeDlUMvgMAQSDm6OiPURDbP3ed9YhKjH4yl5pLaiVPzuvTk2EZosNGBbZvf/ 1X5tEkiEZV5UlD8bnGJiloE9lrKV+cqkHytOTdhlzvio9HTBSn8pGlNpkM2T7aqjV6B8 uXBAOL/ddK933N9o+QEy9fwYSKcJ0SOmuUQzznbyZwivhBk1asUVVqLXvJUVVpBTZSbR +wpn4wV0u8Tj4Ifj9KFMqYsVgExXqpYXkhvYDma48JZDzWtiiVHbuUzhKO2AktVi2WGA MhXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716548943; x=1717153743; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GUAxAxl17Un/j2tMvIXlYjzldu2txD+7ziiQaQEA83I=; b=GdlTraNMOIL9OxYHHs/hLLVNnTBVTqxh84pNhW+BUES9t9KEhVyhXNpb8cz/zg1tO0 xphWwjtfeJRXJ+TttcCxnRpr+2UF3Mw8DGjKbH+inq/ulTdWDj1GMlIXj0wrhIXKv1ax MHcCh0N2Zxj7PKf/CJoEM0ZFLOIrXXUZZs+BjO+FUXHPmFy75LTaoUYayZ3pdc72Rth5 WIkk+diRpJMyv65cDsUKBEFtLv2DzmM6skcepscXmZoQb/w/jA0CeJd2okhcTqbL3VLq yBQ6oNTd4suW/IqjFe0ATfiZuerbzGXQwiILjgaHSGTtf+4YSotT8NO7ZtJvzPUvlhs+ wKcQ== X-Gm-Message-State: AOJu0YxacdgaFa8KAMFfIJurnOy+xD8w+3zCGkPVEq7Hn1gm+8av7NS4 q7u6LJkhg0Oak71foC2sPWWEd23ZWlwqVb8aWZX5FxOcssUo+MnCsmNMnM1A X-Google-Smtp-Source: AGHT+IHE/a5m9fzX2m1slVE057V0x6OasQt0uN7p/KQTRS+O+SESh703FTrh7+fom4J4NszhaHKe5g== X-Received: by 2002:a17:906:b21a:b0:a61:9877:a26b with SMTP id a640c23a62f3a-a62647cdcf1mr113951166b.43.1716548943237; Fri, 24 May 2024 04:09:03 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v11 5/9] xen/riscv: add definition of __read_mostly Date: Fri, 24 May 2024 13:08:51 +0200 Message-ID: <09d5f6bdd3bbd8fe1f97317009ee6d0d0fc7dd39.1716547693.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 The definition of __read_mostly should be removed in: https://lore.kernel.org/xen-devel/f25eb5c9-7c14-6e23-8535-2c66772b333e@suse.com/ The patch introduces it in arch-specific header to not block enabling of full Xen build for RISC-V. Signed-off-by: Oleksii Kurochko --- - [PATCH] move __read_mostly to xen/cache.h [2] Right now, the patch series doesn't have a direct dependency on [2] and it provides __read_mostly in the patch: [PATCH v3 26/34] xen/riscv: add definition of __read_mostly However, it will be dropped as soon as [2] is merged or at least when the final version of the patch [2] is provided. Considering that there is still no still final decision regarding patch [2] my suggestion is to merge RISC-V specific patch and just drop the changes in patch [2]. [2] https://lore.kernel.org/xen-devel/f25eb5c9-7c14-6e23-8535-2c66772b333e@suse.com/ --- Changes in V9-V11: - Only rebase was done. --- Change in V8: - update the footer after Signed-off. --- Changes in V4-V7: - Nothing changed. Only rebase. --- xen/arch/riscv/include/asm/cache.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/riscv/include/asm/cache.h b/xen/arch/riscv/include/asm/cache.h index 69573eb051..94bd94db53 100644 --- a/xen/arch/riscv/include/asm/cache.h +++ b/xen/arch/riscv/include/asm/cache.h @@ -3,4 +3,6 @@ #ifndef _ASM_RISCV_CACHE_H #define _ASM_RISCV_CACHE_H +#define __read_mostly __section(".data.read_mostly") + #endif /* _ASM_RISCV_CACHE_H */ From patchwork Fri May 24 11:08:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13673088 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59BCDC41513 for ; Fri, 24 May 2024 11:09:15 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.729361.1134547 (Exim 4.92) (envelope-from ) id 1sASnM-0004id-FF; Fri, 24 May 2024 11:09:08 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 729361.1134547; Fri, 24 May 2024 11:09:08 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sASnM-0004iT-Bq; Fri, 24 May 2024 11:09:08 +0000 Received: by outflank-mailman (input) for mailman id 729361; Fri, 24 May 2024 11:09:07 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sASnL-0003Cz-Bc for xen-devel@lists.xenproject.org; Fri, 24 May 2024 11:09:07 +0000 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [2a00:1450:4864:20::630]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 08c59efb-19be-11ef-b4bb-af5377834399; Fri, 24 May 2024 13:09:05 +0200 (CEST) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-a59cc765c29so346715766b.3 for ; Fri, 24 May 2024 04:09:05 -0700 (PDT) Received: from fedora.. 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Fri, 24 May 2024 04:09:04 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v11 6/9] xen/riscv: add minimal stuff to mm.h to build full Xen Date: Fri, 24 May 2024 13:08:52 +0200 Message-ID: <55506cc9a19615a6f25b4b989c739a894b308968.1716547693.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V8-V11: - Nothing changed only rebase. --- Changes in V7: - update argument type of maddr_to_virt() function: unsigned long -> paddr_t - rename argument of PFN_ORDER(): pfn -> pg. - add Acked-by: Jan Beulich --- Changes in V6: - drop __virt_to_maddr() ( transform to macro ) and __maddr_to_virt ( rename to maddr_to_virt ). - parenthesize va in definition of vmap_to_mfn(). - Code style fixes. --- Changes in V5: - update the comment around "struct domain *domain;" : zero -> NULL - fix ident. for unsigned long val; - put page_to_virt() and virt_to_page() close to each other. - drop unnessary leading underscore - drop a space before the comment: /* Count of uses of this frame as its current type. */ - drop comment about a page 'not as a shadow'. it is not necessary for RISC-V --- Changes in V4: - update an argument name of PFN_ORDERN macros. - drop pad at the end of 'struct page_info'. - Change message -> subject in "Changes in V3" - delete duplicated macros from riscv/mm.h - fix identation in struct page_info - align comment for PGC_ macros - update definitions of domain_set_alloc_bitsize() and domain_clamp_alloc_bitsize() - drop unnessary comments. - s/BUG/BUG_ON("...") - define __virt_to_maddr, __maddr_to_virt as stubs - add inclusion of xen/mm-frame.h for mfn_x and others - include "xen/mm.h" instead of "asm/mm.h" to fix compilation issues: In file included from arch/riscv/setup.c:7: ./arch/riscv/include/asm/mm.h:60:28: error: field 'list' has incomplete type 60 | struct page_list_entry list; | ^~~~ ./arch/riscv/include/asm/mm.h:81:43: error: 'MAX_ORDER' undeclared here (not in a function) 81 | unsigned long first_dirty:MAX_ORDER + 1; | ^~~~~~~~~ ./arch/riscv/include/asm/mm.h:81:31: error: bit-field 'first_dirty' width not an integer constant 81 | unsigned long first_dirty:MAX_ORDER + 1; - Define __virt_to_mfn() and __mfn_to_virt() using maddr_to_mfn() and mfn_to_maddr(). --- Changes in V3: - update the commit title - introduce DIRECTMAP_VIRT_START. - drop changes related pfn_to_paddr() and paddr_to_pfn as they were remvoe in [PATCH v2 32/39] xen/riscv: add minimal stuff to asm/page.h to build full Xen - code style fixes. - drop get_page_nr and put_page_nr as they don't need for time being - drop CONFIG_STATIC_MEMORY related things - code style fixes --- Changes in V2: - define stub for arch_get_dma_bitsize(void) --- xen/arch/riscv/include/asm/mm.h | 240 ++++++++++++++++++++++++++++++++ xen/arch/riscv/mm.c | 2 +- xen/arch/riscv/setup.c | 2 +- 3 files changed, 242 insertions(+), 2 deletions(-) diff --git a/xen/arch/riscv/include/asm/mm.h b/xen/arch/riscv/include/asm/mm.h index 07c7a0abba..cc4a07a71c 100644 --- a/xen/arch/riscv/include/asm/mm.h +++ b/xen/arch/riscv/include/asm/mm.h @@ -3,11 +3,246 @@ #ifndef _ASM_RISCV_MM_H #define _ASM_RISCV_MM_H +#include +#include +#include +#include +#include + #include #define pfn_to_paddr(pfn) ((paddr_t)(pfn) << PAGE_SHIFT) #define paddr_to_pfn(pa) ((unsigned long)((pa) >> PAGE_SHIFT)) +#define paddr_to_pdx(pa) mfn_to_pdx(maddr_to_mfn(pa)) +#define gfn_to_gaddr(gfn) pfn_to_paddr(gfn_x(gfn)) +#define gaddr_to_gfn(ga) _gfn(paddr_to_pfn(ga)) +#define mfn_to_maddr(mfn) pfn_to_paddr(mfn_x(mfn)) +#define maddr_to_mfn(ma) _mfn(paddr_to_pfn(ma)) +#define vmap_to_mfn(va) maddr_to_mfn(virt_to_maddr((vaddr_t)(va))) +#define vmap_to_page(va) mfn_to_page(vmap_to_mfn(va)) + +static inline void *maddr_to_virt(paddr_t ma) +{ + BUG_ON("unimplemented"); + return NULL; +} + +#define virt_to_maddr(va) ({ BUG_ON("unimplemented"); 0; }) + +/* Convert between Xen-heap virtual addresses and machine frame numbers. */ +#define __virt_to_mfn(va) mfn_x(maddr_to_mfn(virt_to_maddr(va))) +#define __mfn_to_virt(mfn) maddr_to_virt(mfn_to_maddr(_mfn(mfn))) + +/* + * We define non-underscored wrappers for above conversion functions. + * These are overriden in various source files while underscored version + * remain intact. + */ +#define virt_to_mfn(va) __virt_to_mfn(va) +#define mfn_to_virt(mfn) __mfn_to_virt(mfn) + +struct page_info +{ + /* Each frame can be threaded onto a doubly-linked list. */ + struct page_list_entry list; + + /* Reference count and various PGC_xxx flags and fields. */ + unsigned long count_info; + + /* Context-dependent fields follow... */ + union { + /* Page is in use: ((count_info & PGC_count_mask) != 0). */ + struct { + /* Type reference count and various PGT_xxx flags and fields. */ + unsigned long type_info; + } inuse; + + /* Page is on a free list: ((count_info & PGC_count_mask) == 0). */ + union { + struct { + /* + * Index of the first *possibly* unscrubbed page in the buddy. + * One more bit than maximum possible order to accommodate + * INVALID_DIRTY_IDX. + */ +#define INVALID_DIRTY_IDX ((1UL << (MAX_ORDER + 1)) - 1) + unsigned long first_dirty:MAX_ORDER + 1; + + /* Do TLBs need flushing for safety before next page use? */ + bool need_tlbflush:1; + +#define BUDDY_NOT_SCRUBBING 0 +#define BUDDY_SCRUBBING 1 +#define BUDDY_SCRUB_ABORT 2 + unsigned long scrub_state:2; + }; + + unsigned long val; + } free; + } u; + + union { + /* Page is in use */ + struct { + /* Owner of this page (NULL if page is anonymous). */ + struct domain *domain; + } inuse; + + /* Page is on a free list. */ + struct { + /* Order-size of the free chunk this page is the head of. */ + unsigned int order; + } free; + } v; + + union { + /* + * Timestamp from 'TLB clock', used to avoid extra safety flushes. + * Only valid for: a) free pages, and b) pages with zero type count + */ + uint32_t tlbflush_timestamp; + }; +}; + +#define frame_table ((struct page_info *)FRAMETABLE_VIRT_START) + +/* PDX of the first page in the frame table. */ +extern unsigned long frametable_base_pdx; + +/* Convert between machine frame numbers and page-info structures. */ +#define mfn_to_page(mfn) \ + (frame_table + (mfn_to_pdx(mfn) - frametable_base_pdx)) +#define page_to_mfn(pg) \ + pdx_to_mfn((unsigned long)((pg) - frame_table) + frametable_base_pdx) + +static inline void *page_to_virt(const struct page_info *pg) +{ + return mfn_to_virt(mfn_x(page_to_mfn(pg))); +} + +/* Convert between Xen-heap virtual addresses and page-info structures. */ +static inline struct page_info *virt_to_page(const void *v) +{ + BUG_ON("unimplemented"); + return NULL; +} + +/* + * Common code requires get_page_type and put_page_type. + * We don't care about typecounts so we just do the minimum to make it + * happy. + */ +static inline int get_page_type(struct page_info *page, unsigned long type) +{ + return 1; +} + +static inline void put_page_type(struct page_info *page) +{ +} + +static inline void put_page_and_type(struct page_info *page) +{ + put_page_type(page); + put_page(page); +} + +/* + * RISC-V does not have an M2P, but common code expects a handful of + * M2P-related defines and functions. Provide dummy versions of these. + */ +#define INVALID_M2P_ENTRY (~0UL) +#define SHARED_M2P_ENTRY (~0UL - 1UL) +#define SHARED_M2P(_e) ((_e) == SHARED_M2P_ENTRY) + +#define set_gpfn_from_mfn(mfn, pfn) do { (void)(mfn), (void)(pfn); } while (0) +#define mfn_to_gfn(d, mfn) ((void)(d), _gfn(mfn_x(mfn))) + +#define PDX_GROUP_SHIFT (PAGE_SHIFT + VPN_BITS) + +static inline unsigned long domain_get_maximum_gpfn(struct domain *d) +{ + BUG_ON("unimplemented"); + return 0; +} + +static inline long arch_memory_op(int op, XEN_GUEST_HANDLE_PARAM(void) arg) +{ + BUG_ON("unimplemented"); + return 0; +} + +/* + * On RISCV, all the RAM is currently direct mapped in Xen. + * Hence return always true. + */ +static inline bool arch_mfns_in_directmap(unsigned long mfn, unsigned long nr) +{ + return true; +} + +#define PG_shift(idx) (BITS_PER_LONG - (idx)) +#define PG_mask(x, idx) (x ## UL << PG_shift(idx)) + +#define PGT_none PG_mask(0, 1) /* no special uses of this page */ +#define PGT_writable_page PG_mask(1, 1) /* has writable mappings? */ +#define PGT_type_mask PG_mask(1, 1) /* Bits 31 or 63. */ + +/* Count of uses of this frame as its current type. */ +#define PGT_count_width PG_shift(2) +#define PGT_count_mask ((1UL << PGT_count_width) - 1) + +/* + * Page needs to be scrubbed. Since this bit can only be set on a page that is + * free (i.e. in PGC_state_free) we can reuse PGC_allocated bit. + */ +#define _PGC_need_scrub _PGC_allocated +#define PGC_need_scrub PGC_allocated + +/* Cleared when the owning guest 'frees' this page. */ +#define _PGC_allocated PG_shift(1) +#define PGC_allocated PG_mask(1, 1) +/* Page is Xen heap? */ +#define _PGC_xen_heap PG_shift(2) +#define PGC_xen_heap PG_mask(1, 2) +/* Page is broken? */ +#define _PGC_broken PG_shift(7) +#define PGC_broken PG_mask(1, 7) +/* Mutually-exclusive page states: { inuse, offlining, offlined, free }. */ +#define PGC_state PG_mask(3, 9) +#define PGC_state_inuse PG_mask(0, 9) +#define PGC_state_offlining PG_mask(1, 9) +#define PGC_state_offlined PG_mask(2, 9) +#define PGC_state_free PG_mask(3, 9) +#define page_state_is(pg, st) (((pg)->count_info&PGC_state) == PGC_state_##st) + +/* Count of references to this frame. */ +#define PGC_count_width PG_shift(9) +#define PGC_count_mask ((1UL << PGC_count_width) - 1) + +#define _PGC_extra PG_shift(10) +#define PGC_extra PG_mask(1, 10) + +#define is_xen_heap_page(page) ((page)->count_info & PGC_xen_heap) +#define is_xen_heap_mfn(mfn) \ + (mfn_valid(mfn) && is_xen_heap_page(mfn_to_page(mfn))) + +#define is_xen_fixed_mfn(mfn) \ + ((mfn_to_maddr(mfn) >= virt_to_maddr((vaddr_t)_start)) && \ + (mfn_to_maddr(mfn) <= virt_to_maddr((vaddr_t)_end - 1))) + +#define page_get_owner(p) (p)->v.inuse.domain +#define page_set_owner(p, d) ((p)->v.inuse.domain = (d)) + +/* TODO: implement */ +#define mfn_valid(mfn) ({ (void)(mfn); 0; }) + +#define domain_set_alloc_bitsize(d) ((void)(d)) +#define domain_clamp_alloc_bitsize(d, b) ((void)(d), (b)) + +#define PFN_ORDER(pg) ((pg)->v.free.order) + extern unsigned char cpu0_boot_stack[]; void setup_initial_pagetables(void); @@ -20,4 +255,9 @@ unsigned long calc_phys_offset(void); void turn_on_mmu(unsigned long ra); +static inline unsigned int arch_get_dma_bitsize(void) +{ + return 32; /* TODO */ +} + #endif /* _ASM_RISCV_MM_H */ diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index 053f043a3d..fe3a43be20 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -5,12 +5,12 @@ #include #include #include +#include #include #include #include #include -#include #include #include diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 6593f601c1..98a94c4c48 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -2,9 +2,9 @@ #include #include +#include #include -#include /* Xen stack for bringing up the first CPU. */ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] From patchwork Fri May 24 11:08:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13673094 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D70FC25B74 for ; Fri, 24 May 2024 11:09:18 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.729363.1134562 (Exim 4.92) (envelope-from ) id 1sASnO-00054W-CK; Fri, 24 May 2024 11:09:10 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 729363.1134562; Fri, 24 May 2024 11:09:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sASnO-00053h-2Q; Fri, 24 May 2024 11:09:10 +0000 Received: by outflank-mailman (input) for mailman id 729363; Fri, 24 May 2024 11:09:08 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sASnM-0003Cz-Bu for xen-devel@lists.xenproject.org; Fri, 24 May 2024 11:09:08 +0000 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [2a00:1450:4864:20::235]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 0919f488-19be-11ef-b4bb-af5377834399; Fri, 24 May 2024 13:09:06 +0200 (CEST) Received: by mail-lj1-x235.google.com with SMTP id 38308e7fff4ca-2e576057c2bso128759731fa.1 for ; Fri, 24 May 2024 04:09:06 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a626c817c81sm116051366b.28.2024.05.24.04.09.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 04:09:04 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 0919f488-19be-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716548945; x=1717153745; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8soMyFnI8t1ld70bWlw2X55VwVVkeYWhI/zk046fYOA=; b=HEx2jywNHGwkZybkNLgWDx0mC/+qt5l3sGLf5NuXHUO2IZ3pvcEPgRdojYbVvmgJCs W9FbAAPhiN58yur60+rodF1S2FBgRbalhhVofLW4xH6B0eFHS9Vd9P9O6uUFrYkRdsBl Cks38qS1vTJKEZlmdK595VFkdfm4Mc8HwcjRsibATWSieDcmNUz0ppCdqeGDKFHmGfgi dAD44s83iY6SRVbah91TAey0vl0QWc2h+RpetKzUUR2/e3Ff4/pd4umohcASkGP3pjw+ jVPhUst6XIa6PPQwamm8rUV+ya/Ca/HgIb5Vt7Oul6Pi4yI4ySCOUr/Z3i/ly/clqlXD 8Tfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716548945; x=1717153745; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8soMyFnI8t1ld70bWlw2X55VwVVkeYWhI/zk046fYOA=; b=RKJikxWZunn7LmUCDZdlokyHaTFzH6JYdLmhPUlaakiB74+RpooJJmCODOiFNBF02B 9wP210vDUDXyvI1OCLEiWfiZEQHdW6xj8gQvGS91cpp2WfAsFADAFZWyuvW48K7hXXSG J0cPDG0Hr5ZGWH1XzrRGAPSacLFVJZf4aVGcdsHy8aP3HdwLvXGSQxcbm049xR2ICIed 5NfPj83EcWVggRulK4vM/ik+oTEvxY8HVWP2PHW1XmDvOtpq7YgzNgDbW48c799ZvhuH IP3VTqYSiDy9P5yi1PqWUyKWkdOXAIIZHegntPiy71DMOsmZbNYsigM4Eo/Jv15IFfWK kbXg== X-Gm-Message-State: AOJu0Yz5m+G8ZV811FkSj1fShJBeKVdjNf7BfylMPsjzLYinjd9Sl0Cx +t1zxocMYjfVGjF8Cce1GETATnGCAeeixX9O14uQzk1JYEldnngSDQy7D6/E X-Google-Smtp-Source: AGHT+IFMmS7tWE3sAjBB+4Kh33RHI5xwLFwXue+VgMCUrIRS+RXeg5+XNW1aif+08Wj0lxUzWN07Qg== X-Received: by 2002:a2e:b2c7:0:b0:2e8:5d2:5e9b with SMTP id 38308e7fff4ca-2e95b096b9cmr17169121fa.13.1716548945146; Fri, 24 May 2024 04:09:05 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v11 7/9] xen/riscv: add minimal amount of stubs to build full Xen Date: Fri, 24 May 2024 13:08:53 +0200 Message-ID: <94d628999fd4cf32d7ca82a5f6f20297d06d3cef.1716547693.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in V7-V11: - Only rebase was done. --- Changes in V6: - update the commit in stubs.c around /* ... common/irq.c ... */ - add Acked-by: Jan Beulich --- Changes in V5: - drop unrelated changes - assert_failed("unimplmented...") change to BUG_ON() --- Changes in V4: - added new stubs which are necessary for compilation after rebase: __cpu_up(), __cpu_disable(), __cpu_die() from smpboot.c - back changes related to printk() in early_printk() as they should be removed in the next patch to avoid compilation error. - update definition of cpu_khz: __read_mostly -> __ro_after_init. - drop vm_event_reset_vmtrace(). It is defibed in asm-generic/vm_event.h. - move vm_event_*() functions from stubs.c to riscv/vm_event.c. - s/BUG/BUG_ON("unimplemented") in stubs.c - back irq_actor_none() and irq_actor_none() as common/irq.c isn't compiled at this moment, so this function are needed to avoid compilation error. - defined max_page to avoid compilation error, it will be removed as soon as common/page_alloc.c will be compiled. --- Changes in V3: - code style fixes. - update attribute for frametable_base_pdx and frametable_virt_end to __ro_after_init. insteaf of read_mostly. - use BUG() instead of assert_failed/WARN for newly introduced stubs. - drop "#include " in stubs.c and use forward declaration instead. - drop ack_node() and end_node() as they aren't used now. --- Changes in V2: - define udelay stub - remove 'select HAS_PDX' from RISC-V Kconfig because of https://lore.kernel.org/xen-devel/20231006144405.1078260-1-andrew.cooper3@citrix.com/ --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/mm.c | 50 +++++ xen/arch/riscv/setup.c | 8 + xen/arch/riscv/stubs.c | 439 ++++++++++++++++++++++++++++++++++++++++ xen/arch/riscv/traps.c | 25 +++ 5 files changed, 523 insertions(+) create mode 100644 xen/arch/riscv/stubs.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 1ed1a8369b..60afbc0ad9 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -4,6 +4,7 @@ obj-y += mm.o obj-$(CONFIG_RISCV_64) += riscv64/ obj-y += sbi.o obj-y += setup.o +obj-y += stubs.o obj-y += traps.o obj-y += vm_event.o diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c index fe3a43be20..2c3fb7d72e 100644 --- a/xen/arch/riscv/mm.c +++ b/xen/arch/riscv/mm.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -14,6 +15,9 @@ #include #include +unsigned long __ro_after_init frametable_base_pdx; +unsigned long __ro_after_init frametable_virt_end; + struct mmu_desc { unsigned int num_levels; unsigned int pgtbl_count; @@ -294,3 +298,49 @@ unsigned long __init calc_phys_offset(void) phys_offset = load_start - XEN_VIRT_START; return phys_offset; } + +void put_page(struct page_info *page) +{ + BUG_ON("unimplemented"); +} + +unsigned long get_upper_mfn_bound(void) +{ + /* No memory hotplug yet, so current memory limit is the final one. */ + return max_page - 1; +} + +void arch_dump_shared_mem_info(void) +{ + BUG_ON("unimplemented"); +} + +int populate_pt_range(unsigned long virt, unsigned long nr_mfns) +{ + BUG_ON("unimplemented"); + return -1; +} + +int xenmem_add_to_physmap_one(struct domain *d, unsigned int space, + union add_to_physmap_extra extra, + unsigned long idx, gfn_t gfn) +{ + BUG_ON("unimplemented"); + + return 0; +} + +int destroy_xen_mappings(unsigned long s, unsigned long e) +{ + BUG_ON("unimplemented"); + return -1; +} + +int map_pages_to_xen(unsigned long virt, + mfn_t mfn, + unsigned long nr_mfns, + unsigned int flags) +{ + BUG_ON("unimplemented"); + return -1; +} diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 98a94c4c48..8bb5bdb2ae 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -1,11 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include +#include + #include +void arch_get_xen_caps(xen_capabilities_info_t *info) +{ + BUG_ON("unimplemented"); +} + /* Xen stack for bringing up the first CPU. */ unsigned char __initdata cpu0_boot_stack[STACK_SIZE] __aligned(STACK_SIZE); diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c new file mode 100644 index 0000000000..8285bcffef --- /dev/null +++ b/xen/arch/riscv/stubs.c @@ -0,0 +1,439 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include +#include +#include +#include + +#include + +/* smpboot.c */ + +cpumask_t cpu_online_map; +cpumask_t cpu_present_map; +cpumask_t cpu_possible_map; + +/* ID of the PCPU we're running on */ +DEFINE_PER_CPU(unsigned int, cpu_id); +/* XXX these seem awfully x86ish... */ +/* representing HT siblings of each logical CPU */ +DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_mask); +/* representing HT and core siblings of each logical CPU */ +DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_mask); + +nodemask_t __read_mostly node_online_map = { { [0] = 1UL } }; + +/* + * max_page is defined in page_alloc.c which isn't complied for now. + * definition of max_page will be remove as soon as page_alloc is built. + */ +unsigned long __read_mostly max_page; + +/* time.c */ + +unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ + +s_time_t get_s_time(void) +{ + BUG_ON("unimplemented"); +} + +int reprogram_timer(s_time_t timeout) +{ + BUG_ON("unimplemented"); +} + +void send_timer_event(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void domain_set_time_offset(struct domain *d, int64_t time_offset_seconds) +{ + BUG_ON("unimplemented"); +} + +/* shutdown.c */ + +void machine_restart(unsigned int delay_millisecs) +{ + BUG_ON("unimplemented"); +} + +void machine_halt(void) +{ + BUG_ON("unimplemented"); +} + +/* domctl.c */ + +long arch_do_domctl(struct xen_domctl *domctl, struct domain *d, + XEN_GUEST_HANDLE_PARAM(xen_domctl_t) u_domctl) +{ + BUG_ON("unimplemented"); +} + +void arch_get_domain_info(const struct domain *d, + struct xen_domctl_getdomaininfo *info) +{ + BUG_ON("unimplemented"); +} + +void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c) +{ + BUG_ON("unimplemented"); +} + +/* monitor.c */ + +int arch_monitor_domctl_event(struct domain *d, + struct xen_domctl_monitor_op *mop) +{ + BUG_ON("unimplemented"); +} + +/* smp.c */ + +void arch_flush_tlb_mask(const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +void smp_send_event_check_mask(const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +void smp_send_call_function_mask(const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +/* irq.c */ + +struct pirq *alloc_pirq_struct(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +int pirq_guest_bind(struct vcpu *v, struct pirq *pirq, int will_share) +{ + BUG_ON("unimplemented"); +} + +void pirq_guest_unbind(struct domain *d, struct pirq *pirq) +{ + BUG_ON("unimplemented"); +} + +void pirq_set_affinity(struct domain *d, int pirq, const cpumask_t *mask) +{ + BUG_ON("unimplemented"); +} + +hw_irq_controller no_irq_type = { + .typename = "none", + .startup = irq_startup_none, + .shutdown = irq_shutdown_none, + .enable = irq_enable_none, + .disable = irq_disable_none, +}; + +int arch_init_one_irq_desc(struct irq_desc *desc) +{ + BUG_ON("unimplemented"); +} + +void smp_send_state_dump(unsigned int cpu) +{ + BUG_ON("unimplemented"); +} + +/* domain.c */ + +DEFINE_PER_CPU(struct vcpu *, curr_vcpu); +unsigned long __per_cpu_offset[NR_CPUS]; + +void context_switch(struct vcpu *prev, struct vcpu *next) +{ + BUG_ON("unimplemented"); +} + +void continue_running(struct vcpu *same) +{ + BUG_ON("unimplemented"); +} + +void sync_local_execstate(void) +{ + BUG_ON("unimplemented"); +} + +void sync_vcpu_execstate(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void startup_cpu_idle_loop(void) +{ + BUG_ON("unimplemented"); +} + +void free_domain_struct(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void dump_pageframe_info(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void free_vcpu_struct(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +int arch_vcpu_create(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void arch_vcpu_destroy(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_switch_to_aarch64_mode(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) +{ + BUG_ON("unimplemented"); +} + +int arch_domain_create(struct domain *d, + struct xen_domctl_createdomain *config, + unsigned int flags) +{ + BUG_ON("unimplemented"); +} + +int arch_domain_teardown(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_destroy(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_shutdown(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_pause(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_unpause(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +int arch_domain_soft_reset(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_domain_creation_finished(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c) +{ + BUG_ON("unimplemented"); +} + +int arch_initialise_vcpu(struct vcpu *v, XEN_GUEST_HANDLE_PARAM(void) arg) +{ + BUG_ON("unimplemented"); +} + +int arch_vcpu_reset(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +int domain_relinquish_resources(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_dump_domain_info(struct domain *d) +{ + BUG_ON("unimplemented"); +} + +void arch_dump_vcpu_info(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_mark_events_pending(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_update_evtchn_irq(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_block_unless_event_pending(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void vcpu_kick(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +struct domain *alloc_domain_struct(void) +{ + BUG_ON("unimplemented"); +} + +struct vcpu *alloc_vcpu_struct(const struct domain *d) +{ + BUG_ON("unimplemented"); +} + +unsigned long +hypercall_create_continuation(unsigned int op, const char *format, ...) +{ + BUG_ON("unimplemented"); +} + +int __init parse_arch_dom0_param(const char *s, const char *e) +{ + BUG_ON("unimplemented"); +} + +/* guestcopy.c */ + +unsigned long raw_copy_to_guest(void *to, const void *from, unsigned int len) +{ + BUG_ON("unimplemented"); +} + +unsigned long raw_copy_from_guest(void *to, const void __user *from, + unsigned int len) +{ + BUG_ON("unimplemented"); +} + +/* sysctl.c */ + +long arch_do_sysctl(struct xen_sysctl *sysctl, + XEN_GUEST_HANDLE_PARAM(xen_sysctl_t) u_sysctl) +{ + BUG_ON("unimplemented"); +} + +void arch_do_physinfo(struct xen_sysctl_physinfo *pi) +{ + BUG_ON("unimplemented"); +} + +/* p2m.c */ + +int arch_set_paging_mempool_size(struct domain *d, uint64_t size) +{ + BUG_ON("unimplemented"); +} + +int unmap_mmio_regions(struct domain *d, + gfn_t start_gfn, + unsigned long nr, + mfn_t mfn) +{ + BUG_ON("unimplemented"); +} + +int map_mmio_regions(struct domain *d, + gfn_t start_gfn, + unsigned long nr, + mfn_t mfn) +{ + BUG_ON("unimplemented"); +} + +int set_foreign_p2m_entry(struct domain *d, const struct domain *fd, + unsigned long gfn, mfn_t mfn) +{ + BUG_ON("unimplemented"); +} + +/* Return the size of the pool, in bytes. */ +int arch_get_paging_mempool_size(struct domain *d, uint64_t *size) +{ + BUG_ON("unimplemented"); +} + +/* delay.c */ + +void udelay(unsigned long usecs) +{ + BUG_ON("unimplemented"); +} + +/* guest_access.h */ + +static inline unsigned long raw_clear_guest(void *to, unsigned int len) +{ + BUG_ON("unimplemented"); +} + +/* smpboot.c */ + +int __cpu_up(unsigned int cpu) +{ + BUG_ON("unimplemented"); +} + +void __cpu_disable(void) +{ + BUG_ON("unimplemented"); +} + +void __cpu_die(unsigned int cpu) +{ + BUG_ON("unimplemented"); +} + +/* + * The following functions are defined in common/irq.c, but common/irq.c isn't + * built for now. These changes will be removed there when common/irq.c is + * ready. + */ + +void cf_check irq_actor_none(struct irq_desc *desc) +{ + BUG_ON("unimplemented"); +} + +unsigned int cf_check irq_startup_none(struct irq_desc *desc) +{ + BUG_ON("unimplemented"); + + return 0; +} diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index ccd3593f5a..5415cf8d90 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -4,6 +4,10 @@ * * RISC-V Trap handlers */ + +#include +#include + #include #include @@ -11,3 +15,24 @@ void do_trap(struct cpu_user_regs *cpu_regs) { die(); } + +void vcpu_show_execution_state(struct vcpu *v) +{ + BUG_ON("unimplemented"); +} + +void show_execution_state(const struct cpu_user_regs *regs) +{ + printk("implement show_execution_state(regs)\n"); +} + +void arch_hypercall_tasklet_result(struct vcpu *v, long res) +{ + BUG_ON("unimplemented"); +} + +enum mc_disposition arch_do_multicall_call(struct mc_state *state) +{ + BUG_ON("unimplemented"); + return mc_continue; +} From patchwork Fri May 24 11:08:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13673093 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4DEDCC27C44 for ; Fri, 24 May 2024 11:09:19 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.729364.1134571 (Exim 4.92) (envelope-from ) id 1sASnP-0005FR-3a; Fri, 24 May 2024 11:09:11 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 729364.1134571; Fri, 24 May 2024 11:09:10 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sASnO-0005CV-N3; Fri, 24 May 2024 11:09:10 +0000 Received: by outflank-mailman (input) for mailman id 729364; Fri, 24 May 2024 11:09:09 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sASnN-0003Cz-Bt for xen-devel@lists.xenproject.org; Fri, 24 May 2024 11:09:09 +0000 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [2a00:1450:4864:20::135]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 09aac8da-19be-11ef-b4bb-af5377834399; Fri, 24 May 2024 13:09:06 +0200 (CEST) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-529614b8c29so1080110e87.2 for ; Fri, 24 May 2024 04:09:06 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a626c817c81sm116051366b.28.2024.05.24.04.09.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 04:09:05 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 09aac8da-19be-11ef-b4bb-af5377834399 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716548946; x=1717153746; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b94wI6kNLTmJ8tMNKvMfG5/MPujiYvHPiuL4CtLKoSc=; b=TGApL4xbpj1bi+C+A/R1tnjLrosORRiReivdaxuhQOpKsnNvCNJ+0seR7+K0OZpTlo sUo+XqjON0yg0Xr5KPiOj5+KCToKwH4dvXM5AS4D/Eml9gfVI67C1ignHcYCfTfW8V4d sKgxw8BEyaQFuBYwBQpjfynBvC7MiK5rrFdHSzFJRCt3EpxSJXh688seRzHWcrwBJ5iU vCa2xMa87+iHMeNVjZVBq7v3YFM0HL8Pu2pILBHqTBbKISXCt50nfiRmYyz/umwAFU6e a6MtJ9GSnkVeF4r31tMNiuPakaoQnXKgVQGN8gTbXiFIT9PZXy7GXX+VrgNN6q1D9TYm Hc3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716548946; x=1717153746; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b94wI6kNLTmJ8tMNKvMfG5/MPujiYvHPiuL4CtLKoSc=; b=R5bDn17ycChOAUX2Nq4Qbjw2NAsVDpwpSy1nsdC9x839okL7JPI8SnGdwKTKtc+wlG p4zoZjC9CxoxUn9Ty7bpF5yDuBPtij2O5qlg/bI6UT+rn02XfYJe57ZMxTp9hfnF+5A5 6dWRc4bkRPAnCOTvINZK6GPhmCwLixdMDX8aJBbdz6MAc07+PsEGdSy49sOiiS8ubA7H JfzbT1B37Wkm96dYrEwoFtoGsSscdsGMZyaDEu87yyXoix/OfFRCYQPPMw4nZuuwdg3q NbCKtLEFD3t79+F3zNDvU2j4pVBILfe8Dtok0kQsQu1V7FdqXtinTabRXndwuEdp2ofz aSBQ== X-Gm-Message-State: AOJu0YzATpinc9dqHr10zXU+MqqBlK8oQc9+fBM1rR1sluWGb1VA4RVk nF7TR39MxXvsHbaZFAwGRpzgw89eiBArDZfQNFoObPCiVImfU4PdRhH58tLS X-Google-Smtp-Source: AGHT+IGTH7Y8u4ycvlLBGeDfRcjwpph4JM2NgKLV/prJHx2KwU7K2TBeDUfL+BiJjbWFST7ABLYYbA== X-Received: by 2002:ac2:4c49:0:b0:51d:8842:f0b8 with SMTP id 2adb3069b0e04-5296529053bmr2240082e87.13.1716548946203; Fri, 24 May 2024 04:09:06 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v11 8/9] xen/riscv: enable full Xen build Date: Fri, 24 May 2024 13:08:54 +0200 Message-ID: <0a684923efb23fb6094aeab680022b6b14196eef.1716547693.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- At least this patch cann't be merged w/o Andrew's patch series is merged as ffs related functions are used from that patch series: https://lore.kernel.org/xen-devel/20240313172716.2325427-1-andrew.cooper3@citrix.com/T/#t --- Changes in V5-V11: - Nothing changed. Only rebase. - Add the footer after Signed-off section. --- Changes in V4: - drop stubs for irq_actor_none() and irq_actor_none() as common/irq.c is compiled now. - drop defintion of max_page in stubs.c as common/page_alloc.c is compiled now. - drop printk() related changes in riscv/early_printk.c as common version will be used. --- Changes in V3: - Reviewed-by: Jan Beulich - unrealted change dropped in tiny64_defconfig --- Changes in V2: - Nothing changed. Only rebase. --- xen/arch/riscv/Makefile | 16 +++- xen/arch/riscv/arch.mk | 4 - xen/arch/riscv/early_printk.c | 168 ---------------------------------- xen/arch/riscv/stubs.c | 24 ----- 4 files changed, 15 insertions(+), 197 deletions(-) diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 60afbc0ad9..81b77b13d6 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -12,10 +12,24 @@ $(TARGET): $(TARGET)-syms $(OBJCOPY) -O binary -S $< $@ $(TARGET)-syms: $(objtree)/prelink.o $(obj)/xen.lds - $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) -o $@ + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(objtree)/common/symbols-dummy.o -o $(dot-target).0 + $(NM) -pa --format=sysv $(dot-target).0 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).0.S + $(MAKE) $(build)=$(@D) $(dot-target).0.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< \ + $(dot-target).0.o -o $(dot-target).1 + $(NM) -pa --format=sysv $(dot-target).1 \ + | $(objtree)/tools/symbols $(all_symbols) --sysv --sort \ + > $(dot-target).1.S + $(MAKE) $(build)=$(@D) $(dot-target).1.o + $(LD) $(XEN_LDFLAGS) -T $(obj)/xen.lds -N $< $(build_id_linker) \ + $(dot-target).1.o -o $@ $(NM) -pa --format=sysv $@ \ | $(objtree)/tools/symbols --all-symbols --xensyms --sysv --sort \ > $@.map + rm -f $(@D)/.$(@F).[0-9]* $(obj)/xen.lds: $(src)/xen.lds.S FORCE $(call if_changed_dep,cpp_lds_S) diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk index 8c071aff65..17827c302c 100644 --- a/xen/arch/riscv/arch.mk +++ b/xen/arch/riscv/arch.mk @@ -38,7 +38,3 @@ extensions := $(subst $(space),,$(extensions)) # -mcmodel=medlow would force Xen into the lower half. CFLAGS += $(riscv-generic-flags)$(extensions) -mstrict-align -mcmodel=medany - -# TODO: Drop override when more of the build is working -override ALL_OBJS-y = arch/$(SRCARCH)/built_in.o -override ALL_LIBS-y = diff --git a/xen/arch/riscv/early_printk.c b/xen/arch/riscv/early_printk.c index 60742a042d..610c814f54 100644 --- a/xen/arch/riscv/early_printk.c +++ b/xen/arch/riscv/early_printk.c @@ -40,171 +40,3 @@ void early_printk(const char *str) str++; } } - -/* - * The following #if 1 ... #endif should be removed after printk - * and related stuff are ready. - */ -#if 1 - -#include -#include - -/** - * strlen - Find the length of a string - * @s: The string to be sized - */ -size_t (strlen)(const char * s) -{ - const char *sc; - - for (sc = s; *sc != '\0'; ++sc) - /* nothing */; - return sc - s; -} - -/** - * memcpy - Copy one area of memory to another - * @dest: Where to copy to - * @src: Where to copy from - * @count: The size of the area. - * - * You should not use this function to access IO space, use memcpy_toio() - * or memcpy_fromio() instead. - */ -void *(memcpy)(void *dest, const void *src, size_t count) -{ - char *tmp = (char *) dest, *s = (char *) src; - - while (count--) - *tmp++ = *s++; - - return dest; -} - -int vsnprintf(char* str, size_t size, const char* format, va_list args) -{ - size_t i = 0; /* Current position in the output string */ - size_t written = 0; /* Total number of characters written */ - char* dest = str; - - while ( format[i] != '\0' && written < size - 1 ) - { - if ( format[i] == '%' ) - { - i++; - - if ( format[i] == '\0' ) - break; - - if ( format[i] == '%' ) - { - if ( written < size - 1 ) - { - dest[written] = '%'; - written++; - } - i++; - continue; - } - - /* - * Handle format specifiers. - * For simplicity, only %s and %d are implemented here. - */ - - if ( format[i] == 's' ) - { - char* arg = va_arg(args, char*); - size_t arglen = strlen(arg); - - size_t remaining = size - written - 1; - - if ( arglen > remaining ) - arglen = remaining; - - memcpy(dest + written, arg, arglen); - - written += arglen; - i++; - } - else if ( format[i] == 'd' ) - { - int arg = va_arg(args, int); - - /* Convert the integer to string representation */ - char numstr[32]; /* Assumes a maximum of 32 digits */ - int numlen = 0; - int num = arg; - size_t remaining; - - if ( arg < 0 ) - { - if ( written < size - 1 ) - { - dest[written] = '-'; - written++; - } - - num = -arg; - } - - do - { - numstr[numlen] = '0' + num % 10; - num = num / 10; - numlen++; - } while ( num > 0 ); - - /* Reverse the string */ - for (int j = 0; j < numlen / 2; j++) - { - char tmp = numstr[j]; - numstr[j] = numstr[numlen - 1 - j]; - numstr[numlen - 1 - j] = tmp; - } - - remaining = size - written - 1; - - if ( numlen > remaining ) - numlen = remaining; - - memcpy(dest + written, numstr, numlen); - - written += numlen; - i++; - } - } - else - { - if ( written < size - 1 ) - { - dest[written] = format[i]; - written++; - } - i++; - } - } - - if ( size > 0 ) - dest[written] = '\0'; - - return written; -} - -void printk(const char *format, ...) -{ - static char buf[1024]; - - va_list args; - va_start(args, format); - - (void)vsnprintf(buf, sizeof(buf), format, args); - - early_printk(buf); - - va_end(args); -} - -#endif - diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index 8285bcffef..bda35fc347 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -24,12 +24,6 @@ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_mask); nodemask_t __read_mostly node_online_map = { { [0] = 1UL } }; -/* - * max_page is defined in page_alloc.c which isn't complied for now. - * definition of max_page will be remove as soon as page_alloc is built. - */ -unsigned long __read_mostly max_page; - /* time.c */ unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ @@ -419,21 +413,3 @@ void __cpu_die(unsigned int cpu) { BUG_ON("unimplemented"); } - -/* - * The following functions are defined in common/irq.c, but common/irq.c isn't - * built for now. These changes will be removed there when common/irq.c is - * ready. - */ - -void cf_check irq_actor_none(struct irq_desc *desc) -{ - BUG_ON("unimplemented"); -} - -unsigned int cf_check irq_startup_none(struct irq_desc *desc) -{ - BUG_ON("unimplemented"); - - return 0; -} From patchwork Fri May 24 11:08:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 13673092 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A117FC25B79 for ; Fri, 24 May 2024 11:09:17 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.729362.1134556 (Exim 4.92) (envelope-from ) id 1sASnN-000523-VA; Fri, 24 May 2024 11:09:09 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 729362.1134556; Fri, 24 May 2024 11:09:09 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sASnN-00051d-R2; Fri, 24 May 2024 11:09:09 +0000 Received: by outflank-mailman (input) for mailman id 729362; Fri, 24 May 2024 11:09:08 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sASnM-0003D0-55 for xen-devel@lists.xenproject.org; Fri, 24 May 2024 11:09:08 +0000 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [2a00:1450:4864:20::52f]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 09f980d5-19be-11ef-90a1-e314d9c70b13; Fri, 24 May 2024 13:09:07 +0200 (CEST) Received: by mail-ed1-x52f.google.com with SMTP id 4fb4d7f45d1cf-5751bcb3139so10252483a12.1 for ; Fri, 24 May 2024 04:09:07 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a626c817c81sm116051366b.28.2024.05.24.04.09.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 04:09:06 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 09f980d5-19be-11ef-90a1-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716548947; x=1717153747; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XB3BQ9Ks71hVlpF8icLLnQrVXglnlCkVcQJiFBF5cYk=; b=kCmgAl7x5+CvmMKUDN4s9Q5mzDfAcb187cuBbQdXMUWF/A1rMWO1lH+YhZ2cBJW6CR DXsigv8yGPDBjOTbqoQVNrMDREYO73FFLTR6FhHreDA5jxwFWJWizbjvsIsVXmTtQk/I jkfsICERj2SdZ36n/YAYTPf2wLbnjg22F9buRVGmwhkyYuC8F2+y/HWxyUHU6XdhOSk2 zeNCs+q4jodZC543tDdtOIkP68SRs8NPmnhWBMVdKiOy34hBhbooGB8Xq6+/ey1DL3UL 1F3wh9wKTJqtsFe/YvqbYtcRUy0c4REdv++ssRZxxJFW+ASKGgS8JTnpGoz/LKdfwM82 NR1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716548947; x=1717153747; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XB3BQ9Ks71hVlpF8icLLnQrVXglnlCkVcQJiFBF5cYk=; b=uWWYepng1XWP7ZkRlq5irqvxGjw62quLY7PJNR9nql1By0eMlZOuWCgjEPTI+C7ZFS Jiiyc3CgAJGDEuMQlFCBsnTHCRdG4yygg1m6THcSCH3VnXcwICmJD3mUzRj1nFrbQdoW JqCW+VvWh0so51+nMUYZaN1oGMgo/TZ6YEV17Tk+WwlkuiONEMjc0+2QxGMVRakmvPn9 7fz/zLjEMz8X2dGgEaL/hSuHZ5c3LAecnprWEVvkF3r2nx8IquFf/r8NWANzlsD3BP1P akCe79Dza7oJnmFyAYf0gpm/jCGxoLpVjoQt6JABh/hF03oWW5aGJW1Xu9lIotxe782H aRDw== X-Gm-Message-State: AOJu0YxHu/dwaOBhIBvE9dqSC+RbuWyBh3wjn2asdCydlnE3NGGZeijQ guTRukwcWxmlWKeShxrIJ/zwpe51nfmhaeanE3ZXAxn0WAn4XYIREgIXZ+bX X-Google-Smtp-Source: AGHT+IE/+7IppVaU2G3CaM5P+fJkei1eqO2U3AsyLE9MeoJBZJMccDaLoNzpcShLv8KPR9U78aVM0g== X-Received: by 2002:a17:907:60a:b0:a5c:db98:c29e with SMTP id a640c23a62f3a-a62641b4507mr143859366b.18.1716548946975; Fri, 24 May 2024 04:09:06 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v11 9/9] xen/README: add compiler and binutils versions for RISC-V64 Date: Fri, 24 May 2024 13:08:55 +0200 Message-ID: X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 This patch doesn't represent a strict lower bound for GCC and GNU Binutils; rather, these versions are specifically employed by the Xen RISC-V container and are anticipated to undergo continuous testing. Older GCC and GNU Binutils would work, but this is not a guarantee. While it is feasible to utilize Clang, it's important to note that, currently, there is no Xen RISC-V CI job in place to verify the seamless functioning of the build with Clang. Signed-off-by: Oleksii Kurochko --- Changes in V5-V11: - Nothing changed. Only rebase. --- Changes in V6: - update the message in README. --- Changes in V5: - update the commit message and README file with additional explanation about GCC and GNU Binutils version. Additionally, it was added information about Clang. --- Changes in V4: - Update version of GCC (12.2) and GNU Binutils (2.39) to the version which are in Xen's contrainter for RISC-V --- Changes in V3: - new patch --- README | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/README b/README index c8a108449e..30da5ff9c0 100644 --- a/README +++ b/README @@ -48,6 +48,10 @@ provided by your OS distributor: - For ARM 64-bit: - GCC 5.1 or later - GNU Binutils 2.24 or later + - For RISC-V 64-bit: + - GCC 12.2 or later + - GNU Binutils 2.39 or later + Older GCC and GNU Binutils would work, but this is not a guarantee. * POSIX compatible awk * Development install of zlib (e.g., zlib-dev) * Development install of Python 2.7 or later (e.g., python-dev)