From patchwork Wed May 29 08:09:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC1F9C25B75 for ; Wed, 29 May 2024 08:10:45 +0000 (UTC) Received: from mail-lj1-f170.google.com (mail-lj1-f170.google.com [209.85.208.170]) by mx.groups.io with SMTP id smtpd.web10.8628.1716970245254500270 for ; Wed, 29 May 2024 01:10:45 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=RxhKlvpx; spf=pass (domain: tuxon.dev, ip: 209.85.208.170, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lj1-f170.google.com with SMTP id 38308e7fff4ca-2e95a1d5ee2so32855931fa.0 for ; Wed, 29 May 2024 01:10:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970243; x=1717575043; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QEoQuJHyn2Mh9Mw3YZSnCxftwhyhkacyw3vyfCZ+U3k=; b=RxhKlvpx6AVfPsPYDgRm11AYalPmnJeDILsVf1L4x+aPyoozDXUu5NffKOwmSlQmel DIo6KRGQjuAarnHpnSp4jqY0uYYdTA/HgCFTFXtS2tBa5ut5yYCxZ7wc06aFHm99EYsc 7s71Tax/V0S86yeVYsbdl/Evg9jIz61GnQYbBe5+5jmlv9NAdmhycM3pHjqCq6mYHEN+ FwHLeyspbQs4t48zzYp70Y4/q6PAzUlMUf3jcx9dMNBTBd4jBPUn2y5xC099qLDvLVn9 ffOUAcOUBbnIeLmSAw1V3fOF1k8iFEBQ3jNKVIKWiuGrctjaYW9Od1fEwxU+qI1HK+h4 vs+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970243; x=1717575043; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QEoQuJHyn2Mh9Mw3YZSnCxftwhyhkacyw3vyfCZ+U3k=; b=W/9rg6sr/0xZMn4s3I60EhaF6Znyk0WvIL2l6RnhL3AgtqxjTEco6KrUv0AEPkiJhi EzV/2BQW4/knpfRk3Cz4ZC6W3RS+RofK9zLwqMV2NyKP/vCHi04Lm7PodYaJMdzfWWi8 McNBYTYHImQ2T8FZxjeR4HM1Gn1FX4wQNK4ia5NOWE5xGyZ28mExaKif+iljCC+4hGYB HtjXtJSiUTis4KdcU4CNVz7yxGqcR40blrftBN9DEbZtOgkUVhf+XpIh68aok50rw9So C/5Oq387CQV2MbQT38u9GJV1gT3TSrNMiB1RRyQdq5uGlFzqwndfFIi+0ecxnZLX7g4q dlUA== X-Gm-Message-State: AOJu0YyXu6IBDOf/YXNWQ36qNP+GnZDMk0RXIH3ahKMj6r0jKsgyUXK5 ZajpbNPD7IS/M757LFNv3otwJpXbzV9vQDAO0uXbinQ12YWyB+vKNZ9vIqbwfJw+NLxVByzMU1d X9i8= X-Google-Smtp-Source: AGHT+IEwqEWjjXp5h6+Jg4CzoQ/PsW1+hOJlICGu1VJpz23h0o66V1BLnCX6dUFdsShGFTpS98Adew== X-Received: by 2002:a2e:3514:0:b0:2ea:7e39:bd38 with SMTP id 38308e7fff4ca-2ea7e39c68dmr4109541fa.34.1716970243154; Wed, 29 May 2024 01:10:43 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.10.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:10:42 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 01/47] clk: renesas: r9a08g045: Add clock and reset support for ETH0 and ETH1 Date: Wed, 29 May 2024 11:09:53 +0300 Message-Id: <20240529081039.639010-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:10:45 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15981 From: Claudiu Beznea commit 515f05da372aedf347a1ac99d17fb832ba371d4d upstream. RZ/G3S has 2 Gigabit Ethernet interfaces available. Add clock and reset support for both of them. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a08g045-cpg.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index 4394cb241d99..a6d3bea968c0 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -181,9 +181,11 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { DEF_G3S_DIV("P3", R9A08G045_CLK_P3, CLK_PLL3_DIV2_4, DIVPL3C, G3S_DIVPL3C_STS, dtable_1_32, 0, 0, 0, NULL), DEF_FIXED("P3_DIV2", CLK_P3_DIV2, R9A08G045_CLK_P3, 1, 2), + DEF_FIXED("ZT", R9A08G045_CLK_ZT, CLK_PLL3_DIV2_8, 1, 1), DEF_FIXED("S0", R9A08G045_CLK_S0, CLK_SEL_PLL4, 1, 2), DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1), DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3), + DEF_FIXED("HP", R9A08G045_CLK_HP, CLK_PLL6, 1, 2), }; static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { @@ -202,6 +204,12 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9), DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10), DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11), + DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0), + DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0), + DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8), + DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1), + DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1), + DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9), DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), }; @@ -212,6 +220,8 @@ static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2), + DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0), + DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1), DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0), DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), From patchwork Wed May 29 08:09:54 2024 Content-Type: text/plain; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.10.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:10:43 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 02/47] pinctrl: renesas: rzg2l: Move arg and index in the main function block Date: Wed, 29 May 2024 11:09:54 +0300 Message-Id: <20240529081039.639010-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:10:55 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15982 From: Claudiu Beznea commit 906b545b16594e45f2d3433028dcf649d2c05ebb upstream. Move arg and index in the main block of the function as they are used by more than one case block of switch-case (3 out of 4 for arg, 2 out of 4 for index). In this way some lines of code are removed. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index a3f31065c4bc..480d4bba2704 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -838,7 +838,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; unsigned int *pin_data = pin->drv_data; enum pin_config_param param; - unsigned int i; + unsigned int i, arg, index; u32 cfg, off; int ret; u8 bit; @@ -860,24 +860,21 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, for (i = 0; i < num_configs; i++) { param = pinconf_to_config_param(_configs[i]); switch (param) { - case PIN_CONFIG_INPUT_ENABLE: { - unsigned int arg = - pinconf_to_config_argument(_configs[i]); + case PIN_CONFIG_INPUT_ENABLE: + arg = pinconf_to_config_argument(_configs[i]); if (!(cfg & PIN_CFG_IEN)) return -EINVAL; rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); break; - } case PIN_CONFIG_POWER_SOURCE: settings.power_source = pinconf_to_config_argument(_configs[i]); break; - case PIN_CONFIG_DRIVE_STRENGTH: { - unsigned int arg = pinconf_to_config_argument(_configs[i]); - unsigned int index; + case PIN_CONFIG_DRIVE_STRENGTH: + arg = pinconf_to_config_argument(_configs[i]); if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) return -EINVAL; @@ -892,7 +889,6 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); break; - } case PIN_CONFIG_DRIVE_STRENGTH_UA: if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || @@ -902,9 +898,8 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, settings.drive_strength_ua = pinconf_to_config_argument(_configs[i]); break; - case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { - unsigned int arg = pinconf_to_config_argument(_configs[i]); - unsigned int index; + case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: + arg = pinconf_to_config_argument(_configs[i]); if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) return -EINVAL; @@ -918,7 +913,6 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); break; - } default: return -EOPNOTSUPP; From patchwork Wed May 29 08:09:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678234 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00D95C27C50 for ; Wed, 29 May 2024 08:10:56 +0000 (UTC) Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) by mx.groups.io with SMTP id smtpd.web10.8631.1716970247802302655 for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.10.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:10:45 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 03/47] pinctrl: renesas: rzg2l: Add pin configuration support for pinmux groups Date: Wed, 29 May 2024 11:09:55 +0300 Message-Id: <20240529081039.639010-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:10:55 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15983 From: Claudiu Beznea commit d3aaa7203a17e8399df41e7c3f088f51368b001c upstream. On RZ/G3S different Ethernet pins need to be configured with different settings (e.g. power-source needs to be set, RGMII TXC and TX_CTL pins need output-enable). Adjust the driver to allow specifying pin configuration for pinmux groups. With this, DT settings like the following are taken into account by the driver: eth0_pins: eth0 { tx_ctl { pinmux = ; /* ET0_TX_CTL */ power-source = <1800>; output-enable; drive-strength-microamp = <5200>; }; }; Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 480d4bba2704..329edc31ed00 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -372,8 +372,11 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, goto done; } - if (num_pinmux) + if (num_pinmux) { nmaps += 1; + if (num_configs) + nmaps += 1; + } if (num_pins) nmaps += num_pins; @@ -458,6 +461,16 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, maps[idx].data.mux.function = name; idx++; + if (num_configs) { + ret = rzg2l_map_add_config(&maps[idx], name, + PIN_MAP_TYPE_CONFIGS_GROUP, + configs, num_configs); + if (ret < 0) + goto remove_group; + + idx++; + } + dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); ret = 0; goto done; From patchwork Wed May 29 08:09:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2DCBC41513 for ; Wed, 29 May 2024 08:10:55 +0000 (UTC) Received: from mail-lj1-f179.google.com (mail-lj1-f179.google.com [209.85.208.179]) by mx.groups.io with SMTP id smtpd.web11.8563.1716970249454568037 for ; Wed, 29 May 2024 01:10:49 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=rGPqDblY; spf=pass (domain: tuxon.dev, ip: 209.85.208.179, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lj1-f179.google.com with SMTP id 38308e7fff4ca-2e95a7622cfso18379481fa.2 for ; Wed, 29 May 2024 01:10:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970248; x=1717575048; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7hkiJVmuVuG3EmX8P3qW7RhBmIImFt4kWHBoSr6CBEw=; b=rGPqDblYqCbBpmcwGUtn55irF3y/bAGhzMoF8LPgz3HltmMEq/vRx+nDHiCo8PtWpg rDLIqCiTO42ezZS1t+rzaB3+lcW8cv7MHc+1YtDTBo6iP6wGZpr6VDk1v2oYrrL9Q2dw WPQVJu5rdKzed/xgS7S7Al3ZPH5Ds/s4pWV0TJbgAk5obap2ZdGdt5W9U7cakUnrOp4f pzoih40bUOHu9FcMFIVpIXSUoIC1tptBz3FTzYuqYfq1wB6ECXGCMv6KdxV+nDgUiiMx VjmbHrAU9enqoKSFMauslooTwt7bYtX3SjeOo+kpn6B/RxGY10MjKubhh5EkvFLEcbGf LYTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970248; x=1717575048; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7hkiJVmuVuG3EmX8P3qW7RhBmIImFt4kWHBoSr6CBEw=; b=jpA69UloN7CUI93mtKjDheciJutsecAWU51HkrSs/jG7xO1goSU8f5cib0y3jJ3ioC J+tssPdvyasZzlZSplT7g+8OaMdZyfAuowC7YTeIjFlGhFxAFMGxBUCnGdm3krZzxnp6 HrjWLW+H84WVb1nbF7zJ6zb1GnGtqFQz8EdTbOxp1uAC2Ru0NNu56m9oKXb9B46TG115 +iHE2bmdhvFFBa/HQB4seq5u4RlLRHcAYIGfWYKo1T6TptFV6oH/TsqCsFZrXqyw3+Bl z7jot5SD65f4asN5IsZ4NDe49ybMqO15/4hmNcyLumEWutKmXfSrVoJp6Vl4jslIEu1n mDPQ== X-Gm-Message-State: AOJu0YxTJZWOIKAFhdRFzRQye3W/nxps3nNDyKijkX9dLC6fn5HtWM6D FtghEyeHi014+mTAKPC2o41pTeWa3bD0jzCpXSshMBmKijSnUKReQnQl0hgQzwZ9i3WQdcPB546 zev8= X-Google-Smtp-Source: AGHT+IHryTE4Qw4+KC7Oz3ZXsHCcbSTEdgUX0m03xP9+b9S8yJyMWp8aSSmORmrxQE1k0SlprVk3Ig== X-Received: by 2002:a05:651c:546:b0:2ea:7f9e:34dd with SMTP id 38308e7fff4ca-2ea7f9e3577mr1060651fa.47.1716970247516; Wed, 29 May 2024 01:10:47 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.10.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:10:47 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 04/47] pinctrl: renesas: rzg2l: Add support to select power source for Ethernet pins Date: Wed, 29 May 2024 11:09:56 +0300 Message-Id: <20240529081039.639010-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:10:55 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15984 From: Claudiu Beznea commit 51996952b8b50942ed3069141ebc1dee13756b95 upstream. The GPIO controller available on RZ/G3S (but also on RZ/G2L) supports setting the power source for Ethernet pins. Based on the interface b/w the Ethernet controller and the Ethernet PHY, and on board design, a specific power source needs to be selected. The GPIO controller supports 1.8V, 2.5V, and 3.3V power source selection for the Ethernet pins. This can be selected though the ETHx_POC registers (x={0, 1}). Adjust the driver to support this, and to do proper instantiation for the RZ/G3S and RZ/G2L SoCs. On RZ/G2L only the get operation has been tested at the moment. While at it, as the power registers on RZ/G2L support access sizes of 8 bits, and these registers on RZ/G3S support access sizes of 8/16/32 bits, replace writel()/readl() on these registers with writeb()/readb(). This should allow us to use the same code on both SoCs w/o any issues. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 42 +++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 329edc31ed00..4a649dc43946 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -103,8 +103,10 @@ #define IEN(off) (0x1800 + (off) * 8) #define ISEL(off) (0x2C00 + (off) * 8) #define SD_CH(off, ch) ((off) + (ch) * 4) +#define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) +#define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ @@ -112,7 +114,6 @@ #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ #define PM_MASK 0x03 -#define PVDD_MASK 0x01 #define PFC_MASK 0x07 #define IEN_MASK 0x01 #define IOLH_MASK 0x03 @@ -131,10 +132,12 @@ * struct rzg2l_register_offsets - specific register offsets * @pwpr: PWPR register offset * @sd_ch: SD_CH register offset + * @eth_poc: ETH_POC register offset */ struct rzg2l_register_offsets { u16 pwpr; u16 sd_ch; + u16 eth_poc; }; /** @@ -600,6 +603,10 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 return SD_CH(regs->sd_ch, 0); if (caps & PIN_CFG_IO_VMC_SD1) return SD_CH(regs->sd_ch, 1); + if (caps & PIN_CFG_IO_VMC_ETH0) + return ETH_POC(regs->eth_poc, 0); + if (caps & PIN_CFG_IO_VMC_ETH1) + return ETH_POC(regs->eth_poc, 1); if (caps & PIN_CFG_IO_VMC_QSPI) return QSPI; @@ -611,6 +618,7 @@ static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs = &hwcfg->regs; int pwr_reg; + u8 val; if (caps & PIN_CFG_SOFT_PS) return pctrl->settings[pin].power_source; @@ -619,7 +627,18 @@ static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps if (pwr_reg < 0) return pwr_reg; - return (readl(pctrl->base + pwr_reg) & PVDD_MASK) ? 1800 : 3300; + val = readb(pctrl->base + pwr_reg); + switch (val) { + case PVDD_1800: + return 1800; + case PVDD_2500: + return 2500; + case PVDD_3300: + return 3300; + default: + /* Should not happen. */ + return -EINVAL; + } } static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) @@ -627,17 +646,32 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs = &hwcfg->regs; int pwr_reg; + u8 val; if (caps & PIN_CFG_SOFT_PS) { pctrl->settings[pin].power_source = ps; return 0; } + switch (ps) { + case 1800: + val = PVDD_1800; + break; + case 2500: + val = PVDD_2500; + break; + case 3300: + val = PVDD_3300; + break; + default: + return -EINVAL; + } + pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); if (pwr_reg < 0) return pwr_reg; - writel((ps == 1800) ? PVDD_1800 : PVDD_3300, pctrl->base + pwr_reg); + writeb(val, pctrl->base + pwr_reg); pctrl->settings[pin].power_source = ps; return 0; @@ -1882,6 +1916,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { .regs = { .pwpr = 0x3014, .sd_ch = 0x3000, + .eth_poc = 0x300c, }, .iolh_groupa_ua = { /* 3v3 power source */ @@ -1894,6 +1929,7 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = { .regs = { .pwpr = 0x3000, .sd_ch = 0x3004, + .eth_poc = 0x3010, }, .iolh_groupa_ua = { /* 1v8 power source */ From patchwork Wed May 29 08:09:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678236 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D06A5C25B7E for ; Wed, 29 May 2024 08:10:55 +0000 (UTC) Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) by mx.groups.io with SMTP id smtpd.web10.8632.1716970251095466801 for ; Wed, 29 May 2024 01:10:51 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=q9I6KIta; spf=pass (domain: tuxon.dev, ip: 209.85.128.43, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f43.google.com with SMTP id 5b1f17b1804b1-421140314d5so14291055e9.0 for ; Wed, 29 May 2024 01:10:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970249; x=1717575049; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NZFnjVwRGScu41dlvZxly8tP4a85kgtzHL1tDwzU+lU=; b=q9I6KItaDewZA04C5zmfv8DdOxM+fEPvCmy1NpWwWs0r94FS9EsyEWUSZPxlW0e9TG Re9fSWAdX5qm95dbtEH0oNj7bzhfZEGbAfWy+iJ1OOeUfskE+QZZxnZxtd79WmQ3Df3Q /aSE/boIuD5SLteZm8FbY5PMi/aFGJDcfqTbT0FIF56JKBKw/rpT1Y/ytGViGtbs4Xjk QRUqpIt7+8b3KSL9F/UjYA4uM7CcgjBqUJHZYVfRobrzvBwQOxg5MfsN99lWHYEdMYWw 4ZYWnb62DS0jJa/mn8kw4Ys1oMGth31fFSd99zEk3mB61nvRBZebQ6jgHMll1fHJ94VS sgbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970249; x=1717575049; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NZFnjVwRGScu41dlvZxly8tP4a85kgtzHL1tDwzU+lU=; b=UfkFyekZZJsg23LZ9pshwVuInj10Z5by8i5G2hwLd/jctVtXU0hBVX6a6V6Yclt/y5 21O+T0Qmy3WIPkudA8gq94PYnbORC7qPelKgvafIAdWQ4eS6WsoQHIGOedwYp3CAuOvt SmZp8ejdjmpdZEr5R31Uf7jtKwdzDPsQoJO1lMlcnla7hZQ8AYeH2uen15PTAxyiJIAq uAJ1ia9LfQ7n9l0HHMAiLT50Rg5+XFjNhNpx/52FER7uFjleGAQx/D59cyGnrKDxPDAW zfSp4/1bT30tjg3tFgtsErsC096B0w7bKpQFRLcg74nl1xLU+Xp7AiuibbTmS2doj277 TIeA== X-Gm-Message-State: AOJu0YxwknIff2wXkL05hlghLCz2jJjI04DbIoSw5EFmyCpBe9cOx/3a 0/fwrXxy7JQSYBYuhtzRNvAPRtbQyFfRYhKUWZGyyPa1+CYOMpqENvzco1SlAyY= X-Google-Smtp-Source: AGHT+IF76c0lC/ZWVVkTAkkZL4u5F83KmeUey8pGBBxqQ4+N6/Lcl3RlKLmpOi2GF0LHdz8e9yhG4Q== X-Received: by 2002:a7b:c403:0:b0:420:e24b:dbc with SMTP id 5b1f17b1804b1-42108a0007cmr111802295e9.27.1716970249555; Wed, 29 May 2024 01:10:49 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.10.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:10:49 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 05/47] pinctrl: renesas: rzg2l: Add output enable support Date: Wed, 29 May 2024 11:09:57 +0300 Message-Id: <20240529081039.639010-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:10:55 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15985 From: Claudiu Beznea commit 1bbc8ee40826164d16e32d377654c93ef48d1458 upstream. Some of the Ethernet pins on RZ/G3S (but also valid for RZ/G2L) need to have the direction of the IO buffer set as output for Ethernet to work properly. On RZ/G3S, these pins are P1_0/P7_0, P1_1/P7_1, and can have the following Ethernet functions: TXC/TX_CLK or TX_CTL/TX_EN. As the pins supporting output enable are SoC specific, and there is a limited number of these pins (TXC/TX_CLK and/or TX_CTL/TX_EN), specify output enable capable port limits in the platform-based configuration data structure, to ensure proper validation. The OEN support has been intantiated for RZ/G3S at the moment. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-7-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 87 ++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 4a649dc43946..6d0b10f77692 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -53,6 +53,7 @@ #define PIN_CFG_FILCLKSEL BIT(12) #define PIN_CFG_IOLH_C BIT(13) #define PIN_CFG_SOFT_PS BIT(14) +#define PIN_CFG_OEN BIT(15) #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ (PIN_CFG_IOLH_##group | \ @@ -105,6 +106,7 @@ #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) +#define ETH_MODE (0x3018) #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ @@ -166,6 +168,8 @@ enum rzg2l_iolh_index { * @iolh_groupb_oi: IOLH group B output impedance specific values * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported) * @func_base: base number for port function (see register PFC) + * @oen_max_pin: the maximum pin number supporting output enable + * @oen_max_port: the maximum port number supporting output enable */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; @@ -175,6 +179,8 @@ struct rzg2l_hwcfg { u16 iolh_groupb_oi[4]; bool drive_strength_ua; u8 func_base; + u8 oen_max_pin; + u8 oen_max_port; }; struct rzg2l_dedicated_configs { @@ -778,6 +784,66 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, return false; } +static bool rzg2l_oen_is_supported(u32 caps, u8 pin, u8 max_pin) +{ + if (!(caps & PIN_CFG_OEN)) + return false; + + if (pin > max_pin) + return false; + + return true; +} + +static u8 rzg2l_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port) +{ + if (pin) + pin *= 2; + + if (offset / RZG2L_PINS_PER_PORT == max_port) + pin += 1; + + return pin; +} + +static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin) +{ + u8 max_port = pctrl->data->hwcfg->oen_max_port; + u8 max_pin = pctrl->data->hwcfg->oen_max_pin; + u8 bit; + + if (!rzg2l_oen_is_supported(caps, pin, max_pin)) + return 0; + + bit = rzg2l_pin_to_oen_bit(offset, pin, max_port); + + return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); +} + +static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen) +{ + u8 max_port = pctrl->data->hwcfg->oen_max_port; + u8 max_pin = pctrl->data->hwcfg->oen_max_pin; + unsigned long flags; + u8 val, bit; + + if (!rzg2l_oen_is_supported(caps, pin, max_pin)) + return -EINVAL; + + bit = rzg2l_pin_to_oen_bit(offset, pin, max_port); + + spin_lock_irqsave(&pctrl->lock, flags); + val = readb(pctrl->base + ETH_MODE); + if (oen) + val &= ~BIT(bit); + else + val |= BIT(bit); + writeb(val, pctrl->base + ETH_MODE); + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, unsigned int _pin, unsigned long *config) @@ -815,6 +881,12 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, return -EINVAL; break; + case PIN_CONFIG_OUTPUT_ENABLE: + arg = rzg2l_read_oen(pctrl, cfg, _pin, bit); + if (!arg) + return -EINVAL; + break; + case PIN_CONFIG_POWER_SOURCE: ret = rzg2l_get_power_source(pctrl, _pin, cfg); if (ret < 0) @@ -916,6 +988,13 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); break; + case PIN_CONFIG_OUTPUT_ENABLE: + arg = pinconf_to_config_argument(_configs[i]); + ret = rzg2l_write_oen(pctrl, cfg, _pin, bit, !!arg); + if (ret) + return ret; + break; + case PIN_CONFIG_POWER_SOURCE: settings.power_source = pinconf_to_config_argument(_configs[i]); break; @@ -1360,7 +1439,8 @@ static const u32 r9a07g043_gpio_configs[] = { static const u32 r9a08g045_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | - PIN_CFG_IO_VMC_ETH0)), /* P1 */ + PIN_CFG_IO_VMC_ETH0)) | + PIN_CFG_OEN, /* P1 */ RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH0)), /* P2 */ RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | @@ -1370,7 +1450,8 @@ static const u32 r9a08g045_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */ RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */ RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | - PIN_CFG_IO_VMC_ETH1)), /* P7 */ + PIN_CFG_IO_VMC_ETH1)) | + PIN_CFG_OEN, /* P7 */ RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH1)), /* P8 */ RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | @@ -1953,6 +2034,8 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = { }, .drive_strength_ua = true, .func_base = 1, + .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */ + .oen_max_port = 7, /* P7_1 is the maximum OEN port. */ }; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.10.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:10:50 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 06/47] pinctrl: renesas: rzg2l: Add input enable to the Ethernet pins Date: Wed, 29 May 2024 11:09:58 +0300 Message-Id: <20240529081039.639010-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:10:55 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15986 From: Claudiu Beznea commit 9e5889c68d992b65efd10aa0a4523c96fd07077f upstream. Some of the RZ/G3S Ethernet pins (P1_0, P7_0) can be configured with input enable. Enable this functionality for these pins. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-8-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 6d0b10f77692..bd54ab706654 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1440,7 +1440,7 @@ static const u32 r9a08g045_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH0)) | - PIN_CFG_OEN, /* P1 */ + PIN_CFG_OEN | PIN_CFG_IEN, /* P1 */ RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH0)), /* P2 */ RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | @@ -1451,7 +1451,7 @@ static const u32 r9a08g045_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */ RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH1)) | - PIN_CFG_OEN, /* P7 */ + PIN_CFG_OEN | PIN_CFG_IEN, /* P7 */ RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH1)), /* P8 */ RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | From patchwork Wed May 29 08:09:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCB5DC3DA40 for ; Wed, 29 May 2024 08:10:55 +0000 (UTC) Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) by mx.groups.io with SMTP id smtpd.web10.8634.1716970253661455566 for ; Wed, 29 May 2024 01:10:53 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=TPt0flS3; spf=pass (domain: tuxon.dev, ip: 209.85.128.44, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4202cea9a2fso14144095e9.3 for ; Wed, 29 May 2024 01:10:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970252; x=1717575052; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+yfM9PqjJzcRP3D5IlsUWqrorPDN5bZe/Rv5u+w2hyc=; b=TPt0flS3QUDXQOmyxahN5VOknduFTp7bL6Ra1tZAxvIn7NnyZxWJ5L0k+z+i8Nue3f CuUy+QrXD9bXK5zF/BBGzgbLZeCJZ37KvPez4OxJijhGMA71pbZ3MTrjIrL5EBNP95lV xG0hG2rzE1Yw6lwFih3zWlSXdbkGSC+OTE8YbaJZO5IOttvrMS+k2evvEL2/QOmBnGmM Ee2G8j/tFSpixC8/dUAH4bMl4XfHFN7oGUu8db6fs7bIoG8rUzG2Lu1P5nXraGrx7B0G eF0bnrGq4ZFZEP0H48Japtia6hQnZF8Zg6OYSz/vN5u2EXgLia7GK597TfjEXM4vzszA 2/3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970252; x=1717575052; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+yfM9PqjJzcRP3D5IlsUWqrorPDN5bZe/Rv5u+w2hyc=; b=Kn4+bqGbK/dxsz1Y0WHjg8dEuqJUtRXUTHD1sYNJ3AWPedCYPfnP9fpYZyXY4aLvA8 Wqz0sCtR9fYbCx4oAE7/1CJ1L1fG+tq/cdanDYnA/WP5ss86mQa4F0GlndUh29k5cPkv 5vlvAU4Dubx3gs+td5zZ79YKtMmMWZvo39bxpW26AzMozGYbl35c6u7bTT6Pk5IuUL2m jyoD4QHO2Ql6hqKnVRyIUUM28grce2IRZEzVwtC3iisVlcGRf4BCI58YYwL3sCEhzCwa BTqt3uKC6HRrJd8qXfHKeLczpiGn4YoqflnY0IZ1P3JNtx8LWVhQfZwf9kN4ZqgkrjyP UI/w== X-Gm-Message-State: AOJu0YxhG5y4i2yzMYJNR9VOs8XJTPr4mdLCrGBSjk2iVoBgF15uAyST 37mmalmusCRJtRH6nrB7HAMC3BzaAD7m7JxkNP2n8UzPx/LAYptbH8TvO2+Isy8= X-Google-Smtp-Source: AGHT+IGxOH7jN0JJSAHcNUw+y1THhmoPFLB5dQIwVgf5sjLH/v7h2IvhxQrCENrZqfl9Y3CEpFN/jA== X-Received: by 2002:a1c:4b0b:0:b0:418:5ed2:5aa6 with SMTP id 5b1f17b1804b1-42108a1fa4dmr131588055e9.31.1716970252152; Wed, 29 May 2024 01:10:52 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.10.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:10:51 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 07/47] pinctrl: renesas: rzg2l: Fix locking in rzg2l_dt_subnode_to_map() Date: Wed, 29 May 2024 11:09:59 +0300 Message-Id: <20240529081039.639010-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:10:55 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15987 From: Claudiu Beznea commit bd433c25ca81b2ac6dca7ea288a8474eea4fb8a0 upstream. Commit d3aaa7203a17 ("pinctrl: renesas: rzg2l: Add pin configuration support for pinmux groups") introduced the possibility to parse pin configuration for pinmux groups. It did that by calling rzg2l_map_add_config() at the end of rzg2l_dt_subnode_to_map() and jumping to the remove_group label in case rzg2l_map_add_config() failed. But if that happens, the mutex will already be unlocked, thus this it will lead to double mutex unlock operation. To fix this move the rzg2l_map_add_config() call just after all the name argument is ready and before the mutex is locked. There is no harm in doing this, as this only parses the data from device tree that will be further processed by pinctrl core code. Fixes: d3aaa7203a17 ("pinctrl: renesas: rzg2l: Add pin configuration support for pinmux groups") Reported-by: Dan Carpenter Closes: https://lore.kernel.org/all/f8c3a3a0-7c48-4e40-8af0-ed4e9d9b049f@moroto.mountain Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240115153453.99226-1-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index bd54ab706654..32ca9da27d11 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -443,6 +443,16 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, name = np->name; } + if (num_configs) { + ret = rzg2l_map_add_config(&maps[idx], name, + PIN_MAP_TYPE_CONFIGS_GROUP, + configs, num_configs); + if (ret < 0) + goto done; + + idx++; + } + mutex_lock(&pctrl->mutex); /* Register a single pin group listing all the pins we read from DT */ @@ -470,16 +480,6 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, maps[idx].data.mux.function = name; idx++; - if (num_configs) { - ret = rzg2l_map_add_config(&maps[idx], name, - PIN_MAP_TYPE_CONFIGS_GROUP, - configs, num_configs); - if (ret < 0) - goto remove_group; - - idx++; - } - dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); ret = 0; goto done; From patchwork Wed May 29 08:10:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678235 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DAABC25B75 for ; Wed, 29 May 2024 08:10:56 +0000 (UTC) Received: from mail-lj1-f175.google.com (mail-lj1-f175.google.com [209.85.208.175]) by mx.groups.io with SMTP id smtpd.web11.8566.1716970255417657808 for ; Wed, 29 May 2024 01:10:55 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=TNvXHSt9; spf=pass (domain: tuxon.dev, ip: 209.85.208.175, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lj1-f175.google.com with SMTP id 38308e7fff4ca-2e6f2534e41so17679161fa.0 for ; Wed, 29 May 2024 01:10:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970253; x=1717575053; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BPqKikLqckUS0vslC+LtQNcecFHVGqqKyf+de1iE5Ns=; b=TNvXHSt9Cc5+uqXfOry4yTLkpoKJfUnFNrWLy2a3Np6JwLBjabAChQRWVR7aatJmgo ipY+P2JjMo623HFBPAaJk7ApZhOsIjGoHGLs1QpJDhuAtTKmKupHtTlT2nHNh6WymmZh 98a3+MtPca2dXdMhFW/FLSkrLGmDAmQE95G5aLcvzPnMK9QWWgTf+6oo9WHytOPa+0kW bcY/QxJHS41sj71HBr7fNZ7AoJhGICNk8jzDrCstIckKfhcTQJaSVEsGYCXXQoZbeY0d MIpd5+cAzoqR9LEo3c75A07G4vscvLALXadGSg/oN+YQclPxGD+S9T0V/fD6Wm3uxhvZ jplA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970253; x=1717575053; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BPqKikLqckUS0vslC+LtQNcecFHVGqqKyf+de1iE5Ns=; b=bemALVS/P34gqw+Uw27Awn74quo8U11bb5FLj/FR7ry1dbl6WPz7S74aGiprK06CP1 zwohoYguhoDNE9DKFZ6LR/SX6Q4X9nz4ig3+zztTjDVy5zpa33PzVVMbyOsY/u2pdkwx sEwfbNJayaCbEYaJizNVIraBoV6QeTT41hwhfqtZ4JPNo24fMjRT6G4g58EWaN5lGZqM +uK156J0EjzZzcgieUL2I0sTRdJcW+gjJJ2JFkm1JZp4ivBbYwVA14rDINND2/Rzuypj xRjomyrNuqagCXzQRDUFz0dNrhWtKOhGOOjQ5C5SE4loQlFNZzFSEhnitwpqKxteSY/J bA+Q== X-Gm-Message-State: AOJu0Yy4QqhWAkiprwYksfmVgcBanqmdokHJpd0BMjOx/7milBIXVYZV 6heJx26Xqb9uqp0jsSZ4xjEyIA6lZl8Vg4nUksJwfvF9r+AQVq68rjtLSzM7aI4= X-Google-Smtp-Source: AGHT+IE/O1iGSmFEHPDVx7xjKkOhajYODaZPUGoZlGVyMQQwqDHqZw4RaEgOaQIoBXs9hE4RsqrIag== X-Received: by 2002:a2e:b385:0:b0:2da:736d:3cf5 with SMTP id 38308e7fff4ca-2e95b24c909mr81808801fa.41.1716970253441; Wed, 29 May 2024 01:10:53 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.10.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:10:52 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 08/47] ravb: Fix potential use-after-free in ravb_rx_gbeth() Date: Wed, 29 May 2024 11:10:00 +0300 Message-Id: <20240529081039.639010-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:10:56 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15988 From: YueHaibing commit 5a5a3e564de6a8db987410c5c2f4748d50ea82b8 upstream. The skb is delivered to napi_gro_receive() which may free it, after calling this, dereferencing skb may trigger use-after-free. Fixes: 1c59eb678cbd ("ravb: Fillup ravb_rx_gbeth() stub") Signed-off-by: YueHaibing Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20221203092941.10880-1-yuehaibing@huawei.com Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index fd1c5ee676b7..23fb75b9ee0d 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -838,7 +838,7 @@ static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) napi_gro_receive(&priv->napi[q], priv->rx_1st_skb); stats->rx_packets++; - stats->rx_bytes += priv->rx_1st_skb->len; + stats->rx_bytes += pkt_len; break; } } From patchwork Wed May 29 08:10:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678238 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F34E5C25B7C for ; Wed, 29 May 2024 08:11:05 +0000 (UTC) Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) by mx.groups.io with SMTP id smtpd.web10.8636.1716970257464464662 for ; Wed, 29 May 2024 01:10:57 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=kTucsQpZ; spf=pass (domain: tuxon.dev, ip: 209.85.167.44, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f44.google.com with SMTP id 2adb3069b0e04-529682e013dso2087924e87.3 for ; Wed, 29 May 2024 01:10:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970256; x=1717575056; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lHwaqK8FDbrUJOjMh40D051saX2MZgSoYnTbNQAYvkk=; b=kTucsQpZ8vC6oV6YziDNiSYFMYkCLEq9+hVmSncczRIsmQXOLyRSl7/t8THDUnRCFm JzrVSW1yQk5dHfRoDDpTHwb7AOGbU+8Z0A/IlU+s4Uy7f9S61nd6rpobHaljsjjBvpF+ 1Kn0XMvPCr4C7A0t6cInw9fbCMCo0gT4C2ZF/mZTWkGe26TCkRrkwi0s1Nclhj2ei8YM PFHYhT/ef+Aq1wzdtynWGP4bDOVYprGGSdH9HJsITfkPgxno4L+uDCM7On544vCkSDRH l1SwMemE+7BQPL6+pepmLtbNk32rcVxbmspr4J6c/Egb+cFP9JUiHvEF1Hoz5v2dHBMw /oPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970256; x=1717575056; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lHwaqK8FDbrUJOjMh40D051saX2MZgSoYnTbNQAYvkk=; b=KEIBtVNXEqV12/0nz+Q726oTfSA2QE9Obo7FPQpm6DuZaGny9z6lf7q8sajBQgy5v/ jt0jfBtdvY1dE5jUYI4SM4Xbvud/MPzyDEx8zPxDBzwyYlCAxeY3zsi59uA/t8bCjqF9 fDAaxU1k7XWpnELXKPoMnXBI/xbNg8AGm1Ykfl64tTJBCNTxOjMwMxYP4gt2CEMWEdgB g1DQdy0Nc8SCnEIOF8ffeZEFrKcbHXC1vmwag5XLbBZjqB47cgDTtWO2r3Yjxbv3ZGGm cbojhcMR4e5+sMPy9ebupA1zCikSj66nMpSadF/x7jJ4S/LLWkDUV8mNo12vYodw3fEu MB9Q== X-Gm-Message-State: AOJu0YwlDyeQ9437UL4DgTL8d2bcdwOyzUO2k1kqiwGYY0mIFtNbpU2J E0eiLrQUmCn2EYXr26AEpAT0+qxKVqp6SRILzK35x/3Fer+bWntCuyJeUf3KN7I= X-Google-Smtp-Source: AGHT+IGUQfqe8sx4jqWwk63f7ASn1lJGX+KTDnq07Sz4Lr/2/Wnzx4Z/+Wq+9XXnUmTLl1a3pbtSMg== X-Received: by 2002:ac2:58f7:0:b0:515:d038:5548 with SMTP id 2adb3069b0e04-529650a4281mr8135561e87.31.1716970255684; Wed, 29 May 2024 01:10:55 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.10.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:10:54 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 09/47] net: ravb: Fix lack of register setting after system resumed for Gen3 Date: Wed, 29 May 2024 11:10:01 +0300 Message-Id: <20240529081039.639010-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:05 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15989 From: Yoshihiro Shimoda commit c2b6cdee1d13ffbb24baca3c9b8a572d6b541e4e upstream. After system entered Suspend to RAM, registers setting of this hardware is reset because the SoC will be turned off. On R-Car Gen3 (info->ccc_gac), ravb_ptp_init() is called in ravb_probe() only. So, after system resumed, it lacks of the initial settings for ptp. So, add ravb_ptp_{init,stop}() into ravb_{resume,suspend}(). Fixes: f5d7837f96e5 ("ravb: ptp: Add CONFIG mode support") Signed-off-by: Yoshihiro Shimoda Reviewed-by: Sergey Shtylyov Signed-off-by: David S. Miller Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 23fb75b9ee0d..c15a4d56e79f 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2994,6 +2994,9 @@ static int __maybe_unused ravb_suspend(struct device *dev) else ret = ravb_close(ndev); + if (priv->info->ccc_gac) + ravb_ptp_stop(ndev); + return ret; } @@ -3032,6 +3035,9 @@ static int __maybe_unused ravb_resume(struct device *dev) /* Restore descriptor base address table */ ravb_write(ndev, priv->desc_bat_dma, DBAT); + if (priv->info->ccc_gac) + ravb_ptp_init(ndev, priv->pdev); + if (netif_running(ndev)) { if (priv->wol_enabled) { ret = ravb_wol_restore(ndev); From patchwork Wed May 29 08:10:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678239 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19DD9C25B7E for ; Wed, 29 May 2024 08:11:06 +0000 (UTC) Received: from mail-lj1-f175.google.com (mail-lj1-f175.google.com [209.85.208.175]) by mx.groups.io with SMTP id smtpd.web10.8639.1716970259266039354 for ; Wed, 29 May 2024 01:10:59 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=axpjIn4E; spf=pass (domain: tuxon.dev, ip: 209.85.208.175, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lj1-f175.google.com with SMTP id 38308e7fff4ca-2e95a74d51fso24531591fa.2 for ; Wed, 29 May 2024 01:10:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970257; x=1717575057; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tOLHZx555kbJ+Nz+oy4ud3S/v5u8QAeS8Cx1sKq0Hlw=; b=axpjIn4E4VPSWo6eYcwYd4WOdmDyTCLSlVJoBuWf3v5V3FrxwsgcOMli9nOqvxz3bu jeaVmh6Pm100a2yu/KO03p17rJWFFzhXJ4T9OjSGZtYT13WTf89jS57x2z/hOWaHnhpT MOKcRqhZYFZli+5WTAFL9afjGoukE1zSlvSFIokh/fqQm4Ht92uFlJUQ50goPr9I6FFS In/95owFLd4dZAjHYGml2c256xkWQgGTre05PC2JQMzfb00/gic9xdmnnc5shYW8LJOf OWxJoF3t5y6LJ57yk9cZMJde8QBs/bhn/wofvcmPFVJBqiRJPf8qn3BgonDB3PA6gRmV dffg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970257; x=1717575057; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tOLHZx555kbJ+Nz+oy4ud3S/v5u8QAeS8Cx1sKq0Hlw=; b=Qnx/wj2hqF679QqoX9WJOk5QwRum40ARAH6XJ2q8L9zsjaCQtui2juGD8MD69TpU9/ E98di7+OMwl7IuCrBI/33w5kxT8iYh85Y7TU0xHh94F94ASV0qaGiqqYybW6arHEOTvN n44uHg/hFW4hL+fWZsmp8xvuOg3XHQzes6CtqtzqJqbbeYt2gLx2oI3xVmjSl00PNK3B 57uqxh6I73Uw0CcRYqTIXJSCA8qq1sPjQvYRY/yJDongYgWv6M8q28cmOxrjQiSxrQw6 OltfOPh44WHGqv1gEcp+9o9/8y1JsIQmlItNPn8LdaGRCjbCID6sBS/osM0vTdgs6DG/ YWhQ== X-Gm-Message-State: AOJu0YybdwOmg5N7OYKUYaM18LohrMe7J6tR9IEY1FtETdipTHk+Hsqe nDUicphkDy0kuSOiCi+xftCRgVejqOwYyGCofDNbrniTuO81bpwyX+s5/GheMAs= X-Google-Smtp-Source: AGHT+IGQp4kjwwbMdyMLJmU+bgeZS8bmDl6G8O/qottjaiZM82msMmjwujbhw5INAk330Z0wO6OYrg== X-Received: by 2002:a2e:961a:0:b0:2e5:6957:187a with SMTP id 38308e7fff4ca-2e95b041638mr112052231fa.4.1716970257536; Wed, 29 May 2024 01:10:57 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.10.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:10:56 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 10/47] net: ravb: Check return value of reset_control_deassert() Date: Wed, 29 May 2024 11:10:02 +0300 Message-Id: <20240529081039.639010-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15990 From: Claudiu Beznea commit d8eb6ea4b302e7ff78535c205510e359ac10a0bd upstream. reset_control_deassert() could return an error. Some devices cannot work if reset signal de-assert operation fails. To avoid this check the return code of reset_control_deassert() in ravb_probe() and take proper action. Along with it, the free_netdev() call from the error path was moved after reset_control_assert() on its own label (out_free_netdev) to free netdev in case reset_control_deassert() fails. Fixes: 0d13a1a464a0 ("ravb: Add reset support") Reviewed-by: Sergey Shtylyov Reviewed-by: Philipp Zabel Signed-off-by: Claudiu Beznea Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index c15a4d56e79f..ef7ab9a3ff29 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2666,7 +2666,10 @@ static int ravb_probe(struct platform_device *pdev) ndev->features = info->net_features; ndev->hw_features = info->net_hw_features; - reset_control_deassert(rstc); + error = reset_control_deassert(rstc); + if (error) + goto out_free_netdev; + pm_runtime_enable(&pdev->dev); error = pm_runtime_resume_and_get(&pdev->dev); if (error < 0) @@ -2895,12 +2898,12 @@ static int ravb_probe(struct platform_device *pdev) out_disable_refclk: clk_disable_unprepare(priv->refclk); out_release: - free_netdev(ndev); - pm_runtime_put(&pdev->dev); out_rpm_disable: pm_runtime_disable(&pdev->dev); reset_control_assert(rstc); +out_free_netdev: + free_netdev(ndev); return error; } From patchwork Wed May 29 08:10:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3512C41513 for ; Wed, 29 May 2024 08:11:05 +0000 (UTC) Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) by mx.groups.io with SMTP id smtpd.web11.8568.1716970260238349468 for ; Wed, 29 May 2024 01:11:00 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=qVAjRk6J; spf=pass (domain: tuxon.dev, ip: 209.85.128.47, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-4211e42e362so15721635e9.1 for ; Wed, 29 May 2024 01:11:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970259; x=1717575059; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fnYK0FlMFdlJH+oB0H6OKLH8zMQrUGogAWbkopNk9zI=; b=qVAjRk6JtM+JzIKwt0XpTGrmQ2W+y59eybEVoSSkRzU3mu5LoJhmERl0UYSmlpWmR4 Pj2kKgyc1Z9RJwTKr4X457Ohz94N6W0ac3xuSIcox6dsJivJCsgQUsxbHORbgN4lC1x8 SH/3/rJvr2uA7vNItwHu9hI6XWuiPySbOOYtMVPCfBMw62ceaHL3lcoqW823nDQ+PQZh 2/rrtL+6XVUTVf8vWj5L8mfg3R7JsTL70qwvpUUTtcfaqMtms14RyvBPEJ5VjFqQywqi e20a3fJy3IZanw/0dxzKh/PumVenUtaBtGne/4mietrIKX1gCqEzFk8Xa2CVvuVevxqD mnfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970259; x=1717575059; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fnYK0FlMFdlJH+oB0H6OKLH8zMQrUGogAWbkopNk9zI=; b=vhIQn8lIbG71Iytu5rzp3dJ7Zz3lZsNcMem1rO5xCP64/PhVfaJisY1IpR17nS5HXY +BjH8tEgWLuLcHBDbSDbFgpdGjwMIzNJOfHEc2baENLQPxxqwvg4X2zj+WKtAttg5QKS dFc/M1WlKghWcsjDuNtaGhr349uv5M83cnPAHuoEtvr9hkY3IeR65HTqKuoVARANxw0c OZgNltqBULPrPCqafxU8hy4vnZjhIC6pGKOuSBuErdNaaS5yM8UQKHz9RT3LOh0KwFsR ObQWuC9hLqGwVLVmUEVUxW+NB8fYRrCIL4fRSYjW7s19UJgX/9QhEnq+CE7b2R+Yo/vv Nhpg== X-Gm-Message-State: AOJu0YzU7gtCaCjeJQwdchjwfB0wK+eRB/U11TEPO8kooBeZKg9KE5Mc GE2PmQ8LBvzPTh6sD0NrdNGYCHqWl+ZY3Fe+kuzj64ou5DGrMbsK0UG0XRkNcX4= X-Google-Smtp-Source: AGHT+IFqrrqrRkNBsCkMBzo40fxtOf9xmiBvPKn6nEI3XO6lCX01YD5UYeLnMAqtOb8jAvRJ57ELZA== X-Received: by 2002:a05:600c:314d:b0:421:7ad:daab with SMTP id 5b1f17b1804b1-42108a4f606mr105500695e9.7.1716970258746; Wed, 29 May 2024 01:10:58 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.10.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:10:58 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 11/47] net: ravb: Make write access to CXR35 first before accessing other EMAC registers Date: Wed, 29 May 2024 11:10:03 +0300 Message-Id: <20240529081039.639010-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:05 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15991 From: Claudiu Beznea commit d78c0ced60d5e2f8b5a4a0468a5c400b24aeadf2 upstream. Hardware manual of RZ/G3S (and RZ/G2L) specifies the following on the description of CXR35 register (chapter "PHY interface select register (CXR35)"): "After release reset, make write-access to this register before making write-access to other registers (except MDIOMOD). Even if not need to change the value of this register, make write-access to this register at least one time. Because RGMII/MII MODE is recognized by accessing this register". The setup procedure for EMAC module (chapter "Setup procedure" of RZ/G3S, RZ/G2L manuals) specifies the E-MAC.CXR35 register is the first EMAC register that is to be configured. Note [A] from chapter "PHY interface select register (CXR35)" specifies the following: [A] The case which CXR35 SEL_XMII is used for the selection of RGMII/MII in APB Clock 100 MHz. (1) To use RGMII interface, Set ‘H’03E8_0000’ to this register. (2) To use MII interface, Set ‘H’03E8_0002’ to this register. Take into account these indication. Fixes: 1089877ada8d ("ravb: Add RZ/G2L MII interface support") Reviewed-by: Sergey Shtylyov Signed-off-by: Claudiu Beznea Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index ef7ab9a3ff29..420d6926d33d 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -514,6 +514,15 @@ static void ravb_emac_init_gbeth(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); + if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { + ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); + ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); + } else { + ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35); + ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, + CXR31_SEL_LINK0); + } + /* Receive frame limit set register */ ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR); @@ -536,14 +545,6 @@ static void ravb_emac_init_gbeth(struct net_device *ndev) /* E-MAC interrupt enable register */ ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); - - if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { - ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); - ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); - } else { - ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, - CXR31_SEL_LINK0); - } } static void ravb_emac_init_rcar(struct net_device *ndev) From patchwork Wed May 29 08:10:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678240 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D9C4C25B75 for ; Wed, 29 May 2024 08:11:06 +0000 (UTC) Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) by mx.groups.io with SMTP id smtpd.web11.8571.1716970263706604245 for ; Wed, 29 May 2024 01:11:04 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=C854Km0D; spf=pass (domain: tuxon.dev, ip: 209.85.167.41, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-5238b7d0494so2206248e87.3 for ; Wed, 29 May 2024 01:11:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970262; x=1717575062; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vo5fKBw87CvhptCwnAJhn1ZB3RBppO2dvL2JdH8m2VM=; b=C854Km0DvDv4cdP8x7+Uv72O2Cfv88NvYXJr9eK9LJqOzmls0NN4YLcwbebbYAWaLz ZlKSC5Hoo7UGdKQtB9McCvffcIxIivUAHAq7DfbNsdA3jRVdih2mFwbGrhd3skiM1QmL LNRDkwNJhAcrrBowYttC/wJvMk/YmU6PZpyKxBnnu7ML6/cstFGrdOT5qdGPQ4EN9CBm 0060vaUDmLgGYzqOmCi4MSr0hshyip9sYFUQ6iCBh+V7R/U83IThiKvdQvz3M56gYcBV fYGfD7OsrlSSq0U6SHGoy+g6RndXuv7hTQq0vM7PZtOPkjcV+zy4FLJ7p3BlmrbLB+6+ jYjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970262; x=1717575062; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vo5fKBw87CvhptCwnAJhn1ZB3RBppO2dvL2JdH8m2VM=; b=oC5l914jHzDteBg9vrFW7E8iZOIYu5hvTiHULHNELaoXXAgFzAWOvylmPh5s+COBHN bHsIRK9fH3HEvIsQIHWZ/sGl6WhTf6tIAI8EtrvK9u8G8XdQbpNRkxHboPs16mOrQlam dX8pLDfQf09JGebRmv81KsNHbhDcjMSfWXcGn35lHQwZcrBoiqXmgkka3JjREQ2/PtbG 6zZyB+l6frD1BSGrRaTFTRGlJohAwlqVxpTtVt8GDGCC6HMydhcT0ZH0cZHvWuODdhHm ad/8AqQeVpkqrwzcfD9+ZRtdM0gaxYfRCpBfseKDtJSdD3mlK4y1gQVYCYlTPKjYABsE x4ag== X-Gm-Message-State: AOJu0YwLqBViexkUcCGEX2eVZsejtfaT7E0cRGyiiApWX7Dr/Zzeuehh +52jDTD9zoBwzKSmj32AY7Dle0wGzHuDBb4TSip07rhc5QFtlgfmmNcz5NcZSmE= X-Google-Smtp-Source: AGHT+IFx2YcaILCUoapx+QbhZ/EXHJWTOQBID7U1b8Pn4L5exzSHEmDEByQKjQA0srd4stL/pTEOcA== X-Received: by 2002:a05:6512:794:b0:529:46e:b2a5 with SMTP id 2adb3069b0e04-52964eac45fmr12081289e87.2.1716970261027; Wed, 29 May 2024 01:11:01 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.10.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:00 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 12/47] net: ravb: Stop DMA in case of failures on ravb_open() Date: Wed, 29 May 2024 11:10:04 +0300 Message-Id: <20240529081039.639010-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:06 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15992 From: Claudiu Beznea commit eac16a733427ba0de2449ffc7bd3da32ddb65cb7 upstream. In case ravb_phy_start() returns with error the settings applied in ravb_dmac_init() are not reverted (e.g. config mode). For this call ravb_stop_dma() on failure path of ravb_open(). Fixes: a0d2f20650e8 ("Renesas Ethernet AVB PTP clock driver") Reviewed-by: Sergey Shtylyov Signed-off-by: Claudiu Beznea Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 420d6926d33d..17a461ae84ef 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1843,6 +1843,7 @@ static int ravb_open(struct net_device *ndev) /* Stop PTP Clock driver */ if (info->gptp) ravb_ptp_stop(ndev); + ravb_stop_dma(ndev); out_free_irq_mgmta: if (!info->multi_irqs) goto out_free_irq; From patchwork Wed May 29 08:10:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678242 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C287C25B7C for ; Wed, 29 May 2024 08:11:16 +0000 (UTC) Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by mx.groups.io with SMTP id smtpd.web10.8641.1716970266872002858 for ; Wed, 29 May 2024 01:11:07 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=fouOiQ/P; spf=pass (domain: tuxon.dev, ip: 209.85.128.46, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-4202ca70270so21099385e9.3 for ; Wed, 29 May 2024 01:11:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970265; x=1717575065; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iQAHUJGjPROmWGGyTUMWT0CDvD42t4CgjOPY+7RlqZ4=; b=fouOiQ/PmRe+PxT/bX9IGindF3DOrrRHrIlRJIRP6PQE6+sOp9xl2YKLZT5tdYBKLo 7hA+xo26DkXdcx3pjLrXFpWkGuGsKBHSuWCDPQYuinwGhh0rOSxoWI32hH7NsZTI4CVU SqGkL44fWxKRK/7ZEsicx4J04Sw6rSjdHSleybDOl0kzSrsGEFh0O+a7F4JQsl07vPQ8 SEXiczQNsd7HPZpeN1x2RYxIrYga+hZ3AuOfkLBs9sRqiDk8cBBoL5Gn4o1ut7EXdN/8 E1jEREAy4IsBZYsdAsArfWjXXjKPYQKTnhoOqxtg3CWAf6RJSpPgBMz1yqFuvL+Su6Lf ZJpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970265; x=1717575065; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iQAHUJGjPROmWGGyTUMWT0CDvD42t4CgjOPY+7RlqZ4=; b=nun0Cli97E+WDv8IrvKAR22qbLxhRIrFRuLmAROMWMXLtU+TsyhlVoOIAi6c8gCQDJ QJRBZmETsIlwXrJ6ed+XBQgRQwusdPM1NB66JilK0mQOmjzXdIe25BZTHNctKdeqqKGx gO6UHw9EIozvsd1CKi7+Y8IZbKabvmxJupgI5qiav7qbAWwxOKLDK3dPGjtdHlnWVx8C tAEX0dxEY7V4WFoowUV4ygOYXUjumfnKsn0ru6aY8G2N5KHj5GR3HrYdaDZ9dXg19fUM BQHz9M4p8iEA5IVNkOs1GKFw0O0zNskR7RlInZNIFn6AgCsG/Ee8lGCmBxDXZXfBIMx2 gU4g== X-Gm-Message-State: AOJu0YyE/w4GSF5hvghHKBWn9ESmQzFBDDX3ZDQ+fl2bzCvNqJqBSndh c2KUEaBBlGDGXvxbGBZ55vTq7pR5fbImDsBoh+Wey4VcDLqZAxWsnUP9kQwSvDs1z0jq5kD1HNi dbqk= X-Google-Smtp-Source: AGHT+IHkRtgywwDFsif8LFoSCu4biQAjaS4FS/EcnLcr66jT5/5AAYifyaX4VYH8A0JFRuKIMXaZVQ== X-Received: by 2002:a7b:ce8c:0:b0:41b:edf4:4071 with SMTP id 5b1f17b1804b1-42108aa6fc3mr168473945e9.35.1716970265238; Wed, 29 May 2024 01:11:05 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:04 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 13/47] net: ravb: Keep reverse order of operations in ravb_remove() Date: Wed, 29 May 2024 11:10:05 +0300 Message-Id: <20240529081039.639010-14-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:16 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15993 From: Claudiu Beznea commit edf9bc396e05081ca281ffb0cd41e44db478ff26 upstream. On RZ/G3S SMARC Carrier II board having RGMII connections b/w Ethernet MACs and PHYs it has been discovered that doing unbind/bind for ravb driver in a loop leads to wrong speed and duplex for Ethernet links and broken connectivity (the connectivity cannot be restored even with bringing interface down/up). Before doing unbind/bind the Ethernet interfaces were configured though systemd. The sh instructions used to do unbind/bind were: $ cd /sys/bus/platform/drivers/ravb/ $ while :; do echo 11c30000.ethernet > unbind ; \ echo 11c30000.ethernet > bind; done It has been discovered that there is a race b/w IOCTLs initialized by systemd at the response of success binding and the "ravb_write(ndev, CCC_OPC_RESET, CCC)" call in ravb_remove() as follows: 1/ as a result of bind success the user space open/configures the interfaces tough an IOCTL; the following stack trace has been identified on RZ/G3S: Call trace: dump_backtrace+0x9c/0x100 show_stack+0x20/0x38 dump_stack_lvl+0x48/0x60 dump_stack+0x18/0x28 ravb_open+0x70/0xa58 __dev_open+0xf4/0x1e8 __dev_change_flags+0x198/0x218 dev_change_flags+0x2c/0x80 devinet_ioctl+0x640/0x708 inet_ioctl+0x1e4/0x200 sock_do_ioctl+0x50/0x108 sock_ioctl+0x240/0x358 __arm64_sys_ioctl+0xb0/0x100 invoke_syscall+0x50/0x128 el0_svc_common.constprop.0+0xc8/0xf0 do_el0_svc+0x24/0x38 el0_svc+0x34/0xb8 el0t_64_sync_handler+0xc0/0xc8 el0t_64_sync+0x190/0x198 2/ this call may execute concurrently with ravb_remove() as the unbind/bind operation was executed in a loop 3/ if the operation mode is changed to RESET (through ravb_write(ndev, CCC_OPC_RESET, CCC) call in ravb_remove()) while the above ravb_open() is in progress it may lead to MAC (or PHY, or MAC-PHY connection, the right point hasn't been identified at the moment) to be broken, thus the Ethernet connectivity fails to restore. The simple fix for this is to move ravb_write(ndev, CCC_OPC_RESET, CCC)) after unregister_netdev() to avoid resetting the controller while the netdev interface is still registered. To avoid future issues in ravb_remove(), the patch follows the proper order of operations in ravb_remove(): reverse order compared with ravb_probe(). This avoids described races as the IOCTLs as well as unregister_netdev() (called now at the beginning of ravb_remove()) calls rtnl_lock() before continuing and IOCTLs check (though devinet_ioctl()) if device is still registered just after taking the lock: int devinet_ioctl(struct net *net, unsigned int cmd, struct ifreq *ifr) { // ... rtnl_lock(); ret = -ENODEV; dev = __dev_get_by_name(net, ifr->ifr_name); if (!dev) goto done; // ... done: rtnl_unlock(); out: return ret; } Fixes: c156633f1353 ("Renesas Ethernet AVB driver proper") Reviewed-by: Sergey Shtylyov Signed-off-by: Claudiu Beznea Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 17a461ae84ef..9362f60a584d 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2915,22 +2915,26 @@ static int ravb_remove(struct platform_device *pdev) struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; - /* Stop PTP Clock driver */ - if (info->ccc_gac) - ravb_ptp_stop(ndev); - - clk_disable_unprepare(priv->gptp_clk); - clk_disable_unprepare(priv->refclk); - - /* Set reset mode */ - ravb_write(ndev, CCC_OPC_RESET, CCC); unregister_netdev(ndev); if (info->nc_queues) netif_napi_del(&priv->napi[RAVB_NC]); netif_napi_del(&priv->napi[RAVB_BE]); + ravb_mdio_release(priv); + + /* Stop PTP Clock driver */ + if (info->ccc_gac) + ravb_ptp_stop(ndev); + dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, priv->desc_bat_dma); + + /* Set reset mode */ + ravb_write(ndev, CCC_OPC_RESET, CCC); + + clk_disable_unprepare(priv->gptp_clk); + clk_disable_unprepare(priv->refclk); + pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); reset_control_assert(priv->rstc); From patchwork Wed May 29 08:10:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678246 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69DE5C27C50 for ; Wed, 29 May 2024 08:11:16 +0000 (UTC) Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.groups.io with SMTP id smtpd.web11.8573.1716970268016269243 for ; Wed, 29 May 2024 01:11:08 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=Wnylr+ei; spf=pass (domain: tuxon.dev, ip: 209.85.128.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-42120e3911eso12040265e9.0 for ; Wed, 29 May 2024 01:11:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970266; x=1717575066; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SIlnHj9VBbONH267YeDVwHcJgFeFOsKkBKHMRk/Tg1o=; b=Wnylr+ei0MYVJyNWSarW9TP7FKQ1w6ENT+Rw2UOcYexQyjqXVNsihHq4Jtfm9wuLsp WUHcPeuaXqnxk27OJVGFYlOUuMeln3f/GAeAHkd7kGo0MI/KNHm7gKvtCqzOmsQd6zx1 UQyNMKsWzOW05W1qDfUuZPpkXEe+q5HQYSCAHBfEwLbe/2IrawEHwUvzSuO5dvrrhRqe u6CCvf+vQ1hlsWZXK7qHCmpKhieUH4GG1bBaUbimuoTJKZtJC4X/pgIxU1kgte9PXNnd ZzypdCihd1BwYxStxjVv3crhvKoD+/dvorfPN1IecFEExg0dlpZz0EtZKPa+VDl+zEfc ib0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970266; x=1717575066; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SIlnHj9VBbONH267YeDVwHcJgFeFOsKkBKHMRk/Tg1o=; b=blDWG6kGNTlwPf/nzNj8RcwitYScS1OI6RKPxAFfQdBDBgodwW26V1NQVb/DfpZTl3 g7ZLwkZ6FQ/hHX1T9l8VRCNk8hLbq4x3t/LsK8b/qWuiaOkuPQEWjn3668WWFjInegwE JyFmSj2YbekaCZEhZ9ajD2BJTalijHlHG6q4LAXrk5FHqekVqlf810P1bVEoxgwJsFUX 2ktVVG3+33G4sopWrmlJvz042zm5d0BijoVMC+CPLAWrhsPSxWP2bGE/reV+bvISaJnI 1c428qjbAXQQU+EHl+WwPMjRy3dmTt9OPHfRciadapXsRTsJ8N9vMtpuuiWgNeJ2CvVh x5yA== X-Gm-Message-State: AOJu0Yx9FSj9Jej17A++Tpsap6J+2I8AkYoZqh4e6H5hiuEQnf57UQwd bCZx2RQ6zYpAd6RwxBmiZFmIHaCNXGePfq93xZ4zCvtLcQB+QghIYYe2X7BK4cw= X-Google-Smtp-Source: AGHT+IFmaTy0aFfpK4A+bvsgoV7A6jjl5YrS2f2gb2B6+tqsU4H5pyZdOk1CcnjHyn9dcd31CxHOww== X-Received: by 2002:a05:600c:3b1d:b0:421:129e:98a0 with SMTP id 5b1f17b1804b1-421129e9a97mr75441775e9.19.1716970266423; Wed, 29 May 2024 01:11:06 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:06 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 14/47] net: ravb: Wait for operating mode to be applied Date: Wed, 29 May 2024 11:10:06 +0300 Message-Id: <20240529081039.639010-15-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:16 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15994 From: Claudiu Beznea commit 9039cd4c61635b2d541009a7cd5e2cc052402f28 upstream. CSR.OPS bits specify the current operating mode and (according to documentation) they are updated by HW when the operating mode change request is processed. To comply with this check CSR.OPS before proceeding. Commit introduces ravb_set_opmode() that does all the necessities for setting the operating mode (set CCC.OPC (and CCC.GAC, CCC.CSEL, if any) and wait for CSR.OPS) and call it where needed. This should comply with all the HW manuals requirements as different manual variants specify that different modes need to be checked in CSR.OPS when setting CCC.OPC. If gPTP active in config mode is supported and it needs to be enabled, the CCC.GAC and CCC.CSEL needs to be configured along with CCC.OPC in the same write access. For this, ravb_set_opmode() allows passing GAC and CSEL as part of opmode and the function updates accordingly CCC register. Fixes: c156633f1353 ("Renesas Ethernet AVB driver proper") Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: David S. Miller Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 65 +++++++++++++++--------- 1 file changed, 42 insertions(+), 23 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 9362f60a584d..1420c41b6480 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -69,16 +69,27 @@ int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) return -ETIMEDOUT; } -static int ravb_config(struct net_device *ndev) +static int ravb_set_opmode(struct net_device *ndev, u32 opmode) { + u32 csr_ops = 1U << (opmode & CCC_OPC); + u32 ccc_mask = CCC_OPC; int error; - /* Set config mode */ - ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); - /* Check if the operating mode is changed to the config mode */ - error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); - if (error) - netdev_err(ndev, "failed to switch device to config mode\n"); + /* If gPTP active in config mode is supported it needs to be configured + * along with CSEL and operating mode in the same access. This is a + * hardware limitation. + */ + if (opmode & CCC_GAC) + ccc_mask |= CCC_GAC | CCC_CSEL; + + /* Set operating mode */ + ravb_modify(ndev, CCC, ccc_mask, opmode); + /* Check if the operating mode is changed to the requested one */ + error = ravb_wait(ndev, CSR, CSR_OPS, csr_ops); + if (error) { + netdev_err(ndev, "failed to switch device to requested mode (%u)\n", + opmode & CCC_OPC); + } return error; } @@ -672,7 +683,7 @@ static int ravb_dmac_init(struct net_device *ndev) int error; /* Set CONFIG mode */ - error = ravb_config(ndev); + error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); if (error) return error; @@ -681,9 +692,7 @@ static int ravb_dmac_init(struct net_device *ndev) return error; /* Setting the control will start the AVB-DMAC process. */ - ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); - - return 0; + return ravb_set_opmode(ndev, CCC_OPC_OPERATION); } static void ravb_get_tx_tstamp(struct net_device *ndev) @@ -1045,7 +1054,7 @@ static int ravb_stop_dma(struct net_device *ndev) return error; /* Stop AVB-DMAC process */ - return ravb_config(ndev); + return ravb_set_opmode(ndev, CCC_OPC_CONFIG); } /* E-MAC interrupt handler */ @@ -2572,21 +2581,25 @@ static int ravb_set_gti(struct net_device *ndev) return 0; } -static void ravb_set_config_mode(struct net_device *ndev) +static int ravb_set_config_mode(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; + int error; if (info->gptp) { - ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); + error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); + if (error) + return error; /* Set CSEL value */ ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); } else if (info->ccc_gac) { - ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | - CCC_GAC | CCC_CSEL_HPB); + error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB); } else { - ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); + error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); } + + return error; } /* Set tx and rx clock internal delay modes */ @@ -2806,7 +2819,9 @@ static int ravb_probe(struct platform_device *pdev) ndev->ethtool_ops = &ravb_ethtool_ops; /* Set AVB config mode */ - ravb_set_config_mode(ndev); + error = ravb_set_config_mode(ndev); + if (error) + goto out_disable_gptp_clk; if (info->gptp || info->ccc_gac) { /* Set GTI value */ @@ -2929,8 +2944,7 @@ static int ravb_remove(struct platform_device *pdev) dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, priv->desc_bat_dma); - /* Set reset mode */ - ravb_write(ndev, CCC_OPC_RESET, CCC); + ravb_set_opmode(ndev, CCC_OPC_RESET); clk_disable_unprepare(priv->gptp_clk); clk_disable_unprepare(priv->refclk); @@ -3017,8 +3031,11 @@ static int __maybe_unused ravb_resume(struct device *dev) int ret = 0; /* If WoL is enabled set reset mode to rearm the WoL logic */ - if (priv->wol_enabled) - ravb_write(ndev, CCC_OPC_RESET, CCC); + if (priv->wol_enabled) { + ret = ravb_set_opmode(ndev, CCC_OPC_RESET); + if (ret) + return ret; + } /* All register have been reset to default values. * Restore all registers which where setup at probe time and @@ -3026,7 +3043,9 @@ static int __maybe_unused ravb_resume(struct device *dev) */ /* Set AVB config mode */ - ravb_set_config_mode(ndev); + ret = ravb_set_config_mode(ndev); + if (ret) + return ret; if (info->gptp || info->ccc_gac) { /* Set GTI value */ From patchwork Wed May 29 08:10:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678241 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E47DC41513 for ; Wed, 29 May 2024 08:11:16 +0000 (UTC) Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by mx.groups.io with SMTP id smtpd.web11.8574.1716970269103757782 for ; Wed, 29 May 2024 01:11:09 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=inCVSpeG; spf=pass (domain: tuxon.dev, ip: 209.85.128.45, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-42120e3911eso12040355e9.0 for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:07 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 15/47] net: ravb: Count packets instead of descriptors in GbEth RX path Date: Wed, 29 May 2024 11:10:07 +0300 Message-Id: <20240529081039.639010-16-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:16 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15995 From: Paul Barker commit ed4adc07207d9165a4b3b36199231a22e9f51a55 upstream. The units of "work done" in the RX path should be packets instead of descriptors, as large packets can be spread over multiple descriptors. Fixes: 1c59eb678cbd ("ravb: Fillup ravb_rx_gbeth() stub") Signed-off-by: Paul Barker Reviewed-by: Sergey Shtylyov Link: https://lore.kernel.org/r/20240214151204.2976-1-paul.barker.ct@bp.renesas.com Signed-off-by: Jakub Kicinski Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 1420c41b6480..6cc3dc8d85f4 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -771,29 +771,25 @@ static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) struct ravb_rx_desc *desc; struct sk_buff *skb; dma_addr_t dma_addr; + int rx_packets = 0; u8 desc_status; - int boguscnt; u16 pkt_len; u8 die_dt; int entry; int limit; + int i; entry = priv->cur_rx[q] % priv->num_rx_ring[q]; - boguscnt = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; + limit = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; stats = &priv->stats[q]; - boguscnt = min(boguscnt, *quota); - limit = boguscnt; desc = &priv->gbeth_rx_ring[entry]; - while (desc->die_dt != DT_FEMPTY) { + for (i = 0; i < limit && rx_packets < *quota && desc->die_dt != DT_FEMPTY; i++) { /* Descriptor type must be checked before all other reads */ dma_rmb(); desc_status = desc->msc; pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; - if (--boguscnt < 0) - break; - /* We use 0-byte descriptors to mark the DMA mapping errors */ if (!pkt_len) continue; @@ -819,7 +815,7 @@ static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) skb_put(skb, pkt_len); skb->protocol = eth_type_trans(skb, ndev); napi_gro_receive(&priv->napi[q], skb); - stats->rx_packets++; + rx_packets++; stats->rx_bytes += pkt_len; break; case DT_FSTART: @@ -847,7 +843,7 @@ static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) eth_type_trans(priv->rx_1st_skb, ndev); napi_gro_receive(&priv->napi[q], priv->rx_1st_skb); - stats->rx_packets++; + rx_packets++; stats->rx_bytes += pkt_len; break; } @@ -886,9 +882,9 @@ static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) desc->die_dt = DT_FEMPTY; } - *quota -= limit - (++boguscnt); - - return boguscnt <= 0; + stats->rx_packets += rx_packets; + *quota -= rx_packets; + return *quota == 0; } /* Packet receive function for Ethernet AVB */ From patchwork Wed May 29 08:10:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678245 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44BE0C25B75 for ; Wed, 29 May 2024 08:11:16 +0000 (UTC) Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) by mx.groups.io with SMTP id smtpd.web10.8643.1716970270826544824 for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:08 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 16/47] ethernet: renesas: Use div64_ul instead of do_div Date: Wed, 29 May 2024 11:10:08 +0300 Message-Id: <20240529081039.639010-17-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:16 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15996 From: Yang Li commit d9f31aeaa1e5aefa68130878af3c3513d41c1e2d upstream. do_div() does a 64-by-32 division. Here the divisor is an unsigned long which on some platforms is 64 bit wide. So use div64_ul instead of do_div to avoid a possible truncation. Eliminate the following coccicheck warning: ./drivers/net/ethernet/renesas/ravb_main.c:2492:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead. Reported-by: Abaci Robot Signed-off-by: Yang Li Reviewed-by: Geert Uytterhoeven Reviewed-by: Sergey Shtylyov Link: https://lore.kernel.org/r/1637228883-100100-1-git-send-email-yang.lee@linux.alibaba.com Signed-off-by: Jakub Kicinski Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 6cc3dc8d85f4..9b6594ef011b 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -30,8 +30,7 @@ #include #include #include - -#include +#include #include "ravb.h" @@ -2563,8 +2562,7 @@ static int ravb_set_gti(struct net_device *ndev) if (!rate) return -EINVAL; - inc = 1000000000ULL << 20; - do_div(inc, rate); + inc = div64_ul(1000000000ULL << 20, rate); if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", From patchwork Wed May 29 08:10:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 497C5C27C44 for ; Wed, 29 May 2024 08:11:16 +0000 (UTC) Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) by mx.groups.io with SMTP id smtpd.web11.8575.1716970272611886580 for ; Wed, 29 May 2024 01:11:12 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=UCizq0hN; spf=pass (domain: tuxon.dev, ip: 209.85.167.44, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f44.google.com with SMTP id 2adb3069b0e04-52a6ef5e731so765183e87.0 for ; Wed, 29 May 2024 01:11:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970271; x=1717575071; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NVoK2RgdcMTKBoqzAy0bfobXWH9WMI+Aknn/n1mx1X0=; b=UCizq0hNO/hInr7Uzm5PPw07UUAIMHtq2VWsuTPGYsEUGAiJeMR8FzLrQhyIrhhuh8 qxnfqkm9tW1AqMjiYT7DlFuyXZ0pMbqHlN/trbOzaxTHsCsO1b06KO6PvvCt1yet2l0O 1mvDRPvPbHIuNvsYNmOA9w827fyqKksC84dVChItlFaJHkNbiTfgMvQDFKDvgcoDyT18 +K41zT54qf8tI/PTSeOBVcR0szfMLW/sVtRas+I70WqgWdaiRevS7JVFkWSSOalKsSau GL4WEhoLqL6eFKutrIfbQvHKvp5N1iT8V6Hgzau/onCXLxiYdWscgldBnBVINTQJk6f2 aYuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970271; x=1717575071; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NVoK2RgdcMTKBoqzAy0bfobXWH9WMI+Aknn/n1mx1X0=; b=gZ1Bsja22iUACNoo3RyIAw1yBf8ZfQTAZ/esV9JFFE8Ld+5YRxZ2Eql7tF1xPAK8if 5UY9WyeLw6yRnzh+X0tHSWXFt+kcbad5hA1ab3HMZb6UTNiA2eU9qiocVf4UI7+1ilBP Eqxk1/XjCiey/A8wHqW168XtRdnROSWTqxhzRsF6wOxXcc2FNFROIDZGUgsaFSC7OW1g J0OlzkOuTmPqke81r7fbwkoa+dDzc3D99R/BPj/l9PbZm1zTHXR4u88DIbH4BLefN0eH WsZWmvOLzSbvHTlPlpy1dgqDDXHwK/PL0iUsxSFBcGCfHteHRIiaM53KAQJ+PI2maSO5 vzpg== X-Gm-Message-State: AOJu0YxUwJB2oZiL1ITnQdraiqGS85cE0rm+/rmo5pjc4cbjjLVfzW7J 3nBisDCRrev0hOc5Z/bMCNXrwPDn9D6Qiuajm6XFQgrieiYybXh+wD0zHmSfFdE= X-Google-Smtp-Source: AGHT+IGc/qmbrbqg3WBLiqd6/RRlszlVWv4YZHw5OCAvGtXNWCXmTKzXzGbgtg8AjXuA48A2d+cmAA== X-Received: by 2002:a19:7705:0:b0:523:bb4c:7b99 with SMTP id 2adb3069b0e04-5296420821fmr8959178e87.8.1716970270833; Wed, 29 May 2024 01:11:10 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:10 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 17/47] ravb: ravb_close() always returns 0 Date: Wed, 29 May 2024 11:10:09 +0300 Message-Id: <20240529081039.639010-18-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:16 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15997 From: Sergey Shtylyov commit be94a51f3e5eee72ba4251c1b1c463872b03cf54 upstream. ravb_close() always returns 0, hence the check in ravb_wol_restore() is pointless (however, we cannot change the prototype of ravb_close() as it implements the driver's ndo_stop() method). Found by Linux Verification Center (linuxtesting.org) with the SVACE static analysis tool. Signed-off-by: Sergey Shtylyov Signed-off-by: David S. Miller Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 9b6594ef011b..0c803f697825 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2979,7 +2979,6 @@ static int ravb_wol_restore(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; - int ret; if (info->nc_queues) napi_enable(&priv->napi[RAVB_NC]); @@ -2988,9 +2987,7 @@ static int ravb_wol_restore(struct net_device *ndev) /* Disable MagicPacket */ ravb_modify(ndev, ECMR, ECMR_MPDE, 0); - ret = ravb_close(ndev); - if (ret < 0) - return ret; + ravb_close(ndev); return disable_irq_wake(priv->emac_irq); } From patchwork Wed May 29 08:10:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D8BEC25B7E for ; Wed, 29 May 2024 08:11:16 +0000 (UTC) Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) by mx.groups.io with SMTP id smtpd.web10.8644.1716970274489228161 for ; Wed, 29 May 2024 01:11:14 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=Ygt+0/Tc; spf=pass (domain: tuxon.dev, ip: 209.85.128.48, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-42120fc8d1dso12651865e9.2 for ; Wed, 29 May 2024 01:11:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970273; x=1717575073; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ObUMt87zR5wNoXAOudqiZOvZcx8Oy7K4WW+L5RX9pUA=; b=Ygt+0/Tc0usfYHS1QcKFHPLAZCiGI9Fgr36AZKkAUYNXnEmt2u0anulNuGTPq6Sjhk lpfdg2f1BE4E8ys8bY86yFI0FckzXt5dJB2qamYDW9iaRAAk286gUPhG/4Fgq0ZCcxTn hPB16Sbq8QszfzmHVxKGtRzImM4YmLkWtreW795Y/QznrcEr6q5oiRu2wjEUsdceHfbr 8ysCUFWhf5XiURfI8gwKh71z3j7SdrGpA9EF1b2T1EkKNVSkVOLfuSXtgljFTRa9Xdym fOeUnE9E6cEMmOIcza2CSvJgNum4H+WzJTcYALqRB3VfyGqq642iP9mOKTlg43YtdBT+ f2xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970273; x=1717575073; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ObUMt87zR5wNoXAOudqiZOvZcx8Oy7K4WW+L5RX9pUA=; b=fPFLD7s0J0yD9W8Nj/DYKRqLhi5HnEhYWwNJ99BD6GR9uLhzsHOZzPDz8HoQSuOo/3 EvqOrnkjS1kJtMWwXyNt5v9qy9CpqpHaNS7xthOuyNirLdCnysjcmWCuOI0xmrvJ4ikl ASc94NgxWLbDLYiaFbZM5RZnu0JfN2JkAoE4nx/nwrqFWMXFOuXsIf0MiLTipOjPE0kp cIzeb3mY/sPj3EGmt7deV7NJrlKSldGsVOhVRnaMVkjQfTHvmuStH5A4wDXzjjHTP+4V zm0z2kRNfOOKSluS8RcwOV+Ozajul1FqN/luYFoQuhSDdDUz8vTV13C5jT2ELFA8j5aw qvlQ== X-Gm-Message-State: AOJu0Yxon9AuAnvPylHTEdutHTgr+TFLQdFG9dKPPf1RgonKpAursS8B nv+st9mDhVxsJk3sDbxho/KmVwIbI0FC3DDAVix881FYCwO92WD5gjBArSlRBHE= X-Google-Smtp-Source: AGHT+IEnDzVZYXNAbrPDMRBTvZl8c2gqNlB4BNYjqI4j0z2vI6YQtskEUFnveo8kKvZPCyMft0KqhA== X-Received: by 2002:a05:600c:45d4:b0:41c:ab7:fa0f with SMTP id 5b1f17b1804b1-42108aba51fmr113675795e9.34.1716970272967; Wed, 29 May 2024 01:11:12 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:11 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 18/47] ravb: Use GFP_KERNEL instead of GFP_ATOMIC when possible Date: Wed, 29 May 2024 11:10:10 +0300 Message-Id: <20240529081039.639010-19-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:16 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15998 From: Christophe JAILLET commit 91398a960edf50d27206d808182e3357f9f5c668 upstream. 'max_rx_len' can be up to GBETH_RX_BUFF_MAX (i.e. 8192) (see 'gbeth_hw_info'). The default value of 'num_rx_ring' can be BE_RX_RING_SIZE (i.e. 1024). So this loop can allocate 8 Mo of memory. Previous memory allocations in this function already use GFP_KERNEL, so use __netdev_alloc_skb() and an explicit GFP_KERNEL instead of a implicit GFP_ATOMIC. This gives more opportunities of successful allocation. Signed-off-by: Christophe JAILLET Reviewed-by: Sergey Shtylyov Reviewed-by: Biju Das Signed-off-by: David S. Miller Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 0c803f697825..ed19026e0976 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -482,7 +482,7 @@ static int ravb_ring_init(struct net_device *ndev, int q) goto error; for (i = 0; i < priv->num_rx_ring[q]; i++) { - skb = netdev_alloc_skb(ndev, info->max_rx_len); + skb = __netdev_alloc_skb(ndev, info->max_rx_len, GFP_KERNEL); if (!skb) goto error; ravb_set_buffer_align(skb); From patchwork Wed May 29 08:10:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678247 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 608DAC25B75 for ; Wed, 29 May 2024 08:11:26 +0000 (UTC) Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) by mx.groups.io with SMTP id smtpd.web10.8645.1716970276041530704 for ; Wed, 29 May 2024 01:11:16 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=WWtR0IkT; spf=pass (domain: tuxon.dev, ip: 209.85.128.50, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-421087b6f3fso15309315e9.1 for ; Wed, 29 May 2024 01:11:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970274; x=1717575074; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WuC1pmed93/VuJSLGFO56pT00C9lVNQIsULD3rUi6GE=; b=WWtR0IkTT8naMwNmhcVe4j52xjL20Ppr40wUeJn7bDl/66AK99JQrxRuTq7VsVeIXx v32RWz8C9Wq6M91tuM5CmN8F/nKCPulgNBvosAms+BoLvqyOHv2alfAnXBHB2fTTGfKv akoa1yR60stcZzWfS8RFDQajnubPLA1CdWXfR0spI78dWzBrMdXI3R41uak3pG8EdVuH YQWsOW7hcHViaA+fvhGlwMbD4RQrO771NXg4unHmlUHfXiRBafkIxd0Qoff86X28vm/U Xts1HI9V5Yzc35Rvf9eSljxQZDEi8bTh5ReRF3qfY3f/XgY2TXRuSogk5oKeaQO1OM+j OyOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970274; x=1717575074; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WuC1pmed93/VuJSLGFO56pT00C9lVNQIsULD3rUi6GE=; b=DRkOHeRJ04MgOEFjDi/295hu5u+TCYtKiPB6myBsRmalv9tJzcIXWoD6FqRweMkrH/ E/np3TXozyQsJd7daCkMMFUOz7v7xjXEyW09B/bBIBDlojgIACZL32S01attzigqioWf 1e39vc/2AcBOhjlNy5qGxOaVV+O3dO80BDeJ5Qx6qAYmy90MjJXEoT83XzPtS5L7cffN ZNZ8DSB/yrMAnwrZ8WhX+FNTckZt5Kva4ley994Kp3KOlvie+DiPxNk/Pfa+imZm+ZUv CshOuzoxj5mVJMNr9CcRpRrzv3iNKrZ0DousCakyiufkgz6MWRm56cai05Zd+s9LR1oC c2yA== X-Gm-Message-State: AOJu0YwwSNZp2VKKlSsDanMBYBok1+0PF3vJMR8hqkYxIKO7cYBjoWWf dYkRA+w9zkCfvsC0C84rSHbeOl3927w7tghFexbIWUJUTj2cBZHSTuT/OOpIqeA= X-Google-Smtp-Source: AGHT+IHWpQlwgZokPgaKKtKVfljkI2E8OSy6cZp0yTPDwRUEB34wysNWxD705T/80/pl+V9elmVamQ== X-Received: by 2002:a05:600c:21d5:b0:41f:ed4b:93f9 with SMTP id 5b1f17b1804b1-421089de9f0mr114843025e9.19.1716970274553; Wed, 29 May 2024 01:11:14 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:14 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 19/47] dt-bindings: net: renesas,etheravb: Document RZ/G3S support Date: Wed, 29 May 2024 11:10:11 +0300 Message-Id: <20240529081039.639010-20-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:26 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/15999 From: Claudiu Beznea commit 060baa9b90d4e14eac7123abc563070dd30b21a2 upstream. Document Ethernet RZ/G3S support. Ethernet IP is similar to the one available on RZ/G2L devices. Signed-off-by: Claudiu Beznea Acked-by: Conor Dooley Reviewed-by: Sergey Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Jakub Kicinski Signed-off-by: Claudiu Beznea --- Documentation/devicetree/bindings/net/renesas,etheravb.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml index 846ad0352c71..d302cb12babf 100644 --- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml +++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml @@ -52,6 +52,7 @@ properties: - renesas,r9a07g043-gbeth # RZ/G2UL - renesas,r9a07g044-gbeth # RZ/G2{L,LC} - renesas,r9a07g054-gbeth # RZ/V2L + - renesas,r9a08g045-gbeth # RZ/G3S - const: renesas,rzg2l-gbeth # RZ/{G2L,G2UL,V2L} family reg: true From patchwork Wed May 29 08:10:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADB7DC27C51 for ; Wed, 29 May 2024 08:11:26 +0000 (UTC) Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.groups.io with SMTP id smtpd.web11.8578.1716970277337611209 for ; Wed, 29 May 2024 01:11:17 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=P+o6pdiJ; spf=pass (domain: tuxon.dev, ip: 209.85.128.51, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-42108739ed8so21250745e9.0 for ; Wed, 29 May 2024 01:11:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970276; x=1717575076; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uzoNf9JbIV0LzI7jLpdqeO6pw0YrqrRLljLSKRy/Xfg=; b=P+o6pdiJRLPAR9buBCgCvndFrYE+IKr5uftHwRnOu/EnY9C2d9FJlk8oLMFX57yUwc Mh2mrmpT34P+MZAiqNEb8Cm9x/A5Bs2rerWbEaaHZmjw/eMN7Hkg4l6OBjvf6EY3GC3h 3jL7Gt5Y47WYfAShvot5Z5LckMdMt2cftx1dWPiepErxXpem6vrF97GHdmgJrdRCQQ7g ZJTgc6sDdA7AWDuBniF+69qj7PrbvyNPmMltqS5h6e2jZJAzLUsXTxnMXLOGoQ87HcsK suyVYE8/iiXJwCoyF2jBqRY3PkZlnV7spD7h+MjiKaccqwvljxTt0qsgcPVsaF0SKoWA N1FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970276; x=1717575076; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uzoNf9JbIV0LzI7jLpdqeO6pw0YrqrRLljLSKRy/Xfg=; b=UfoQPo4VEBAQjFLxDFNuIjwb3aj0sSseWY6P3/PD7Ov8rZlrVmGfd76mDAmJFdobGx Z58pKn5AVnPrL2/8JDWpSCMONOEyCKvOQSswxowcofb+/ySq2MD9Yr+zNIgjt5rdPOp3 0WzWreVy2E5XErCeArDd9E4bjv6OMGRFlb986He6eq4iNy70UlVrk7z6QFZlRjaoQfvx NPS9xZ0MPjAsRs9pxgirFOokOKb3bK0IpGaW0iFRg8ueb8ilC8LE9WDz2OzzfYP3yEyA FSvYoaLoAlOqAp2wBDFBXIfPtWzs4JgeeP9zkXDxU9mq1jW+SbhYo7QvbBSF3KsOSDuQ FeRg== X-Gm-Message-State: AOJu0YxzAsiHRzdi9EIzicg3ks7EZOZzL0viA8p2XhAh2gO8nZLd3Qq4 p7j8v3V4SB/h2cs8Rwgd3newkNKVmjSEL8MZlAuc8ImlwGLcFnvPudeYmYs8SHY= X-Google-Smtp-Source: AGHT+IEirTyfMnyoQe9iPV+BAxogPjaFp0+SENqpl0B3N9ibma2N7UfukzC90U01oJrg+4n6P8WdjQ== X-Received: by 2002:a05:600c:3586:b0:41f:e10f:88b1 with SMTP id 5b1f17b1804b1-42108a99f18mr145555715e9.27.1716970275848; Wed, 29 May 2024 01:11:15 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:15 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 20/47] net: ravb: Let IP-specific receive function to interrogate descriptors Date: Wed, 29 May 2024 11:10:12 +0300 Message-Id: <20240529081039.639010-21-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:26 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16000 From: Claudiu Beznea commit 2b993bfdb47b3aaafd8fe9cd5038b5e297b18ee1 upstream. ravb_poll() initial code used to interrogate the first descriptor of the RX queue in case gPTP is false to determine if ravb_rx() should be called. This is done for non-gPTP IPs. For gPTP IPs the driver PTP-specific information was used to determine if receive function should be called. As every IP has its own receive function that interrogates the RX descriptors list in the same way the ravb_poll() was doing there is no need to double check this in ravb_poll(). Removing the code from ravb_poll() leads to a cleaner code. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni [claudiu.beznea: fixed conflict in ravb_poll()] Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index ed19026e0976..546a32c6d130 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1282,24 +1282,16 @@ static int ravb_poll(struct napi_struct *napi, int budget) struct net_device *ndev = napi->dev; struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; - bool gptp = info->gptp || info->ccc_gac; - struct ravb_rx_desc *desc; unsigned long flags; int q = napi - priv->napi; int mask = BIT(q); int quota = budget; - unsigned int entry; - bool unmask; - if (!gptp) { - entry = priv->cur_rx[q] % priv->num_rx_ring[q]; - desc = &priv->gbeth_rx_ring[entry]; - } /* Processing RX Descriptor Ring */ /* Clear RX interrupt */ ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); - if (gptp || desc->die_dt != DT_FEMPTY) - unmask = !ravb_rx(ndev, "a, q); + if (ravb_rx(ndev, "a, q)) + goto out; /* Processing TX Descriptor Ring */ spin_lock_irqsave(&priv->lock, flags); @@ -1309,10 +1301,6 @@ static int ravb_poll(struct napi_struct *napi, int budget) netif_wake_subqueue(ndev, q); spin_unlock_irqrestore(&priv->lock, flags); - if (gptp || desc->die_dt != DT_FEMPTY) - if (!unmask) - goto out; - napi_complete(napi); /* Re-enable RX/TX interrupts */ From patchwork Wed May 29 08:10:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60ABAC41513 for ; Wed, 29 May 2024 08:11:26 +0000 (UTC) Received: from mail-lj1-f173.google.com (mail-lj1-f173.google.com [209.85.208.173]) by mx.groups.io with SMTP id smtpd.web10.8646.1716970279103936959 for ; Wed, 29 May 2024 01:11:19 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=GGqKNZ6m; spf=pass (domain: tuxon.dev, ip: 209.85.208.173, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lj1-f173.google.com with SMTP id 38308e7fff4ca-2e95a1f9c53so21263171fa.0 for ; Wed, 29 May 2024 01:11:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970277; x=1717575077; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I/3xBresTmjspqu22A2IKtdhVbktNBoVmxHYo5+aEYI=; b=GGqKNZ6m6k6JqzxgdFetf5vMjUMnlr9fBFN1EOQouxdfdv66lpfvWcT+aWV9bzpYTq 86vTmSRrDlqG/ZS8bpd3XFOBZfQx7WkdhHUVRaiv/yI3IYq4ZpLvJvUWxJK7CKfC5Ay/ JdXbV9m5EAWnE/yv1w6NqKM/q1z4pos9VwFUw7idNvCsL6OjbEFlczTnZB+7MGmIXDDw a8+3hniuzPigBreInvBGFIIgAMr0FQkXv7ALFYKq1orPndGgw11X/2Pf8twiVQVaeqzO +JcrLjM3c/2njfoxG/0UPLSbO8/7beiMxbdpxArqSaEeUdbRQkQOFoTq0x3FckRdR4Bb XTmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970277; x=1717575077; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I/3xBresTmjspqu22A2IKtdhVbktNBoVmxHYo5+aEYI=; b=K2QVvu70vp/iyAmUSqwokAHqMDWWVPAGptXhAS9+FI4YtRnVQZpSL0Hg0Ho5Vhacoy e3/zkSrblMH2QEpYO5yLLWT4axj5cxmFXaJYuOVF5rv/6q14RN4+kqH26xZe84PTGth1 yxTE/pfQ8KW4jWIJf5VjsTX5a3C4p9J99YzMkLRt/NfCDqhqFRICizoIB90+Y7RDtwXs 3zhL6bmJL6s5l1M7PRz0Qk9dwb4Fnvc2RBPfQCKYqfQq4PkbZIombDsZB3irS52+UYvg zc0afwampglpdBk9OfbIV3AUNVqS0yaG98fb8q1olEepfq8mYtvJJ90NBmOx+fThuqqa +w1Q== X-Gm-Message-State: AOJu0Yz9aW9avs3CEH3mDq6L1C4GWdZIGQAz8F9Lwvd2vsEA+I57Gar2 RfZBj1BbCCuBDOJ1xGbdzEmzqJ9zZQVjDWwtX3vY57VZp69ExHUuENmS3Kcw9iw= X-Google-Smtp-Source: AGHT+IHglkzxldV0yIKibDMHwUbeD0dDcznsvM+qQSxQ7L+apURurpIMpNtIpC47NURKNZNFlfYH5w== X-Received: by 2002:a2e:b0f6:0:b0:2e9:8661:927d with SMTP id 38308e7fff4ca-2e9866195a4mr24589601fa.51.1716970277323; Wed, 29 May 2024 01:11:17 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:16 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 21/47] net: ravb: Rely on PM domain to enable gptp_clk Date: Wed, 29 May 2024 11:10:13 +0300 Message-Id: <20240529081039.639010-22-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:26 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16001 From: Claudiu Beznea commit e1da043f2b2d956818728ca74c8eacd17feccf5c upstream. ravb_rzv2m_hw_info::gptp_ref_clk is enabled only for RZ/V2M. RZ/V2M is an ARM64-based device which selects power domains by default and CONFIG_PM. The RZ/V2M Ethernet DT node has proper power-domain binding available in device tree from the commit that added the Ethernet node. (4872ca1f92b0 ("arm64: dts: renesas: r9a09g011: Add ethernet nodes")). Power domain support was available in the rzg2l-cpg.c driver when the Ethernet DT node has been enabled in RZ/V2M device tree. (ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")). Thus, remove the explicit clock enable for gptp_clk (and treat it as the other clocks are treated) as it is not needed and removing it doesn't break the ABI according to the above explanations. By removing the enable/disable operation from the driver we can add runtime PM support (which operates on clocks) w/o the need to handle the gptp_clk in the Ethernet driver functions like ravb_runtime_nop(). PM domain does all that is needed. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 546a32c6d130..09796da2bd57 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2783,7 +2783,6 @@ static int ravb_probe(struct platform_device *pdev) error = PTR_ERR(priv->gptp_clk); goto out_disable_refclk; } - clk_prepare_enable(priv->gptp_clk); } ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); @@ -2803,13 +2802,13 @@ static int ravb_probe(struct platform_device *pdev) /* Set AVB config mode */ error = ravb_set_config_mode(ndev); if (error) - goto out_disable_gptp_clk; + goto out_disable_refclk; if (info->gptp || info->ccc_gac) { /* Set GTI value */ error = ravb_set_gti(ndev); if (error) - goto out_disable_gptp_clk; + goto out_disable_refclk; /* Request GTI loading */ ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); @@ -2829,7 +2828,7 @@ static int ravb_probe(struct platform_device *pdev) "Cannot allocate desc base address table (size %d bytes)\n", priv->desc_bat_size); error = -ENOMEM; - goto out_disable_gptp_clk; + goto out_disable_refclk; } for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) priv->desc_bat[q].die_dt = DT_EOS; @@ -2892,8 +2891,6 @@ static int ravb_probe(struct platform_device *pdev) /* Stop PTP Clock driver */ if (info->ccc_gac) ravb_ptp_stop(ndev); -out_disable_gptp_clk: - clk_disable_unprepare(priv->gptp_clk); out_disable_refclk: clk_disable_unprepare(priv->refclk); out_release: @@ -2928,7 +2925,6 @@ static int ravb_remove(struct platform_device *pdev) ravb_set_opmode(ndev, CCC_OPC_RESET); - clk_disable_unprepare(priv->gptp_clk); clk_disable_unprepare(priv->refclk); pm_runtime_put_sync(&pdev->dev); From patchwork Wed May 29 08:10:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74D21C25B7E for ; Wed, 29 May 2024 08:11:26 +0000 (UTC) Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) by mx.groups.io with SMTP id smtpd.web11.8579.1716970280285076207 for ; Wed, 29 May 2024 01:11:20 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=SQGUp7if; spf=pass (domain: tuxon.dev, ip: 209.85.167.41, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-52b4fcbf078so172186e87.0 for ; Wed, 29 May 2024 01:11:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970278; x=1717575078; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mIeKQaRtpmgRSoGDGwFwTs+Vs07bTk3synoDo6BLgUI=; b=SQGUp7ifCi6Q1T7MTl/EDOXr9BOgvW55DsGcLXnPAVR+eVGcYnKA0Up5ikjcG91FNM qxLUC8Q+0+lzpyw+QujHT5vgxudz55QEaM7b72omiCKlxYCYKn+qGM2k+BiN6wVrSk8Q NMClP24iCCe5p0zhwlBYaAaC0MKsgBcOhoEUfXg9hn+d8YLuyqsBQ4rdZSJhLmqMMRtp PeCyXq/wcBGLj2Q0KTM64zWDCCa2dXPrwXjvjTShJwSPMf4O/TVt752fIoELHQSFiSvT 4gQvDfrwVGWPFcJxJU1bGYy1b7C8RraALBCsfJboNXrnKHC7a+kWoC8bphA3SrTR3jLK oVrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970278; x=1717575078; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mIeKQaRtpmgRSoGDGwFwTs+Vs07bTk3synoDo6BLgUI=; b=eJgWye3QHPqud+WYsqmEgUrPSX0HezMK1Abdf+aLZ/b+YJicp82mN6U4muxPG+d0Zh AAPPK+pm1QIZdJZtrNsRkQRM4L2Dxy83wKcJcSdFZdZFQ+wb3lXuQVEh6Qturh07cLy7 5Pfk0DIVDeoyjKO0IKDgZEgqG9TXAtBXGPMPs2tp75WPE3yQupxl7KayomLugVdhvOvX diu8og1NTn8czzjEla1VO7VPExwO9ER9KobYt943yqDMNNJ/GsCMgBidYUdr1tOGLluJ IaaVAmczoOvj9WbX1jMm8JxlFBvLPNFPXIeI37AfDoe3sTBc2CZ19Cm9Dc+49m6QdP7S MJUA== X-Gm-Message-State: AOJu0YzLv2L2O1j9zcOGb2G6nm0H4tJ+LKX0ZNkVRLl06s6cCJfO2Yh0 69eEFjOatXTMoBF5LF3fCo41Fvzy89V3AiG63x4Caslazsee6V6zMiIeIhrywPY= X-Google-Smtp-Source: AGHT+IGemxDqLh49O7fjbNlvFKwJtZsWv4Lf3eKmZpzVRu+ziHl/CZbO/bnPFigMK7Vyp8kGWgybdQ== X-Received: by 2002:a05:6512:ad4:b0:529:b57a:31ce with SMTP id 2adb3069b0e04-529b57a3277mr5702454e87.29.1716970278611; Wed, 29 May 2024 01:11:18 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:18 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 22/47] net: ravb: Make reset controller support mandatory Date: Wed, 29 May 2024 11:10:14 +0300 Message-Id: <20240529081039.639010-23-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:26 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16002 From: Claudiu Beznea commit b1768e3dc47792ac5876643604be25bc8ed17cd4 upstream. On the RZ/G3S SoC the reset controller is mandatory for the IP to work. The device tree binding documentation for the ravb driver specifies that the resets are mandatory. Based on this, make the resets mandatory also in driver for all ravb devices. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni [claudiu.beznea: fixed conflict in Kconfig] Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/Kconfig | 1 + drivers/net/ethernet/renesas/ravb_main.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/renesas/Kconfig b/drivers/net/ethernet/renesas/Kconfig index 5a2a4af31812..d1f1e1ee2757 100644 --- a/drivers/net/ethernet/renesas/Kconfig +++ b/drivers/net/ethernet/renesas/Kconfig @@ -36,6 +36,7 @@ config RAVB select MII select MDIO_BITBANG select PHYLIB + select RESET_CONTROLLER imply PTP_1588_CLOCK help Renesas Ethernet AVB device driver. diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 09796da2bd57..44cdef3d2b18 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2648,7 +2648,7 @@ static int ravb_probe(struct platform_device *pdev) return -EINVAL; } - rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); + rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(rstc)) return dev_err_probe(&pdev->dev, PTR_ERR(rstc), "failed to get cpg reset\n"); From patchwork Wed May 29 08:10:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E389C25B7C for ; Wed, 29 May 2024 08:11:26 +0000 (UTC) Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) by mx.groups.io with SMTP id smtpd.web10.8648.1716970281699473405 for ; Wed, 29 May 2024 01:11:21 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=A52zUcsV; spf=pass (domain: tuxon.dev, ip: 209.85.128.54, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-4210aa012e5so16611855e9.0 for ; Wed, 29 May 2024 01:11:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970280; x=1717575080; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3LzsHXa4OakELPHllrwwEvUfLcOdKyJ/XyOT1ZLf7Tw=; b=A52zUcsVKFekwizSvDjcLQ+9lIFpMckq1NZok2K7Cs72znigQMeTBJTxRpsMAlJeZP 1hUrToGrTbTPPPHSbximhplJ5g/iVBdOeOktkv3SSEi0T1v1L613rzBGSD9IkZHmvcwD ZEgzq0nfegohDuxJtsWLkvYcuTJP7QZuvCHnryVEYxk//1W5X00r1sansYvVWQEX+FBs re1GcST+ObyE2kGgF1ZrB1t8p3j6bhjGtf6bUAwiisJLA/Cfiaq1+1VlT4jcjB32cKOE aSixpaToaKzquuCx1IfVMjFc5bzV0fnNqM92Y0Uy+VTrzfEGS5941fG0X8FT4hOgSeKi d92g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970280; x=1717575080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3LzsHXa4OakELPHllrwwEvUfLcOdKyJ/XyOT1ZLf7Tw=; b=aUcM0hSJ5THWdKXI+STbb4uWCHS51Mw/6W9Gzxg3vm75OYsJiCNZiM+aj5W0fZaxMx w/VlN2liJegwChOdZecCxxhdljoPBKC0Jt4ROP64r3zu3W6OYikLIufFUituH/UucGSH zDrcRXHBsJMsoc9GLkd+m7GUy06BrYa4teKym0mro61iyg4/BRfF7/aWKU4b3R6XqF3I kLLaigMN3a2PDZcsqN3DGBsYFws7FvXrMU4EwBWlxeRyXCDGXohM2/+SNvJlPpa0GQgF WDNrnDfAB/f4YUNvQeTSZfi3pUza8W7c23yYA7gEyvdoFT1QbDGJVLSHW4tUHjPl3Qe/ Z2IQ== X-Gm-Message-State: AOJu0Yyhs5DCWT4cSCG5istim/iAJG0N0oNivEalg5S1YKkTyNy5uJ7Q 9qpZWEi+yGuCz2/RdTYL/HuL5EZO8sgBTRUQTEqHPgJzgCrznECNKnzBD5cwa96IJgNDOTpqU90 DXAI= X-Google-Smtp-Source: AGHT+IECCb283izpKI2eYd6xMEZPgHN7GbCDUAq4Ne2atpGzUWcyMLonQgwlLa7QYTlWNW9Qx9NXuA== X-Received: by 2002:a05:600c:5121:b0:41e:3272:6476 with SMTP id 5b1f17b1804b1-42108a5929dmr117720755e9.10.1716970280236; Wed, 29 May 2024 01:11:20 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:19 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 23/47] net: ravb: Assert/de-assert reset on suspend/resume Date: Wed, 29 May 2024 11:10:15 +0300 Message-Id: <20240529081039.639010-24-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:26 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16003 From: Claudiu Beznea commit c5c0714e29508fd748ee5df09ae242476bf2e451 upstream. RZ/G3S can go to deep sleep states where power to most of the SoC parts is off. When resuming from such a state, the Ethernet controller needs to be reinitialized. De-asserting the reset signal for it should also be done. Thus, add reset assert/de-assert on suspend/resume functions. On the resume function, the de-assert was not reverted in case of failures to give the user a chance to restore the interface (e.g., bringing down/up the interface) in case suspend/resume failed. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 44cdef3d2b18..5e7b5857d347 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2983,7 +2983,7 @@ static int __maybe_unused ravb_suspend(struct device *dev) int ret; if (!netif_running(ndev)) - return 0; + goto reset_assert; netif_device_detach(ndev); @@ -2995,7 +2995,11 @@ static int __maybe_unused ravb_suspend(struct device *dev) if (priv->info->ccc_gac) ravb_ptp_stop(ndev); - return ret; + if (priv->wol_enabled) + return ret; + +reset_assert: + return reset_control_assert(priv->rstc); } static int __maybe_unused ravb_resume(struct device *dev) @@ -3003,7 +3007,11 @@ static int __maybe_unused ravb_resume(struct device *dev) struct net_device *ndev = dev_get_drvdata(dev); struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; - int ret = 0; + int ret; + + ret = reset_control_deassert(priv->rstc); + if (ret) + return ret; /* If WoL is enabled set reset mode to rearm the WoL logic */ if (priv->wol_enabled) { From patchwork Wed May 29 08:10:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C55FC27C50 for ; Wed, 29 May 2024 08:11:26 +0000 (UTC) Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) by mx.groups.io with SMTP id smtpd.web11.8581.1716970283770682337 for ; Wed, 29 May 2024 01:11:24 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=UUbOrpFJ; spf=pass (domain: tuxon.dev, ip: 209.85.167.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f42.google.com with SMTP id 2adb3069b0e04-52b119986f2so299502e87.1 for ; Wed, 29 May 2024 01:11:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970282; x=1717575082; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Fia4iY/LqSkrgqV0nx8icdq2dZUgvuZTfUUf21Pf+Po=; b=UUbOrpFJ3IhhcxEw3RN2fEebF1ChWN0ZPGzG5CpZb6mMkrlMtTZMMHAUJ3lh3AI1ev R9Q1LkfOMwqGD+WeH+ok7Pv0p0MNt9kA8VSfKUoWTgqn8dq6c/gSLFXuqz9q+9TGQ0Bt N6P3TWoTAWAwt5nHaW/BdNvxMW1URXicVtjQvv6X+XTuN1JRQ72udjOjtKudFsC5raSi qinSjH30p6L0qXlib9tab2KfS2LiVtV9Yx9/kVC3KM5Lq+STiy9V+XHg4w9SOTrzY0Fw MtWIKFIxs1hP/3MB+RBdB7jJrq5ixsEa718t5avulKUCPpf6EgwDZfCHDoQhpl7wn6E3 5d8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970282; x=1717575082; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Fia4iY/LqSkrgqV0nx8icdq2dZUgvuZTfUUf21Pf+Po=; b=rTq3kXhC+SbEsCKuXyU7qNOsXhyRfjN4Vw+x0al6g/azY7rfIVofQm1XgpsWl8WwJs PONX/iRnjnh+Md03AJ1gHEwzyiy5mmM8JmTJOEdk0LrBcHifHFKx4Rj67/CifAi1qXl3 i+gNgTrPpyqL0DlHMN3Y/yTQCJiWrOy7HoEXTLGLELZ12My3PfGjO1XC95AsazTrr+hi dcxZA2Fv5ul/MB3nseHKr48iADyG05RLheRX0p9uuGqONvtEpZ5N4t9jW6XuNC1m7SX3 3M9VsEwiVNOhE9spwYduIJfei7twSX924qcyR3h1+pm6RKeosAeEXM4sGmRyClRiGvbI IBTg== X-Gm-Message-State: AOJu0Yy0Q5Ygh3SMo2GEET49+IfWaSXbf8agUkRAaEZGB94OoHiE4TV/ XEQyXN8vffze69MxBFNUNhjVGAqWRXWLxT79Mx7tEqidZhHNpqixQFx4D44/o5lEcT0lxhw2iXw CYEk= X-Google-Smtp-Source: AGHT+IFcAkb00EbT90Z7XHhHW7nob0OTQRj96GoUIXzmqdMQtIagSrgfrRej/XyZNjIp+0Q5199vVg== X-Received: by 2002:ac2:43b7:0:b0:51f:b781:72a7 with SMTP id 2adb3069b0e04-52966ab5947mr9311548e87.60.1716970281955; Wed, 29 May 2024 01:11:21 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:21 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 24/47] net: ravb: Move reference clock enable/disable on runtime PM APIs Date: Wed, 29 May 2024 11:10:16 +0300 Message-Id: <20240529081039.639010-25-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:26 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16004 From: Claudiu Beznea commit a654f6e875b753d11643840e266f7fd75e5ee1fa upstream. Reference clock could be or not be part of the power domain. If it is part of the power domain, the power domain takes care of properly setting it. In case it is not part of the power domain and full runtime PM support is available in driver the clock will not be propertly disabled/enabled at runtime. For this, keep the prepare/unprepare operations in the driver's probe()/remove() functions and move the enable/disable in runtime PM functions. By doing this, the previous ravb_runtime_nop() function was renamed ravb_runtime_suspend() and the comment was removed. A proper runtime PM resume function was added (ravb_runtime_resume()). The current driver still don't need to make any register settings on runtime suspend/resume (as expressed in the removed comment) because, currently, pm_runtime_put_sync() is called on the driver remove function. This will be changed in the next commits (that extends the runtime PM support) such that proper register settings (along with runtime resume/suspend) will be done on ravb_open()/ravb_close(). Along with it, the other clock request operations were moved close to reference clock request and prepare to have all the clock requests specific code grouped together. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni [claudiu.beznea: - added __maybe_unused to ravb_runtime_suspend(), ravb_runtime_resume() - fixed conflict around SET_RUNTIME_PM_OPS()] Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 110 ++++++++++++----------- 1 file changed, 57 insertions(+), 53 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 5e7b5857d347..112939f13577 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2667,11 +2667,6 @@ static int ravb_probe(struct platform_device *pdev) if (error) goto out_free_netdev; - pm_runtime_enable(&pdev->dev); - error = pm_runtime_resume_and_get(&pdev->dev); - if (error < 0) - goto out_rpm_disable; - if (info->multi_irqs) { if (info->err_mgmt_irqs) irq = platform_get_irq_byname(pdev, "dia"); @@ -2682,7 +2677,7 @@ static int ravb_probe(struct platform_device *pdev) } if (irq < 0) { error = irq; - goto out_release; + goto out_reset_assert; } ndev->irq = irq; @@ -2700,10 +2695,37 @@ static int ravb_probe(struct platform_device *pdev) priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; } + priv->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(priv->clk)) { + error = PTR_ERR(priv->clk); + goto out_reset_assert; + } + + if (info->gptp_ref_clk) { + priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); + if (IS_ERR(priv->gptp_clk)) { + error = PTR_ERR(priv->gptp_clk); + goto out_reset_assert; + } + } + + priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); + if (IS_ERR(priv->refclk)) { + error = PTR_ERR(priv->refclk); + goto out_reset_assert; + } + clk_prepare(priv->refclk); + + platform_set_drvdata(pdev, ndev); + pm_runtime_enable(&pdev->dev); + error = pm_runtime_resume_and_get(&pdev->dev); + if (error < 0) + goto out_rpm_disable; + priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(priv->addr)) { error = PTR_ERR(priv->addr); - goto out_release; + goto out_rpm_put; } /* The Ether-specific entries in the device structure. */ @@ -2714,7 +2736,7 @@ static int ravb_probe(struct platform_device *pdev) error = of_get_phy_mode(np, &priv->phy_interface); if (error && error != -ENODEV) - goto out_release; + goto out_rpm_put; priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); priv->avb_link_active_low = @@ -2727,14 +2749,14 @@ static int ravb_probe(struct platform_device *pdev) irq = platform_get_irq_byname(pdev, "ch24"); if (irq < 0) { error = irq; - goto out_release; + goto out_rpm_put; } priv->emac_irq = irq; for (i = 0; i < NUM_RX_QUEUE; i++) { irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); if (irq < 0) { error = irq; - goto out_release; + goto out_rpm_put; } priv->rx_irqs[i] = irq; } @@ -2742,7 +2764,7 @@ static int ravb_probe(struct platform_device *pdev) irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); if (irq < 0) { error = irq; - goto out_release; + goto out_rpm_put; } priv->tx_irqs[i] = irq; } @@ -2751,40 +2773,19 @@ static int ravb_probe(struct platform_device *pdev) irq = platform_get_irq_byname(pdev, "err_a"); if (irq < 0) { error = irq; - goto out_release; + goto out_rpm_put; } priv->erra_irq = irq; irq = platform_get_irq_byname(pdev, "mgmt_a"); if (irq < 0) { error = irq; - goto out_release; + goto out_rpm_put; } priv->mgmta_irq = irq; } } - priv->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(priv->clk)) { - error = PTR_ERR(priv->clk); - goto out_release; - } - - priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); - if (IS_ERR(priv->refclk)) { - error = PTR_ERR(priv->refclk); - goto out_release; - } - clk_prepare_enable(priv->refclk); - - if (info->gptp_ref_clk) { - priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); - if (IS_ERR(priv->gptp_clk)) { - error = PTR_ERR(priv->gptp_clk); - goto out_disable_refclk; - } - } - ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); ndev->min_mtu = ETH_MIN_MTU; @@ -2802,13 +2803,13 @@ static int ravb_probe(struct platform_device *pdev) /* Set AVB config mode */ error = ravb_set_config_mode(ndev); if (error) - goto out_disable_refclk; + goto out_rpm_put; if (info->gptp || info->ccc_gac) { /* Set GTI value */ error = ravb_set_gti(ndev); if (error) - goto out_disable_refclk; + goto out_rpm_put; /* Request GTI loading */ ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); @@ -2828,7 +2829,7 @@ static int ravb_probe(struct platform_device *pdev) "Cannot allocate desc base address table (size %d bytes)\n", priv->desc_bat_size); error = -ENOMEM; - goto out_disable_refclk; + goto out_rpm_put; } for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) priv->desc_bat[q].die_dt = DT_EOS; @@ -2874,8 +2875,6 @@ static int ravb_probe(struct platform_device *pdev) netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); - platform_set_drvdata(pdev, ndev); - return 0; out_napi_del: @@ -2891,12 +2890,12 @@ static int ravb_probe(struct platform_device *pdev) /* Stop PTP Clock driver */ if (info->ccc_gac) ravb_ptp_stop(ndev); -out_disable_refclk: - clk_disable_unprepare(priv->refclk); -out_release: +out_rpm_put: pm_runtime_put(&pdev->dev); out_rpm_disable: pm_runtime_disable(&pdev->dev); + clk_unprepare(priv->refclk); +out_reset_assert: reset_control_assert(rstc); out_free_netdev: free_netdev(ndev); @@ -2925,10 +2924,9 @@ static int ravb_remove(struct platform_device *pdev) ravb_set_opmode(ndev, CCC_OPC_RESET); - clk_disable_unprepare(priv->refclk); - pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); + clk_unprepare(priv->refclk); reset_control_assert(priv->rstc); free_netdev(ndev); platform_set_drvdata(pdev, NULL); @@ -3065,21 +3063,27 @@ static int __maybe_unused ravb_resume(struct device *dev) return ret; } -static int __maybe_unused ravb_runtime_nop(struct device *dev) +static int __maybe_unused ravb_runtime_suspend(struct device *dev) { - /* Runtime PM callback shared between ->runtime_suspend() - * and ->runtime_resume(). Simply returns success. - * - * This driver re-initializes all registers after - * pm_runtime_get_sync() anyway so there is no need - * to save and restore registers here. - */ + struct net_device *ndev = dev_get_drvdata(dev); + struct ravb_private *priv = netdev_priv(ndev); + + clk_disable(priv->refclk); + return 0; } +static int __maybe_unused ravb_runtime_resume(struct device *dev) +{ + struct net_device *ndev = dev_get_drvdata(dev); + struct ravb_private *priv = netdev_priv(ndev); + + return clk_enable(priv->refclk); +} + static const struct dev_pm_ops ravb_dev_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) - SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) + SET_RUNTIME_PM_OPS(ravb_runtime_suspend, ravb_runtime_resume, NULL) }; static struct platform_driver ravb_driver = { From patchwork Wed May 29 08:10:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678252 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D88EC27C44 for ; Wed, 29 May 2024 08:11:26 +0000 (UTC) Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) by mx.groups.io with SMTP id smtpd.web10.8649.1716970285143418129 for ; Wed, 29 May 2024 01:11:25 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=nr+ablj/; spf=pass (domain: tuxon.dev, ip: 209.85.167.54, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-529b79609cbso2727431e87.3 for ; Wed, 29 May 2024 01:11:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970283; x=1717575083; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sBPXQ9NOH2876e4EiDZm2RUzMP8Z/F3D9PjVHBqj9oE=; b=nr+ablj/A0gBjSxPB1B2s/JzxMUe+xFFG1SreLx+77MkilUu51WA8AgoUqBH5Mj+g3 E9L9nBrKL4PZFOQnkkfCKcZcbpX+ybZBi6SeJh7ajYh4UEmyusH0JkG2c8wc+bhzGxuz q/bUjAPXj8NDagCH10sKqaBSXzrq1FM9bwCDsvcr5cNzuZjLGvLM3H2NBoA6AlTTmaeD C7en9PAuDeDSkrQs8ytd7MMEnQy1NfCqOw8P5+/eEfAhmdgL2zI+WHDSMiE1mCAKuiWf 9pRcC92vk7oS2fWC1YsYLj/oKPYfA8/hdUti86lXiboOtxUQWF6JozkdE7i/189z9Fuv UF0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970283; x=1717575083; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sBPXQ9NOH2876e4EiDZm2RUzMP8Z/F3D9PjVHBqj9oE=; b=Cqi6JsKhAlU4uGbPwg66jtDN5wbr3dqFRZbC64C/0GNNXlSeedVIbiGVCHhMHjGB90 RHlzzMrskw3lz9jty1hnnhrrT0E5D/0zA2U9ptIa919CShxn70d6UpP05Y9g/vJ+Vu8d efN4tNd5VQHiR4HmYo1zK2HjGN1C5a7ZfvIXyE8lLi7zAxjon4NY3DsP0gGglp0e1t0a y5jug6ygSU4RdILoz0NRtrxZeQFKZOsjCvUQRY6PfO3tkea0TPhoBeii6DD0OoaXzouO ufsnqS0Tyjz+6Z+qX7kK/7KDCFEdVjp376RDzlS9M2g1EJB2Px+Bmm+V/q6URTBosR29 9Jkw== X-Gm-Message-State: AOJu0YzE4fl2IwfXW+gbu2ucRyALgKXfmuwl5f0M+NIUGkHe6IsBc2JR OjXp0FDISLdi/G3SYWupJkEzORmGCie6z0TxK0Tvag0Q/Q2m6ZqbmrcXL2jx5AM= X-Google-Smtp-Source: AGHT+IHsOETF0S3WpgQJPNWwvTxX/Xa+9nentbG1j55NMPgqKzx9GNWYXBj9D2jIRKzpzN8RgSMFCw== X-Received: by 2002:a19:914d:0:b0:518:dfed:f021 with SMTP id 2adb3069b0e04-529645e2b3dmr9022089e87.24.1716970283265; Wed, 29 May 2024 01:11:23 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:22 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 25/47] net: ravb: Move getting/requesting IRQs in the probe() method Date: Wed, 29 May 2024 11:10:17 +0300 Message-Id: <20240529081039.639010-26-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:26 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16005 From: Claudiu Beznea commit 32f012b8c01ca9fd26a28134cc2165ead93c22d0 upstream. The runtime PM implementation will disable clocks at the end of ravb_probe(). As some IP variants switch to reset mode as a result of setting module standby through clock disable APIs, to implement runtime PM the resource parsing and requesting are moved in the probe function and IP settings are moved in the open function. This is done because at the end of the probe some IP variants will switch anyway to reset mode and the registers content is lost. Also keeping only register settings operations in the ravb_open()/ravb_close() functions will make them faster. Commit moves IRQ requests to ravb_probe() to have all the IRQs ready when the interface is open. As now getting/requesting IRQs is done in a single place there is no need to keep intermediary data (like ravb_rx_irqs[] and ravb_tx_irqs[] arrays or IRQs in struct ravb_private). In order to avoid accessing the IP registers while the IP is runtime suspended (e.g. in the timeframe b/w the probe requests shared IRQs and IP clocks are enabled) in the interrupt handlers were introduced pm_runtime_active() checks. The device runtime PM usage counter has been incremented to avoid disabling the device's clocks while the check is in progress (if any). This is a preparatory change to add runtime PM support for all IP variants. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb.h | 4 - drivers/net/ethernet/renesas/ravb_main.c | 299 ++++++++++------------- 2 files changed, 130 insertions(+), 173 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index 29b8b163a3ca..2226c757fa9a 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -1089,10 +1089,6 @@ struct ravb_private { int msg_enable; int speed; int emac_irq; - int erra_irq; - int mgmta_irq; - int rx_irqs[NUM_RX_QUEUE]; - int tx_irqs[NUM_TX_QUEUE]; unsigned no_avb_link:1; unsigned avb_link_active_low:1; diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 112939f13577..7dbd8130fdc1 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -40,16 +40,6 @@ NETIF_MSG_RX_ERR | \ NETIF_MSG_TX_ERR) -static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { - "ch0", /* RAVB_BE */ - "ch1", /* RAVB_NC */ -}; - -static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { - "ch18", /* RAVB_BE */ - "ch19", /* RAVB_NC */ -}; - void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, u32 set) { @@ -1086,11 +1076,23 @@ static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) { struct net_device *ndev = dev_id; struct ravb_private *priv = netdev_priv(ndev); + struct device *dev = &priv->pdev->dev; + irqreturn_t result = IRQ_HANDLED; + + pm_runtime_get_noresume(dev); + + if (unlikely(!pm_runtime_active(dev))) { + result = IRQ_NONE; + goto out_rpm_put; + } spin_lock(&priv->lock); ravb_emac_interrupt_unlocked(ndev); spin_unlock(&priv->lock); - return IRQ_HANDLED; + +out_rpm_put: + pm_runtime_put_noidle(dev); + return result; } /* Error interrupt handler */ @@ -1170,9 +1172,15 @@ static irqreturn_t ravb_interrupt(int irq, void *dev_id) struct net_device *ndev = dev_id; struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; + struct device *dev = &priv->pdev->dev; irqreturn_t result = IRQ_NONE; u32 iss; + pm_runtime_get_noresume(dev); + + if (unlikely(!pm_runtime_active(dev))) + goto out_rpm_put; + spin_lock(&priv->lock); /* Get interrupt status */ iss = ravb_read(ndev, ISS); @@ -1216,6 +1224,9 @@ static irqreturn_t ravb_interrupt(int irq, void *dev_id) } spin_unlock(&priv->lock); + +out_rpm_put: + pm_runtime_put_noidle(dev); return result; } @@ -1224,9 +1235,15 @@ static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) { struct net_device *ndev = dev_id; struct ravb_private *priv = netdev_priv(ndev); + struct device *dev = &priv->pdev->dev; irqreturn_t result = IRQ_NONE; u32 iss; + pm_runtime_get_noresume(dev); + + if (unlikely(!pm_runtime_active(dev))) + goto out_rpm_put; + spin_lock(&priv->lock); /* Get interrupt status */ iss = ravb_read(ndev, ISS); @@ -1248,6 +1265,9 @@ static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) } spin_unlock(&priv->lock); + +out_rpm_put: + pm_runtime_put_noidle(dev); return result; } @@ -1255,8 +1275,14 @@ static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) { struct net_device *ndev = dev_id; struct ravb_private *priv = netdev_priv(ndev); + struct device *dev = &priv->pdev->dev; irqreturn_t result = IRQ_NONE; + pm_runtime_get_noresume(dev); + + if (unlikely(!pm_runtime_active(dev))) + goto out_rpm_put; + spin_lock(&priv->lock); /* Network control/Best effort queue RX/TX */ @@ -1264,6 +1290,9 @@ static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) result = IRQ_HANDLED; spin_unlock(&priv->lock); + +out_rpm_put: + pm_runtime_put_noidle(dev); return result; } @@ -1737,85 +1766,21 @@ static const struct ethtool_ops ravb_ethtool_ops = { .set_wol = ravb_set_wol, }; -static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, - struct net_device *ndev, struct device *dev, - const char *ch) -{ - char *name; - int error; - - name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); - if (!name) - return -ENOMEM; - error = request_irq(irq, handler, 0, name, ndev); - if (error) - netdev_err(ndev, "cannot request IRQ %s\n", name); - - return error; -} - /* Network device open function for Ethernet AVB */ static int ravb_open(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; - struct platform_device *pdev = priv->pdev; - struct device *dev = &pdev->dev; int error; napi_enable(&priv->napi[RAVB_BE]); if (info->nc_queues) napi_enable(&priv->napi[RAVB_NC]); - if (!info->multi_irqs) { - error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, - ndev->name, ndev); - if (error) { - netdev_err(ndev, "cannot request IRQ\n"); - goto out_napi_off; - } - } else { - error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, - dev, "ch22:multi"); - if (error) - goto out_napi_off; - error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, - dev, "ch24:emac"); - if (error) - goto out_free_irq; - error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, - ndev, dev, "ch0:rx_be"); - if (error) - goto out_free_irq_emac; - error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, - ndev, dev, "ch18:tx_be"); - if (error) - goto out_free_irq_be_rx; - error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, - ndev, dev, "ch1:rx_nc"); - if (error) - goto out_free_irq_be_tx; - error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, - ndev, dev, "ch19:tx_nc"); - if (error) - goto out_free_irq_nc_rx; - - if (info->err_mgmt_irqs) { - error = ravb_hook_irq(priv->erra_irq, ravb_multi_interrupt, - ndev, dev, "err_a"); - if (error) - goto out_free_irq_nc_tx; - error = ravb_hook_irq(priv->mgmta_irq, ravb_multi_interrupt, - ndev, dev, "mgmt_a"); - if (error) - goto out_free_irq_erra; - } - } - /* Device init */ error = ravb_dmac_init(ndev); if (error) - goto out_free_irq_mgmta; + goto out_napi_off; ravb_emac_init(ndev); /* Initialise PTP Clock driver */ @@ -1836,26 +1801,6 @@ static int ravb_open(struct net_device *ndev) if (info->gptp) ravb_ptp_stop(ndev); ravb_stop_dma(ndev); -out_free_irq_mgmta: - if (!info->multi_irqs) - goto out_free_irq; - if (info->err_mgmt_irqs) - free_irq(priv->mgmta_irq, ndev); -out_free_irq_erra: - if (info->err_mgmt_irqs) - free_irq(priv->erra_irq, ndev); -out_free_irq_nc_tx: - free_irq(priv->tx_irqs[RAVB_NC], ndev); -out_free_irq_nc_rx: - free_irq(priv->rx_irqs[RAVB_NC], ndev); -out_free_irq_be_tx: - free_irq(priv->tx_irqs[RAVB_BE], ndev); -out_free_irq_be_rx: - free_irq(priv->rx_irqs[RAVB_BE], ndev); -out_free_irq_emac: - free_irq(priv->emac_irq, ndev); -out_free_irq: - free_irq(ndev->irq, ndev); out_napi_off: if (info->nc_queues) napi_disable(&priv->napi[RAVB_NC]); @@ -2190,19 +2135,6 @@ static int ravb_close(struct net_device *ndev) cancel_work_sync(&priv->work); - if (info->multi_irqs) { - free_irq(priv->tx_irqs[RAVB_NC], ndev); - free_irq(priv->rx_irqs[RAVB_NC], ndev); - free_irq(priv->tx_irqs[RAVB_BE], ndev); - free_irq(priv->rx_irqs[RAVB_BE], ndev); - free_irq(priv->emac_irq, ndev); - if (info->err_mgmt_irqs) { - free_irq(priv->erra_irq, ndev); - free_irq(priv->mgmta_irq, ndev); - } - } - free_irq(ndev->irq, ndev); - if (info->nc_queues) napi_disable(&priv->napi[RAVB_NC]); napi_disable(&priv->napi[RAVB_BE]); @@ -2619,6 +2551,90 @@ static void ravb_parse_delay_mode(struct device_node *np, struct net_device *nde } } +static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, + const char *ch, int *irq, irq_handler_t handler) +{ + struct platform_device *pdev = priv->pdev; + struct net_device *ndev = priv->ndev; + struct device *dev = &pdev->dev; + const char *dev_name; + unsigned long flags; + int error; + + if (irq_name) { + dev_name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); + if (!dev_name) + return -ENOMEM; + + *irq = platform_get_irq_byname(pdev, irq_name); + flags = 0; + } else { + dev_name = ndev->name; + *irq = platform_get_irq(pdev, 0); + flags = IRQF_SHARED; + } + if (*irq < 0) + return *irq; + + error = devm_request_irq(dev, *irq, handler, flags, dev_name, ndev); + if (error) + netdev_err(ndev, "cannot request IRQ %s\n", dev_name); + + return error; +} + +static int ravb_setup_irqs(struct ravb_private *priv) +{ + const struct ravb_hw_info *info = priv->info; + struct net_device *ndev = priv->ndev; + const char *irq_name, *emac_irq_name; + int error, irq; + + if (!info->multi_irqs) + return ravb_setup_irq(priv, NULL, NULL, &ndev->irq, ravb_interrupt); + + if (info->err_mgmt_irqs) { + irq_name = "dia"; + emac_irq_name = "line3"; + } else { + irq_name = "ch22"; + emac_irq_name = "ch24"; + } + + error = ravb_setup_irq(priv, irq_name, "ch22:multi", &ndev->irq, ravb_multi_interrupt); + if (error) + return error; + + error = ravb_setup_irq(priv, emac_irq_name, "ch24:emac", &priv->emac_irq, + ravb_emac_interrupt); + if (error) + return error; + + if (info->err_mgmt_irqs) { + error = ravb_setup_irq(priv, "err_a", "err_a", &irq, ravb_multi_interrupt); + if (error) + return error; + + error = ravb_setup_irq(priv, "mgmt_a", "mgmt_a", &irq, ravb_multi_interrupt); + if (error) + return error; + } + + error = ravb_setup_irq(priv, "ch0", "ch0:rx_be", &irq, ravb_be_interrupt); + if (error) + return error; + + error = ravb_setup_irq(priv, "ch1", "ch1:rx_nc", &irq, ravb_nc_interrupt); + if (error) + return error; + + error = ravb_setup_irq(priv, "ch18", "ch18:tx_be", &irq, ravb_be_interrupt); + if (error) + return error; + + return ravb_setup_irq(priv, "ch19", "ch19:tx_nc", &irq, ravb_nc_interrupt); +} + static void ravb_set_delay_mode(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); @@ -2638,9 +2654,8 @@ static int ravb_probe(struct platform_device *pdev) struct reset_control *rstc; struct ravb_private *priv; struct net_device *ndev; - int error, irq, q; struct resource *res; - int i; + int error, q; if (!np) { dev_err(&pdev->dev, @@ -2667,20 +2682,6 @@ static int ravb_probe(struct platform_device *pdev) if (error) goto out_free_netdev; - if (info->multi_irqs) { - if (info->err_mgmt_irqs) - irq = platform_get_irq_byname(pdev, "dia"); - else - irq = platform_get_irq_byname(pdev, "ch22"); - } else { - irq = platform_get_irq(pdev, 0); - } - if (irq < 0) { - error = irq; - goto out_reset_assert; - } - ndev->irq = irq; - SET_NETDEV_DEV(ndev, &pdev->dev); priv = netdev_priv(ndev); @@ -2695,6 +2696,10 @@ static int ravb_probe(struct platform_device *pdev) priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; } + error = ravb_setup_irqs(priv); + if (error) + goto out_reset_assert; + priv->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(priv->clk)) { error = PTR_ERR(priv->clk); @@ -2742,50 +2747,6 @@ static int ravb_probe(struct platform_device *pdev) priv->avb_link_active_low = of_property_read_bool(np, "renesas,ether-link-active-low"); - if (info->multi_irqs) { - if (info->err_mgmt_irqs) - irq = platform_get_irq_byname(pdev, "line3"); - else - irq = platform_get_irq_byname(pdev, "ch24"); - if (irq < 0) { - error = irq; - goto out_rpm_put; - } - priv->emac_irq = irq; - for (i = 0; i < NUM_RX_QUEUE; i++) { - irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); - if (irq < 0) { - error = irq; - goto out_rpm_put; - } - priv->rx_irqs[i] = irq; - } - for (i = 0; i < NUM_TX_QUEUE; i++) { - irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); - if (irq < 0) { - error = irq; - goto out_rpm_put; - } - priv->tx_irqs[i] = irq; - } - - if (info->err_mgmt_irqs) { - irq = platform_get_irq_byname(pdev, "err_a"); - if (irq < 0) { - error = irq; - goto out_rpm_put; - } - priv->erra_irq = irq; - - irq = platform_get_irq_byname(pdev, "mgmt_a"); - if (irq < 0) { - error = irq; - goto out_rpm_put; - } - priv->mgmta_irq = irq; - } - } - ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); ndev->min_mtu = ETH_MIN_MTU; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:24 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 26/47] net: ravb: Split GTI computation and set operations Date: Wed, 29 May 2024 11:10:18 +0300 Message-Id: <20240529081039.639010-27-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:36 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16006 From: Claudiu Beznea commit f384ab481cab6ad71afdf9c80a8b407a70a8624c upstream. ravb_set_gti() was computing the value of GTI based on the reference clock rate and then applied it to register. This was done on the driver's probe function. In order to implement runtime PM for all IP variants (as some IP variants switches to reset mode (and thus the registers content is lost) when module standby is configured through clock APIs) the GTI setup was split in 2 parts: one computing the value of the GTI register (done in the driver's probe function) and one applying the computed value to register (done in the driver's ndo_open API). Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb.h | 2 + drivers/net/ethernet/renesas/ravb_main.c | 96 ++++++++++++------------ 2 files changed, 52 insertions(+), 46 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index 2226c757fa9a..3b7016bbf716 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -1102,6 +1102,8 @@ struct ravb_private { const struct ravb_hw_info *info; struct reset_control *rstc; + + u32 gti_tiv; }; static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 7dbd8130fdc1..2e96ce403da0 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1766,6 +1766,50 @@ static const struct ethtool_ops ravb_ethtool_ops = { .set_wol = ravb_set_wol, }; +static void ravb_set_gti(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + const struct ravb_hw_info *info = priv->info; + + if (!(info->gptp || info->ccc_gac)) + return; + + ravb_write(ndev, priv->gti_tiv, GTI); + + /* Request GTI loading */ + ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); +} + +static int ravb_compute_gti(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + const struct ravb_hw_info *info = priv->info; + struct device *dev = ndev->dev.parent; + unsigned long rate; + u64 inc; + + if (!(info->gptp || info->ccc_gac)) + return 0; + + if (info->gptp_ref_clk) + rate = clk_get_rate(priv->gptp_clk); + else + rate = clk_get_rate(priv->clk); + if (!rate) + return -EINVAL; + + inc = div64_ul(1000000000ULL << 20, rate); + + if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { + dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", + inc, GTI_TIV_MIN, GTI_TIV_MAX); + return -EINVAL; + } + priv->gti_tiv = inc; + + return 0; +} + /* Network device open function for Ethernet AVB */ static int ravb_open(struct net_device *ndev) { @@ -1783,6 +1827,8 @@ static int ravb_open(struct net_device *ndev) goto out_napi_off; ravb_emac_init(ndev); + ravb_set_gti(ndev); + /* Initialise PTP Clock driver */ if (info->gptp) ravb_ptp_init(ndev, priv->pdev); @@ -2467,34 +2513,6 @@ static const struct of_device_id ravb_match_table[] = { }; MODULE_DEVICE_TABLE(of, ravb_match_table); -static int ravb_set_gti(struct net_device *ndev) -{ - struct ravb_private *priv = netdev_priv(ndev); - const struct ravb_hw_info *info = priv->info; - struct device *dev = ndev->dev.parent; - unsigned long rate; - uint64_t inc; - - if (info->gptp_ref_clk) - rate = clk_get_rate(priv->gptp_clk); - else - rate = clk_get_rate(priv->clk); - if (!rate) - return -EINVAL; - - inc = div64_ul(1000000000ULL << 20, rate); - - if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { - dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", - inc, GTI_TIV_MIN, GTI_TIV_MAX); - return -EINVAL; - } - - ravb_write(ndev, inc, GTI); - - return 0; -} - static int ravb_set_config_mode(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); @@ -2766,15 +2784,9 @@ static int ravb_probe(struct platform_device *pdev) if (error) goto out_rpm_put; - if (info->gptp || info->ccc_gac) { - /* Set GTI value */ - error = ravb_set_gti(ndev); - if (error) - goto out_rpm_put; - - /* Request GTI loading */ - ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); - } + error = ravb_compute_gti(ndev); + if (error) + goto out_rpm_put; if (info->internal_delay) { ravb_parse_delay_mode(np, ndev); @@ -2989,15 +3001,7 @@ static int __maybe_unused ravb_resume(struct device *dev) if (ret) return ret; - if (info->gptp || info->ccc_gac) { - /* Set GTI value */ - ret = ravb_set_gti(ndev); - if (ret) - return ret; - - /* Request GTI loading */ - ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); - } + ravb_set_gti(ndev); if (info->internal_delay) ravb_set_delay_mode(ndev); From patchwork Wed May 29 08:10:19 2024 Content-Type: text/plain; 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Wed, 29 May 2024 01:11:26 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:25 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 27/47] net: ravb: Move delay mode set in the driver's ndo_open API Date: Wed, 29 May 2024 11:10:19 +0300 Message-Id: <20240529081039.639010-28-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:36 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16007 From: Claudiu Beznea commit 23698a9abb629009b42ef419072e567b43ca6866 upstream. Delay parsing and setting were done in the driver's probe API. As some IP variants switch to reset mode (and thus the register contents is lost) when setting clocks (due to module standby functionality) to be able to implement runtime PM keep the delay parsing in the driver's probe function and move the delay applying function to the driver's ndo_open API. Along with it, ravb_parse_delay_mode() function was moved close to ravb_set_delay_mode() function to have the delay specific code in the same place. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 107 ++++++++++++----------- 1 file changed, 56 insertions(+), 51 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 2e96ce403da0..bf909302ecf4 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1810,6 +1810,59 @@ static int ravb_compute_gti(struct net_device *ndev) return 0; } +/* Set tx and rx clock internal delay modes */ +static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + bool explicit_delay = false; + u32 delay; + + if (!priv->info->internal_delay) + return; + + if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { + /* Valid values are 0 and 1800, according to DT bindings */ + priv->rxcidm = !!delay; + explicit_delay = true; + } + if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { + /* Valid values are 0 and 2000, according to DT bindings */ + priv->txcidm = !!delay; + explicit_delay = true; + } + + if (explicit_delay) + return; + + /* Fall back to legacy rgmii-*id behavior */ + if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || + priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { + priv->rxcidm = 1; + priv->rgmii_override = 1; + } + + if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || + priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { + priv->txcidm = 1; + priv->rgmii_override = 1; + } +} + +static void ravb_set_delay_mode(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + u32 set = 0; + + if (!priv->info->internal_delay) + return; + + if (priv->rxcidm) + set |= APSR_RDM; + if (priv->txcidm) + set |= APSR_TDM; + ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); +} + /* Network device open function for Ethernet AVB */ static int ravb_open(struct net_device *ndev) { @@ -1821,6 +1874,8 @@ static int ravb_open(struct net_device *ndev) if (info->nc_queues) napi_enable(&priv->napi[RAVB_NC]); + ravb_set_delay_mode(ndev); + /* Device init */ error = ravb_dmac_init(ndev); if (error) @@ -2534,41 +2589,6 @@ static int ravb_set_config_mode(struct net_device *ndev) return error; } -/* Set tx and rx clock internal delay modes */ -static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) -{ - struct ravb_private *priv = netdev_priv(ndev); - bool explicit_delay = false; - u32 delay; - - if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { - /* Valid values are 0 and 1800, according to DT bindings */ - priv->rxcidm = !!delay; - explicit_delay = true; - } - if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { - /* Valid values are 0 and 2000, according to DT bindings */ - priv->txcidm = !!delay; - explicit_delay = true; - } - - if (explicit_delay) - return; - - /* Fall back to legacy rgmii-*id behavior */ - if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || - priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { - priv->rxcidm = 1; - priv->rgmii_override = 1; - } - - if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || - priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { - priv->txcidm = 1; - priv->rgmii_override = 1; - } -} - static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, const char *ch, int *irq, irq_handler_t handler) { @@ -2653,18 +2673,6 @@ static int ravb_setup_irqs(struct ravb_private *priv) return ravb_setup_irq(priv, "ch19", "ch19:tx_nc", &irq, ravb_nc_interrupt); } -static void ravb_set_delay_mode(struct net_device *ndev) -{ - struct ravb_private *priv = netdev_priv(ndev); - u32 set = 0; - - if (priv->rxcidm) - set |= APSR_RDM; - if (priv->txcidm) - set |= APSR_TDM; - ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); -} - static int ravb_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -2788,10 +2796,7 @@ static int ravb_probe(struct platform_device *pdev) if (error) goto out_rpm_put; - if (info->internal_delay) { - ravb_parse_delay_mode(np, ndev); - ravb_set_delay_mode(ndev); - } + ravb_parse_delay_mode(np, ndev); /* Allocate descriptor base address table */ priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; From patchwork Wed May 29 08:10:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678255 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A325CC25B75 for ; Wed, 29 May 2024 08:11:36 +0000 (UTC) Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) by mx.groups.io with SMTP id smtpd.web10.8652.1716970289878943453 for ; Wed, 29 May 2024 01:11:30 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=fgWgNYE+; spf=pass (domain: tuxon.dev, ip: 209.85.167.48, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f48.google.com with SMTP id 2adb3069b0e04-52ab11ecdbaso628291e87.3 for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:27 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 28/47] net: ravb: Move DBAT configuration to the driver's ndo_open API Date: Wed, 29 May 2024 11:10:20 +0300 Message-Id: <20240529081039.639010-29-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:36 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16008 From: Claudiu Beznea commit cd1fb46e02de3c70d6379b00c0e860ca44954574 upstream. DBAT setup was done in the driver's probe API. As some IP variants switch to reset mode (and thus registers content is lost) when setting clocks (due to module standby functionality) to be able to implement runtime PM move the DBAT configuration in the driver's ndo_open API. This commit prepares the code for the addition of runtime PM. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index bf909302ecf4..1989320b84c7 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1875,6 +1875,7 @@ static int ravb_open(struct net_device *ndev) napi_enable(&priv->napi[RAVB_NC]); ravb_set_delay_mode(ndev); + ravb_write(ndev, priv->desc_bat_dma, DBAT); /* Device init */ error = ravb_dmac_init(ndev); @@ -2811,7 +2812,6 @@ static int ravb_probe(struct platform_device *pdev) } for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) priv->desc_bat[q].die_dt = DT_EOS; - ravb_write(ndev, priv->desc_bat_dma, DBAT); /* Initialise HW timestamp list */ INIT_LIST_HEAD(&priv->ts_skb_list); From patchwork Wed May 29 08:10:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0363C25B7C for ; Wed, 29 May 2024 08:11:36 +0000 (UTC) Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) by mx.groups.io with SMTP id smtpd.web10.8653.1716970291094705567 for ; Wed, 29 May 2024 01:11:31 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=HsvtnmSG; spf=pass (domain: tuxon.dev, ip: 209.85.167.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f42.google.com with SMTP id 2adb3069b0e04-5295e488248so2130646e87.2 for ; Wed, 29 May 2024 01:11:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970289; x=1717575089; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wUHTj+LaLoksDFk973VDojZyuJWn7SJL62EdH4Nj4m4=; b=HsvtnmSGCEdMQ+ZRPlpJCAcmWXkH0FPfVTRv+P0lUiksMKbnc2Nury7nSaILYqwPbg 9/6Tc4d0S3U/GIU/Qdynr9Uz1SfLUD7Q6OXmBP6OV8UzENmZP6iFRZilfNxIlxUxmR4O FC5+2dptPVKmvFPOIVMNVA9WuGMtQNTG0BdPyssvCa5Trs8pvuYZrURLgQ2bDnLXwMng t9w3jZuDprsniE26kguVW5Nxjve34copxTiDjxJWb+OYKSiUzozheCh/OYdit1c0o6ma gbcdsuVD88/Z6gfty7Sz8O6Ih585cM8Bz3Ib6tuJLHAxVPO0DxqgtSAr87THmmUfbDeF 1Ygw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970289; x=1717575089; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wUHTj+LaLoksDFk973VDojZyuJWn7SJL62EdH4Nj4m4=; b=a35uhFlS0AfUqJFnUZyc6zhGZsnefru0Vl0aTxWdQVgkD/6js83vO1LWjYufNUMzaD t8Huh032+KEe/qvQSDr3uC3NDA00OD8daVXHBvfzFR5kwxLobRUGFlUH3HQeH0OKYcQM czUYcquUxQLE5VcKqMwtgHkM1k2sfsya7suipzdPubjTPnE0G7NPFdQ00Sdl1+qTMPFr yk4dxjg8HjClWZ8aKxkwq8zjT6Tp9K8aIEOIapnCGUEgFlU6ahwKtYfNZ2WvkJ4/pHd5 EoA88L2AWonfqiZGY9ahjLThJrSDS9XdFctNr7MPuyQttL+mrxmVf8CGjbhQeoFBTyKb wHVw== X-Gm-Message-State: AOJu0YwnIo8Et35UrrEHIjkAGO5mFqYgKXE0pHILfQil+yCXW1iCp2Ot o3FgDsA65rgNAFGSRvUSuqlwp76oVRWFW9djTXOA2Ab8TUbP5MJQI8C5x17nWzc= X-Google-Smtp-Source: AGHT+IEiCdgzl55r8olKsWHD+lbRa2BEMwOeu7412rDA8/5PjovX8hq0uDQjLwpL0myC2dAg8zICAQ== X-Received: by 2002:ac2:4d10:0:b0:523:bbcd:ed5f with SMTP id 2adb3069b0e04-52964bb2cb3mr8022848e87.33.1716970289383; Wed, 29 May 2024 01:11:29 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:28 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 29/47] net: ravb: Move PTP initialization in the driver's ndo_open API for ccc_gac platorms Date: Wed, 29 May 2024 11:10:21 +0300 Message-Id: <20240529081039.639010-30-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:36 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16009 From: Claudiu Beznea commit a6a85ba36fd0d3e5595a4fcf57e0811826254ff7 upstream. The initialization sequence for PTP is the same for platforms with ccc_gac and gptp (according to "Figure 50.71 Flow of gPTP Initialization (Normal, Common to All Modes)" of the R-Car Series, 3rd generation hardware manual and "Figure 37A.53 Flow of gPTP Initialization (Normal, Common to All Modes)" of the RZ/G Series hardware manual). As some IP variants switch to reset mode (and thus the registers content is lost) when setting clocks (due to module standby functionality) to be able to implement runtime PM, move the PTP initialization to the driver's ndo_open API. This commit prepares the code for the addition of runtime PM. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 1989320b84c7..b3c7defac9a2 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1886,7 +1886,7 @@ static int ravb_open(struct net_device *ndev) ravb_set_gti(ndev); /* Initialise PTP Clock driver */ - if (info->gptp) + if (info->gptp || info->ccc_gac) ravb_ptp_init(ndev, priv->pdev); /* PHY control start */ @@ -1900,7 +1900,7 @@ static int ravb_open(struct net_device *ndev) out_ptp_stop: /* Stop PTP Clock driver */ - if (info->gptp) + if (info->gptp || info->ccc_gac) ravb_ptp_stop(ndev); ravb_stop_dma(ndev); out_napi_off: @@ -2210,7 +2210,7 @@ static int ravb_close(struct net_device *ndev) ravb_write(ndev, 0, TIC); /* Stop PTP Clock driver */ - if (info->gptp) + if (info->gptp || info->ccc_gac) ravb_ptp_stop(ndev); /* Set the config mode to stop the AVB-DMAC's processes */ @@ -2816,10 +2816,6 @@ static int ravb_probe(struct platform_device *pdev) /* Initialise HW timestamp list */ INIT_LIST_HEAD(&priv->ts_skb_list); - /* Initialise PTP Clock driver */ - if (info->ccc_gac) - ravb_ptp_init(ndev, pdev); - /* Debug message level */ priv->msg_enable = RAVB_DEF_MSG_ENABLE; @@ -2864,10 +2860,6 @@ static int ravb_probe(struct platform_device *pdev) out_dma_free: dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, priv->desc_bat_dma); - - /* Stop PTP Clock driver */ - if (info->ccc_gac) - ravb_ptp_stop(ndev); out_rpm_put: pm_runtime_put(&pdev->dev); out_rpm_disable: @@ -2893,10 +2885,6 @@ static int ravb_remove(struct platform_device *pdev) ravb_mdio_release(priv); - /* Stop PTP Clock driver */ - if (info->ccc_gac) - ravb_ptp_stop(ndev); - dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, priv->desc_bat_dma); From patchwork Wed May 29 08:10:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6D36C27C44 for ; Wed, 29 May 2024 08:11:36 +0000 (UTC) Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) by mx.groups.io with SMTP id smtpd.web10.8654.1716970292240721373 for ; Wed, 29 May 2024 01:11:32 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=cnOA4Z70; spf=pass (domain: tuxon.dev, ip: 209.85.128.50, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-4210aa0154eso9498465e9.0 for ; Wed, 29 May 2024 01:11:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970291; x=1717575091; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=caqnFdvNHcL/9oR4yU50B9YaYGJzmvmNugRh3DbyxVQ=; b=cnOA4Z70R6j0cxUf5r72MD+1Sz5Og0litvtDEk31gRu9BL1swfiOCFVeJfk+XTwisU ZmMEAGB/8o5swh2c5CS/2AgQTxJAio8X7bvtlOAHIOdJqAOJ6L91+pmK9DBW39617N0D OXi5O9bpT/Ic0Lgukcy5S+LeWCVpCy85JhS2RUDyyGFmMgV1pCZfRzhmHZFnRwyEDgv2 wjgHoDOXiOfYlJS4mzD0CQCCUekv43AG/On2+/35Ze0p/sQou1DcyoXzHLx5rTNoH5UT WQq7HavApufQJmtbXjnzxdKxj+tTjJlC2ZdG/8aX7yp3XuakFRzUuj14dX0CUwcfJkVW yL1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970291; x=1717575091; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=caqnFdvNHcL/9oR4yU50B9YaYGJzmvmNugRh3DbyxVQ=; b=dNGd+Is43fzMVHt14ZqBJeIXXdjST6/zlogNqvVXaz2pMBKvVPXUiIDvY2fiQfvQZa MsyLGPNcYvtxzKb1uXBNTl01yY6PXhxidZoD0gZjMAjYVqs49KFoHNC36F6f3nuHirMV oUJUQJF8yNMc258zMjN0E9Gykq+0wrdBKhD3+4U1cn+XMmVtMDeQYDPZcwQFQPvVGlhU 2vREx/gDxHDRGqopwrOiIqE21sMKVranq/rAy9x+uAKngbLkpyZ/D2L9DPOd4eAhX1Lz KrQmPDp5iDH92DfLbV26MUhZvD0sunJBZdKu3jYjiq31JMyo+wvm8oZdKRaKAhncSTCk f3tQ== X-Gm-Message-State: AOJu0Yy14tCdLVlQFdRHGEDt/gOuZjETFWuDQkg1H9iSQX12EijEGY+r deHknDGXdSF2dr8UA5rcsnLbBB/wg20nRQkEzJ+1dZPM1EronaCN/exqoy2hCpM= X-Google-Smtp-Source: AGHT+IEFxuZlRjfF0tSpG1rHJNmUo1qC5yiXZ0C4mAwcaCh49RmspukGO+SumUmNNlbnGGZA3g6h6w== X-Received: by 2002:a1c:4c18:0:b0:417:e00c:fdb8 with SMTP id 5b1f17b1804b1-421089d5133mr166016065e9.1.1716970290631; Wed, 29 May 2024 01:11:30 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:30 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 30/47] net: ravb: Set config mode in ndo_open and reset mode in ndo_close Date: Wed, 29 May 2024 11:10:22 +0300 Message-Id: <20240529081039.639010-31-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:36 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16010 From: Claudiu Beznea commit 76fd52c1007785fcea1d3405907cec940d44f403 upstream. As some IP variants switch to reset mode (and thus the register contents is lost) when setting clocks (due to module standby functionality) to be able to implement runtime PM and save more power, set the IP's operating mode to reset at the end of the probe. Along with it, in the ndo_open API the IP will be switched to configuration, then operation mode. In the ndo_close API, the IP will be switched back to reset mode. This allows implementing runtime PM and, along with it, save more power when the IP is not used. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni [claudiu.beznea: fixed conflict] Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 78 ++++++++++++++---------- 1 file changed, 46 insertions(+), 32 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index b3c7defac9a2..597c303610ca 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1766,6 +1766,27 @@ static const struct ethtool_ops ravb_ethtool_ops = { .set_wol = ravb_set_wol, }; +static int ravb_set_config_mode(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + const struct ravb_hw_info *info = priv->info; + int error; + + if (info->gptp) { + error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); + if (error) + return error; + /* Set CSEL value */ + ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); + } else if (info->ccc_gac) { + error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB); + } else { + error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); + } + + return error; +} + static void ravb_set_gti(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); @@ -1874,13 +1895,19 @@ static int ravb_open(struct net_device *ndev) if (info->nc_queues) napi_enable(&priv->napi[RAVB_NC]); + /* Set AVB config mode */ + error = ravb_set_config_mode(ndev); + if (error) + goto out_napi_off; + ravb_set_delay_mode(ndev); ravb_write(ndev, priv->desc_bat_dma, DBAT); /* Device init */ error = ravb_dmac_init(ndev); if (error) - goto out_napi_off; + goto out_set_reset; + ravb_emac_init(ndev); ravb_set_gti(ndev); @@ -1903,6 +1930,8 @@ static int ravb_open(struct net_device *ndev) if (info->gptp || info->ccc_gac) ravb_ptp_stop(ndev); ravb_stop_dma(ndev); +out_set_reset: + ravb_set_opmode(ndev, CCC_OPC_RESET); out_napi_off: if (info->nc_queues) napi_disable(&priv->napi[RAVB_NC]); @@ -2246,7 +2275,8 @@ static int ravb_close(struct net_device *ndev) if (info->nc_queues) ravb_ring_free(ndev, RAVB_NC); - return 0; + /* Set reset mode. */ + return ravb_set_opmode(ndev, CCC_OPC_RESET); } static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) @@ -2569,27 +2599,6 @@ static const struct of_device_id ravb_match_table[] = { }; MODULE_DEVICE_TABLE(of, ravb_match_table); -static int ravb_set_config_mode(struct net_device *ndev) -{ - struct ravb_private *priv = netdev_priv(ndev); - const struct ravb_hw_info *info = priv->info; - int error; - - if (info->gptp) { - error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); - if (error) - return error; - /* Set CSEL value */ - ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); - } else if (info->ccc_gac) { - error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB); - } else { - error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); - } - - return error; -} - static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, const char *ch, int *irq, irq_handler_t handler) { @@ -2788,11 +2797,6 @@ static int ravb_probe(struct platform_device *pdev) ndev->netdev_ops = &ravb_netdev_ops; ndev->ethtool_ops = &ravb_ethtool_ops; - /* Set AVB config mode */ - error = ravb_set_config_mode(ndev); - if (error) - goto out_rpm_put; - error = ravb_compute_gti(ndev); if (error) goto out_rpm_put; @@ -2819,6 +2823,11 @@ static int ravb_probe(struct platform_device *pdev) /* Debug message level */ priv->msg_enable = RAVB_DEF_MSG_ENABLE; + /* Set config mode as this is needed for PHY initialization. */ + error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); + if (error) + goto out_rpm_put; + /* Read and set MAC address */ ravb_read_mac_address(ndev, of_get_mac_address(np)); if (!is_valid_ether_addr(ndev->dev_addr)) { @@ -2831,9 +2840,14 @@ static int ravb_probe(struct platform_device *pdev) error = ravb_mdio_init(priv); if (error) { dev_err(&pdev->dev, "failed to initialize MDIO\n"); - goto out_dma_free; + goto out_reset_mode; } + /* Undo previous switch to config opmode. */ + error = ravb_set_opmode(ndev, CCC_OPC_RESET); + if (error) + goto out_mdio_release; + netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); if (info->nc_queues) netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); @@ -2856,8 +2870,10 @@ static int ravb_probe(struct platform_device *pdev) netif_napi_del(&priv->napi[RAVB_NC]); netif_napi_del(&priv->napi[RAVB_BE]); +out_mdio_release: ravb_mdio_release(priv); -out_dma_free: +out_reset_mode: + ravb_set_opmode(ndev, CCC_OPC_RESET); dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, priv->desc_bat_dma); out_rpm_put: @@ -2888,8 +2904,6 @@ static int ravb_remove(struct platform_device *pdev) dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, priv->desc_bat_dma); - ravb_set_opmode(ndev, CCC_OPC_RESET); - pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); clk_unprepare(priv->refclk); From patchwork Wed May 29 08:10:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678256 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C39E9C25B7E for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:32 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 31/47] net: ravb: Simplify ravb_suspend() Date: Wed, 29 May 2024 11:10:23 +0300 Message-Id: <20240529081039.639010-32-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:36 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16011 From: Claudiu Beznea commit b07bc55cbb1cf88a527d687fccd4a12bac744486 upstream. As ravb_close() contains now the call to ravb_ptp_stop() for both ccc_gac and gPTP aware platforms, there is no need to keep the separate call in ravb_suspend(). Instead, move it to ravb_wol_setup(). In this way the resulting code is cleaner. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 597c303610ca..2a7ff0037676 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2934,6 +2934,9 @@ static int ravb_wol_setup(struct net_device *ndev) /* Enable MagicPacket */ ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); + if (priv->info->ccc_gac) + ravb_ptp_stop(ndev); + return enable_irq_wake(priv->emac_irq); } @@ -2966,14 +2969,10 @@ static int __maybe_unused ravb_suspend(struct device *dev) netif_device_detach(ndev); if (priv->wol_enabled) - ret = ravb_wol_setup(ndev); - else - ret = ravb_close(ndev); + return ravb_wol_setup(ndev); - if (priv->info->ccc_gac) - ravb_ptp_stop(ndev); - - if (priv->wol_enabled) + ret = ravb_close(ndev); + if (ret) return ret; reset_assert: From patchwork Wed May 29 08:10:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA859C41513 for ; Wed, 29 May 2024 08:11:46 +0000 (UTC) Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.groups.io with SMTP id smtpd.web11.8587.1716970296581846941 for ; Wed, 29 May 2024 01:11:36 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=Anwv2ISh; spf=pass (domain: tuxon.dev, ip: 209.85.128.51, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4211e42e362so15725115e9.1 for ; Wed, 29 May 2024 01:11:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970295; x=1717575095; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zuh9Nnb5kLz1Nta1Z19AlO8/bBYYXcZgLTiw/AQamgU=; b=Anwv2IShWzNsZsW3L6OyjnKpHxpBQ15f7+1Ho3ttADwvPntrDXQspXx8+m5GmuAlLi 204h68iQKeePItKfinyOPffKM1SBf1QPA372OO1WvyfdtsrUgNcZ+1BuKEWdBg6DD7ry 4w27WMvXeu9KoWXl/Qn9Fqb/QlUV1CBlgnEQyBXpboTMM/QQnRdKUr2ZHfbStB+gx/FC HTYR4h23nkMv+BwPk/rGFfx9mJ5HUqPoc3YL0hSzeqnwWqHJ26+7KPRWtdtig0zbHFVY SBSH5kSA7zwOyrjzqHoABlR6yVGtjrANrdBOREIZiuO7s7vKB1TK3AQwMM6XDC4ROe5O nKuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970295; x=1717575095; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zuh9Nnb5kLz1Nta1Z19AlO8/bBYYXcZgLTiw/AQamgU=; b=riNwOQ1UvyIgv6WG1lqALz9RqlHznnXe9ydZhvXWTkowiUQirN8dAx/c7+C3lDJ3fb P+iTt4Y1VH95JRzZp/2qYOQ2LSgfJEPJynZZBPuvG2MWxCcLJx4NKu2kcaUzzqakv5Sf gYaHZCp5oNqbmsCc6Q12ht6xS+FtabbAdg6HCmjqj46/drDg1gYHhFH04NXd0chc20e3 kMJkAnEWT/MkL5f20VVMa9k5Z+H/54Fta/npKqPi56vZnKJG4fXR3alsQ91ozjlOLphH 3Gu+YAUV575+K5fXFtXV8QpQ9ro+4L6TiG5V8RhDtDmPW/exlOvjbkzLc9MVCztUQuUh 4H5g== X-Gm-Message-State: AOJu0Yy0O7JCvDfW0qhwk19icUr/y8mmGL5hAvxTgpGH6VabePxN9LQ2 tgWBrLQR0Dj0NEmlRKbi7m8MatJQdU3PeUSvpyjG49fLrnuGox0pPcHaJZKXeO0= X-Google-Smtp-Source: AGHT+IH1931hlWqse831Rz6uDl6Um/yjXFnzSFo0LHJvMVzXnFp55+c5EWDIxzfBtC79NsnguqoPcA== X-Received: by 2002:a05:600c:5690:b0:41c:3e1:9db9 with SMTP id 5b1f17b1804b1-42108aa8a00mr110047075e9.27.1716970295053; Wed, 29 May 2024 01:11:35 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:34 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 32/47] net: ravb: Simplify ravb_resume() Date: Wed, 29 May 2024 11:10:24 +0300 Message-Id: <20240529081039.639010-33-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:46 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16012 From: Claudiu Beznea commit e95273fe4d02a6096ba5fe8287bcd9513396ec71 upstream. Remove explicit calls to functions that are called by ravb_open(). There is no need to have them doubled now that the ravb_open() already contains what is needed for the interface configuration. Along with it, configurations needed by PTP were moved to ravb_wol_restore(). With this, code in ravb_resume() becomes simpler. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 58 ++++++++++-------------- 1 file changed, 24 insertions(+), 34 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 2a7ff0037676..478c75c94f50 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2944,6 +2944,20 @@ static int ravb_wol_restore(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; + int error; + + /* Set reset mode to rearm the WoL logic. */ + error = ravb_set_opmode(ndev, CCC_OPC_RESET); + if (error) + return error; + + /* Set AVB config mode. */ + error = ravb_set_config_mode(ndev); + if (error) + return error; + + if (priv->info->ccc_gac) + ravb_ptp_init(ndev, priv->pdev); if (info->nc_queues) napi_enable(&priv->napi[RAVB_NC]); @@ -2983,53 +2997,29 @@ static int __maybe_unused ravb_resume(struct device *dev) { struct net_device *ndev = dev_get_drvdata(dev); struct ravb_private *priv = netdev_priv(ndev); - const struct ravb_hw_info *info = priv->info; int ret; ret = reset_control_deassert(priv->rstc); if (ret) return ret; - /* If WoL is enabled set reset mode to rearm the WoL logic */ + if (!netif_running(ndev)) + return 0; + + /* If WoL is enabled restore the interface. */ if (priv->wol_enabled) { - ret = ravb_set_opmode(ndev, CCC_OPC_RESET); + ret = ravb_wol_restore(ndev); if (ret) return ret; } - /* All register have been reset to default values. - * Restore all registers which where setup at probe time and - * reopen device if it was running before system suspended. - */ - - /* Set AVB config mode */ - ret = ravb_set_config_mode(ndev); - if (ret) + /* Reopening the interface will restore the device to the working state. */ + ret = ravb_open(ndev); + if (ret < 0) return ret; - ravb_set_gti(ndev); - - if (info->internal_delay) - ravb_set_delay_mode(ndev); - - /* Restore descriptor base address table */ - ravb_write(ndev, priv->desc_bat_dma, DBAT); - - if (priv->info->ccc_gac) - ravb_ptp_init(ndev, priv->pdev); - - if (netif_running(ndev)) { - if (priv->wol_enabled) { - ret = ravb_wol_restore(ndev); - if (ret) - return ret; - } - ret = ravb_open(ndev); - if (ret < 0) - return ret; - ravb_set_rx_mode(ndev); - netif_device_attach(ndev); - } + ravb_set_rx_mode(ndev); + netif_device_attach(ndev); return ret; } From patchwork Wed May 29 08:10:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678266 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 114B9C27C53 for ; Wed, 29 May 2024 08:11:47 +0000 (UTC) Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.groups.io with SMTP id smtpd.web11.8588.1716970297725894718 for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:35 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 33/47] ravb: Add Rx checksum offload support for GbEth Date: Wed, 29 May 2024 11:10:25 +0300 Message-Id: <20240529081039.639010-34-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:47 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16013 From: Biju Das commit c2da9408579d52fdf9b0ec494534d6ac66d4511e upstream. TOE has hardware support for calculating IP header and TCP/UDP/ICMP checksum for both IPv4 and IPv6. Add Rx checksum offload supported by TOE for IPv4 and TCP/UDP protocols. For Rx, the 4-byte result of checksum calculation is attached to the Ethernet frames.First 2-bytes is result of IPv4 header checksum and next 2-bytes is TCP/UDP/ICMP checksum. If a frame does not have checksum error, 0x0000 is attached as checksum calculation result. For unsupported frames 0xFFFF is attached as checksum calculation result. In case of an IPv6 packet, IPv4 checksum is always set to 0xFFFF. We can test this functionality by the below commands ethtool -K eth0 rx on --> to turn on Rx checksum offload ethtool -K eth0 rx off --> to turn off Rx checksum offload Signed-off-by: Biju Das Reviewed-by: Sergey Shtylyov Link: https://lore.kernel.org/r/20240207092838.160627-2-biju.das.jz@bp.renesas.com Signed-off-by: Jakub Kicinski Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb.h | 19 ++++- drivers/net/ethernet/renesas/ravb_main.c | 92 +++++++++++++++++++++++- 2 files changed, 107 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index 3b7016bbf716..5f573121f941 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -205,7 +205,10 @@ enum ravb_reg { TLFRCR = 0x0758, RFCR = 0x0760, MAFCR = 0x0778, - CSR0 = 0x0800, /* RZ/G2L only */ + + /* TOE registers (RZ/G2L only) */ + CSR0 = 0x0800, + CSR2 = 0x0808, }; @@ -978,6 +981,20 @@ enum CSR0_BIT { CSR0_RPE = 0x00000020, }; +enum CSR2_BIT { + CSR2_RIP4 = 0x00000001, + CSR2_RTCP4 = 0x00000010, + CSR2_RUDP4 = 0x00000020, + CSR2_RICMP4 = 0x00000040, + CSR2_RTCP6 = 0x00100000, + CSR2_RUDP6 = 0x00200000, + CSR2_RICMP6 = 0x00400000, + CSR2_RHOP = 0x01000000, + CSR2_RROUT = 0x02000000, + CSR2_RAHD = 0x04000000, + CSR2_RDHD = 0x08000000, +}; + #define DBAT_ENTRY_NUM 22 #define RX_QUEUE_OFFSET 4 #define NUM_RX_QUEUE 2 diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 478c75c94f50..d6c53ca4068d 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -510,6 +510,24 @@ static int ravb_ring_init(struct net_device *ndev, int q) return -ENOMEM; } +static void ravb_csum_init_gbeth(struct net_device *ndev) +{ + if (!(ndev->features & NETIF_F_RXCSUM)) + goto done; + + ravb_write(ndev, 0, CSR0); + if (ravb_wait(ndev, CSR0, CSR0_RPE, 0)) { + netdev_err(ndev, "Timeout enabling hardware checksum\n"); + ndev->features &= ~NETIF_F_RXCSUM; + } else { + ravb_write(ndev, CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4, + CSR2); + } + +done: + ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); +} + static void ravb_emac_init_gbeth(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); @@ -541,7 +559,8 @@ static void ravb_emac_init_gbeth(struct net_device *ndev) /* E-MAC status register clear */ ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); - ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); + + ravb_csum_init_gbeth(ndev); /* E-MAC interrupt enable register */ ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); @@ -722,6 +741,30 @@ static void ravb_get_tx_tstamp(struct net_device *ndev) } } +static void ravb_rx_csum_gbeth(struct sk_buff *skb) +{ + __wsum csum_ip_hdr, csum_proto; + u8 *hw_csum; + + /* The hardware checksum status is contained in sizeof(__sum16) * 2 = 4 + * bytes appended to packet data. First 2 bytes is ip header checksum + * and last 2 bytes is protocol checksum. + */ + if (unlikely(skb->len < sizeof(__sum16) * 2)) + return; + + hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); + csum_proto = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); + + hw_csum -= sizeof(__sum16); + csum_ip_hdr = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); + skb_trim(skb, skb->len - 2 * sizeof(__sum16)); + + /* TODO: IPV6 Rx checksum */ + if (skb->protocol == htons(ETH_P_IP) && !csum_ip_hdr && !csum_proto) + skb->ip_summed = CHECKSUM_UNNECESSARY; +} + static void ravb_rx_csum(struct sk_buff *skb) { u8 *hw_csum; @@ -803,6 +846,8 @@ static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) skb = ravb_get_skb_gbeth(ndev, entry, desc); skb_put(skb, pkt_len); skb->protocol = eth_type_trans(skb, ndev); + if (ndev->features & NETIF_F_RXCSUM) + ravb_rx_csum_gbeth(skb); napi_gro_receive(&priv->napi[q], skb); rx_packets++; stats->rx_bytes += pkt_len; @@ -830,6 +875,8 @@ static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) dev_kfree_skb(skb); priv->rx_1st_skb->protocol = eth_type_trans(priv->rx_1st_skb, ndev); + if (ndev->features & NETIF_F_RXCSUM) + ravb_rx_csum_gbeth(skb); napi_gro_receive(&priv->napi[q], priv->rx_1st_skb); rx_packets++; @@ -2403,11 +2450,48 @@ static void ravb_set_rx_csum(struct net_device *ndev, bool enable) spin_unlock_irqrestore(&priv->lock, flags); } +static int ravb_endisable_csum_gbeth(struct net_device *ndev, enum ravb_reg reg, + u32 val, u32 mask) +{ + u32 csr0 = CSR0_TPE | CSR0_RPE; + int ret; + + ravb_write(ndev, csr0 & ~mask, CSR0); + ret = ravb_wait(ndev, CSR0, mask, 0); + if (!ret) + ravb_write(ndev, val, reg); + + ravb_write(ndev, csr0, CSR0); + + return ret; +} + static int ravb_set_features_gbeth(struct net_device *ndev, netdev_features_t features) { - /* Place holder */ - return 0; + netdev_features_t changed = ndev->features ^ features; + struct ravb_private *priv = netdev_priv(ndev); + unsigned long flags; + int ret = 0; + u32 val; + + spin_lock_irqsave(&priv->lock, flags); + if (changed & NETIF_F_RXCSUM) { + if (features & NETIF_F_RXCSUM) + val = CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4; + else + val = 0; + + ret = ravb_endisable_csum_gbeth(ndev, CSR2, val, CSR0_RPE); + if (ret) + goto done; + } + + ndev->features = features; +done: + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; } static int ravb_set_features_rcar(struct net_device *ndev, @@ -2577,6 +2661,8 @@ static const struct ravb_hw_info gbeth_hw_info = { .emac_init = ravb_emac_init_gbeth, .gstrings_stats = ravb_gstrings_stats_gbeth, .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), + .net_hw_features = NETIF_F_RXCSUM, + .net_features = NETIF_F_RXCSUM, .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN), .tccr_mask = TCCR_TSRQ0, From patchwork Wed May 29 08:10:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678260 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA800C25B7E for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:37 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 34/47] ravb: Add Tx checksum offload support for GbEth Date: Wed, 29 May 2024 11:10:26 +0300 Message-Id: <20240529081039.639010-35-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:46 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16014 From: Biju Das commit 6c8e2803ef36d3c0c20c7019a19c668c3b0ac1d1 upstream. TOE has hardware support for calculating IP header and TCP/UDP/ICMP checksum for both IPv4 and IPv6. Add Tx checksum offload supported by TOE for IPv4 and TCP/UDP. For Tx, the result of checksum calculation is set to the checksum field of each IPv4 Header/TCP/UDP/ICMP of ethernet frames. For the unsupported frames, those fields are not changed. If a transmission frame is an UDPv4 frame and its checksum value in the UDP header field is 0x0000, TOE does not calculate checksum for UDP part of this frame as it is optional function as per standards. We can test this functionality by the below commands ethtool -K eth0 tx on --> to turn on Tx checksum offload ethtool -K eth0 tx off --> to turn off Tx checksum offload Signed-off-by: Biju Das Reviewed-by: Sergey Shtylyov Link: https://lore.kernel.org/r/20240207092838.160627-3-biju.das.jz@bp.renesas.com Signed-off-by: Jakub Kicinski Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb.h | 15 +++++ drivers/net/ethernet/renesas/ravb_main.c | 71 +++++++++++++++++++++--- 2 files changed, 79 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index 5f573121f941..82fea6f9a3f6 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -208,6 +208,7 @@ enum ravb_reg { /* TOE registers (RZ/G2L only) */ CSR0 = 0x0800, + CSR1 = 0x0804, CSR2 = 0x0808, }; @@ -981,6 +982,20 @@ enum CSR0_BIT { CSR0_RPE = 0x00000020, }; +enum CSR1_BIT { + CSR1_TIP4 = 0x00000001, + CSR1_TTCP4 = 0x00000010, + CSR1_TUDP4 = 0x00000020, + CSR1_TICMP4 = 0x00000040, + CSR1_TTCP6 = 0x00100000, + CSR1_TUDP6 = 0x00200000, + CSR1_TICMP6 = 0x00400000, + CSR1_THOP = 0x01000000, + CSR1_TROUT = 0x02000000, + CSR1_TAHD = 0x04000000, + CSR1_TDHD = 0x08000000, +}; + enum CSR2_BIT { CSR2_RIP4 = 0x00000001, CSR2_RTCP4 = 0x00000010, diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index d6c53ca4068d..e3f475b73ea4 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "ravb.h" @@ -512,16 +513,28 @@ static int ravb_ring_init(struct net_device *ndev, int q) static void ravb_csum_init_gbeth(struct net_device *ndev) { - if (!(ndev->features & NETIF_F_RXCSUM)) + bool tx_enable = ndev->features & NETIF_F_HW_CSUM; + bool rx_enable = ndev->features & NETIF_F_RXCSUM; + + if (!(tx_enable || rx_enable)) goto done; ravb_write(ndev, 0, CSR0); - if (ravb_wait(ndev, CSR0, CSR0_RPE, 0)) { + if (ravb_wait(ndev, CSR0, CSR0_TPE | CSR0_RPE, 0)) { netdev_err(ndev, "Timeout enabling hardware checksum\n"); - ndev->features &= ~NETIF_F_RXCSUM; + + if (tx_enable) + ndev->features &= ~NETIF_F_HW_CSUM; + + if (rx_enable) + ndev->features &= ~NETIF_F_RXCSUM; } else { - ravb_write(ndev, CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4, - CSR2); + if (tx_enable) + ravb_write(ndev, CSR1_TIP4 | CSR1_TTCP4 | CSR1_TUDP4, CSR1); + + if (rx_enable) + ravb_write(ndev, CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4, + CSR2); } done: @@ -2063,6 +2076,36 @@ static void ravb_tx_timeout_work(struct work_struct *work) rtnl_unlock(); } +static bool ravb_can_tx_csum_gbeth(struct sk_buff *skb) +{ + struct iphdr *ip = ip_hdr(skb); + + /* TODO: Need to add support for VLAN tag 802.1Q */ + if (skb_vlan_tag_present(skb)) + return false; + + /* TODO: Need to add hardware checksum for IPv6 */ + if (skb->protocol != htons(ETH_P_IP)) + return false; + + switch (ip->protocol) { + case IPPROTO_TCP: + break; + case IPPROTO_UDP: + /* If the checksum value in the UDP header field is 0, TOE does + * not calculate checksum for UDP part of this frame as it is + * optional function as per standards. + */ + if (udp_hdr(skb)->check == 0) + return false; + break; + default: + return false; + } + + return true; +} + /* Packet transmit function for Ethernet AVB */ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) { @@ -2078,6 +2121,9 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) u32 entry; u32 len; + if (skb->ip_summed == CHECKSUM_PARTIAL && !ravb_can_tx_csum_gbeth(skb)) + skb_checksum_help(skb); + spin_lock_irqsave(&priv->lock, flags); if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * num_tx_desc) { @@ -2487,6 +2533,17 @@ static int ravb_set_features_gbeth(struct net_device *ndev, goto done; } + if (changed & NETIF_F_HW_CSUM) { + if (features & NETIF_F_HW_CSUM) + val = CSR1_TIP4 | CSR1_TTCP4 | CSR1_TUDP4; + else + val = 0; + + ret = ravb_endisable_csum_gbeth(ndev, CSR1, val, CSR0_TPE); + if (ret) + goto done; + } + ndev->features = features; done: spin_unlock_irqrestore(&priv->lock, flags); @@ -2661,8 +2718,8 @@ static const struct ravb_hw_info gbeth_hw_info = { .emac_init = ravb_emac_init_gbeth, .gstrings_stats = ravb_gstrings_stats_gbeth, .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), - .net_hw_features = NETIF_F_RXCSUM, - .net_features = NETIF_F_RXCSUM, + .net_hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, + .net_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN), .tccr_mask = TCCR_TSRQ0, From patchwork Wed May 29 08:10:27 2024 Content-Type: text/plain; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:39 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 35/47] net: ravb: Get rid of the temporary variable irq Date: Wed, 29 May 2024 11:10:27 +0300 Message-Id: <20240529081039.639010-36-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:46 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16015 From: Claudiu Beznea commit a260f080660ef8bac97404dd0b9ddbe35a608426 upstream. The 4th argument of ravb_setup_irq() is used to save the IRQ number that will be further used by the driver code. Not all ravb_setup_irqs() calls need to save the IRQ number. The previous code used to pass a dummy variable as the 4th argument in case the IRQ is not needed for further usage. That is not necessary as the code from ravb_setup_irq() can detect by itself if the IRQ needs to be saved. Thus, get rid of the code that is not needed. Reported-by: Sergey Shtylyov Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: David S. Miller Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 29 +++++++++++++----------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index e3f475b73ea4..d9c6a4d048c8 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2750,24 +2750,27 @@ static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, struct device *dev = &pdev->dev; const char *dev_name; unsigned long flags; - int error; + int error, irq_num; if (irq_name) { dev_name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); if (!dev_name) return -ENOMEM; - *irq = platform_get_irq_byname(pdev, irq_name); + irq_num = platform_get_irq_byname(pdev, irq_name); flags = 0; } else { dev_name = ndev->name; - *irq = platform_get_irq(pdev, 0); + irq_num = platform_get_irq(pdev, 0); flags = IRQF_SHARED; } - if (*irq < 0) - return *irq; + if (irq_num < 0) + return irq_num; + + if (irq) + *irq = irq_num; - error = devm_request_irq(dev, *irq, handler, flags, dev_name, ndev); + error = devm_request_irq(dev, irq_num, handler, flags, dev_name, ndev); if (error) netdev_err(ndev, "cannot request IRQ %s\n", dev_name); @@ -2779,7 +2782,7 @@ static int ravb_setup_irqs(struct ravb_private *priv) const struct ravb_hw_info *info = priv->info; struct net_device *ndev = priv->ndev; const char *irq_name, *emac_irq_name; - int error, irq; + int error; if (!info->multi_irqs) return ravb_setup_irq(priv, NULL, NULL, &ndev->irq, ravb_interrupt); @@ -2802,28 +2805,28 @@ static int ravb_setup_irqs(struct ravb_private *priv) return error; if (info->err_mgmt_irqs) { - error = ravb_setup_irq(priv, "err_a", "err_a", &irq, ravb_multi_interrupt); + error = ravb_setup_irq(priv, "err_a", "err_a", NULL, ravb_multi_interrupt); if (error) return error; - error = ravb_setup_irq(priv, "mgmt_a", "mgmt_a", &irq, ravb_multi_interrupt); + error = ravb_setup_irq(priv, "mgmt_a", "mgmt_a", NULL, ravb_multi_interrupt); if (error) return error; } - error = ravb_setup_irq(priv, "ch0", "ch0:rx_be", &irq, ravb_be_interrupt); + error = ravb_setup_irq(priv, "ch0", "ch0:rx_be", NULL, ravb_be_interrupt); if (error) return error; - error = ravb_setup_irq(priv, "ch1", "ch1:rx_nc", &irq, ravb_nc_interrupt); + error = ravb_setup_irq(priv, "ch1", "ch1:rx_nc", NULL, ravb_nc_interrupt); if (error) return error; - error = ravb_setup_irq(priv, "ch18", "ch18:tx_be", &irq, ravb_be_interrupt); + error = ravb_setup_irq(priv, "ch18", "ch18:tx_be", NULL, ravb_be_interrupt); if (error) return error; - return ravb_setup_irq(priv, "ch19", "ch19:tx_nc", &irq, ravb_nc_interrupt); + return ravb_setup_irq(priv, "ch19", "ch19:tx_nc", NULL, ravb_nc_interrupt); } static int ravb_probe(struct platform_device *pdev) From patchwork Wed May 29 08:10:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0364C27C50 for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:40 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 36/47] net: ravb: Keep the reverse order of operations in ravb_close() Date: Wed, 29 May 2024 11:10:28 +0300 Message-Id: <20240529081039.639010-37-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:46 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16016 From: Claudiu Beznea commit a5f149a97d09cc9340d8fb4e22a3074a7bc1e02d upstream. Keep the reverse order of operations in ravb_close() when compared with ravb_open(). This is the recommended configuration sequence. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: David S. Miller Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index d9c6a4d048c8..83b08ff417f6 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2331,6 +2331,14 @@ static int ravb_close(struct net_device *ndev) ravb_write(ndev, 0, RIC2); ravb_write(ndev, 0, TIC); + /* PHY disconnect */ + if (ndev->phydev) { + phy_stop(ndev->phydev); + phy_disconnect(ndev->phydev); + if (of_phy_is_fixed_link(np)) + of_phy_deregister_fixed_link(np); + } + /* Stop PTP Clock driver */ if (info->gptp || info->ccc_gac) ravb_ptp_stop(ndev); @@ -2349,14 +2357,6 @@ static int ravb_close(struct net_device *ndev) } } - /* PHY disconnect */ - if (ndev->phydev) { - phy_stop(ndev->phydev); - phy_disconnect(ndev->phydev); - if (of_phy_is_fixed_link(np)) - of_phy_deregister_fixed_link(np); - } - cancel_work_sync(&priv->work); if (info->nc_queues) From patchwork Wed May 29 08:10:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678264 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7E9EC25B7C for ; Wed, 29 May 2024 08:11:46 +0000 (UTC) Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.groups.io with SMTP id smtpd.web10.8658.1716970304604974979 for ; Wed, 29 May 2024 01:11:44 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=i3drNVKk; spf=pass (domain: tuxon.dev, ip: 209.85.128.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-4202ca70270so21103655e9.3 for ; Wed, 29 May 2024 01:11:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970303; x=1717575103; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qqBLLg0SpKEPSEmPNwjc+KfOGmoOd83xGC6XKChYGtw=; b=i3drNVKkA59qJU01WdjnRNg4yts9vSbi7VZ1YfpPQGRz7duvqgRN28Bl+e2eobUnW6 9yCJ+Tv0xaAGPE94m7RqHYHJZeBsFpeU/FUfetfvbVQpBrxsYkY+5dihS2SMSXD20TQ3 /t6VcZ/DA5A1xIGvISMEjrY/5zYTb0Wx+Cxdov3iZvP3HyennohBiLPDeWMDl6nodKYs PukDEeS8v2BcVwQqWvIVqsOQETy9rLzpW8IPIIjNsUkFqMXMSTE5Sikf2rzV6Pq0efH3 Pige1yxrZLtZOBcPHQFEgq8nDd3QxFxakmBseD9DAg9IY9Z3AfT5GYRzLBLy1QkJRJrW 6/OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970303; x=1717575103; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qqBLLg0SpKEPSEmPNwjc+KfOGmoOd83xGC6XKChYGtw=; b=elPReUvGU3YMjYTw918i3ZLlYvghmnmKIsHLxJe3Ano8KAn0rqaen90gdx+OqKWwTo kSr07HdNSDarAASB6PVPp6zlRt8PKN9/DblodtqVHGk2gXrsrUGv5sUVnePsq7q0LnMI zi2SmPa++kTcub7ooo0HBrozNlzIho6MYtGL+mUuCHt90WVJvlOQ9W/8E7JBoCP43DNo L2zH2yYJApc1E5TSrqG0GV0BS4Ja8QUZLResZqXebdXbD1mt+RFmzhmoSO419a9DyNLq BLG81JEjB+A4f6GWWkWw3mulQqR62T7OzTrcyM0Qx5T0WKsbJx3rZPs/8/9Th8OBhhaP Qoow== X-Gm-Message-State: AOJu0YwEioTUiD15jQBIuqsaIeC2fROiZ2Mo9SRp66OhYgwCa6ufbgnP BcCcG7N+7sRmxV81vzviWv7iSEeQmb6AAgTys5izFC4YcH3JBf7DhspayOkPf60= X-Google-Smtp-Source: AGHT+IHCC0YnHnLKtJ8iD4maUJZEMuBeOzuvWHBiZ43yr5WPXUaYU/oFpdDi6BL4mCI84lQi6nulwQ== X-Received: by 2002:a05:600c:5613:b0:415:540e:74e3 with SMTP id 5b1f17b1804b1-42108aa7e26mr133704075e9.40.1716970302962; Wed, 29 May 2024 01:11:42 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:42 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 37/47] net: ravb: Return cached statistics if the interface is down Date: Wed, 29 May 2024 11:10:29 +0300 Message-Id: <20240529081039.639010-38-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:46 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16017 From: Claudiu Beznea commit bbf2345fa6582c5292bc5c537e7a29aad918be0c upstream. Return the cached statistics in case the interface is down. There should be no drawback to this, as cached statistics are updated in ravb_close(). In order to avoid accessing the IP registers while the IP is runtime suspended pm_runtime_active() check was introduced. The device runtime PM usage counter has been incremented to avoid disabling the device clocks while the check is in progress (if any). The commit prepares the code for the addition of runtime PM support. Suggested-by: Sergey Shtylyov Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: David S. Miller Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 83b08ff417f6..791a65183a48 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2258,8 +2258,15 @@ static struct net_device_stats *ravb_get_stats(struct net_device *ndev) struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; struct net_device_stats *nstats, *stats0, *stats1; + struct device *dev = &priv->pdev->dev; nstats = &ndev->stats; + + pm_runtime_get_noresume(dev); + + if (!pm_runtime_active(dev)) + goto out_rpm_put; + stats0 = &priv->stats[RAVB_BE]; if (info->tx_counters) { @@ -2301,6 +2308,8 @@ static struct net_device_stats *ravb_get_stats(struct net_device *ndev) nstats->rx_over_errors += stats1->rx_over_errors; } +out_rpm_put: + pm_runtime_put_noidle(dev); return nstats; } @@ -2368,6 +2377,9 @@ static int ravb_close(struct net_device *ndev) if (info->nc_queues) ravb_ring_free(ndev, RAVB_NC); + /* Update statistics. */ + ravb_get_stats(ndev); + /* Set reset mode. */ return ravb_set_opmode(ndev, CCC_OPC_RESET); } From patchwork Wed May 29 08:10:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678265 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02306C27C51 for ; Wed, 29 May 2024 08:11:47 +0000 (UTC) Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.groups.io with SMTP id smtpd.web10.8660.1716970305706929806 for ; Wed, 29 May 2024 01:11:46 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=SjgJg820; spf=pass (domain: tuxon.dev, ip: 209.85.128.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-4211a86f124so15064725e9.0 for ; Wed, 29 May 2024 01:11:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970304; x=1717575104; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K2Mkhe8Sds9oK4AvQt0vChY01f/jyL7Ufva/hJ3oa2w=; b=SjgJg820lhqqawZ+h/vAvigOKZQVfr8mrmP5Z26JHHtpx40+14Rg+s7DrSaKkPTz+B 9KWCagHNYbDsBuv1+ll79E64kx/QUKOZGyhK7pFCdf8vCR/GoGRoQ5gMsoqSeS7Ri7um EcEdvWmmWGz/7e5mNxphsEfs00OeJxFo5wSoWpBa6+Fa7a8cu6pppRqqCV6gRaUsnCdU oS/y6JK895u59PemSHVuo4uQ2Fj/yrYQLXM4Z/J5V5YcInudIE/z2PCEg+CS0+fchRQw voBA1WbBv1Ot7Ljlbz20+sNp9TdDvFKjABdRYooQ1GKIPWPqiSGXuA4KzSi9JDbcO1sc x60w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970304; x=1717575104; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K2Mkhe8Sds9oK4AvQt0vChY01f/jyL7Ufva/hJ3oa2w=; b=G0A8C3Z663ijG1h81SFxngnnSHS7QUtrufAQwwpTNcdz2vw5vWVrD9q6WduqzAvJiz Fa+fOg1VLX5qdfj/f7cIeseOdl8eOppW7Xgoo+gFNLuVEPdaKYeyY0fWw8HRkpsRWM7Q GkKk8HDdI/OX1Vxm/zHIB5wKYdHPEFyScxwu/vEoasVPweYsprSX6O0Ekmn8aFaXWxHO WL/p8cdJAxDDQq4RGqpVZ/3K54avXtoAthQsEubBDi8kQUGF2rONn0R/xlbnrZDMz4Zk AU+Jhh58s8B2IINMThHbbe42adR+nMZfzd44ZU91+cRjVJ7VKangbaUtsvV2AmTh8Kzl ZMEA== X-Gm-Message-State: AOJu0YwhyWpEDdKSuDIskkBZ1D0FpjQzCQMbFZxa9y7g8+H9R3B4hcnG eSUhE9KuB5ZjDz1EnmNkVtQiwFQ3fjM1RvLfqFMXji+kvbf+JrRaE+FZ6s2aZSQ= X-Google-Smtp-Source: AGHT+IEOSEqEpX4H09IbaqF0fZ6qGVyXbn2KRUrfk0XOjyopOJafom1NgX7XpxoLz79MLYxIHCISmQ== X-Received: by 2002:a05:600c:198d:b0:41b:f41a:c67e with SMTP id 5b1f17b1804b1-42108a20cf4mr91538735e9.33.1716970304159; Wed, 29 May 2024 01:11:44 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:43 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 38/47] net: ravb: Move the update of ndev->features to ravb_set_features() Date: Wed, 29 May 2024 11:10:30 +0300 Message-Id: <20240529081039.639010-39-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:47 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16018 From: Claudiu Beznea commit 7bddccc9911cdff377e16b9a5a386721279b4438 upstream. Commit c2da9408579d ("ravb: Add Rx checksum offload support for GbEth") introduced support for setting GbEth features. With this the IP-specific features update functions update the ndev->features individually. Next commits add runtime PM support for the ravb driver. The runtime PM implementation will enable/disable the IP clocks on the ravb_open()/ravb_close() functions. Accessing the IP registers with clocks disabled blocks the system. The ravb_set_features() function could be executed when the Ethernet interface is closed so we need to ensure we don't access IP registers while the interface is down when runtime PM support will be in place. For these, move the update of ndev->features to ravb_set_features(). In this way we update the ndev->features only when the IP-specific features set function returns success and we can avoid code duplication when introducing runtime PM registers protection. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: David S. Miller Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 791a65183a48..2324b2dd59a5 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2556,7 +2556,6 @@ static int ravb_set_features_gbeth(struct net_device *ndev, goto done; } - ndev->features = features; done: spin_unlock_irqrestore(&priv->lock, flags); @@ -2571,8 +2570,6 @@ static int ravb_set_features_rcar(struct net_device *ndev, if (changed & NETIF_F_RXCSUM) ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); - ndev->features = features; - return 0; } @@ -2581,8 +2578,15 @@ static int ravb_set_features(struct net_device *ndev, { struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; + int ret; + + ret = info->set_feature(ndev, features); + if (ret) + return ret; - return info->set_feature(ndev, features); + ndev->features = features; + + return 0; } static const struct net_device_ops ravb_netdev_ops = { From patchwork Wed May 29 08:10:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678268 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09B6AC25B75 for ; Wed, 29 May 2024 08:11:57 +0000 (UTC) Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) by mx.groups.io with SMTP id smtpd.web11.8595.1716970307533068527 for ; Wed, 29 May 2024 01:11:47 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=HjboJI4H; spf=pass (domain: tuxon.dev, ip: 209.85.167.54, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-52ae38957e8so419012e87.1 for ; Wed, 29 May 2024 01:11:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970306; x=1717575106; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vRspZq/JdEPxTwBOFKReBYsJHFQhHEPH8GqLa6asvI0=; b=HjboJI4Hp0rXRlFUZo8hnjvM3qvfKYLBXaJfQjuUBFpEg6O1aOQOR5gIUhaSyeEMZP nm7H+ZPwxBbo0Zf8je3QK2vzhhGJSMSVeOIkd+Fvo2tNG15JEvV1FjlC8GWSRgHYOO9G DFm+exWHOIR0eTZt/RceBXJ84i1tOynWe2I3FjGW3tWKpipMX4jWVpZRTM23TxdOcFqz 9Di5x2FYFHdEwKzGXSkk5NfJO1AjpxY+HZV86fmuo+inXP69hkMfHORMT5OHDTM5+cx/ RNcWziJ84vckZuHZEcE9/Pam9zv8lU5IV0VZGiU92at49rFuFQBOSKWFgvPkwGTKRu7i CcMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970306; x=1717575106; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vRspZq/JdEPxTwBOFKReBYsJHFQhHEPH8GqLa6asvI0=; b=XhXu1/H0pq2DUN1tI6csaaJfVu/YJXXzXMf6n8ffr8+xWWTS4w/emVpnG1FJHpLQnK gpqYi9F2Hs0/xbB1835zVFAobyUpEALHZ3ClFdDXki+xBwCc3hIQNemtS4Li7hoSWEqj NzdPMOOf1E8rI1urBgIggC+lPDPp9RmqqX5tVeIeDpZljNwLtpdNMppAXI31hqDvzSjE Im45TaTcRXNDsk21AU0dnjfsE27k9xfJX5qg3Ot5I6AD0YQXlzErhZ1Ml8A5sq92Wm2C BwTGHjIiVBCZ7oEbfRpj8eBPjE3P/efiIeLkvQGgxtK4jhtA5a0oIQKCi+vx1zwl8TUG It5A== X-Gm-Message-State: AOJu0YxY7mpT04rMeQANMYoJ+OAwLt9Khbe5dJU3eZN9BNwrH/TIdQws 64T8wCxEusJwc3eK5citDjgoyJkET43pul4bCdAwlj9NADVySz1H74HgiKP8oozyUJ6jc0iRQlc zSzw= X-Google-Smtp-Source: AGHT+IEk2DMfEMBMUm4E/miOhSIIl4X7BS1EItNcD3dvw2AlqQNoyZa6ketAdGyVWAfF5O5L9OmViQ== X-Received: by 2002:a05:6512:544:b0:529:b632:ae4e with SMTP id 2adb3069b0e04-529b632af8bmr3392493e87.2.1716970305684; Wed, 29 May 2024 01:11:45 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:45 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 39/47] net: ravb: Do not apply features to hardware if the interface is down Date: Wed, 29 May 2024 11:10:31 +0300 Message-Id: <20240529081039.639010-40-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16019 From: Claudiu Beznea commit a71a50e391bf00fdc88bb13a867620c59ad744da upstream. Do not apply features to hardware if the interface is down. In case runtime PM is enabled, and while the interface is down, the IP will be in reset mode (as for some platforms disabling the clocks will switch the IP to reset mode, which will lead to losing register contents) and applying settings in reset mode is not an option. Instead, cache the features and apply them in ravb_open() through ravb_emac_init(). To avoid accessing the hardware while the interface is down pm_runtime_active() check was introduced. Along with it the device runtime PM usage counter has been incremented to avoid disabling the device clocks while the check is in progress (if any). Commit prepares for the addition of runtime PM. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: David S. Miller Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 2324b2dd59a5..a9046c620808 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2578,9 +2578,18 @@ static int ravb_set_features(struct net_device *ndev, { struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; + struct device *dev = &priv->pdev->dev; int ret; - ret = info->set_feature(ndev, features); + pm_runtime_get_noresume(dev); + + if (pm_runtime_active(dev)) + ret = info->set_feature(ndev, features); + else + ret = 0; + + pm_runtime_put_noidle(dev); + if (ret) return ret; From patchwork Wed May 29 08:10:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678272 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 365C1C27C50 for ; Wed, 29 May 2024 08:11:57 +0000 (UTC) Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) by mx.groups.io with SMTP id smtpd.web10.8661.1716970308514821997 for ; Wed, 29 May 2024 01:11:48 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=asrO2zIC; spf=pass (domain: tuxon.dev, ip: 209.85.128.48, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-4211249fdf4so16469415e9.3 for ; Wed, 29 May 2024 01:11:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970307; x=1717575107; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uBVcx36jO/PSdp3Opi87Nuqb5fO37jxAByWe1W7vRVk=; b=asrO2zICPukOGiDlpJwJRb4JQU3CoQbwBOjQlP5lb98QfnUVJeaOk+c9z8JiyWovnO fraZzfkDQB6uHd9VyqYH4BTWa9Nb9V2weXt06A0dSeB/T8G5Tg1NJQdp+Nmyz6QW/ltq 9DX6OjLls5sYt9f8XgQ6RvYexSBI9GmJD4EHtskmFw9QLjWEkrgnS9CiJ/WLuRafB2ff mufsx2tqSPZAZ9i2KtdGpwMZ1jybgXRFdWOO5ZugkyD37kz/jRB01IPk8HOaX5QeUwC6 B1ugr0xQ3q/qzeERv597IWixcJ24IHM2W52ckOU7rHCJYL2JixN3KDqufo0OdMKxwsiR 0iwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970307; x=1717575107; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uBVcx36jO/PSdp3Opi87Nuqb5fO37jxAByWe1W7vRVk=; b=Er9nD0A3IO2sOv7ZZacglN6hWk3Bn/kr6ZjhIcGR3MqX5y532oqJ2L6SNo49Os0mqG Ltp6ZijP19T5MNJQzJSNLnw6AZWc8Yfzv2AIEgYLoUuUGLoSc4KbU2eXPw6i7qcOyH8f JvcZY1aMT1zyNOvXzxUuMsttraXrpRUmjqoWAtxiMcomLWqwqEq6AkH3/cVjdCgqomkl qNs733X9ozDUp3aSybDguIcA1OAM1fEJ0QfMfvUonS/Q7QwzIslVi7fP8f7crULEDl/E Ojgs65Hdxq/xbDfCM++Sf9Qw8vdz2tiQjOevC3NYAQP28KgVPUrv4L8gsXwODwDhWtnk dKKA== X-Gm-Message-State: AOJu0YyyrOplmDnfgKe3CIhjHfZupDfyKcdU31guxLmHcdo21WK4IuXj HfaySNQT7atKLD6pR/hxZWYu1eVywo6qxxO6YmYp2rbYCwkjFNiZJJgAb2bwojc= X-Google-Smtp-Source: AGHT+IF1OqM0pESyP/QaL6fOjtKXBiG9zrKHSbNUcC6b8+aau6xYbddA1KG76VD99rm/dlva++sNbQ== X-Received: by 2002:a05:600c:1c88:b0:41a:b961:9495 with SMTP id 5b1f17b1804b1-42108aa8a2bmr117037625e9.25.1716970306926; Wed, 29 May 2024 01:11:46 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:46 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 40/47] net: ravb: Add runtime PM support Date: Wed, 29 May 2024 11:10:32 +0300 Message-Id: <20240529081039.639010-41-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16020 From: Claudiu Beznea commit 48f894ab07c444b9b26a0913d2032de663f4aecb upstream. Add runtime PM support for the ravb driver. As the driver is used by different IP variants, with different behaviors, to be able to have the runtime PM support available for all devices, the preparatory commits moved all the resources parsing and allocations in the driver's probe function and kept the settings for ravb_open(). This is due to the fact that on some IP variants-platforms tuples disabling/enabling the clocks will switch the IP to the reset operation mode where register contents is lost and reconfiguration needs to be done. For this the rabv_open() function enables the clocks, switches the IP to configuration mode, applies all the register settings and switches the IP to the operational mode. At the end of ravb_open() IP is ready to send/receive data. In ravb_close() necessary reverts are done (compared with ravb_open()), the IP is switched to reset mode and clocks are disabled. The ethtool APIs or IOCTLs that might execute while the interface is down are either cached (and applied in ravb_open()) or rejected (as at that time the IP is in reset mode). Keeping the IP in the reset mode also increases the power saved (according to the hardware manual). Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: David S. Miller [claudiu.beznea: adjusted to return error in ravb_remove() if pm_runtime_resume_and_get() fail] Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 54 ++++++++++++++++++++++-- 1 file changed, 50 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index a9046c620808..a64a8ea84c57 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1949,16 +1949,21 @@ static int ravb_open(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; + struct device *dev = &priv->pdev->dev; int error; napi_enable(&priv->napi[RAVB_BE]); if (info->nc_queues) napi_enable(&priv->napi[RAVB_NC]); + error = pm_runtime_resume_and_get(dev); + if (error < 0) + goto out_napi_off; + /* Set AVB config mode */ error = ravb_set_config_mode(ndev); if (error) - goto out_napi_off; + goto out_rpm_put; ravb_set_delay_mode(ndev); ravb_write(ndev, priv->desc_bat_dma, DBAT); @@ -1992,6 +1997,9 @@ static int ravb_open(struct net_device *ndev) ravb_stop_dma(ndev); out_set_reset: ravb_set_opmode(ndev, CCC_OPC_RESET); +out_rpm_put: + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); out_napi_off: if (info->nc_queues) napi_disable(&priv->napi[RAVB_NC]); @@ -2332,6 +2340,8 @@ static int ravb_close(struct net_device *ndev) struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; struct ravb_tstamp_skb *ts_skb, *ts_skb2; + struct device *dev = &priv->pdev->dev; + int error; netif_tx_stop_all_queues(ndev); @@ -2381,7 +2391,14 @@ static int ravb_close(struct net_device *ndev) ravb_get_stats(ndev); /* Set reset mode. */ - return ravb_set_opmode(ndev, CCC_OPC_RESET); + error = ravb_set_opmode(ndev, CCC_OPC_RESET); + if (error) + return error; + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return 0; } static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) @@ -2929,6 +2946,8 @@ static int ravb_probe(struct platform_device *pdev) clk_prepare(priv->refclk); platform_set_drvdata(pdev, ndev); + pm_runtime_set_autosuspend_delay(&pdev->dev, 100); + pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_enable(&pdev->dev); error = pm_runtime_resume_and_get(&pdev->dev); if (error < 0) @@ -3034,6 +3053,9 @@ static int ravb_probe(struct platform_device *pdev) netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); + return 0; out_napi_del: @@ -3051,6 +3073,7 @@ static int ravb_probe(struct platform_device *pdev) pm_runtime_put(&pdev->dev); out_rpm_disable: pm_runtime_disable(&pdev->dev); + pm_runtime_dont_use_autosuspend(&pdev->dev); clk_unprepare(priv->refclk); out_reset_assert: reset_control_assert(rstc); @@ -3064,6 +3087,12 @@ static int ravb_remove(struct platform_device *pdev) struct net_device *ndev = platform_get_drvdata(pdev); struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; + struct device *dev = &priv->pdev->dev; + int error; + + error = pm_runtime_resume_and_get(dev); + if (error < 0) + return error; unregister_netdev(ndev); if (info->nc_queues) @@ -3075,8 +3104,9 @@ static int ravb_remove(struct platform_device *pdev) dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, priv->desc_bat_dma); - pm_runtime_put_sync(&pdev->dev); + pm_runtime_put_sync_suspend(&pdev->dev); pm_runtime_disable(&pdev->dev); + pm_runtime_dont_use_autosuspend(dev); clk_unprepare(priv->refclk); reset_control_assert(priv->rstc); free_netdev(ndev); @@ -3160,6 +3190,10 @@ static int __maybe_unused ravb_suspend(struct device *dev) if (ret) return ret; + ret = pm_runtime_force_suspend(&priv->pdev->dev); + if (ret) + return ret; + reset_assert: return reset_control_assert(priv->rstc); } @@ -3182,16 +3216,28 @@ static int __maybe_unused ravb_resume(struct device *dev) ret = ravb_wol_restore(ndev); if (ret) return ret; + } else { + ret = pm_runtime_force_resume(dev); + if (ret) + return ret; } /* Reopening the interface will restore the device to the working state. */ ret = ravb_open(ndev); if (ret < 0) - return ret; + goto out_rpm_put; ravb_set_rx_mode(ndev); netif_device_attach(ndev); + return 0; + +out_rpm_put: + if (!priv->wol_enabled) { + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + } + return ret; } From patchwork Wed May 29 08:10:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678267 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09C4BC41513 for ; Wed, 29 May 2024 08:11:57 +0000 (UTC) Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.groups.io with SMTP id smtpd.web10.8663.1716970310138043340 for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:48 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 41/47] net: ravb: Fix GbEth jumbo packet RX checksum handling Date: Wed, 29 May 2024 11:10:33 +0300 Message-Id: <20240529081039.639010-42-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16021 From: Paul Barker commit c7c449502b51c5b5de79f97a42be750b28f6ecee upstream. Sending a 7kB ping packet to the RZ/G2L in v6.9-rc2 causes the following backtrace: WARNING: CPU: 0 PID: 0 at include/linux/skbuff.h:3127 skb_trim+0x30/0x38 Hardware name: Renesas SMARC EVK based on r9a07g044l2 (DT) pc : skb_trim+0x30/0x38 lr : ravb_rx_csum_gbeth+0x40/0x90 Call trace: skb_trim+0x30/0x38 ravb_rx_gbeth+0x56c/0x5cc ravb_poll+0xa0/0x204 __napi_poll+0x38/0x17c This is caused by ravb_rx_gbeth() calling ravb_rx_csum_gbeth() with the wrong skb for a packet which spans multiple descriptors. To fix this, use the correct skb. Fixes: c2da9408579d ("ravb: Add Rx checksum offload support for GbEth") Signed-off-by: Paul Barker Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index a64a8ea84c57..fb0fc86a2239 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -889,7 +889,7 @@ static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) priv->rx_1st_skb->protocol = eth_type_trans(priv->rx_1st_skb, ndev); if (ndev->features & NETIF_F_RXCSUM) - ravb_rx_csum_gbeth(skb); + ravb_rx_csum_gbeth(priv->rx_1st_skb); napi_gro_receive(&priv->napi[q], priv->rx_1st_skb); rx_packets++; From patchwork Wed May 29 08:10:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678271 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 181E8C25B7E for ; Wed, 29 May 2024 08:11:57 +0000 (UTC) Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by mx.groups.io with SMTP id smtpd.web10.8664.1716970311568917415 for ; Wed, 29 May 2024 01:11:51 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=fqkAibwe; spf=pass (domain: tuxon.dev, ip: 209.85.128.46, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-420180b5838so9413495e9.2 for ; Wed, 29 May 2024 01:11:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970310; x=1717575110; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7vS+pq8MH7tDsD9QZljjbHYf+LZeL98CDK0/iuomJdI=; b=fqkAibwe6q8lVvI9ak8/qWq/lh21MfdpHeJgeDfTDpuM4GMj2+1jX5Xaq3zKNwx8uC 6HotqbgLEruQTA9utzTm1LSbukblXgDCF2WJOR8XBW4/HDibf96BU9ps472ywSHgLuOI UE8b6vJ8Lp6rWttLegXODZtehXW7Iz2JNZat91gNV2XxKR5svZJIAJF8ph7Sph4o/oL5 Wh4mDIWdxdImCzu55H68hlvoM3nOIuh0K+BbVX/qwi7NaD7ODM+8/6Or/Em4454Guxbj sebZb4srXMkBVlCJaoX+v8eHHRM8KtaDBGZPtZsveT3vR54BWVDUPeRVJJpCazibyHJD PcgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970310; x=1717575110; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7vS+pq8MH7tDsD9QZljjbHYf+LZeL98CDK0/iuomJdI=; b=YeLAG/Gr5vSLc0s4a7EDbg2HZ3CtlHDmVb6gW3pnSiDEPQVPQQVXrza7fK/BoxzZx8 qTAInxrzXUlhKuDOKPbIz3yh4AnMv8nrdvkb6z8xcd+iZ0mogYBqeU1XDGZJT5l6NjJw QZNoGDu+zPlTBKJ+fJHfgLAFeC9Snr7HeBiaog8MOCTTySAjfgq2m7jrj2m5TOaZGlKw J1CUS5F2HmSTNy0C4oSbflgXOys+Zu+PH+Np/Moc+XBKhu/tZTAh7vSZJi8kHY157uUM AS4GB4JWFcwQyw3X9Z3OMLqVykO3WRczvAIRmo6mgwDmQ3rUMdkvnN9tPCJI5nFAN86Y AcLA== X-Gm-Message-State: AOJu0Yxy1cro/ubSwjouG35NLLrNkiJLQ85R1XZqmLAOD09DY3FgcXhw z5dhwk6QPSPf8N0B6Zznt/vHpObY2J2OUGwFivIGpmHuR0vdu4YlW3lgFsbL3ME= X-Google-Smtp-Source: AGHT+IFjrDneHBlvV8saQaRWG3iH/Qqns5k5fn7xwQEKQP10L/V5wJDmaGSKC9nprhZEtefMUARVjg== X-Received: by 2002:a05:600c:4f90:b0:41b:f979:e19b with SMTP id 5b1f17b1804b1-42108a18a20mr133486995e9.39.1716970310123; Wed, 29 May 2024 01:11:50 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:49 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 42/47] net: ravb: Fix RX byte accounting for jumbo packets Date: Wed, 29 May 2024 11:10:34 +0300 Message-Id: <20240529081039.639010-43-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16022 From: Paul Barker commit 2e36c9fbc476f95a1b19e3fa0a2cdf408475ff56 upstream. The RX byte accounting for jumbo packets was changed to fix a potential use-after-free bug. However, that fix used the wrong variable and so only accounted for the number of bytes in the final descriptor, not the number of bytes in the whole packet. To fix this, we can simply update our stats with the correct number of bytes before calling napi_gro_receive(). Also rename pkt_len to desc_len in ravb_rx_gbeth() to avoid any future confusion. The variable name pkt_len is correct in ravb_rx_rcar() as that function does not handle packets spanning multiple descriptors. Fixes: 5a5a3e564de6 ("ravb: Fix potential use-after-free in ravb_rx_gbeth()") Signed-off-by: Paul Barker Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index fb0fc86a2239..c4ee77d41329 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -818,7 +818,7 @@ static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) dma_addr_t dma_addr; int rx_packets = 0; u8 desc_status; - u16 pkt_len; + u16 desc_len; u8 die_dt; int entry; int limit; @@ -833,10 +833,10 @@ static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) /* Descriptor type must be checked before all other reads */ dma_rmb(); desc_status = desc->msc; - pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; + desc_len = le16_to_cpu(desc->ds_cc) & RX_DS; /* We use 0-byte descriptors to mark the DMA mapping errors */ - if (!pkt_len) + if (!desc_len) continue; if (desc_status & MSC_MC) @@ -857,25 +857,25 @@ static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) switch (die_dt) { case DT_FSINGLE: skb = ravb_get_skb_gbeth(ndev, entry, desc); - skb_put(skb, pkt_len); + skb_put(skb, desc_len); skb->protocol = eth_type_trans(skb, ndev); if (ndev->features & NETIF_F_RXCSUM) ravb_rx_csum_gbeth(skb); napi_gro_receive(&priv->napi[q], skb); rx_packets++; - stats->rx_bytes += pkt_len; + stats->rx_bytes += desc_len; break; case DT_FSTART: priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc); - skb_put(priv->rx_1st_skb, pkt_len); + skb_put(priv->rx_1st_skb, desc_len); break; case DT_FMID: skb = ravb_get_skb_gbeth(ndev, entry, desc); skb_copy_to_linear_data_offset(priv->rx_1st_skb, priv->rx_1st_skb->len, skb->data, - pkt_len); - skb_put(priv->rx_1st_skb, pkt_len); + desc_len); + skb_put(priv->rx_1st_skb, desc_len); dev_kfree_skb(skb); break; case DT_FEND: @@ -883,17 +883,17 @@ static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) skb_copy_to_linear_data_offset(priv->rx_1st_skb, priv->rx_1st_skb->len, skb->data, - pkt_len); - skb_put(priv->rx_1st_skb, pkt_len); + desc_len); + skb_put(priv->rx_1st_skb, desc_len); dev_kfree_skb(skb); priv->rx_1st_skb->protocol = eth_type_trans(priv->rx_1st_skb, ndev); if (ndev->features & NETIF_F_RXCSUM) ravb_rx_csum_gbeth(priv->rx_1st_skb); + stats->rx_bytes += priv->rx_1st_skb->len; napi_gro_receive(&priv->napi[q], priv->rx_1st_skb); rx_packets++; - stats->rx_bytes += pkt_len; break; } } From patchwork Wed May 29 08:10:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678270 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D2AEC25B7C for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:51 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 43/47] net: ravb: Fix registered interrupt names Date: Wed, 29 May 2024 11:10:35 +0300 Message-Id: <20240529081039.639010-44-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16023 From: Geert Uytterhoeven commit 0c81ea5a8e231fa120e3f76aa9ea99fa3950cc59 upstream. As interrupts are now requested from ravb_probe(), before calling register_netdev(), ndev->name still contains the template "eth%d", leading to funny names in /proc/interrupts. E.g. on R-Car E3: 89: 0 0 GICv2 93 Level eth%d:ch22:multi 90: 0 3 GICv2 95 Level eth%d:ch24:emac 91: 0 23484 GICv2 71 Level eth%d:ch0:rx_be 92: 0 0 GICv2 72 Level eth%d:ch1:rx_nc 93: 0 13735 GICv2 89 Level eth%d:ch18:tx_be 94: 0 0 GICv2 90 Level eth%d:ch19:tx_nc Worse, on platforms with multiple RAVB instances (e.g. R-Car V4H), all interrupts have similar names. Fix this by using the device name instead, like is done in several other drivers: 89: 0 0 GICv2 93 Level e6800000.ethernet:ch22:multi 90: 0 1 GICv2 95 Level e6800000.ethernet:ch24:emac 91: 0 28578 GICv2 71 Level e6800000.ethernet:ch0:rx_be 92: 0 0 GICv2 72 Level e6800000.ethernet:ch1:rx_nc 93: 0 14044 GICv2 89 Level e6800000.ethernet:ch18:tx_be 94: 0 0 GICv2 90 Level e6800000.ethernet:ch19:tx_nc Rename the local variable dev_name, as it shadows the dev_name() function, and pre-initialize it, to simplify the code. Fixes: 32f012b8c01ca9fd ("net: ravb: Move getting/requesting IRQs in the probe() method") Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Reviewed-by: Sergey Shtylyov Reviewed-by: Claudiu Beznea Tested-by: Claudiu Beznea # on RZ/G3S Link: https://lore.kernel.org/r/cde67b68adf115b3cf0b44c32334ae00b2fbb321.1713944647.git.geert+renesas@glider.be Signed-off-by: Jakub Kicinski Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index c4ee77d41329..e86b4a006dc3 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2790,19 +2790,18 @@ static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, struct platform_device *pdev = priv->pdev; struct net_device *ndev = priv->ndev; struct device *dev = &pdev->dev; - const char *dev_name; + const char *devname = dev_name(dev); unsigned long flags; int error, irq_num; if (irq_name) { - dev_name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); - if (!dev_name) + devname = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", devname, ch); + if (!devname) return -ENOMEM; irq_num = platform_get_irq_byname(pdev, irq_name); flags = 0; } else { - dev_name = ndev->name; irq_num = platform_get_irq(pdev, 0); flags = IRQF_SHARED; } @@ -2812,9 +2811,9 @@ static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, if (irq) *irq = irq_num; - error = devm_request_irq(dev, irq_num, handler, flags, dev_name, ndev); + error = devm_request_irq(dev, irq_num, handler, flags, devname, ndev); if (error) - netdev_err(ndev, "cannot request IRQ %s\n", dev_name); + netdev_err(ndev, "cannot request IRQ %s\n", devname); return error; } From patchwork Wed May 29 08:10:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678269 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2520CC27C44 for ; Wed, 29 May 2024 08:11:57 +0000 (UTC) Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) by mx.groups.io with SMTP id smtpd.web10.8666.1716970315938631742 for ; Wed, 29 May 2024 01:11:56 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=noL3Y+T0; spf=pass (domain: tuxon.dev, ip: 209.85.208.177, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lj1-f177.google.com with SMTP id 38308e7fff4ca-2e974862b00so18447211fa.0 for ; Wed, 29 May 2024 01:11:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970314; x=1717575114; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5IDTuuUmMn75Lwct81/xNe16cbwwQxJv0yqy2cX1aHk=; b=noL3Y+T0HLwyybwlnpuM3W/ql5EEoFz7JdrGxMl2CEE91xsno1dX/dUvns2gPZLAl3 a8DSDru+zUPqHW7hoplM9EinIGglsYYPkHIhx4R2BOOiTe29Q6cyfWU1VZ9IlxOZQiLZ MgiEVftGsBYULOQqP2kjZzEMYPPl+qSFFSVS5DWvkC/PQl00QlT/tb1iC0iO1a4yq/q0 uHrIHRElxRb4Yz+Q/YyETHQOUg4WvyUyEutDFJ5dAprHgKkDG1inx2SsG5acvLCNhHQv aBFQI/aKVnVxNtMUI5wSFHRGekfmGWLtl6PU3yZ7hqu/OGvPYQem9HyovKS1SaIDquCs cSWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970314; x=1717575114; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5IDTuuUmMn75Lwct81/xNe16cbwwQxJv0yqy2cX1aHk=; b=ORakpVb2qGdUP8WG2Hm1BC3KAEL3+MkGiRYqNsRnN1b1hsS7+feFwHnnLcxbjM3m2I IS8a4ZMsKvPfacEBuRqFP2DIJyhJb8i7H5rKPWYhl/iXJ3q07ZyfsBcxSARFpifOfZ/u JvD6z09pMn1+rjlLMBhAzvOZD1ED1c3mx8Aw93y76UE2lxm4lA83Ntm8ftaXZb62M8E+ powe0aP5eGgurwyjjAVQXPmOTlWG60/m7t0EnBRBD5Jji6GhRdOVUbqe92ZXPFtDepnc 3HMBmN5B4RQ1Zoqyfuau814T2JOXLaNuHBlluSawfZwVLicw9KzoFGPm75iHgrG2I3Y4 dkIQ== X-Gm-Message-State: AOJu0Yxrx7PWeN5xDqZkQJkOugmthQ+P82HfNDhGhvccSwtuJUdJC6R3 NnEVsPM1pYGBkn0dzQNZxgKwR/StjWMrc0d+CInrvQ4uXozq6jcEvbIO1hH1ccjFEnl5E2bv+Hy VhJQ= X-Google-Smtp-Source: AGHT+IFlmt0QmzW1exxYWUXpP8GOfKdTY5S6+TZs7N0pyrHZIVeVRNrOlo6447g90bJADKzTZ47w4g== X-Received: by 2002:a2e:3517:0:b0:2e9:87f6:b133 with SMTP id 38308e7fff4ca-2e987f6b269mr27938471fa.3.1716970314207; Wed, 29 May 2024 01:11:54 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:53 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 44/47] arm64: dts: renesas: r9a08g045: Add Ethernet nodes Date: Wed, 29 May 2024 11:10:36 +0300 Message-Id: <20240529081039.639010-45-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:11:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16024 From: Claudiu Beznea commit aefd220c5791ea3471fc920feba380aacd2dcfa7 upstream. Add the Ethernet nodes available on RZ/G3S (R9A08G045). Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-10-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 6c7b29b69d0e..aaab5739c134 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -149,6 +149,44 @@ sdhi2: mmc@11c20000 { status = "disabled"; }; + eth0: ethernet@11c30000 { + compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>, + <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A08G045_ETH0_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth1: ethernet@11c40000 { + compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; + reg = <0 0x11c40000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>, + <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A08G045_ETH1_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@12400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From patchwork Wed May 29 08:10:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678273 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35B15C41513 for ; Wed, 29 May 2024 08:12:07 +0000 (UTC) Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) by mx.groups.io with SMTP id smtpd.web11.8597.1716970317835745973 for ; Wed, 29 May 2024 01:11:58 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=bXMKIukn; spf=pass (domain: tuxon.dev, ip: 209.85.167.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f49.google.com with SMTP id 2adb3069b0e04-529682e013dso2089033e87.3 for ; Wed, 29 May 2024 01:11:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970316; x=1717575116; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0+R7AZabC2j7Eqa8GxbK2zoq/iJA7/S2Tp64qTSI1+w=; b=bXMKIuknTaVfQVsboba53wgNpqjmqDLVCGsplf1Z0RDlPsxH4+WRg1Q+TPkN4MsQXH 0M9SGONOcptWTA1WJDP1qqOCPn6yuDBhnU1cSxJ7CatZr9HyTiZ6XrL6u4lfpr9fWom6 LYSxDtoQgzZ8LUnW2YzkVvfeBej589kxr21bm8zkhS4+Hok70pMHMMvHVxd0rtpARez/ x8rhNr7ALAYyHNJ+KXfxNOZ/Jpa3M/ozPaOhvgVkgB6qaevE+gNXWbQK3tutS3HJ0DIu fvMFhrjd3p3CNa+otlgoaz5xauBw9Zp55T6/7jQAUENKXfXN5Q8Ehzh7q3Ha+jIE26gI PC0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970316; x=1717575116; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0+R7AZabC2j7Eqa8GxbK2zoq/iJA7/S2Tp64qTSI1+w=; b=NPocHoGO9JpwLza3TG801ePJgFGsdtXkUp/Z7Tivz42x7moQ99FznxnSOTiACdnyfI ePIalXeQ5ZEe1qkVxyGoos4c8Mza5YLsM3ETBaBeL154CzG0KUbzqeDrnHtkNwATIQac SgHtn6WtYp7kAImH0kCWjk582y270dhGPlYVM79A8/cbv7WsdMsuDfXjW3R5SaU4I3Vs rYBJAjvkYF5xoeEIseWVK4mchE31mkDZl83WIuBabDtN5osqnMwSk41HD6vHDZDaD3SQ kEMahiHAzt0TyuK/IuTQEN9gkyF1+vM56JkKUp53OsBF9K6K4YuQ4DKJOV6eLKp8hq5V AEeg== X-Gm-Message-State: AOJu0YyovFsFk2sL7t3y859HDnfGl9QV1H5N01I4UiVcPx2sc771j/4A aMx03il3lpqfZPJHRlS+3rYTy79TYZm2CeUDM4wXFn9TVmMSOExfAcwL3wMjsG4= X-Google-Smtp-Source: AGHT+IH2ZrFI6S8EXAUQ6nREcX6S6jFGWZklQl6fg/DWer/gwEcFVZ6IH0+xzCc7B7/+iNKODLSl7w== X-Received: by 2002:a19:f716:0:b0:51c:bd90:e60b with SMTP id 2adb3069b0e04-529649c5e74mr8563290e87.25.1716970316036; Wed, 29 May 2024 01:11:56 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:55 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 45/47] arm64: dts: renesas: rzg3s-smarc-som: Use switches' names to select on-board functionalities Date: Wed, 29 May 2024 11:10:37 +0300 Message-Id: <20240529081039.639010-46-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:12:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16025 From: Claudiu Beznea commit 447765986dbfc321e37b13d7c276b106a469ec0b upstream. The intention of the SW_SD0_DEV_SEL and SW_SD2_EN macros was to reflect the state of the SW_CONFIG individual switches available on the RZ/G3S Smarc Module, and at the same time to have a descriptive name for the switches themselves. Each individual switch is associated with a signal name, which might be active-low or not on the board. Using signal names instead of SW_CONFIG switch names may be confusing for a user who just playes with switches to select individual functionalities, but also for an advanced user who looks at the schematics. To avoid even further confusion, use the switches' names here and instantiate them with an ON/OFF state. This should be simpler, even though the name of the switches is not that intuitive. The switches' names documentation reflects the switches' purposes. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-11-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 34 ++++++++++++------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 01a4a9da7afc..f59094701a4a 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -9,23 +9,31 @@ #include /* - * Signals of SW_CONFIG switches: - * @SW_SD0_DEV_SEL: - * 0 - SD0 is connected to eMMC - * 1 - SD0 is connected to uSD0 card - * @SW_SD2_EN: - * 0 - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC - * 1 - SD2 is connected to SoC + * On-board switches' states: + * @SW_OFF: switch's state is OFF + * @SW_ON: switch's state is ON */ -#define SW_SD0_DEV_SEL 1 -#define SW_SD2_EN 1 +#define SW_OFF 0 +#define SW_ON 1 + +/* + * SW_CONFIG[x] switches' states: + * @SW_CONFIG2: + * SW_OFF - SD0 is connected to eMMC + * SW_ON - SD0 is connected to uSD0 card + * @SW_CONFIG3: + * SW_OFF - SD2 is connected to SoC + * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC + */ +#define SW_CONFIG2 SW_ON +#define SW_CONFIG3 SW_OFF / { compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; aliases { mmc0 = &sdhi0; -#if SW_SD2_EN +#if SW_CONFIG3 == SW_OFF mmc2 = &sdhi2; #endif }; @@ -50,7 +58,7 @@ vcc_sdhi0: regulator0 { enable-active-high; }; -#if SW_SD0_DEV_SEL +#if SW_CONFIG2 == SW_ON vccq_sdhi0: regulator1 { compatible = "regulator-gpio"; regulator-name = "SDHI0 VccQ"; @@ -85,7 +93,7 @@ &extal_clk { clock-frequency = <24000000>; }; -#if SW_SD0_DEV_SEL +#if SW_CONFIG2 == SW_ON /* SD0 slot */ &sdhi0 { pinctrl-0 = <&sdhi0_pins>; @@ -116,7 +124,7 @@ &sdhi0 { }; #endif -#if SW_SD2_EN +#if SW_CONFIG3 == SW_OFF &sdhi2 { pinctrl-0 = <&sdhi2_pins>; pinctrl-names = "default"; From patchwork Wed May 29 08:10:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678275 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A55FC25B7E for ; Wed, 29 May 2024 08:12:07 +0000 (UTC) Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) by mx.groups.io with SMTP id smtpd.web10.8669.1716970318847653049 for ; Wed, 29 May 2024 01:11:59 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=dFSfbWml; spf=pass (domain: tuxon.dev, ip: 209.85.128.48, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-42121d27861so7316485e9.0 for ; Wed, 29 May 2024 01:11:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970317; x=1717575117; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Jy0JzQKtDy1pYtA9NTXZluynHW5V8Nkmn5JCqCnSOxM=; b=dFSfbWml1w0Cj4vZzEFjkOmNCbCjGvLVZPdImmflOpEezgIjMxq7lW2X8TH90Pr/93 1ML687Yh9pZWaiwBqX3qOeH+zFH+PIosfVNa4+4+MVx6R/4lTBs/+VPAsGHQE0dVVCyH 7+WBSjE8SM2xWPjz2/Br+Lzyhujunf2eBR2G09hiYhqNaZcpl9OFpkKcGk7fhUL08tky iaV/VEg2s8Q5ZONBBodt2E/tpL13U7XiISl4dIWJEqUtYmCq5++V4/MNH/M5mLwtIuNp vVqccUG3T/bZ+GAyti6apR/ifC6ovKCketnfokqRJNRKYiZXu1zk+wzH1cUui4BhglAj 87HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970317; x=1717575117; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Jy0JzQKtDy1pYtA9NTXZluynHW5V8Nkmn5JCqCnSOxM=; b=LQ+zxcGbpyoXitkvdHpzcRRfr77tiiBI0ECkR1QK9RA75IuOnMAyqCvfDKdD2/yCPy WewXekH4zabYAkTGPdAbUbz6YLindFslJOT2g1VBEMQZ/A4RZRn8h8XR1w2XqKEXRksz YaXDvbnniCMBOXyFzxo9I5Z48G08YVvdtjdZ+j37lKh7EnG6JG96VoeBZfD3KfFGlkYS Te3WfsvCqhTNS2ldMjeo+yzdztkUKtxB6A2Az2tViIyAp4QTlBf9EvhH4mQoUUixwaAL nRJYECUpTOAYYqyrFrwXaYA5Byz+6cgzEcamGMYmw9aK5qx5VWnEzT6ecwiPcXAu1UIu VP3g== X-Gm-Message-State: AOJu0Yxy/qVMJKuq24pupfW6qVRx7a4xjcL3dHUgIRDE9JPT7V6kITrd EQ2OCfXe3aCDRxB2c7JeF47aZx5H0WCVLWkbHXkb+K808euyMEk769KDkay0EB0= X-Google-Smtp-Source: AGHT+IHfqbIWMwOa/uzUZ28n5qJlKQyY5mqw8CKdTDSF2JARq46x8qsKFDY++pI1O37tYBUfu5Nx4w== X-Received: by 2002:a05:600c:1f91:b0:420:16b2:67f4 with SMTP id 5b1f17b1804b1-421089f81dfmr114365025e9.12.1716970317267; Wed, 29 May 2024 01:11:57 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:56 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 46/47] arm64: dts: renesas: rzg3s-smarc-som: Enable the Ethernet interfaces Date: Wed, 29 May 2024 11:10:38 +0300 Message-Id: <20240529081039.639010-47-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:12:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16026 From: Claudiu Beznea commit 932ff0c802c678bb6c7a98740eff930dad41fece upstream. The RZ/G3S Smarc Module has Ethernet PHYs (KSZ9131) connected to each Ethernet IP. For this, add proper DT descriptions to enable Ethernet communication through these PHYs. The interface b/w PHYs and MACs is RGMII. The skew settings were set to zero as based on phy-mode (rgmii-id) the KSZ9131 driver enables internal DLL, which adds a 2ns delay b/w clocks (TX/RX) and data signals. Different pin settings were applied to TXC and TX_CTL compared with the rest of the RGMII pins to comply with requirements for these pins imposed by HW manual of RZ/G3S (see chapters "Ether Ch0 Voltage Mode Control Register (ETH0_POC)", "Ether Ch1 Voltage Mode Control Register (ETH1_POC)", for power source selection, "Ether MII/RGMII Mode Control Register (ETH_MODE)" for output-enable and "Input Enable Control Register (IEN_m)" for input-enable configurations). Also enable the Ethernet interfaces by selecting SW_CONFIG3 = SW_ON. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-12-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 141 +++++++++++++++++- 1 file changed, 140 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index f59094701a4a..f062d4ad78b7 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -26,7 +26,7 @@ * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC */ #define SW_CONFIG2 SW_ON -#define SW_CONFIG3 SW_OFF +#define SW_CONFIG3 SW_ON / { compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; @@ -35,6 +35,9 @@ aliases { mmc0 = &sdhi0; #if SW_CONFIG3 == SW_OFF mmc2 = &sdhi2; +#else + eth0 = ð0; + eth1 = ð1; #endif }; @@ -89,6 +92,60 @@ vcc_sdhi2: regulator2 { }; }; +#if SW_CONFIG3 == SW_ON +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@7 { + reg = <7>; + interrupt-parent = <&pinctrl>; + interrupts = ; + rxc-skew-psec = <0>; + txc-skew-psec = <0>; + rxdv-skew-psec = <0>; + txen-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + +ð1 { + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy1: ethernet-phy@7 { + reg = <7>; + interrupt-parent = <&pinctrl>; + interrupts = ; + rxc-skew-psec = <0>; + txc-skew-psec = <0>; + rxdv-skew-psec = <0>; + txen-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; +#endif + &extal_clk { clock-frequency = <24000000>; }; @@ -136,6 +193,88 @@ &sdhi2 { #endif &pinctrl { + eth0-phy-irq-hog { + gpio-hog; + gpios = ; + input; + line-name = "eth0-phy-irq"; + }; + + eth0_pins: eth0 { + txc { + pinmux = ; /* ET0_TXC */ + power-source = <1800>; + output-enable; + input-enable; + drive-strength-microamp = <5200>; + }; + + tx_ctl { + pinmux = ; /* ET0_TX_CTL */ + power-source = <1800>; + output-enable; + drive-strength-microamp = <5200>; + }; + + mux { + pinmux = , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + , /* ET0_RXD3 */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + ; /* ET0_LINKSTA */ + power-source = <1800>; + }; + }; + + eth1-phy-irq-hog { + gpio-hog; + gpios = ; + input; + line-name = "eth1-phy-irq"; + }; + + eth1_pins: eth1 { + txc { + pinmux = ; /* ET1_TXC */ + power-source = <1800>; + output-enable; + input-enable; + drive-strength-microamp = <5200>; + }; + + tx_ctl { + pinmux = ; /* ET1_TX_CTL */ + power-source = <1800>; + output-enable; + drive-strength-microamp = <5200>; + }; + + mux { + pinmux = , /* ET1_TXD0 */ + , /* ET1_TXD1 */ + , /* ET1_TXD2 */ + , /* ET1_TXD3 */ + , /* ET1_RXC */ + , /* ET1_RX_CTL */ + , /* ET1_RXD0 */ + , /* ET1_RXD1 */ + , /* ET1_RXD2 */ + , /* ET1_RXD3 */ + , /* ET1_MDC */ + , /* ET1_MDIO */ + ; /* ET1_LINKSTA */ + power-source = <1800>; + }; + }; + sdhi0_pins: sd0 { data { pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; From patchwork Wed May 29 08:10:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678274 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 331BEC25B75 for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42108966b63sm171973865e9.1.2024.05.29.01.11.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:11:58 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 5.10.y-cip 47/47] arm64: dts: renesas: rzg3s-smarc-som: Guard Ethernet IRQ GPIO hogs Date: Wed, 29 May 2024 11:10:39 +0300 Message-Id: <20240529081039.639010-48-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081039.639010-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:12:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16027 From: Claudiu Beznea commit 150d81f7a260f36c118cbec253fdd493c671dc29 upstream. Ethernet IRQ GPIOs are marked as GPIO hogs. Thus, these GPIOs are requested at probe time without considering if there are other peripherals that need them. The Ethernet IRQ GPIOs are shared with SDHI2. Selection between Ethernet and SDHI2 is done through a hardware switch. To avoid scenarios where one wants to boot with SDHI2 support and some SDHI pins are not propertly configured because of the GPIO hogs, guard the Ethernet IRQ GPIO hogs with the proper build flag. Fixes: 932ff0c802c6 ("arm64: dts: renesas: rzg3s-smarc-som: Enable the Ethernet interfaces") Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240208124300.2740313-13-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index f062d4ad78b7..d33ab4c88787 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -193,12 +193,14 @@ &sdhi2 { #endif &pinctrl { +#if SW_CONFIG3 == SW_ON eth0-phy-irq-hog { gpio-hog; gpios = ; input; line-name = "eth0-phy-irq"; }; +#endif eth0_pins: eth0 { txc { @@ -234,12 +236,14 @@ mux { }; }; +#if SW_CONFIG3 == SW_ON eth1-phy-irq-hog { gpio-hog; gpios = ; input; line-name = "eth1-phy-irq"; }; +#endif eth1_pins: eth1 { txc {