From patchwork Wed May 29 08:14:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678278 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50BF0C25B75 for ; Wed, 29 May 2024 08:14:47 +0000 (UTC) Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.groups.io with SMTP id smtpd.web11.8664.1716970479489809482 for ; Wed, 29 May 2024 01:14:39 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=EWWpdKu7; spf=pass (domain: tuxon.dev, ip: 209.85.128.51, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4202cea9a2fso14166215e9.3 for ; Wed, 29 May 2024 01:14:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970478; x=1717575278; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QEoQuJHyn2Mh9Mw3YZSnCxftwhyhkacyw3vyfCZ+U3k=; b=EWWpdKu7TSJRbTG4PP6wQDhrzaSArx9Zrizex36gQ5GbSflfZhoEToMjW39OW2cvWs B5/VtWRZbgsEIfYuA4FNWSuRoQmiVopBjIibMNqDpsjYRcmLBQjbr2+z3KdyO9XMZIe6 B24UV5ET8BPsvucG8y2I7DvXkH43/08G++wOsW1Zsrl7Gcd8tsvEsp3pLGR7YbkmOYV4 Wjtxe5LhwuU9Fn+e5IJpUewvon1TqQrr3C8d7n0t9Jkn3uonOjRmjh5ZQOlFieDljcaU mYPB1H3NOCpJKFEY7yPo/3imzxBzVCFxoNxw+TMXoEe7y+IyJVID84A7KYOZU64tCrsx 7qCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970478; x=1717575278; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QEoQuJHyn2Mh9Mw3YZSnCxftwhyhkacyw3vyfCZ+U3k=; b=swPivkrnT1OXbQILCQIzAQgja15zLnAbyy8HiZ+MR/v3T43OEClwcKY77GdAAdsV4M YEem2wS9jjhsRgZgMfBQrL7uua6g31nS885T+8QX9tC6bDzXCzCq2Ru9vdkDlJPDt3Sq IpD9mJHfGNuK0VCsS634nWi5xLOo5GQCkvkCaG83Bry7LzlgRikr465ZhNGSfPc21vhi SNuUMcY96/nDO/ZZI9aQwiX9fYIqWYpriMO0GuGM95hEkVz6CuB4TEJMhzCw6n54D5DC kwZlEx2MxHgAxbFQ93N7pv6K0/fpAcHrcA0nqspf4+DV5sPt5jTbQk7YBtM1DXT6lM5K qgcA== X-Gm-Message-State: AOJu0Yz7HT3UgG9lBar/TOS+Ja+XJD0lhx4an4z5sz6NDrDn8LXgGhSs NF5IsqLFBHhtIi9bU6gmnaKLoc7ZVyt27xhc6X8jdmqEOp5jdfSYtKlTAOBsvm8= X-Google-Smtp-Source: AGHT+IHno5bRO7rlErG5hzFQnUc1ommSsm2kfeFzydySct7EDYsuHl+SxGnNI5tXlY7l2rSUnxD+sQ== X-Received: by 2002:a05:600c:68cb:b0:418:dbad:c57d with SMTP id 5b1f17b1804b1-42108a1f7d3mr97527085e9.28.1716970477936; Wed, 29 May 2024 01:14:37 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.14.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:14:37 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 01/33] clk: renesas: r9a08g045: Add clock and reset support for ETH0 and ETH1 Date: Wed, 29 May 2024 11:14:02 +0300 Message-Id: <20240529081434.639519-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:14:47 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16029 From: Claudiu Beznea commit 515f05da372aedf347a1ac99d17fb832ba371d4d upstream. RZ/G3S has 2 Gigabit Ethernet interfaces available. Add clock and reset support for both of them. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a08g045-cpg.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index 4394cb241d99..a6d3bea968c0 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -181,9 +181,11 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { DEF_G3S_DIV("P3", R9A08G045_CLK_P3, CLK_PLL3_DIV2_4, DIVPL3C, G3S_DIVPL3C_STS, dtable_1_32, 0, 0, 0, NULL), DEF_FIXED("P3_DIV2", CLK_P3_DIV2, R9A08G045_CLK_P3, 1, 2), + DEF_FIXED("ZT", R9A08G045_CLK_ZT, CLK_PLL3_DIV2_8, 1, 1), DEF_FIXED("S0", R9A08G045_CLK_S0, CLK_SEL_PLL4, 1, 2), DEF_FIXED("OSC", R9A08G045_OSCCLK, CLK_EXTAL, 1, 1), DEF_FIXED("OSC2", R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3), + DEF_FIXED("HP", R9A08G045_CLK_HP, CLK_PLL6, 1, 2), }; static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { @@ -202,6 +204,12 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9), DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10), DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11), + DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0), + DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0), + DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8), + DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1), + DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1), + DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9), DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), }; @@ -212,6 +220,8 @@ static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2), + DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0), + DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1), DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0), DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), From patchwork Wed May 29 08:14:03 2024 Content-Type: text/plain; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.14.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:14:38 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 02/33] pinctrl: renesas: rzg2l: Move arg and index in the main function block Date: Wed, 29 May 2024 11:14:03 +0300 Message-Id: <20240529081434.639519-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:14:47 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16030 From: Claudiu Beznea commit 906b545b16594e45f2d3433028dcf649d2c05ebb upstream. Move arg and index in the main block of the function as they are used by more than one case block of switch-case (3 out of 4 for arg, 2 out of 4 for index). In this way some lines of code are removed. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 777d6c291b33..abc4dd44b950 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -841,7 +841,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; unsigned int *pin_data = pin->drv_data; enum pin_config_param param; - unsigned int i; + unsigned int i, arg, index; u32 cfg, off; int ret; u8 bit; @@ -863,24 +863,21 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, for (i = 0; i < num_configs; i++) { param = pinconf_to_config_param(_configs[i]); switch (param) { - case PIN_CONFIG_INPUT_ENABLE: { - unsigned int arg = - pinconf_to_config_argument(_configs[i]); + case PIN_CONFIG_INPUT_ENABLE: + arg = pinconf_to_config_argument(_configs[i]); if (!(cfg & PIN_CFG_IEN)) return -EINVAL; rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); break; - } case PIN_CONFIG_POWER_SOURCE: settings.power_source = pinconf_to_config_argument(_configs[i]); break; - case PIN_CONFIG_DRIVE_STRENGTH: { - unsigned int arg = pinconf_to_config_argument(_configs[i]); - unsigned int index; + case PIN_CONFIG_DRIVE_STRENGTH: + arg = pinconf_to_config_argument(_configs[i]); if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua) return -EINVAL; @@ -895,7 +892,6 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); break; - } case PIN_CONFIG_DRIVE_STRENGTH_UA: if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) || @@ -905,9 +901,8 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, settings.drive_strength_ua = pinconf_to_config_argument(_configs[i]); break; - case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { - unsigned int arg = pinconf_to_config_argument(_configs[i]); - unsigned int index; + case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: + arg = pinconf_to_config_argument(_configs[i]); if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0]) return -EINVAL; @@ -921,7 +916,6 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); break; - } default: return -EOPNOTSUPP; From patchwork Wed May 29 08:14:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678279 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B0DFC25B7E for ; Wed, 29 May 2024 08:14:47 +0000 (UTC) Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) by mx.groups.io with SMTP id smtpd.web11.8666.1716970482219965953 for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.14.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:14:40 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 03/33] pinctrl: renesas: rzg2l: Add pin configuration support for pinmux groups Date: Wed, 29 May 2024 11:14:04 +0300 Message-Id: <20240529081434.639519-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:14:47 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16031 From: Claudiu Beznea commit d3aaa7203a17e8399df41e7c3f088f51368b001c upstream. On RZ/G3S different Ethernet pins need to be configured with different settings (e.g. power-source needs to be set, RGMII TXC and TX_CTL pins need output-enable). Adjust the driver to allow specifying pin configuration for pinmux groups. With this, DT settings like the following are taken into account by the driver: eth0_pins: eth0 { tx_ctl { pinmux = ; /* ET0_TX_CTL */ power-source = <1800>; output-enable; drive-strength-microamp = <5200>; }; }; Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index abc4dd44b950..e38a1ddcfc0c 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -375,8 +375,11 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, goto done; } - if (num_pinmux) + if (num_pinmux) { nmaps += 1; + if (num_configs) + nmaps += 1; + } if (num_pins) nmaps += num_pins; @@ -461,6 +464,16 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, maps[idx].data.mux.function = name; idx++; + if (num_configs) { + ret = rzg2l_map_add_config(&maps[idx], name, + PIN_MAP_TYPE_CONFIGS_GROUP, + configs, num_configs); + if (ret < 0) + goto remove_group; + + idx++; + } + dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); ret = 0; goto done; From patchwork Wed May 29 08:14:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 435E7C25B75 for ; Wed, 29 May 2024 08:14:57 +0000 (UTC) Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) by mx.groups.io with SMTP id smtpd.web11.8669.1716970487047812832 for ; Wed, 29 May 2024 01:14:47 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=GobTunWv; spf=pass (domain: tuxon.dev, ip: 209.85.167.47, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-5295d509178so2239357e87.1 for ; Wed, 29 May 2024 01:14:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970485; x=1717575285; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2NKI3xJx6V4ZzQl3vXut9x0QUUSqRtJ7vZ2vRr6mGyw=; b=GobTunWvARXArK8rA+QFDB0s0IYD0lemAqu2bOomEsSEGPjw/u6dBJbqrt0b4UJpnW nD3Utdc1kQrOIsyFFruh9bF50dcIvAF08ZFL15UNSyGoKDPDbSB+gqUKsTMiTkB2G9t9 SGm9RShN6x8sv4+qLHDFYQMWV4pTzaG1RE983giKUV6qpBYuWayk4/diUpDfxw+hC/Nm SCcomc1BsLHpigENVkS5cRvM4rUUzN9SgUDekHFGPtuTUs/JiZy94T7BExWIPYx46RM9 LQ7/73NT+uvJmh6J3fYp+0z+lamhqXabUHOTQpjtob01gl0PlnyMgjQprVSXExywH7VI CbnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970485; x=1717575285; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2NKI3xJx6V4ZzQl3vXut9x0QUUSqRtJ7vZ2vRr6mGyw=; b=RpHRBL/bES/nn6L34dvlApEURzBvtM0iiAsNEVffFE/xUN5d1Zdlj5h6IM9u9gcdZU 0RzAxUz10KrA7o036KdzDtvjA5oC8GsgNFmpgdLhL7CluNZ6JM421He7Y5l6Lr7soOsM NLQVqBmut9AMRPGBoGtS6uZjdF+Uw+3QKSp6ZhxuNtmaqhdsGkIyabidC/54nXN2VKNO eGDBF4UcLmEvy/txYS1sY/el+KeYgcxJs8w3AE6vbt3S2pbdi2a29ydTX4x8sgg+659x t5zzT+VNeCCsopE9QeLxF9WI/DUy44vhPnf5yjzu1rKdN4YOWMjTYBEKrrB95M6KRgb4 9afw== X-Gm-Message-State: AOJu0Ywvp2JxmpMO/EEDOL+bZVZteeXkgYf8+fLQ2ZJo+4ygEiJxv9Gl ry7FWVg3IqUFCCR+879E754BtXKSqybuc8Al3UjrY26zEk3yMX5f3Yfjb78HTYkyZWasGvYSEbq oY2I= X-Google-Smtp-Source: AGHT+IHXrfFUx4RIl5G3CGQWUc1crLdz2LFu1HTjX5D/OcuslYC8JiU741MxAlXSOUPa+vIy/rHReg== X-Received: by 2002:a05:6512:2507:b0:51a:d9a3:dbf5 with SMTP id 2adb3069b0e04-52966f8f6b1mr17366206e87.47.1716970482146; Wed, 29 May 2024 01:14:42 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.14.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:14:41 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 04/33] pinctrl: renesas: rzg2l: Add support to select power source for Ethernet pins Date: Wed, 29 May 2024 11:14:05 +0300 Message-Id: <20240529081434.639519-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:14:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16032 From: Claudiu Beznea commit 51996952b8b50942ed3069141ebc1dee13756b95 upstream. The GPIO controller available on RZ/G3S (but also on RZ/G2L) supports setting the power source for Ethernet pins. Based on the interface b/w the Ethernet controller and the Ethernet PHY, and on board design, a specific power source needs to be selected. The GPIO controller supports 1.8V, 2.5V, and 3.3V power source selection for the Ethernet pins. This can be selected though the ETHx_POC registers (x={0, 1}). Adjust the driver to support this, and to do proper instantiation for the RZ/G3S and RZ/G2L SoCs. On RZ/G2L only the get operation has been tested at the moment. While at it, as the power registers on RZ/G2L support access sizes of 8 bits, and these registers on RZ/G3S support access sizes of 8/16/32 bits, replace writel()/readl() on these registers with writeb()/readb(). This should allow us to use the same code on both SoCs w/o any issues. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 42 +++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index e38a1ddcfc0c..38d319cebaf6 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -106,8 +106,10 @@ #define IEN(off) (0x1800 + (off) * 8) #define ISEL(off) (0x2C00 + (off) * 8) #define SD_CH(off, ch) ((off) + (ch) * 4) +#define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) +#define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ @@ -115,7 +117,6 @@ #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ #define PM_MASK 0x03 -#define PVDD_MASK 0x01 #define PFC_MASK 0x07 #define IEN_MASK 0x01 #define IOLH_MASK 0x03 @@ -134,10 +135,12 @@ * struct rzg2l_register_offsets - specific register offsets * @pwpr: PWPR register offset * @sd_ch: SD_CH register offset + * @eth_poc: ETH_POC register offset */ struct rzg2l_register_offsets { u16 pwpr; u16 sd_ch; + u16 eth_poc; }; /** @@ -603,6 +606,10 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 return SD_CH(regs->sd_ch, 0); if (caps & PIN_CFG_IO_VMC_SD1) return SD_CH(regs->sd_ch, 1); + if (caps & PIN_CFG_IO_VMC_ETH0) + return ETH_POC(regs->eth_poc, 0); + if (caps & PIN_CFG_IO_VMC_ETH1) + return ETH_POC(regs->eth_poc, 1); if (caps & PIN_CFG_IO_VMC_QSPI) return QSPI; @@ -614,6 +621,7 @@ static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs = &hwcfg->regs; int pwr_reg; + u8 val; if (caps & PIN_CFG_SOFT_PS) return pctrl->settings[pin].power_source; @@ -622,7 +630,18 @@ static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps if (pwr_reg < 0) return pwr_reg; - return (readl(pctrl->base + pwr_reg) & PVDD_MASK) ? 1800 : 3300; + val = readb(pctrl->base + pwr_reg); + switch (val) { + case PVDD_1800: + return 1800; + case PVDD_2500: + return 2500; + case PVDD_3300: + return 3300; + default: + /* Should not happen. */ + return -EINVAL; + } } static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps) @@ -630,17 +649,32 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct rzg2l_register_offsets *regs = &hwcfg->regs; int pwr_reg; + u8 val; if (caps & PIN_CFG_SOFT_PS) { pctrl->settings[pin].power_source = ps; return 0; } + switch (ps) { + case 1800: + val = PVDD_1800; + break; + case 2500: + val = PVDD_2500; + break; + case 3300: + val = PVDD_3300; + break; + default: + return -EINVAL; + } + pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); if (pwr_reg < 0) return pwr_reg; - writel((ps == 1800) ? PVDD_1800 : PVDD_3300, pctrl->base + pwr_reg); + writeb(val, pctrl->base + pwr_reg); pctrl->settings[pin].power_source = ps; return 0; @@ -1884,6 +1918,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { .regs = { .pwpr = 0x3014, .sd_ch = 0x3000, + .eth_poc = 0x300c, }, .iolh_groupa_ua = { /* 3v3 power source */ @@ -1896,6 +1931,7 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = { .regs = { .pwpr = 0x3000, .sd_ch = 0x3004, + .eth_poc = 0x3010, }, .iolh_groupa_ua = { /* 1v8 power source */ From patchwork Wed May 29 08:14:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678286 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90F8DC27C53 for ; Wed, 29 May 2024 08:14:57 +0000 (UTC) Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) by mx.groups.io with SMTP id smtpd.web11.8670.1716970487925023718 for ; Wed, 29 May 2024 01:14:48 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=Ne1jG+JP; spf=pass (domain: tuxon.dev, ip: 209.85.128.54, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-4210c9d1df6so15290675e9.2 for ; Wed, 29 May 2024 01:14:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970486; x=1717575286; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K6Lv4Yj/Fr9dJ3XpL8LW1wvZIcZVh6+d7KnyUjftLjk=; b=Ne1jG+JPJq8idWG0WJNsJHha1RfpUnb1cXqtEAqaKjWtsDISZUKu8nf6dqM07A7yIa N7/cgjDjkGpeSgQVE7o7Ezs9MPiPQC9DtII3FyKKHIKtRq85SWxtZEW0OcWfzARSCSQQ dHYbn0Lj/Z17o22xGeDt2fPTKSOtkUXmI+4EGI6rKlPj092EIybiyKDJuatsE7CmLfjH mKnc/tWis6N0LFn2rVdXbXc28Qh8YJOxayZiUUG2ZpoJgEf8emfrngKut1S1s+zgdQtQ wb3Sa50pfP4HlO14lKfZVG8VBC2sep9uzyCv8+lGsUk8pX18nDqrjJyOhwtucAjpLVRt zwbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970486; x=1717575286; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K6Lv4Yj/Fr9dJ3XpL8LW1wvZIcZVh6+d7KnyUjftLjk=; b=ML419ALdJWhDZn6/L4I8U17yUoFRjySAgpiIcEbu/GwtOdDdJ49rpnaXQQCQvmn4Q+ JBFGpGV3ePaF7UkLN/xZCtMcxMl6bixzqTggbHLXBggZqBEgw4poVBUyZ75ygoJVOXCm OBv9AmFF65vW11nqtDL/XFHuhZWlF9j6FfuNv0VoaX7TAovrDoYUtNq8LRqnAEuayHQb Y+OEjnCE4iyn1faQrNhhWDXPpkHr8r5HqkxEe2PXjGCzDSaqSjWYmn6TdmGgjCSIszyL zLt2mM+0M4JMSmOtm82uK4oosZ2XzhELGxF6AS1D3p8kFhNEOlI/3M/b16+ZSU5epZJT jrRQ== X-Gm-Message-State: AOJu0YyfqrhpcYZM7dQ9LOZ0MtiuCEqGoeR7kMjTN/EjGqc4HQYjOwqq fMW9vIBuxEui6AttLXyw3AfxSHk5DilZEpAEQh8Oweia7Eum3IT9K1sP4OX/1DA= X-Google-Smtp-Source: AGHT+IHcOh28XyX83cn/bRf6jCUMJKK+dJavewFAxn44fcH4IyZV4SYbt8KPEhOc2zlrSI01Glxaxw== X-Received: by 2002:a05:600c:3502:b0:41e:ae29:c807 with SMTP id 5b1f17b1804b1-42108a02fc5mr111804275e9.29.1716970486400; Wed, 29 May 2024 01:14:46 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.14.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:14:46 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 05/33] pinctrl: renesas: rzg2l: Add output enable support Date: Wed, 29 May 2024 11:14:06 +0300 Message-Id: <20240529081434.639519-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:14:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16033 From: Claudiu Beznea commit 1bbc8ee40826164d16e32d377654c93ef48d1458 upstream. Some of the Ethernet pins on RZ/G3S (but also valid for RZ/G2L) need to have the direction of the IO buffer set as output for Ethernet to work properly. On RZ/G3S, these pins are P1_0/P7_0, P1_1/P7_1, and can have the following Ethernet functions: TXC/TX_CLK or TX_CTL/TX_EN. As the pins supporting output enable are SoC specific, and there is a limited number of these pins (TXC/TX_CLK and/or TX_CTL/TX_EN), specify output enable capable port limits in the platform-based configuration data structure, to ensure proper validation. The OEN support has been intantiated for RZ/G3S at the moment. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-7-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 87 ++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 38d319cebaf6..188284e70636 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -56,6 +56,7 @@ #define PIN_CFG_FILCLKSEL BIT(12) #define PIN_CFG_IOLH_C BIT(13) #define PIN_CFG_SOFT_PS BIT(14) +#define PIN_CFG_OEN BIT(15) #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ (PIN_CFG_IOLH_##group | \ @@ -108,6 +109,7 @@ #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) +#define ETH_MODE (0x3018) #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ @@ -169,6 +171,8 @@ enum rzg2l_iolh_index { * @iolh_groupb_oi: IOLH group B output impedance specific values * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported) * @func_base: base number for port function (see register PFC) + * @oen_max_pin: the maximum pin number supporting output enable + * @oen_max_port: the maximum port number supporting output enable */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; @@ -178,6 +182,8 @@ struct rzg2l_hwcfg { u16 iolh_groupb_oi[4]; bool drive_strength_ua; u8 func_base; + u8 oen_max_pin; + u8 oen_max_port; }; struct rzg2l_dedicated_configs { @@ -781,6 +787,66 @@ static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps, return false; } +static bool rzg2l_oen_is_supported(u32 caps, u8 pin, u8 max_pin) +{ + if (!(caps & PIN_CFG_OEN)) + return false; + + if (pin > max_pin) + return false; + + return true; +} + +static u8 rzg2l_pin_to_oen_bit(u32 offset, u8 pin, u8 max_port) +{ + if (pin) + pin *= 2; + + if (offset / RZG2L_PINS_PER_PORT == max_port) + pin += 1; + + return pin; +} + +static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin) +{ + u8 max_port = pctrl->data->hwcfg->oen_max_port; + u8 max_pin = pctrl->data->hwcfg->oen_max_pin; + u8 bit; + + if (!rzg2l_oen_is_supported(caps, pin, max_pin)) + return 0; + + bit = rzg2l_pin_to_oen_bit(offset, pin, max_port); + + return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); +} + +static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen) +{ + u8 max_port = pctrl->data->hwcfg->oen_max_port; + u8 max_pin = pctrl->data->hwcfg->oen_max_pin; + unsigned long flags; + u8 val, bit; + + if (!rzg2l_oen_is_supported(caps, pin, max_pin)) + return -EINVAL; + + bit = rzg2l_pin_to_oen_bit(offset, pin, max_port); + + spin_lock_irqsave(&pctrl->lock, flags); + val = readb(pctrl->base + ETH_MODE); + if (oen) + val &= ~BIT(bit); + else + val |= BIT(bit); + writeb(val, pctrl->base + ETH_MODE); + spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, unsigned int _pin, unsigned long *config) @@ -818,6 +884,12 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, return -EINVAL; break; + case PIN_CONFIG_OUTPUT_ENABLE: + arg = rzg2l_read_oen(pctrl, cfg, _pin, bit); + if (!arg) + return -EINVAL; + break; + case PIN_CONFIG_POWER_SOURCE: ret = rzg2l_get_power_source(pctrl, _pin, cfg); if (ret < 0) @@ -919,6 +991,13 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg); break; + case PIN_CONFIG_OUTPUT_ENABLE: + arg = pinconf_to_config_argument(_configs[i]); + ret = rzg2l_write_oen(pctrl, cfg, _pin, bit, !!arg); + if (ret) + return ret; + break; + case PIN_CONFIG_POWER_SOURCE: settings.power_source = pinconf_to_config_argument(_configs[i]); break; @@ -1363,7 +1442,8 @@ static const u32 r9a07g043_gpio_configs[] = { static const u32 r9a08g045_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | - PIN_CFG_IO_VMC_ETH0)), /* P1 */ + PIN_CFG_IO_VMC_ETH0)) | + PIN_CFG_OEN, /* P1 */ RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH0)), /* P2 */ RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | @@ -1373,7 +1453,8 @@ static const u32 r9a08g045_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */ RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */ RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | - PIN_CFG_IO_VMC_ETH1)), /* P7 */ + PIN_CFG_IO_VMC_ETH1)) | + PIN_CFG_OEN, /* P7 */ RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH1)), /* P8 */ RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | @@ -1955,6 +2036,8 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = { }, .drive_strength_ua = true, .func_base = 1, + .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */ + .oen_max_port = 7, /* P7_1 is the maximum OEN port. */ }; static struct rzg2l_pinctrl_data r9a07g043_data = { From patchwork Wed May 29 08:14:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678282 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50DABC25B7E for ; Wed, 29 May 2024 08:14:57 +0000 (UTC) Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) by mx.groups.io with SMTP id smtpd.web11.8671.1716970489173552514 for ; Wed, 29 May 2024 01:14:49 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=B1zN+7QW; spf=pass (domain: tuxon.dev, ip: 209.85.128.48, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-4210c9d1df6so15290765e9.2 for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.14.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:14:47 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 06/33] pinctrl: renesas: rzg2l: Add input enable to the Ethernet pins Date: Wed, 29 May 2024 11:14:07 +0300 Message-Id: <20240529081434.639519-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:14:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16034 From: Claudiu Beznea commit 9e5889c68d992b65efd10aa0a4523c96fd07077f upstream. Some of the RZ/G3S Ethernet pins (P1_0, P7_0) can be configured with input enable. Enable this functionality for these pins. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-8-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 188284e70636..0277ebf3bcb6 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1443,7 +1443,7 @@ static const u32 r9a08g045_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH0)) | - PIN_CFG_OEN, /* P1 */ + PIN_CFG_OEN | PIN_CFG_IEN, /* P1 */ RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH0)), /* P2 */ RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | @@ -1454,7 +1454,7 @@ static const u32 r9a08g045_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */ RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH1)) | - PIN_CFG_OEN, /* P7 */ + PIN_CFG_OEN | PIN_CFG_IEN, /* P7 */ RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH1)), /* P8 */ RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | From patchwork Wed May 29 08:14:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678284 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 532AAC27C44 for ; Wed, 29 May 2024 08:14:57 +0000 (UTC) Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) by mx.groups.io with SMTP id smtpd.web11.8672.1716970490505219304 for ; Wed, 29 May 2024 01:14:50 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=b+hL4XHr; spf=pass (domain: tuxon.dev, ip: 209.85.128.53, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-420180b5898so14217415e9.2 for ; Wed, 29 May 2024 01:14:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970489; x=1717575289; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pa95+gA2J+pRQDBnGdJr3HYDcAsN/oEWKjQ0fMZXC70=; b=b+hL4XHrE07r6PLsTd3mcj4uhDLXzczAU8t2TDPOYNUGcjlCN+bx+b+hbkAxjf9FWY TzKdUtmloHtRxEYysOWJR20DeGHGkqW99JuUc8w5jHdgOWlhwJ06SvguABM9M0Iz8p+n Z9sYK5h3SA2uljWahSp+uxTXA/8smuqf2sxKJARE8gMu8zDItlbl5NIJ8kVHN99ii1wR Z2RyvwPKXFmzMEH6pH4E7NQaV43yDdnt/D5Knhpg5/H67ft+BhYiZOd1kAEb7xm8CgQ6 PAlAgwFhwdHJRvAXIrt8LM7/CR8+BtLg3PD+k+sXXI3aYVKlWaVfKpKRLCODiHdlMYnp JRTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970489; x=1717575289; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pa95+gA2J+pRQDBnGdJr3HYDcAsN/oEWKjQ0fMZXC70=; b=KMMzF434tgQPtIILiMir3FXEpbNOuuqiArTUqgDzjxd+C1PB6P3lmHeZCo70lHpRmZ JLKPWQcxZh1U4CIjIr9SRmjPmPqYZIuRhXKHX8mGuJ8ifCbM3GVUdENniUrdCIOC0UZe D+X0xjJYj3FwRIYK9IAwjpsrvfjzC3aq4zN+29QVpcAkqYjfM64PIJgJSmTByQAP4S3H 9i1y/FkGrRQ1UI5MmjvVeHVuHTWptk0NZxO2PouYQVlc2c7jeGL2KMxEdN9lFbA6GGjs mwt3B/0700nm/UD5vHylL5UO2H4hZ+7a75waExk0mga5o8vx9oztPEACDWM11XYLPnuA wz3g== X-Gm-Message-State: AOJu0YzdrRqMJjTTiJB5+zxIJqPv2PsR5JCyGzDnNI+ekdrF4ijHOdRa IpUksfqNdlhsx5EcVCWyxAxTpz9c6b9+HFlNakr6SkyIkif3OnLtilho4g8HIhE= X-Google-Smtp-Source: AGHT+IHHn1isi5bwxZ45jHP9d8aD51WDcwu1ANu1phKN/brkB/6VA7R9LHeFfdH3vkbwr5EzkrV3Iw== X-Received: by 2002:a7b:ce14:0:b0:41a:b56c:2929 with SMTP id 5b1f17b1804b1-42108a0dbcdmr114742945e9.34.1716970488925; Wed, 29 May 2024 01:14:48 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.14.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:14:48 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 07/33] pinctrl: renesas: rzg2l: Fix locking in rzg2l_dt_subnode_to_map() Date: Wed, 29 May 2024 11:14:08 +0300 Message-Id: <20240529081434.639519-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:14:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16035 From: Claudiu Beznea commit bd433c25ca81b2ac6dca7ea288a8474eea4fb8a0 upstream. Commit d3aaa7203a17 ("pinctrl: renesas: rzg2l: Add pin configuration support for pinmux groups") introduced the possibility to parse pin configuration for pinmux groups. It did that by calling rzg2l_map_add_config() at the end of rzg2l_dt_subnode_to_map() and jumping to the remove_group label in case rzg2l_map_add_config() failed. But if that happens, the mutex will already be unlocked, thus this it will lead to double mutex unlock operation. To fix this move the rzg2l_map_add_config() call just after all the name argument is ready and before the mutex is locked. There is no harm in doing this, as this only parses the data from device tree that will be further processed by pinctrl core code. Fixes: d3aaa7203a17 ("pinctrl: renesas: rzg2l: Add pin configuration support for pinmux groups") Reported-by: Dan Carpenter Closes: https://lore.kernel.org/all/f8c3a3a0-7c48-4e40-8af0-ed4e9d9b049f@moroto.mountain Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240115153453.99226-1-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 0277ebf3bcb6..c0d5bdd3a9c9 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -446,6 +446,16 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, name = np->name; } + if (num_configs) { + ret = rzg2l_map_add_config(&maps[idx], name, + PIN_MAP_TYPE_CONFIGS_GROUP, + configs, num_configs); + if (ret < 0) + goto done; + + idx++; + } + mutex_lock(&pctrl->mutex); /* Register a single pin group listing all the pins we read from DT */ @@ -473,16 +483,6 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, maps[idx].data.mux.function = name; idx++; - if (num_configs) { - ret = rzg2l_map_add_config(&maps[idx], name, - PIN_MAP_TYPE_CONFIGS_GROUP, - configs, num_configs); - if (ret < 0) - goto remove_group; - - idx++; - } - dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); ret = 0; goto done; From patchwork Wed May 29 08:14:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6ED1CC27C50 for ; Wed, 29 May 2024 08:14:57 +0000 (UTC) Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) by mx.groups.io with SMTP id smtpd.web10.8721.1716970491604596866 for ; Wed, 29 May 2024 01:14:51 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=m8/RFLt9; spf=pass (domain: tuxon.dev, ip: 209.85.128.54, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-4202ca70289so15149655e9.1 for ; Wed, 29 May 2024 01:14:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970490; x=1717575290; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F7p3Yt7Zbc+T1RZ8oQXpb2sjryr9tDTG8GkBnjVhjlY=; b=m8/RFLt9J0hkq0QRJqlvLWrf81zMyDhRO4e+bQzbX3g4YJi5fNKuos44HuCR+AlQ+J Xcp7uSOFS9YyVkxhPaDqbW8bxYkY7jyWV2i6dKaiqRXc64lxAQU4ZuNkhZhZ+KUivnfg AOztMnWDucfTRt7HWGGjvFDkHYR0eUs6ZCR84EkI/JpWWIFaT9/ANAYU1OjvudHXKIRQ DRFGg/nUJn97atH14DRG0OLkoS241nLTlhVISGaYphGIawxKttiQAb6a4dKhFzdeMr0W IQgmw87zst7+tdmhfZUT5bsvNEXNwweFkmzS3iajsikmt90qyCLzven1VlP7wHeyJWp4 /lGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970490; x=1717575290; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F7p3Yt7Zbc+T1RZ8oQXpb2sjryr9tDTG8GkBnjVhjlY=; b=AlkHl9r7SIs9drzHEABcwdINBQKZ8vqUx2pip50gZmPA558Yg4t3P0scuTz495JJHg vFO20uzps2XIemPAJStRm1vKHNhJ9iiX7MwKEy9Al3Nvnr60M9t9ScRPMhcUAtShxaGw iN0RjGLArqbeOclC1XhanPAG2rkkCe1cur7MvuE/JtbWPWd0aofvZjOSe1q9FRS/5MVf wkWpCeG0cD8ZgeSZiw0IE/6coDUJQW/vZMbNcumiiLTHLEaBz90nu9lbRt9Ciirv+dKl VkpkxIR9eIY9ahCWOx9bm6IBHnH5mvBqt654Ruj5KD9KsOkkiVRhksBe44LJEgYThk/T ZFtA== X-Gm-Message-State: AOJu0YyjmSaQoLQ34bGTSK86iiZg5DShBLXSY5ZB5P6wXnnIGOQuf4P4 MZ9jjSosWjlRzVLZQFt212wA4P+578KM2eK9+MFuEBG8rWyYYF2ArpPJjFBrSQHLKXnqCEysuPp 4MLQ= X-Google-Smtp-Source: AGHT+IETU2lGyJvTKWsVJ+GOmwwYze7zjqZxJq0PVYp2rxcmRPlviV1/cERTV0jECf5kBQErf1jPeg== X-Received: by 2002:a7b:c00c:0:b0:419:f31e:267c with SMTP id 5b1f17b1804b1-421089d18fcmr105098435e9.7.1716970490102; Wed, 29 May 2024 01:14:50 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.14.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:14:49 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 08/33] dt-bindings: net: renesas,etheravb: Document RZ/G3S support Date: Wed, 29 May 2024 11:14:09 +0300 Message-Id: <20240529081434.639519-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:14:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16036 From: Claudiu Beznea commit 060baa9b90d4e14eac7123abc563070dd30b21a2 upstream. Document Ethernet RZ/G3S support. Ethernet IP is similar to the one available on RZ/G2L devices. Signed-off-by: Claudiu Beznea Acked-by: Conor Dooley Reviewed-by: Sergey Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Jakub Kicinski Signed-off-by: Claudiu Beznea --- Documentation/devicetree/bindings/net/renesas,etheravb.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml index 3f41294f5997..fa4775461f5f 100644 --- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml +++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml @@ -58,6 +58,7 @@ properties: - renesas,r9a07g043-gbeth # RZ/G2UL - renesas,r9a07g044-gbeth # RZ/G2{L,LC} - renesas,r9a07g054-gbeth # RZ/V2L + - renesas,r9a08g045-gbeth # RZ/G3S - const: renesas,rzg2l-gbeth # RZ/{G2L,G2UL,V2L} family reg: true From patchwork Wed May 29 08:14:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E94FC25B7C for ; Wed, 29 May 2024 08:14:57 +0000 (UTC) Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) by mx.groups.io with SMTP id smtpd.web11.8675.1716970493472186778 for ; Wed, 29 May 2024 01:14:53 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=SEaaMCbr; spf=pass (domain: tuxon.dev, ip: 209.85.128.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-42121d28664so7256995e9.2 for ; Wed, 29 May 2024 01:14:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970492; x=1717575292; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oCO5NtharJrT6sPi0vv7NhSgcIhSp1Y1mRPbGfOczTY=; b=SEaaMCbrzhy1Hvx1Z3h0F6/pVP+MtMhvfSBUCMc6ue/rPglIKZooRWBK+rc2TDCdtf fXxfcFN7qsIHrM/0gN2IkvhCVTn3SIWXSTKBWGxXUadparMIbh4FlY0Ilpf1gI4YLYO/ RTDq/OvB4DtmaOAdIfqYmJAO/OL4n7pPTI3VfEQkYftebItBLBT1O5pkRz32dBWIXaV7 fBvO1b6fECV77TgnoYSz1TV3CCrzBs1cxoiGKrMIfJtIn0dd3ZPwtDKYG3D3BYnoqZDs LUbcKdtCQdr1qKoxAI1M9Hi3kSubuJMXfPE9iFN6n99HmKUuzGP4+/JoqD7yEuueVK9t 4qPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970492; x=1717575292; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oCO5NtharJrT6sPi0vv7NhSgcIhSp1Y1mRPbGfOczTY=; b=R/ygW75nP87RfYS7/jatNne1ybY9GK5KBI9I4wLskxYr6bqUzcDtN52jjYAcwASUHf B/om6mxvqOWg0M4JBdV1n2cukpU82I1HmnZKo/2JKn/d50kAzmKIMwTShOHXCeIhEESZ IlRtt7+k5OMBUPUT9S96ad/ykf4O/ek8vUtyCbeRpWrf6vEtEiyZa7nAhMQsnYXOE5uV 5FAmdRcfBXI/nj/YH7Jl+SJbOB9L6S1+PhUb0m9rGQuSxVSV2/t99+wcH8gSDImuxKNa tPxHz9cbf5KBYn7tR2ZVznZbMRDTBGjgsNxoFbNnS+XOTAPNmM7vN9Fdn8W6JwwLYXsK HmAQ== X-Gm-Message-State: AOJu0YxzrK6dIRIrptsYE55ZwxighKMVHH8Z1/49pFAPs/LpE8cWgGPp +Z1STrp8ykY9/fQdLCnvdqgFsUZNPZn4CQmb3UuecXrNXai+tSdIyD+mhlQGtwM= X-Google-Smtp-Source: AGHT+IHE8wUFijBndIGJSR+DdRCvuHamD0BGVny+KnRNZkkMOv3APvncchy+SbAJ7MYO6bUuMEVA6g== X-Received: by 2002:a05:600c:211a:b0:420:112e:6c1 with SMTP id 5b1f17b1804b1-421089f4becmr115030105e9.13.1716970491970; Wed, 29 May 2024 01:14:51 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.14.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:14:51 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 09/33] net: ravb: Rely on PM domain to enable gptp_clk Date: Wed, 29 May 2024 11:14:10 +0300 Message-Id: <20240529081434.639519-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:14:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16037 From: Claudiu Beznea commit e1da043f2b2d956818728ca74c8eacd17feccf5c upstream. ravb_rzv2m_hw_info::gptp_ref_clk is enabled only for RZ/V2M. RZ/V2M is an ARM64-based device which selects power domains by default and CONFIG_PM. The RZ/V2M Ethernet DT node has proper power-domain binding available in device tree from the commit that added the Ethernet node. (4872ca1f92b0 ("arm64: dts: renesas: r9a09g011: Add ethernet nodes")). Power domain support was available in the rzg2l-cpg.c driver when the Ethernet DT node has been enabled in RZ/V2M device tree. (ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")). Thus, remove the explicit clock enable for gptp_clk (and treat it as the other clocks are treated) as it is not needed and removing it doesn't break the ABI according to the above explanations. By removing the enable/disable operation from the driver we can add runtime PM support (which operates on clocks) w/o the need to handle the gptp_clk in the Ethernet driver functions like ravb_runtime_nop(). PM domain does all that is needed. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 756ac4a07f60..e8df1eca96aa 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2800,7 +2800,6 @@ static int ravb_probe(struct platform_device *pdev) error = PTR_ERR(priv->gptp_clk); goto out_disable_refclk; } - clk_prepare_enable(priv->gptp_clk); } ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); @@ -2820,13 +2819,13 @@ static int ravb_probe(struct platform_device *pdev) /* Set AVB config mode */ error = ravb_set_config_mode(ndev); if (error) - goto out_disable_gptp_clk; + goto out_disable_refclk; if (info->gptp || info->ccc_gac) { /* Set GTI value */ error = ravb_set_gti(ndev); if (error) - goto out_disable_gptp_clk; + goto out_disable_refclk; /* Request GTI loading */ ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); @@ -2846,7 +2845,7 @@ static int ravb_probe(struct platform_device *pdev) "Cannot allocate desc base address table (size %d bytes)\n", priv->desc_bat_size); error = -ENOMEM; - goto out_disable_gptp_clk; + goto out_disable_refclk; } for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) priv->desc_bat[q].die_dt = DT_EOS; @@ -2909,8 +2908,6 @@ static int ravb_probe(struct platform_device *pdev) /* Stop PTP Clock driver */ if (info->ccc_gac) ravb_ptp_stop(ndev); -out_disable_gptp_clk: - clk_disable_unprepare(priv->gptp_clk); out_disable_refclk: clk_disable_unprepare(priv->refclk); out_release: @@ -2945,7 +2942,6 @@ static int ravb_remove(struct platform_device *pdev) ravb_set_opmode(ndev, CCC_OPC_RESET); - clk_disable_unprepare(priv->gptp_clk); clk_disable_unprepare(priv->refclk); pm_runtime_put_sync(&pdev->dev); From patchwork Wed May 29 08:14:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678287 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8425FC27C51 for ; Wed, 29 May 2024 08:14:57 +0000 (UTC) Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) by mx.groups.io with SMTP id smtpd.web10.8722.1716970494923346994 for ; Wed, 29 May 2024 01:14:55 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=o6HP30KB; spf=pass (domain: tuxon.dev, ip: 209.85.167.47, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-5238b5c07efso2010253e87.3 for ; Wed, 29 May 2024 01:14:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970493; x=1717575293; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nbVgHAAFwBvhTTZT0naG/hJwYyjp6OxNiw9DH3Uruyc=; b=o6HP30KBW1pLXEQzAuPLDyiop7P8ILSBfD8FHHmdOis5DTBjv1RL1CkCIPgYSDGPoN cKZ91G1j0RklSdHZwda+gO+RQJVpFWQERxkVojgoNyE5LmYpHD6OHJ+toaS40rTQBtWK +WyNxXGSaXDguGOK1CIIt0UKtcbX+N9OPBGN7IPH7Lue68Pe+MYyQtZ95zbZ/Zd9qdaf JM8y5DrXIcWTZV70Wpl7HfTngjTcaQ68ioHel+YPzfFlm1Sk4tvuZ2qMswVUhMrk4zCB ueHiVM/AenTYWJvzGpqyFNpY/lDPPwlAXveySkvAaW9EcKMiwMq3tS+Bx73OEGH40P3N 2rAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970493; x=1717575293; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nbVgHAAFwBvhTTZT0naG/hJwYyjp6OxNiw9DH3Uruyc=; b=vUhHqs+nJlVoCfsxpTa4fz7bHK8FtAr1+7ZtjsTMoiHD0qDnrcRuWuSz/z69tXQFQ2 Govq3OBU7GXbOkR0zuAW/nghRG1auBxzJ2ErhmbNROF8t+LQKwqWw6zzgsIibvTfzmSu swcYFKUKhhLp43X9u5jlzjcmo5jJuzy2rzxTqhwMI0uQG3qNtd9tIn12jKjt/waDgok9 96A+MAs/xxGT6n9LXTfe2cRQEBQUgJo2crw0RmuY2llIWtcjeEl3AYuYa+aNMDO56Q9T 6hxekoIGXXbLPVFoY5pyxkT/LOLpA5lKYmdHWnPYvvZUuVyNYtobzpQK9ZNNN5LpTiIw 72nA== X-Gm-Message-State: AOJu0YwF6Av/FsPCWWHpuX1AShwuEH1SEHiGGzaVSG0ZfaXQ5qJkUNDX QwTqpFDLfJkqk5bwjZAKAcw9k3g3SHMK5lscMbCn8sW1rSJZgL/zcWwmIA+uiV8= X-Google-Smtp-Source: AGHT+IHScRtEJLt8yhT2gZTZFA/obSweeCL1CJd/OqFyEC1K2Q3QR+ADgziLcts9yy0MC21cPEMang== X-Received: by 2002:a05:6512:1388:b0:51a:c8bb:fcf7 with SMTP id 2adb3069b0e04-5296410a55dmr11003915e87.3.1716970493156; Wed, 29 May 2024 01:14:53 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.14.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:14:52 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 10/33] net: ravb: Make reset controller support mandatory Date: Wed, 29 May 2024 11:14:11 +0300 Message-Id: <20240529081434.639519-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:14:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16038 From: Claudiu Beznea commit b1768e3dc47792ac5876643604be25bc8ed17cd4 upstream. On the RZ/G3S SoC the reset controller is mandatory for the IP to work. The device tree binding documentation for the ravb driver specifies that the resets are mandatory. Based on this, make the resets mandatory also in driver for all ravb devices. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/Kconfig | 1 + drivers/net/ethernet/renesas/ravb_main.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/renesas/Kconfig b/drivers/net/ethernet/renesas/Kconfig index 8008b2f45934..0dd8c5860a54 100644 --- a/drivers/net/ethernet/renesas/Kconfig +++ b/drivers/net/ethernet/renesas/Kconfig @@ -37,6 +37,7 @@ config RAVB select MII select MDIO_BITBANG select PHYLIB + select RESET_CONTROLLER help Renesas Ethernet AVB device driver. This driver supports the following SoCs: diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index e8df1eca96aa..c13966e80db7 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2665,7 +2665,7 @@ static int ravb_probe(struct platform_device *pdev) return -EINVAL; } - rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); + rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(rstc)) return dev_err_probe(&pdev->dev, PTR_ERR(rstc), "failed to get cpg reset\n"); From patchwork Wed May 29 08:14:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678280 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4360DC41513 for ; Wed, 29 May 2024 08:14:57 +0000 (UTC) Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) by mx.groups.io with SMTP id smtpd.web10.8723.1716970496505057792 for ; Wed, 29 May 2024 01:14:56 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=Z8UX9Gt6; spf=pass (domain: tuxon.dev, ip: 209.85.128.51, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-421087b6f3fso15330115e9.1 for ; Wed, 29 May 2024 01:14:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970495; x=1717575295; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MOHOI8uLHUWl/mqKZ9EzFcKZ2y1mL2kj/tIOPWlIieg=; b=Z8UX9Gt6NFLP27ffDYogtp3HfC9J2XfQJw1yMiDYKnQ8hDe+hmaGsdcEZCY+BDXYJp bYKIIM+PiB01T5ZEGvoABsacQ+HUX9pO2Bp8v6a85h9gIE+P3D+LHpZ8F6pns7PJxOER /wGG9oY99yYO1BUThiwp/g7j66ljiT3D9SBgadizVT1w63ISf4LHDIkxdvJ2P+gjgg/Z HEgukhXytP2Xtu03Q3lR7BTSVEYzKeKevSg/t1+7winGdKOIIDekxeJiDxIhn1uxZWqY 39vJw2I5ckBsGe2DeIe1PgylCvs5uF3jdpBfltHNtBaB6bfCZT+y93QIfNfK0/+EQ4VX 317w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970495; x=1717575295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MOHOI8uLHUWl/mqKZ9EzFcKZ2y1mL2kj/tIOPWlIieg=; b=gA7YxXSZrCl8MvTivSi4/yzB1P02k22CuF3EI6iNXqxFXE8bNzCfyyoSplMXU2cRCP nzS5gGdI3vKg9eMyET6qRn0EbpQ6JiPPFM2aorXltzWdpBsS6B3Dhwp57fNxQ+HgE7WR zz/z150aLz0A1fNVhShYZhAwwzvtdN0dzLibdpX1VoowE1k7c7Ot1iCXkXLHSz08Js8I xv480aKtf+JW7rwRzFn0lLlvOtyl2zPRK25fg/10uvvraMW/spUpCnkwV8EHLMuLTM0g 79xrx9SBgYoIQAUcQL13czOIrqz572Ld2Hji0ZJXxhlcsxGyTWyUUmRZIoIsgwtzPakZ uNAg== X-Gm-Message-State: AOJu0YyBqPzb6lwCwQwaBtXRXx31ERhc0j3npt7+Ds3nRJ9tkaLS9oM2 GtpWX7KKrqQcL3TiNYdm0O5hpliodfl6J5Q2s1HLltGADdPEhD36+QCYtT0MrnE= X-Google-Smtp-Source: AGHT+IFRxlng+R+YyfYDDXoIgs5fdjlkXzwJ9CWjiBfdZ2HdJxLkRNk1Bi9Et4hdfqeIsi4bt2WLrg== X-Received: by 2002:a05:600c:581a:b0:41f:f957:96ac with SMTP id 5b1f17b1804b1-421089d9dc3mr117855965e9.13.1716970494994; Wed, 29 May 2024 01:14:54 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.14.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:14:54 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 11/33] net: ravb: Assert/de-assert reset on suspend/resume Date: Wed, 29 May 2024 11:14:12 +0300 Message-Id: <20240529081434.639519-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:14:57 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16039 From: Claudiu Beznea commit c5c0714e29508fd748ee5df09ae242476bf2e451 upstream. RZ/G3S can go to deep sleep states where power to most of the SoC parts is off. When resuming from such a state, the Ethernet controller needs to be reinitialized. De-asserting the reset signal for it should also be done. Thus, add reset assert/de-assert on suspend/resume functions. On the resume function, the de-assert was not reverted in case of failures to give the user a chance to restore the interface (e.g., bringing down/up the interface) in case suspend/resume failed. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index c13966e80db7..13ccb0d65603 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -3000,7 +3000,7 @@ static int __maybe_unused ravb_suspend(struct device *dev) int ret; if (!netif_running(ndev)) - return 0; + goto reset_assert; netif_device_detach(ndev); @@ -3012,7 +3012,11 @@ static int __maybe_unused ravb_suspend(struct device *dev) if (priv->info->ccc_gac) ravb_ptp_stop(ndev); - return ret; + if (priv->wol_enabled) + return ret; + +reset_assert: + return reset_control_assert(priv->rstc); } static int __maybe_unused ravb_resume(struct device *dev) @@ -3020,7 +3024,11 @@ static int __maybe_unused ravb_resume(struct device *dev) struct net_device *ndev = dev_get_drvdata(dev); struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; - int ret = 0; + int ret; + + ret = reset_control_deassert(priv->rstc); + if (ret) + return ret; /* If WoL is enabled set reset mode to rearm the WoL logic */ if (priv->wol_enabled) { From patchwork Wed May 29 08:14:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94902C25B75 for ; Wed, 29 May 2024 08:15:07 +0000 (UTC) Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) by mx.groups.io with SMTP id smtpd.web11.8677.1716970497911219936 for ; Wed, 29 May 2024 01:14:58 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=OMqEjrYE; spf=pass (domain: tuxon.dev, ip: 209.85.128.41, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-42120e3911eso12065325e9.0 for ; Wed, 29 May 2024 01:14:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970496; x=1717575296; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DSY7vACXSDYWIRDopDE0BAx0o1SyfajD52DCnOHz+bs=; b=OMqEjrYEwbczH+kUK8RLYtv+Ih/f2tSZLqn9rlZ+53flFwR6LEMQAt6GHJZNlHi7hQ qRm5gEgvB/LP/9tM7LB3us8urNlge4Sq+KGx4imqCbipTFPhmxOIJBModG5M5eV1DjQV +rNqIPg0XKjAF19Z9qnHo40H2kZa3HC66uNiZnfkIXyoeE0mEdUFAWusTvsFXIR/Amah ct+49Gcxj89gWXjtoIyyDc6gCOGO8VEHIHSDF7V4hm/HNGhKHUEJWBroo7ibunc7Zx/V HNf85ErRleqM2E0gN3FoY7LySnUKyTVqEphZ35t8aDdGfo0y4lKAaPOvNRdrbMJXaCZF oUKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970496; x=1717575296; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DSY7vACXSDYWIRDopDE0BAx0o1SyfajD52DCnOHz+bs=; b=cr+gZiqieN5TJJLl4iTtrhLjaje5qImkw86AI+NEwxbxQSBVhD/wZXHHyG2qVZYKF6 GMsF/janIG3UAZP2BabnmQSGCAbActMN7peIaGoBx9GeRytvZ732+LVkbkV8oq4BrEay f/xDAuvAhkMmINiNjdOobDX3cqtu1FeSaDL4Kdzxbq4qgnYIK1P/k/1f8MRlwvJA/pav XTEGn3w3qVkrS82FRd9wXa+aPq+wBYI69OnIV7nfcal/vHSNAX5CwLisO7NPeLmNGUc+ 3FGV6x1RZ/GAszFsPI73ZT0VijoKEQgPHvav+eA5TKCN6bIB6RuI7R7F22cGhqr26RLT rR3Q== X-Gm-Message-State: AOJu0Yw1rQ9+Z2xW9Mmdff9B++sUXPWu6H67APon/36YFhQ7O5kjOVi4 zk/l8MoI2sIt1XAcKxOQFxgid0SVUatMc1ukYobcXm4vbMEd81zzzhUeki3dutk= X-Google-Smtp-Source: AGHT+IHsPhhBBJloEIOWFj1fLEbswN+EvbmQtLujyekhH9w9kpNSbZHbGZIJ8L5czvCm3febYmMi0Q== X-Received: by 2002:a7b:c345:0:b0:420:ed93:bca0 with SMTP id 5b1f17b1804b1-421089d3a4fmr102455815e9.20.1716970496299; Wed, 29 May 2024 01:14:56 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.14.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:14:55 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 12/33] net: ravb: Move reference clock enable/disable on runtime PM APIs Date: Wed, 29 May 2024 11:14:13 +0300 Message-Id: <20240529081434.639519-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16040 From: Claudiu Beznea commit a654f6e875b753d11643840e266f7fd75e5ee1fa upstream. Reference clock could be or not be part of the power domain. If it is part of the power domain, the power domain takes care of properly setting it. In case it is not part of the power domain and full runtime PM support is available in driver the clock will not be propertly disabled/enabled at runtime. For this, keep the prepare/unprepare operations in the driver's probe()/remove() functions and move the enable/disable in runtime PM functions. By doing this, the previous ravb_runtime_nop() function was renamed ravb_runtime_suspend() and the comment was removed. A proper runtime PM resume function was added (ravb_runtime_resume()). The current driver still don't need to make any register settings on runtime suspend/resume (as expressed in the removed comment) because, currently, pm_runtime_put_sync() is called on the driver remove function. This will be changed in the next commits (that extends the runtime PM support) such that proper register settings (along with runtime resume/suspend) will be done on ravb_open()/ravb_close(). Along with it, the other clock request operations were moved close to reference clock request and prepare to have all the clock requests specific code grouped together. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni [claudiu.beznea: fixed conflict on ravb_runtime_suspend() function and ravb_dev_pm_ops object] Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 112 ++++++++++++----------- 1 file changed, 58 insertions(+), 54 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 13ccb0d65603..fc9800efa340 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2684,11 +2684,6 @@ static int ravb_probe(struct platform_device *pdev) if (error) goto out_free_netdev; - pm_runtime_enable(&pdev->dev); - error = pm_runtime_resume_and_get(&pdev->dev); - if (error < 0) - goto out_rpm_disable; - if (info->multi_irqs) { if (info->err_mgmt_irqs) irq = platform_get_irq_byname(pdev, "dia"); @@ -2699,7 +2694,7 @@ static int ravb_probe(struct platform_device *pdev) } if (irq < 0) { error = irq; - goto out_release; + goto out_reset_assert; } ndev->irq = irq; @@ -2717,10 +2712,37 @@ static int ravb_probe(struct platform_device *pdev) priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; } + priv->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(priv->clk)) { + error = PTR_ERR(priv->clk); + goto out_reset_assert; + } + + if (info->gptp_ref_clk) { + priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); + if (IS_ERR(priv->gptp_clk)) { + error = PTR_ERR(priv->gptp_clk); + goto out_reset_assert; + } + } + + priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); + if (IS_ERR(priv->refclk)) { + error = PTR_ERR(priv->refclk); + goto out_reset_assert; + } + clk_prepare(priv->refclk); + + platform_set_drvdata(pdev, ndev); + pm_runtime_enable(&pdev->dev); + error = pm_runtime_resume_and_get(&pdev->dev); + if (error < 0) + goto out_rpm_disable; + priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(priv->addr)) { error = PTR_ERR(priv->addr); - goto out_release; + goto out_rpm_put; } /* The Ether-specific entries in the device structure. */ @@ -2731,7 +2753,7 @@ static int ravb_probe(struct platform_device *pdev) error = of_get_phy_mode(np, &priv->phy_interface); if (error && error != -ENODEV) - goto out_release; + goto out_rpm_put; priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); priv->avb_link_active_low = @@ -2744,14 +2766,14 @@ static int ravb_probe(struct platform_device *pdev) irq = platform_get_irq_byname(pdev, "ch24"); if (irq < 0) { error = irq; - goto out_release; + goto out_rpm_put; } priv->emac_irq = irq; for (i = 0; i < NUM_RX_QUEUE; i++) { irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); if (irq < 0) { error = irq; - goto out_release; + goto out_rpm_put; } priv->rx_irqs[i] = irq; } @@ -2759,7 +2781,7 @@ static int ravb_probe(struct platform_device *pdev) irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); if (irq < 0) { error = irq; - goto out_release; + goto out_rpm_put; } priv->tx_irqs[i] = irq; } @@ -2768,40 +2790,19 @@ static int ravb_probe(struct platform_device *pdev) irq = platform_get_irq_byname(pdev, "err_a"); if (irq < 0) { error = irq; - goto out_release; + goto out_rpm_put; } priv->erra_irq = irq; irq = platform_get_irq_byname(pdev, "mgmt_a"); if (irq < 0) { error = irq; - goto out_release; + goto out_rpm_put; } priv->mgmta_irq = irq; } } - priv->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(priv->clk)) { - error = PTR_ERR(priv->clk); - goto out_release; - } - - priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); - if (IS_ERR(priv->refclk)) { - error = PTR_ERR(priv->refclk); - goto out_release; - } - clk_prepare_enable(priv->refclk); - - if (info->gptp_ref_clk) { - priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); - if (IS_ERR(priv->gptp_clk)) { - error = PTR_ERR(priv->gptp_clk); - goto out_disable_refclk; - } - } - ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); ndev->min_mtu = ETH_MIN_MTU; @@ -2819,13 +2820,13 @@ static int ravb_probe(struct platform_device *pdev) /* Set AVB config mode */ error = ravb_set_config_mode(ndev); if (error) - goto out_disable_refclk; + goto out_rpm_put; if (info->gptp || info->ccc_gac) { /* Set GTI value */ error = ravb_set_gti(ndev); if (error) - goto out_disable_refclk; + goto out_rpm_put; /* Request GTI loading */ ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); @@ -2845,7 +2846,7 @@ static int ravb_probe(struct platform_device *pdev) "Cannot allocate desc base address table (size %d bytes)\n", priv->desc_bat_size); error = -ENOMEM; - goto out_disable_refclk; + goto out_rpm_put; } for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) priv->desc_bat[q].die_dt = DT_EOS; @@ -2891,8 +2892,6 @@ static int ravb_probe(struct platform_device *pdev) netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); - platform_set_drvdata(pdev, ndev); - return 0; out_napi_del: @@ -2908,12 +2907,12 @@ static int ravb_probe(struct platform_device *pdev) /* Stop PTP Clock driver */ if (info->ccc_gac) ravb_ptp_stop(ndev); -out_disable_refclk: - clk_disable_unprepare(priv->refclk); -out_release: +out_rpm_put: pm_runtime_put(&pdev->dev); out_rpm_disable: pm_runtime_disable(&pdev->dev); + clk_unprepare(priv->refclk); +out_reset_assert: reset_control_assert(rstc); out_free_netdev: free_netdev(ndev); @@ -2942,10 +2941,9 @@ static int ravb_remove(struct platform_device *pdev) ravb_set_opmode(ndev, CCC_OPC_RESET); - clk_disable_unprepare(priv->refclk); - pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); + clk_unprepare(priv->refclk); reset_control_assert(priv->rstc); free_netdev(ndev); platform_set_drvdata(pdev, NULL); @@ -3082,21 +3080,27 @@ static int __maybe_unused ravb_resume(struct device *dev) return ret; } -static int __maybe_unused ravb_runtime_nop(struct device *dev) +static int ravb_runtime_suspend(struct device *dev) { - /* Runtime PM callback shared between ->runtime_suspend() - * and ->runtime_resume(). Simply returns success. - * - * This driver re-initializes all registers after - * pm_runtime_get_sync() anyway so there is no need - * to save and restore registers here. - */ + struct net_device *ndev = dev_get_drvdata(dev); + struct ravb_private *priv = netdev_priv(ndev); + + clk_disable(priv->refclk); + return 0; } +static int ravb_runtime_resume(struct device *dev) +{ + struct net_device *ndev = dev_get_drvdata(dev); + struct ravb_private *priv = netdev_priv(ndev); + + return clk_enable(priv->refclk); +} + static const struct dev_pm_ops ravb_dev_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) - SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) + SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) + RUNTIME_PM_OPS(ravb_runtime_suspend, ravb_runtime_resume, NULL) }; static struct platform_driver ravb_driver = { From patchwork Wed May 29 08:14:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678294 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C316CC27C51 for ; Wed, 29 May 2024 08:15:07 +0000 (UTC) Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) by mx.groups.io with SMTP id smtpd.web11.8680.1716970499211172278 for ; Wed, 29 May 2024 01:14:59 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=YJ6kfifH; spf=pass (domain: tuxon.dev, ip: 209.85.128.48, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-4211249fbafso14958115e9.3 for ; Wed, 29 May 2024 01:14:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970497; x=1717575297; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0mUcNHtOClN2vw+PkuneFC1otJwurnVinR5NVH0i1wU=; b=YJ6kfifHYMmWZRkq03YrcaVzjzoIZ/L1h66nMzy3DwjpGVckhqJSyWQzUD4WN5r6q6 4nQ1X4OksHUfjU7Itnkrl7Wj4p3tEu4aUHt1mk4YGwMWXtBKqoNLyhbv+F9qiKj727Mf G5ezHJS8ix9OrMkqj2tKolNeGAeS5vMyRTSCpvybjm8liF2hr2CMqn0lnoH/D/w9WVe+ 5mCO3ZU4pbFKD7p1zfe+AZpGXipyEYTjhKh0IvQfkA3ifUb8ihzqkLSHdB6HWiitO8K2 A4LYb+sgyodlkP1+qSr/QniXykBb4iCkauloRiT2PH2W1x44MtgPdVKmXdMjGir8OwjK mEwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970497; x=1717575297; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0mUcNHtOClN2vw+PkuneFC1otJwurnVinR5NVH0i1wU=; b=fDej6OuItUz7FwwDfh1pxWZlRtJAjESxqvs2GW4ZSgcL1d5cxUE+1fZ8zLDyhGrhJO tCAyNJ2jPiCTqNq7uwx7+9Y7LN+1TGF3mk/9k5Dgq6RuFr/A8VZiruTlfEaHNjoHBD7c wdZdjsr4Sn2o1gkq7434wEfJ2ka89aiRAVl9ZvVpZ3X9ShUHJUKjoO+jxYJKnYLM6dOC TLUxyqNHRPIb0UEeg3lr1l50mG6THT+3xQ6a6YsoViYLbNB3K4bgLkJGt/Dp+Z+4BCjO tR8rJjBjdGPnlA6PkPkMj0FJsPvwJvQB0tp+8Es9N4y7961ZwxdOzjNfskqDWMV/KyEl CSYw== X-Gm-Message-State: AOJu0Yy7wxmVd01WBlQePlkscvpTZmzp5S3w79604m6YjX/7tDQLb+ij W973gb6XixYD9+2yI83iT6Y/WJGG91xe5lR26BfleTza8pC45zddPvmdvt9Sw3k= X-Google-Smtp-Source: AGHT+IHQCMvHDN3rLc3AhVeuua0GkDd4paXEdzcOKXIrx7iDZP3r7X7XAelhQjA4LiE73fhr4ot++Q== X-Received: by 2002:a05:600c:55d9:b0:41a:408b:dbaa with SMTP id 5b1f17b1804b1-42108989ffcmr101821695e9.0.1716970497603; Wed, 29 May 2024 01:14:57 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.14.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:14:57 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 13/33] net: ravb: Move getting/requesting IRQs in the probe() method Date: Wed, 29 May 2024 11:14:14 +0300 Message-Id: <20240529081434.639519-14-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16041 From: Claudiu Beznea commit 32f012b8c01ca9fd26a28134cc2165ead93c22d0 upstream. The runtime PM implementation will disable clocks at the end of ravb_probe(). As some IP variants switch to reset mode as a result of setting module standby through clock disable APIs, to implement runtime PM the resource parsing and requesting are moved in the probe function and IP settings are moved in the open function. This is done because at the end of the probe some IP variants will switch anyway to reset mode and the registers content is lost. Also keeping only register settings operations in the ravb_open()/ravb_close() functions will make them faster. Commit moves IRQ requests to ravb_probe() to have all the IRQs ready when the interface is open. As now getting/requesting IRQs is done in a single place there is no need to keep intermediary data (like ravb_rx_irqs[] and ravb_tx_irqs[] arrays or IRQs in struct ravb_private). In order to avoid accessing the IP registers while the IP is runtime suspended (e.g. in the timeframe b/w the probe requests shared IRQs and IP clocks are enabled) in the interrupt handlers were introduced pm_runtime_active() checks. The device runtime PM usage counter has been incremented to avoid disabling the device's clocks while the check is in progress (if any). This is a preparatory change to add runtime PM support for all IP variants. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb.h | 4 - drivers/net/ethernet/renesas/ravb_main.c | 299 ++++++++++------------- 2 files changed, 130 insertions(+), 173 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index e0f8276cffed..e3506888cca6 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -1089,10 +1089,6 @@ struct ravb_private { int msg_enable; int speed; int emac_irq; - int erra_irq; - int mgmta_irq; - int rx_irqs[NUM_RX_QUEUE]; - int tx_irqs[NUM_TX_QUEUE]; unsigned no_avb_link:1; unsigned avb_link_active_low:1; diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index fc9800efa340..bbc025017c44 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -40,16 +40,6 @@ NETIF_MSG_RX_ERR | \ NETIF_MSG_TX_ERR) -static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { - "ch0", /* RAVB_BE */ - "ch1", /* RAVB_NC */ -}; - -static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { - "ch18", /* RAVB_BE */ - "ch19", /* RAVB_NC */ -}; - void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, u32 set) { @@ -1094,11 +1084,23 @@ static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) { struct net_device *ndev = dev_id; struct ravb_private *priv = netdev_priv(ndev); + struct device *dev = &priv->pdev->dev; + irqreturn_t result = IRQ_HANDLED; + + pm_runtime_get_noresume(dev); + + if (unlikely(!pm_runtime_active(dev))) { + result = IRQ_NONE; + goto out_rpm_put; + } spin_lock(&priv->lock); ravb_emac_interrupt_unlocked(ndev); spin_unlock(&priv->lock); - return IRQ_HANDLED; + +out_rpm_put: + pm_runtime_put_noidle(dev); + return result; } /* Error interrupt handler */ @@ -1178,9 +1180,15 @@ static irqreturn_t ravb_interrupt(int irq, void *dev_id) struct net_device *ndev = dev_id; struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; + struct device *dev = &priv->pdev->dev; irqreturn_t result = IRQ_NONE; u32 iss; + pm_runtime_get_noresume(dev); + + if (unlikely(!pm_runtime_active(dev))) + goto out_rpm_put; + spin_lock(&priv->lock); /* Get interrupt status */ iss = ravb_read(ndev, ISS); @@ -1224,6 +1232,9 @@ static irqreturn_t ravb_interrupt(int irq, void *dev_id) } spin_unlock(&priv->lock); + +out_rpm_put: + pm_runtime_put_noidle(dev); return result; } @@ -1232,9 +1243,15 @@ static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) { struct net_device *ndev = dev_id; struct ravb_private *priv = netdev_priv(ndev); + struct device *dev = &priv->pdev->dev; irqreturn_t result = IRQ_NONE; u32 iss; + pm_runtime_get_noresume(dev); + + if (unlikely(!pm_runtime_active(dev))) + goto out_rpm_put; + spin_lock(&priv->lock); /* Get interrupt status */ iss = ravb_read(ndev, ISS); @@ -1256,6 +1273,9 @@ static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) } spin_unlock(&priv->lock); + +out_rpm_put: + pm_runtime_put_noidle(dev); return result; } @@ -1263,8 +1283,14 @@ static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) { struct net_device *ndev = dev_id; struct ravb_private *priv = netdev_priv(ndev); + struct device *dev = &priv->pdev->dev; irqreturn_t result = IRQ_NONE; + pm_runtime_get_noresume(dev); + + if (unlikely(!pm_runtime_active(dev))) + goto out_rpm_put; + spin_lock(&priv->lock); /* Network control/Best effort queue RX/TX */ @@ -1272,6 +1298,9 @@ static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) result = IRQ_HANDLED; spin_unlock(&priv->lock); + +out_rpm_put: + pm_runtime_put_noidle(dev); return result; } @@ -1747,85 +1776,21 @@ static const struct ethtool_ops ravb_ethtool_ops = { .set_wol = ravb_set_wol, }; -static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, - struct net_device *ndev, struct device *dev, - const char *ch) -{ - char *name; - int error; - - name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); - if (!name) - return -ENOMEM; - error = request_irq(irq, handler, 0, name, ndev); - if (error) - netdev_err(ndev, "cannot request IRQ %s\n", name); - - return error; -} - /* Network device open function for Ethernet AVB */ static int ravb_open(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; - struct platform_device *pdev = priv->pdev; - struct device *dev = &pdev->dev; int error; napi_enable(&priv->napi[RAVB_BE]); if (info->nc_queues) napi_enable(&priv->napi[RAVB_NC]); - if (!info->multi_irqs) { - error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, - ndev->name, ndev); - if (error) { - netdev_err(ndev, "cannot request IRQ\n"); - goto out_napi_off; - } - } else { - error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, - dev, "ch22:multi"); - if (error) - goto out_napi_off; - error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, - dev, "ch24:emac"); - if (error) - goto out_free_irq; - error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, - ndev, dev, "ch0:rx_be"); - if (error) - goto out_free_irq_emac; - error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, - ndev, dev, "ch18:tx_be"); - if (error) - goto out_free_irq_be_rx; - error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, - ndev, dev, "ch1:rx_nc"); - if (error) - goto out_free_irq_be_tx; - error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, - ndev, dev, "ch19:tx_nc"); - if (error) - goto out_free_irq_nc_rx; - - if (info->err_mgmt_irqs) { - error = ravb_hook_irq(priv->erra_irq, ravb_multi_interrupt, - ndev, dev, "err_a"); - if (error) - goto out_free_irq_nc_tx; - error = ravb_hook_irq(priv->mgmta_irq, ravb_multi_interrupt, - ndev, dev, "mgmt_a"); - if (error) - goto out_free_irq_erra; - } - } - /* Device init */ error = ravb_dmac_init(ndev); if (error) - goto out_free_irq_mgmta; + goto out_napi_off; ravb_emac_init(ndev); /* Initialise PTP Clock driver */ @@ -1846,26 +1811,6 @@ static int ravb_open(struct net_device *ndev) if (info->gptp) ravb_ptp_stop(ndev); ravb_stop_dma(ndev); -out_free_irq_mgmta: - if (!info->multi_irqs) - goto out_free_irq; - if (info->err_mgmt_irqs) - free_irq(priv->mgmta_irq, ndev); -out_free_irq_erra: - if (info->err_mgmt_irqs) - free_irq(priv->erra_irq, ndev); -out_free_irq_nc_tx: - free_irq(priv->tx_irqs[RAVB_NC], ndev); -out_free_irq_nc_rx: - free_irq(priv->rx_irqs[RAVB_NC], ndev); -out_free_irq_be_tx: - free_irq(priv->tx_irqs[RAVB_BE], ndev); -out_free_irq_be_rx: - free_irq(priv->rx_irqs[RAVB_BE], ndev); -out_free_irq_emac: - free_irq(priv->emac_irq, ndev); -out_free_irq: - free_irq(ndev->irq, ndev); out_napi_off: if (info->nc_queues) napi_disable(&priv->napi[RAVB_NC]); @@ -2200,19 +2145,6 @@ static int ravb_close(struct net_device *ndev) cancel_work_sync(&priv->work); - if (info->multi_irqs) { - free_irq(priv->tx_irqs[RAVB_NC], ndev); - free_irq(priv->rx_irqs[RAVB_NC], ndev); - free_irq(priv->tx_irqs[RAVB_BE], ndev); - free_irq(priv->rx_irqs[RAVB_BE], ndev); - free_irq(priv->emac_irq, ndev); - if (info->err_mgmt_irqs) { - free_irq(priv->erra_irq, ndev); - free_irq(priv->mgmta_irq, ndev); - } - } - free_irq(ndev->irq, ndev); - if (info->nc_queues) napi_disable(&priv->napi[RAVB_NC]); napi_disable(&priv->napi[RAVB_BE]); @@ -2636,6 +2568,90 @@ static void ravb_parse_delay_mode(struct device_node *np, struct net_device *nde } } +static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, + const char *ch, int *irq, irq_handler_t handler) +{ + struct platform_device *pdev = priv->pdev; + struct net_device *ndev = priv->ndev; + struct device *dev = &pdev->dev; + const char *dev_name; + unsigned long flags; + int error; + + if (irq_name) { + dev_name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); + if (!dev_name) + return -ENOMEM; + + *irq = platform_get_irq_byname(pdev, irq_name); + flags = 0; + } else { + dev_name = ndev->name; + *irq = platform_get_irq(pdev, 0); + flags = IRQF_SHARED; + } + if (*irq < 0) + return *irq; + + error = devm_request_irq(dev, *irq, handler, flags, dev_name, ndev); + if (error) + netdev_err(ndev, "cannot request IRQ %s\n", dev_name); + + return error; +} + +static int ravb_setup_irqs(struct ravb_private *priv) +{ + const struct ravb_hw_info *info = priv->info; + struct net_device *ndev = priv->ndev; + const char *irq_name, *emac_irq_name; + int error, irq; + + if (!info->multi_irqs) + return ravb_setup_irq(priv, NULL, NULL, &ndev->irq, ravb_interrupt); + + if (info->err_mgmt_irqs) { + irq_name = "dia"; + emac_irq_name = "line3"; + } else { + irq_name = "ch22"; + emac_irq_name = "ch24"; + } + + error = ravb_setup_irq(priv, irq_name, "ch22:multi", &ndev->irq, ravb_multi_interrupt); + if (error) + return error; + + error = ravb_setup_irq(priv, emac_irq_name, "ch24:emac", &priv->emac_irq, + ravb_emac_interrupt); + if (error) + return error; + + if (info->err_mgmt_irqs) { + error = ravb_setup_irq(priv, "err_a", "err_a", &irq, ravb_multi_interrupt); + if (error) + return error; + + error = ravb_setup_irq(priv, "mgmt_a", "mgmt_a", &irq, ravb_multi_interrupt); + if (error) + return error; + } + + error = ravb_setup_irq(priv, "ch0", "ch0:rx_be", &irq, ravb_be_interrupt); + if (error) + return error; + + error = ravb_setup_irq(priv, "ch1", "ch1:rx_nc", &irq, ravb_nc_interrupt); + if (error) + return error; + + error = ravb_setup_irq(priv, "ch18", "ch18:tx_be", &irq, ravb_be_interrupt); + if (error) + return error; + + return ravb_setup_irq(priv, "ch19", "ch19:tx_nc", &irq, ravb_nc_interrupt); +} + static void ravb_set_delay_mode(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); @@ -2655,9 +2671,8 @@ static int ravb_probe(struct platform_device *pdev) struct reset_control *rstc; struct ravb_private *priv; struct net_device *ndev; - int error, irq, q; struct resource *res; - int i; + int error, q; if (!np) { dev_err(&pdev->dev, @@ -2684,20 +2699,6 @@ static int ravb_probe(struct platform_device *pdev) if (error) goto out_free_netdev; - if (info->multi_irqs) { - if (info->err_mgmt_irqs) - irq = platform_get_irq_byname(pdev, "dia"); - else - irq = platform_get_irq_byname(pdev, "ch22"); - } else { - irq = platform_get_irq(pdev, 0); - } - if (irq < 0) { - error = irq; - goto out_reset_assert; - } - ndev->irq = irq; - SET_NETDEV_DEV(ndev, &pdev->dev); priv = netdev_priv(ndev); @@ -2712,6 +2713,10 @@ static int ravb_probe(struct platform_device *pdev) priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; } + error = ravb_setup_irqs(priv); + if (error) + goto out_reset_assert; + priv->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(priv->clk)) { error = PTR_ERR(priv->clk); @@ -2759,50 +2764,6 @@ static int ravb_probe(struct platform_device *pdev) priv->avb_link_active_low = of_property_read_bool(np, "renesas,ether-link-active-low"); - if (info->multi_irqs) { - if (info->err_mgmt_irqs) - irq = platform_get_irq_byname(pdev, "line3"); - else - irq = platform_get_irq_byname(pdev, "ch24"); - if (irq < 0) { - error = irq; - goto out_rpm_put; - } - priv->emac_irq = irq; - for (i = 0; i < NUM_RX_QUEUE; i++) { - irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); - if (irq < 0) { - error = irq; - goto out_rpm_put; - } - priv->rx_irqs[i] = irq; - } - for (i = 0; i < NUM_TX_QUEUE; i++) { - irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); - if (irq < 0) { - error = irq; - goto out_rpm_put; - } - priv->tx_irqs[i] = irq; - } - - if (info->err_mgmt_irqs) { - irq = platform_get_irq_byname(pdev, "err_a"); - if (irq < 0) { - error = irq; - goto out_rpm_put; - } - priv->erra_irq = irq; - - irq = platform_get_irq_byname(pdev, "mgmt_a"); - if (irq < 0) { - error = irq; - goto out_rpm_put; - } - priv->mgmta_irq = irq; - } - } - ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); ndev->min_mtu = ETH_MIN_MTU; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.14.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:14:58 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 14/33] net: ravb: Split GTI computation and set operations Date: Wed, 29 May 2024 11:14:15 +0300 Message-Id: <20240529081434.639519-15-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16042 From: Claudiu Beznea commit f384ab481cab6ad71afdf9c80a8b407a70a8624c upstream. ravb_set_gti() was computing the value of GTI based on the reference clock rate and then applied it to register. This was done on the driver's probe function. In order to implement runtime PM for all IP variants (as some IP variants switches to reset mode (and thus the registers content is lost) when module standby is configured through clock APIs) the GTI setup was split in 2 parts: one computing the value of the GTI register (done in the driver's probe function) and one applying the computed value to register (done in the driver's ndo_open API). Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb.h | 2 + drivers/net/ethernet/renesas/ravb_main.c | 96 ++++++++++++------------ 2 files changed, 52 insertions(+), 46 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index e3506888cca6..268ccfafe7aa 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -1102,6 +1102,8 @@ struct ravb_private { const struct ravb_hw_info *info; struct reset_control *rstc; + + u32 gti_tiv; }; static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index bbc025017c44..90a61e2e1a77 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1776,6 +1776,50 @@ static const struct ethtool_ops ravb_ethtool_ops = { .set_wol = ravb_set_wol, }; +static void ravb_set_gti(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + const struct ravb_hw_info *info = priv->info; + + if (!(info->gptp || info->ccc_gac)) + return; + + ravb_write(ndev, priv->gti_tiv, GTI); + + /* Request GTI loading */ + ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); +} + +static int ravb_compute_gti(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + const struct ravb_hw_info *info = priv->info; + struct device *dev = ndev->dev.parent; + unsigned long rate; + u64 inc; + + if (!(info->gptp || info->ccc_gac)) + return 0; + + if (info->gptp_ref_clk) + rate = clk_get_rate(priv->gptp_clk); + else + rate = clk_get_rate(priv->clk); + if (!rate) + return -EINVAL; + + inc = div64_ul(1000000000ULL << 20, rate); + + if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { + dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", + inc, GTI_TIV_MIN, GTI_TIV_MAX); + return -EINVAL; + } + priv->gti_tiv = inc; + + return 0; +} + /* Network device open function for Ethernet AVB */ static int ravb_open(struct net_device *ndev) { @@ -1793,6 +1837,8 @@ static int ravb_open(struct net_device *ndev) goto out_napi_off; ravb_emac_init(ndev); + ravb_set_gti(ndev); + /* Initialise PTP Clock driver */ if (info->gptp) ravb_ptp_init(ndev, priv->pdev); @@ -2484,34 +2530,6 @@ static const struct of_device_id ravb_match_table[] = { }; MODULE_DEVICE_TABLE(of, ravb_match_table); -static int ravb_set_gti(struct net_device *ndev) -{ - struct ravb_private *priv = netdev_priv(ndev); - const struct ravb_hw_info *info = priv->info; - struct device *dev = ndev->dev.parent; - unsigned long rate; - uint64_t inc; - - if (info->gptp_ref_clk) - rate = clk_get_rate(priv->gptp_clk); - else - rate = clk_get_rate(priv->clk); - if (!rate) - return -EINVAL; - - inc = div64_ul(1000000000ULL << 20, rate); - - if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { - dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", - inc, GTI_TIV_MIN, GTI_TIV_MAX); - return -EINVAL; - } - - ravb_write(ndev, inc, GTI); - - return 0; -} - static int ravb_set_config_mode(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); @@ -2783,15 +2801,9 @@ static int ravb_probe(struct platform_device *pdev) if (error) goto out_rpm_put; - if (info->gptp || info->ccc_gac) { - /* Set GTI value */ - error = ravb_set_gti(ndev); - if (error) - goto out_rpm_put; - - /* Request GTI loading */ - ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); - } + error = ravb_compute_gti(ndev); + if (error) + goto out_rpm_put; if (info->internal_delay) { ravb_parse_delay_mode(np, ndev); @@ -3006,15 +3018,7 @@ static int __maybe_unused ravb_resume(struct device *dev) if (ret) return ret; - if (info->gptp || info->ccc_gac) { - /* Set GTI value */ - ret = ravb_set_gti(ndev); - if (ret) - return ret; - - /* Request GTI loading */ - ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); - } + ravb_set_gti(ndev); if (info->internal_delay) ravb_set_delay_mode(ndev); From patchwork Wed May 29 08:14:16 2024 Content-Type: text/plain; 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Wed, 29 May 2024 01:15:00 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.14.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:14:59 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 15/33] net: ravb: Move delay mode set in the driver's ndo_open API Date: Wed, 29 May 2024 11:14:16 +0300 Message-Id: <20240529081434.639519-16-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16043 From: Claudiu Beznea commit 23698a9abb629009b42ef419072e567b43ca6866 upstream. Delay parsing and setting were done in the driver's probe API. As some IP variants switch to reset mode (and thus the register contents is lost) when setting clocks (due to module standby functionality) to be able to implement runtime PM keep the delay parsing in the driver's probe function and move the delay applying function to the driver's ndo_open API. Along with it, ravb_parse_delay_mode() function was moved close to ravb_set_delay_mode() function to have the delay specific code in the same place. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 107 ++++++++++++----------- 1 file changed, 56 insertions(+), 51 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 90a61e2e1a77..0e2014f172f2 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1820,6 +1820,59 @@ static int ravb_compute_gti(struct net_device *ndev) return 0; } +/* Set tx and rx clock internal delay modes */ +static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + bool explicit_delay = false; + u32 delay; + + if (!priv->info->internal_delay) + return; + + if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { + /* Valid values are 0 and 1800, according to DT bindings */ + priv->rxcidm = !!delay; + explicit_delay = true; + } + if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { + /* Valid values are 0 and 2000, according to DT bindings */ + priv->txcidm = !!delay; + explicit_delay = true; + } + + if (explicit_delay) + return; + + /* Fall back to legacy rgmii-*id behavior */ + if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || + priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { + priv->rxcidm = 1; + priv->rgmii_override = 1; + } + + if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || + priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { + priv->txcidm = 1; + priv->rgmii_override = 1; + } +} + +static void ravb_set_delay_mode(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + u32 set = 0; + + if (!priv->info->internal_delay) + return; + + if (priv->rxcidm) + set |= APSR_RDM; + if (priv->txcidm) + set |= APSR_TDM; + ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); +} + /* Network device open function for Ethernet AVB */ static int ravb_open(struct net_device *ndev) { @@ -1831,6 +1884,8 @@ static int ravb_open(struct net_device *ndev) if (info->nc_queues) napi_enable(&priv->napi[RAVB_NC]); + ravb_set_delay_mode(ndev); + /* Device init */ error = ravb_dmac_init(ndev); if (error) @@ -2551,41 +2606,6 @@ static int ravb_set_config_mode(struct net_device *ndev) return error; } -/* Set tx and rx clock internal delay modes */ -static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) -{ - struct ravb_private *priv = netdev_priv(ndev); - bool explicit_delay = false; - u32 delay; - - if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { - /* Valid values are 0 and 1800, according to DT bindings */ - priv->rxcidm = !!delay; - explicit_delay = true; - } - if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { - /* Valid values are 0 and 2000, according to DT bindings */ - priv->txcidm = !!delay; - explicit_delay = true; - } - - if (explicit_delay) - return; - - /* Fall back to legacy rgmii-*id behavior */ - if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || - priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { - priv->rxcidm = 1; - priv->rgmii_override = 1; - } - - if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || - priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { - priv->txcidm = 1; - priv->rgmii_override = 1; - } -} - static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, const char *ch, int *irq, irq_handler_t handler) { @@ -2670,18 +2690,6 @@ static int ravb_setup_irqs(struct ravb_private *priv) return ravb_setup_irq(priv, "ch19", "ch19:tx_nc", &irq, ravb_nc_interrupt); } -static void ravb_set_delay_mode(struct net_device *ndev) -{ - struct ravb_private *priv = netdev_priv(ndev); - u32 set = 0; - - if (priv->rxcidm) - set |= APSR_RDM; - if (priv->txcidm) - set |= APSR_TDM; - ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); -} - static int ravb_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -2805,10 +2813,7 @@ static int ravb_probe(struct platform_device *pdev) if (error) goto out_rpm_put; - if (info->internal_delay) { - ravb_parse_delay_mode(np, ndev); - ravb_set_delay_mode(ndev); - } + ravb_parse_delay_mode(np, ndev); /* Allocate descriptor base address table */ priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; From patchwork Wed May 29 08:14:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678290 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7329C25B7E for ; Wed, 29 May 2024 08:15:07 +0000 (UTC) Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) by mx.groups.io with SMTP id smtpd.web10.8728.1716970504029151569 for ; Wed, 29 May 2024 01:15:04 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=SZ7LMJ4u; spf=pass (domain: tuxon.dev, ip: 209.85.128.44, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-421124a0b37so9464945e9.1 for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:02 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 16/33] net: ravb: Move DBAT configuration to the driver's ndo_open API Date: Wed, 29 May 2024 11:14:17 +0300 Message-Id: <20240529081434.639519-17-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16044 From: Claudiu Beznea commit cd1fb46e02de3c70d6379b00c0e860ca44954574 upstream. DBAT setup was done in the driver's probe API. As some IP variants switch to reset mode (and thus registers content is lost) when setting clocks (due to module standby functionality) to be able to implement runtime PM move the DBAT configuration in the driver's ndo_open API. This commit prepares the code for the addition of runtime PM. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 0e2014f172f2..b8b82ba03c5b 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1885,6 +1885,7 @@ static int ravb_open(struct net_device *ndev) napi_enable(&priv->napi[RAVB_NC]); ravb_set_delay_mode(ndev); + ravb_write(ndev, priv->desc_bat_dma, DBAT); /* Device init */ error = ravb_dmac_init(ndev); @@ -2828,7 +2829,6 @@ static int ravb_probe(struct platform_device *pdev) } for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) priv->desc_bat[q].die_dt = DT_EOS; - ravb_write(ndev, priv->desc_bat_dma, DBAT); /* Initialise HW timestamp list */ INIT_LIST_HEAD(&priv->ts_skb_list); From patchwork Wed May 29 08:14:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBD68C27C44 for ; Wed, 29 May 2024 08:15:07 +0000 (UTC) Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) by mx.groups.io with SMTP id smtpd.web11.8686.1716970506047651372 for ; Wed, 29 May 2024 01:15:06 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=dvuqGRJC; spf=pass (domain: tuxon.dev, ip: 209.85.128.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-42120fc8cbfso11579135e9.2 for ; Wed, 29 May 2024 01:15:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970504; x=1717575304; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=flqdFv4StWiFTBBlyfk23JzdtIVP1RU0VCG9/2qjmE0=; b=dvuqGRJCu4/SpRb1S3mDVHmofgD3SCJyAVKVhbjAEC5WgiFjadBmzYibEergORY+Hg hCgeTfI4Tg6o2sN02VLvJiT8oISp6nxkefDucJXLL8p4gibT013yph2IoPN75VhgPNTM 1MttSIaN2DkYhK6mOjmGnT0o2g1bNwjW6l4cbDkiC4ApdDQq7AkxnAPOHll8ER7UL2VH YQr63yrxrcaA4f1q9T4+rytZuAIfFl+6woO5s9QhvZuXnu/x2s/H+k6l3qULqlSMnbLL 3e4VAghhksNrSxsJ2MDOZGi5eUEXqvZl8AINIfNeYozF15HJjSCSy4uuejR/G7jjTjt8 mpBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970504; x=1717575304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=flqdFv4StWiFTBBlyfk23JzdtIVP1RU0VCG9/2qjmE0=; b=u+2VLe+gL2GqlByKvWEo7qX6vOc4gkjVyV+roDAm1IQTJG8BCJLU8cYG2h91g/FxCy unB63TjDe4fYw0rXmIAV+vGD8bn4GNN4572ehT8OGD/ep0n0emLDDx1Zs/qNFhXzazcY aeECK4fP9lKuvUq4+2PoJtQjaAcL/KD3YLtjFrkPgqHVR5UqlB2tHhHNdukc4LqkTx9q KzNU6/zNoq4J6w9+u603Nc553zNuL8FfaGQXcbglKQNTsQvpMwBwKNh4TddnJ+Su2/kH kTtIpEJU5ODa3VNfGqmINpcuo5IvD9jKZ050K6hzo/ETZ4bu00mh/AHIpbWtREIQwp1S E0rQ== X-Gm-Message-State: AOJu0YyIwOKMzJwcbUx7t8ZwpgpLgsLE74eEEoeJS27P0zD7VwKEuAeN EiWYiULjar6j98p+rzEYFVpBdKOxtDhI9szj2vlLUtP8FNq6Y6IjWc/ay8+2H5Q2SJ+6/b2gvpm Q04E= X-Google-Smtp-Source: AGHT+IEwRUAQbgEP6OGFkezlSh6V4ldqx03A4Z2TBxxg1t3uehlxdUU9z8u0UsysG+jOY/w88VYGHA== X-Received: by 2002:a05:600c:56d5:b0:41f:ed4c:b8b6 with SMTP id 5b1f17b1804b1-42108a0cac4mr116464165e9.38.1716970504501; Wed, 29 May 2024 01:15:04 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:04 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 17/33] net: ravb: Move PTP initialization in the driver's ndo_open API for ccc_gac platorms Date: Wed, 29 May 2024 11:14:18 +0300 Message-Id: <20240529081434.639519-18-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16045 From: Claudiu Beznea commit a6a85ba36fd0d3e5595a4fcf57e0811826254ff7 upstream. The initialization sequence for PTP is the same for platforms with ccc_gac and gptp (according to "Figure 50.71 Flow of gPTP Initialization (Normal, Common to All Modes)" of the R-Car Series, 3rd generation hardware manual and "Figure 37A.53 Flow of gPTP Initialization (Normal, Common to All Modes)" of the RZ/G Series hardware manual). As some IP variants switch to reset mode (and thus the registers content is lost) when setting clocks (due to module standby functionality) to be able to implement runtime PM, move the PTP initialization to the driver's ndo_open API. This commit prepares the code for the addition of runtime PM. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index b8b82ba03c5b..cb6e9bf8bddc 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1896,7 +1896,7 @@ static int ravb_open(struct net_device *ndev) ravb_set_gti(ndev); /* Initialise PTP Clock driver */ - if (info->gptp) + if (info->gptp || info->ccc_gac) ravb_ptp_init(ndev, priv->pdev); /* PHY control start */ @@ -1910,7 +1910,7 @@ static int ravb_open(struct net_device *ndev) out_ptp_stop: /* Stop PTP Clock driver */ - if (info->gptp) + if (info->gptp || info->ccc_gac) ravb_ptp_stop(ndev); ravb_stop_dma(ndev); out_napi_off: @@ -2220,7 +2220,7 @@ static int ravb_close(struct net_device *ndev) ravb_write(ndev, 0, TIC); /* Stop PTP Clock driver */ - if (info->gptp) + if (info->gptp || info->ccc_gac) ravb_ptp_stop(ndev); /* Set the config mode to stop the AVB-DMAC's processes */ @@ -2833,10 +2833,6 @@ static int ravb_probe(struct platform_device *pdev) /* Initialise HW timestamp list */ INIT_LIST_HEAD(&priv->ts_skb_list); - /* Initialise PTP Clock driver */ - if (info->ccc_gac) - ravb_ptp_init(ndev, pdev); - /* Debug message level */ priv->msg_enable = RAVB_DEF_MSG_ENABLE; @@ -2881,10 +2877,6 @@ static int ravb_probe(struct platform_device *pdev) out_dma_free: dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, priv->desc_bat_dma); - - /* Stop PTP Clock driver */ - if (info->ccc_gac) - ravb_ptp_stop(ndev); out_rpm_put: pm_runtime_put(&pdev->dev); out_rpm_disable: @@ -2910,10 +2902,6 @@ static int ravb_remove(struct platform_device *pdev) ravb_mdio_release(priv); - /* Stop PTP Clock driver */ - if (info->ccc_gac) - ravb_ptp_stop(ndev); - dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, priv->desc_bat_dma); From patchwork Wed May 29 08:14:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBD48C27C50 for ; Wed, 29 May 2024 08:15:07 +0000 (UTC) Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by mx.groups.io with SMTP id smtpd.web10.8733.1716970507201494484 for ; Wed, 29 May 2024 01:15:07 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=WYxB39Cl; spf=pass (domain: tuxon.dev, ip: 209.85.128.45, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-4201986d60aso14210755e9.3 for ; Wed, 29 May 2024 01:15:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970505; x=1717575305; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eszmK4kIKcsHS1rTwlLHwiv6PvRyqqA/nIQOy09JiZo=; b=WYxB39ClSIzn6rTaXqRAnScWJ2oXe2a/QBeehPE4rTOxh6j60jfMra5prUMd74DAE8 BvcVoZwqcKc2jVWJrNDsB9Pnsc4RWqvJxg+RKhf3c4ScCdkBaVf2Ny8LldoRrnmtBorN rzgp8IGm5A6b4hR950aoSDms+Et+Utzhjd2cP3FCGjBdpDkf+cBPSJxoSzbbNPrZX2Wi uIQMDnoa6JkYMrGpxito9tYSa9w4w3k5MO119DLC79BCHpFDRolGY4iz65q7xQna1P+W b82cI6KuLEB9aqifjAj/1Wrr3lD87+RQZwhWfTU7YBgamKy5e1ljBfgj6jG8WX5cP7aL +ytw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970505; x=1717575305; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eszmK4kIKcsHS1rTwlLHwiv6PvRyqqA/nIQOy09JiZo=; b=rL29hvG4cTFCLn2FLK/GvdtJk0t9ge+Ei/0x5eeKaqAZ4o6wS+Y60n/ApxGmHrqqsw N6ZB2Gn15h9YVBF3b9x2vyVHcAGkBSCd3CTqeAXXk90EysXOun82rn9C22+VEhej1khN tlqz03pJCFfBsn1jUhg8aMBKCyCr9ZGgO1LhkulrDM7cY73OdzPdS5ufsXq4s4xtJCxZ XZIE+UAv4n0lZUMxM6C93NCfQNbAmRr10Yr4/j7K8V3j4Ua5n82YWsfmgEI1nylmKPn6 mkXLvh2XRXzINgac1qz/QL/GcwQoBxQwvG1c0hrpKnb16EvkoTE1oHc9ZBpIfnDn+4Pe ItRg== X-Gm-Message-State: AOJu0Yzwgm+NY1pdJj8MzqRGbfPKBxH+ouBUDhAx3B5CAns+82MH2Syb 6LAKD1eb9Nqv86+PpIa0T0PHx3w4FR2b8y4frmSmycuX/abyUK2qkaLxQVlmIMI= X-Google-Smtp-Source: AGHT+IF9XAntZNfD/oPUqBB14q4pvHzchBkn+bLQJWZEsyXj29KoRW+m6lpNBCDZ1CB9bQc0DB+95g== X-Received: by 2002:a1c:7902:0:b0:41b:c024:8e88 with SMTP id 5b1f17b1804b1-42108a0dc79mr94498965e9.33.1716970505693; Wed, 29 May 2024 01:15:05 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:05 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 18/33] net: ravb: Set config mode in ndo_open and reset mode in ndo_close Date: Wed, 29 May 2024 11:14:19 +0300 Message-Id: <20240529081434.639519-19-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:07 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16046 From: Claudiu Beznea commit 76fd52c1007785fcea1d3405907cec940d44f403 upstream. As some IP variants switch to reset mode (and thus the register contents is lost) when setting clocks (due to module standby functionality) to be able to implement runtime PM and save more power, set the IP's operating mode to reset at the end of the probe. Along with it, in the ndo_open API the IP will be switched to configuration, then operation mode. In the ndo_close API, the IP will be switched back to reset mode. This allows implementing runtime PM and, along with it, save more power when the IP is not used. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 78 ++++++++++++++---------- 1 file changed, 46 insertions(+), 32 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index cb6e9bf8bddc..a76cc7aec5df 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1776,6 +1776,27 @@ static const struct ethtool_ops ravb_ethtool_ops = { .set_wol = ravb_set_wol, }; +static int ravb_set_config_mode(struct net_device *ndev) +{ + struct ravb_private *priv = netdev_priv(ndev); + const struct ravb_hw_info *info = priv->info; + int error; + + if (info->gptp) { + error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); + if (error) + return error; + /* Set CSEL value */ + ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); + } else if (info->ccc_gac) { + error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB); + } else { + error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); + } + + return error; +} + static void ravb_set_gti(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); @@ -1884,13 +1905,19 @@ static int ravb_open(struct net_device *ndev) if (info->nc_queues) napi_enable(&priv->napi[RAVB_NC]); + /* Set AVB config mode */ + error = ravb_set_config_mode(ndev); + if (error) + goto out_napi_off; + ravb_set_delay_mode(ndev); ravb_write(ndev, priv->desc_bat_dma, DBAT); /* Device init */ error = ravb_dmac_init(ndev); if (error) - goto out_napi_off; + goto out_set_reset; + ravb_emac_init(ndev); ravb_set_gti(ndev); @@ -1913,6 +1940,8 @@ static int ravb_open(struct net_device *ndev) if (info->gptp || info->ccc_gac) ravb_ptp_stop(ndev); ravb_stop_dma(ndev); +out_set_reset: + ravb_set_opmode(ndev, CCC_OPC_RESET); out_napi_off: if (info->nc_queues) napi_disable(&priv->napi[RAVB_NC]); @@ -2256,7 +2285,8 @@ static int ravb_close(struct net_device *ndev) if (info->nc_queues) ravb_ring_free(ndev, RAVB_NC); - return 0; + /* Set reset mode. */ + return ravb_set_opmode(ndev, CCC_OPC_RESET); } static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) @@ -2586,27 +2616,6 @@ static const struct of_device_id ravb_match_table[] = { }; MODULE_DEVICE_TABLE(of, ravb_match_table); -static int ravb_set_config_mode(struct net_device *ndev) -{ - struct ravb_private *priv = netdev_priv(ndev); - const struct ravb_hw_info *info = priv->info; - int error; - - if (info->gptp) { - error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); - if (error) - return error; - /* Set CSEL value */ - ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); - } else if (info->ccc_gac) { - error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB); - } else { - error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); - } - - return error; -} - static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, const char *ch, int *irq, irq_handler_t handler) { @@ -2805,11 +2814,6 @@ static int ravb_probe(struct platform_device *pdev) ndev->netdev_ops = &ravb_netdev_ops; ndev->ethtool_ops = &ravb_ethtool_ops; - /* Set AVB config mode */ - error = ravb_set_config_mode(ndev); - if (error) - goto out_rpm_put; - error = ravb_compute_gti(ndev); if (error) goto out_rpm_put; @@ -2836,6 +2840,11 @@ static int ravb_probe(struct platform_device *pdev) /* Debug message level */ priv->msg_enable = RAVB_DEF_MSG_ENABLE; + /* Set config mode as this is needed for PHY initialization. */ + error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); + if (error) + goto out_rpm_put; + /* Read and set MAC address */ ravb_read_mac_address(np, ndev); if (!is_valid_ether_addr(ndev->dev_addr)) { @@ -2848,9 +2857,14 @@ static int ravb_probe(struct platform_device *pdev) error = ravb_mdio_init(priv); if (error) { dev_err(&pdev->dev, "failed to initialize MDIO\n"); - goto out_dma_free; + goto out_reset_mode; } + /* Undo previous switch to config opmode. */ + error = ravb_set_opmode(ndev, CCC_OPC_RESET); + if (error) + goto out_mdio_release; + netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll); if (info->nc_queues) netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll); @@ -2873,8 +2887,10 @@ static int ravb_probe(struct platform_device *pdev) netif_napi_del(&priv->napi[RAVB_NC]); netif_napi_del(&priv->napi[RAVB_BE]); +out_mdio_release: ravb_mdio_release(priv); -out_dma_free: +out_reset_mode: + ravb_set_opmode(ndev, CCC_OPC_RESET); dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, priv->desc_bat_dma); out_rpm_put: @@ -2905,8 +2921,6 @@ static int ravb_remove(struct platform_device *pdev) dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, priv->desc_bat_dma); - ravb_set_opmode(ndev, CCC_OPC_RESET); - pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); clk_unprepare(priv->refclk); From patchwork Wed May 29 08:14:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB2C0C25B7C for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:06 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 19/33] net: ravb: Simplify ravb_suspend() Date: Wed, 29 May 2024 11:14:20 +0300 Message-Id: <20240529081434.639519-20-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:17 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16047 From: Claudiu Beznea commit b07bc55cbb1cf88a527d687fccd4a12bac744486 upstream. As ravb_close() contains now the call to ravb_ptp_stop() for both ccc_gac and gPTP aware platforms, there is no need to keep the separate call in ravb_suspend(). Instead, move it to ravb_wol_setup(). In this way the resulting code is cleaner. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index a76cc7aec5df..38b6807428c8 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2951,6 +2951,9 @@ static int ravb_wol_setup(struct net_device *ndev) /* Enable MagicPacket */ ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); + if (priv->info->ccc_gac) + ravb_ptp_stop(ndev); + return enable_irq_wake(priv->emac_irq); } @@ -2983,14 +2986,10 @@ static int __maybe_unused ravb_suspend(struct device *dev) netif_device_detach(ndev); if (priv->wol_enabled) - ret = ravb_wol_setup(ndev); - else - ret = ravb_close(ndev); + return ravb_wol_setup(ndev); - if (priv->info->ccc_gac) - ravb_ptp_stop(ndev); - - if (priv->wol_enabled) + ret = ravb_close(ndev); + if (ret) return ret; reset_assert: From patchwork Wed May 29 08:14:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 088D7C27C50 for ; Wed, 29 May 2024 08:15:18 +0000 (UTC) Received: from mail-lf1-f53.google.com (mail-lf1-f53.google.com [209.85.167.53]) by mx.groups.io with SMTP id smtpd.web11.8690.1716970511295560509 for ; Wed, 29 May 2024 01:15:11 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=O/S9aLv9; spf=pass (domain: tuxon.dev, ip: 209.85.167.53, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f53.google.com with SMTP id 2adb3069b0e04-52962423ed8so2090128e87.2 for ; Wed, 29 May 2024 01:15:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970509; x=1717575309; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q63jGnRIRAKnf3BnFcXOiOV6g8h6lJPpV6e7ogRxN+c=; b=O/S9aLv92zoy8WkC8g8rVdBomA6gVj7sBeMvzl4hJCdfIxfXqzDuAGIwX8Zmv/XDmT duso+uHZQ6XD5lalE2ZC0tY9Hup7TK9JCkGliOS8KXm866gCYxrXRyGAisSxsq+FUea5 ZlEVxrT+sjWA3tuklmTs4TtUIAkLHqrI1Zba8Faf9XXHbC1hWwD6AAUHH3p38UFK+stC nNooloT13Tj8xaxVJ/il5XYM2NnE+fER0ZIzoCb6RU8xSC58y8t3GEHGQQPJK06kMiKM pCM8QwdIRTyiMlCiFyUWI0j4X68MSSKK7szgkSmKNg/HzUtx03N7LiygRhaqtfkMVkGI QG+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970509; x=1717575309; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q63jGnRIRAKnf3BnFcXOiOV6g8h6lJPpV6e7ogRxN+c=; b=YjmXIDdV15f9AVIjU9MRpeLc+tshW13HJuZFtS8ASNIvrAiz/3AGHyl5PQIv9l1U6y Rh360YNl2Rgtw1mT6zkmLELid/hEddLYJ9CikWDGP+Rg/ATVicD+QMvmxIgGB0ANuzFe Ibr1zhs3ahsVXaDNcH1y4no/+pkNVvO/Uj/rYgU0weI2R576b99rq49ZbmNVkfNp/RDH cEfE2D88OI/t+Aog69N0MfnTjj6gJQ7gLf/cfZxIqUbC0IqsBfSmLnf6A3jeIkm6vNL0 tvadukEREkUhtBO6p7DyJU2rWD+VIHcXpQBnWsYV+hAcrtRTYCYNF+qFybogMDVdwaAS 0ITA== X-Gm-Message-State: AOJu0YxnSuc+arHP7ckNhpIHXFpMnkyUcFrHyVtStxiCpPoLxuMeshjr ByrCFfg8JDsrPUz6NsAPQ1lfJdCLhxsiy/Lj36a08jgCAkdODOXAMMKE9P8RJus= X-Google-Smtp-Source: AGHT+IHZnFNaEa7CGCPfKn44DVh19JLw1TcKq5Uu5U8NfUlSr9KWSgNseqa9O7hUEd7Cp4NWW3taiQ== X-Received: by 2002:a05:6512:3f09:b0:529:ac49:45d1 with SMTP id 2adb3069b0e04-529ac494708mr8560822e87.66.1716970509428; Wed, 29 May 2024 01:15:09 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:08 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 20/33] net: ravb: Simplify ravb_resume() Date: Wed, 29 May 2024 11:14:21 +0300 Message-Id: <20240529081434.639519-21-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:18 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16048 From: Claudiu Beznea commit e95273fe4d02a6096ba5fe8287bcd9513396ec71 upstream. Remove explicit calls to functions that are called by ravb_open(). There is no need to have them doubled now that the ravb_open() already contains what is needed for the interface configuration. Along with it, configurations needed by PTP were moved to ravb_wol_restore(). With this, code in ravb_resume() becomes simpler. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: Paolo Abeni Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 58 ++++++++++-------------- 1 file changed, 24 insertions(+), 34 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 38b6807428c8..511352a93cbc 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2961,6 +2961,20 @@ static int ravb_wol_restore(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; + int error; + + /* Set reset mode to rearm the WoL logic. */ + error = ravb_set_opmode(ndev, CCC_OPC_RESET); + if (error) + return error; + + /* Set AVB config mode. */ + error = ravb_set_config_mode(ndev); + if (error) + return error; + + if (priv->info->ccc_gac) + ravb_ptp_init(ndev, priv->pdev); if (info->nc_queues) napi_enable(&priv->napi[RAVB_NC]); @@ -3000,53 +3014,29 @@ static int __maybe_unused ravb_resume(struct device *dev) { struct net_device *ndev = dev_get_drvdata(dev); struct ravb_private *priv = netdev_priv(ndev); - const struct ravb_hw_info *info = priv->info; int ret; ret = reset_control_deassert(priv->rstc); if (ret) return ret; - /* If WoL is enabled set reset mode to rearm the WoL logic */ + if (!netif_running(ndev)) + return 0; + + /* If WoL is enabled restore the interface. */ if (priv->wol_enabled) { - ret = ravb_set_opmode(ndev, CCC_OPC_RESET); + ret = ravb_wol_restore(ndev); if (ret) return ret; } - /* All register have been reset to default values. - * Restore all registers which where setup at probe time and - * reopen device if it was running before system suspended. - */ - - /* Set AVB config mode */ - ret = ravb_set_config_mode(ndev); - if (ret) + /* Reopening the interface will restore the device to the working state. */ + ret = ravb_open(ndev); + if (ret < 0) return ret; - ravb_set_gti(ndev); - - if (info->internal_delay) - ravb_set_delay_mode(ndev); - - /* Restore descriptor base address table */ - ravb_write(ndev, priv->desc_bat_dma, DBAT); - - if (priv->info->ccc_gac) - ravb_ptp_init(ndev, priv->pdev); - - if (netif_running(ndev)) { - if (priv->wol_enabled) { - ret = ravb_wol_restore(ndev); - if (ret) - return ret; - } - ret = ravb_open(ndev); - if (ret < 0) - return ret; - ravb_set_rx_mode(ndev); - netif_device_attach(ndev); - } + ravb_set_rx_mode(ndev); + netif_device_attach(ndev); return ret; } From patchwork Wed May 29 08:14:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678296 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8F33C25B75 for ; Wed, 29 May 2024 08:15:17 +0000 (UTC) Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) by mx.groups.io with SMTP id smtpd.web11.8692.1716970513000531262 for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:10 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 21/33] ravb: Add Rx checksum offload support for GbEth Date: Wed, 29 May 2024 11:14:22 +0300 Message-Id: <20240529081434.639519-22-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:17 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16049 From: Biju Das commit c2da9408579d52fdf9b0ec494534d6ac66d4511e upstream. TOE has hardware support for calculating IP header and TCP/UDP/ICMP checksum for both IPv4 and IPv6. Add Rx checksum offload supported by TOE for IPv4 and TCP/UDP protocols. For Rx, the 4-byte result of checksum calculation is attached to the Ethernet frames.First 2-bytes is result of IPv4 header checksum and next 2-bytes is TCP/UDP/ICMP checksum. If a frame does not have checksum error, 0x0000 is attached as checksum calculation result. For unsupported frames 0xFFFF is attached as checksum calculation result. In case of an IPv6 packet, IPv4 checksum is always set to 0xFFFF. We can test this functionality by the below commands ethtool -K eth0 rx on --> to turn on Rx checksum offload ethtool -K eth0 rx off --> to turn off Rx checksum offload Signed-off-by: Biju Das Reviewed-by: Sergey Shtylyov Link: https://lore.kernel.org/r/20240207092838.160627-2-biju.das.jz@bp.renesas.com Signed-off-by: Jakub Kicinski Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb.h | 19 ++++- drivers/net/ethernet/renesas/ravb_main.c | 92 +++++++++++++++++++++++- 2 files changed, 107 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index 268ccfafe7aa..b98677c7c8e1 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -205,7 +205,10 @@ enum ravb_reg { TLFRCR = 0x0758, RFCR = 0x0760, MAFCR = 0x0778, - CSR0 = 0x0800, /* RZ/G2L only */ + + /* TOE registers (RZ/G2L only) */ + CSR0 = 0x0800, + CSR2 = 0x0808, }; @@ -978,6 +981,20 @@ enum CSR0_BIT { CSR0_RPE = 0x00000020, }; +enum CSR2_BIT { + CSR2_RIP4 = 0x00000001, + CSR2_RTCP4 = 0x00000010, + CSR2_RUDP4 = 0x00000020, + CSR2_RICMP4 = 0x00000040, + CSR2_RTCP6 = 0x00100000, + CSR2_RUDP6 = 0x00200000, + CSR2_RICMP6 = 0x00400000, + CSR2_RHOP = 0x01000000, + CSR2_RROUT = 0x02000000, + CSR2_RAHD = 0x04000000, + CSR2_RDHD = 0x08000000, +}; + #define DBAT_ENTRY_NUM 22 #define RX_QUEUE_OFFSET 4 #define NUM_RX_QUEUE 2 diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 511352a93cbc..d5d660edd481 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -514,6 +514,24 @@ static int ravb_ring_init(struct net_device *ndev, int q) return -ENOMEM; } +static void ravb_csum_init_gbeth(struct net_device *ndev) +{ + if (!(ndev->features & NETIF_F_RXCSUM)) + goto done; + + ravb_write(ndev, 0, CSR0); + if (ravb_wait(ndev, CSR0, CSR0_RPE, 0)) { + netdev_err(ndev, "Timeout enabling hardware checksum\n"); + ndev->features &= ~NETIF_F_RXCSUM; + } else { + ravb_write(ndev, CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4, + CSR2); + } + +done: + ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); +} + static void ravb_emac_init_gbeth(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); @@ -545,7 +563,8 @@ static void ravb_emac_init_gbeth(struct net_device *ndev) /* E-MAC status register clear */ ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); - ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); + + ravb_csum_init_gbeth(ndev); /* E-MAC interrupt enable register */ ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); @@ -726,6 +745,30 @@ static void ravb_get_tx_tstamp(struct net_device *ndev) } } +static void ravb_rx_csum_gbeth(struct sk_buff *skb) +{ + __wsum csum_ip_hdr, csum_proto; + u8 *hw_csum; + + /* The hardware checksum status is contained in sizeof(__sum16) * 2 = 4 + * bytes appended to packet data. First 2 bytes is ip header checksum + * and last 2 bytes is protocol checksum. + */ + if (unlikely(skb->len < sizeof(__sum16) * 2)) + return; + + hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); + csum_proto = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); + + hw_csum -= sizeof(__sum16); + csum_ip_hdr = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); + skb_trim(skb, skb->len - 2 * sizeof(__sum16)); + + /* TODO: IPV6 Rx checksum */ + if (skb->protocol == htons(ETH_P_IP) && !csum_ip_hdr && !csum_proto) + skb->ip_summed = CHECKSUM_UNNECESSARY; +} + static void ravb_rx_csum(struct sk_buff *skb) { u8 *hw_csum; @@ -811,6 +854,8 @@ static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) skb = ravb_get_skb_gbeth(ndev, entry, desc); skb_put(skb, pkt_len); skb->protocol = eth_type_trans(skb, ndev); + if (ndev->features & NETIF_F_RXCSUM) + ravb_rx_csum_gbeth(skb); napi_gro_receive(&priv->napi[q], skb); stats->rx_packets++; stats->rx_bytes += pkt_len; @@ -838,6 +883,8 @@ static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) dev_kfree_skb(skb); priv->rx_1st_skb->protocol = eth_type_trans(priv->rx_1st_skb, ndev); + if (ndev->features & NETIF_F_RXCSUM) + ravb_rx_csum_gbeth(skb); napi_gro_receive(&priv->napi[q], priv->rx_1st_skb); stats->rx_packets++; @@ -2409,11 +2456,48 @@ static void ravb_set_rx_csum(struct net_device *ndev, bool enable) spin_unlock_irqrestore(&priv->lock, flags); } +static int ravb_endisable_csum_gbeth(struct net_device *ndev, enum ravb_reg reg, + u32 val, u32 mask) +{ + u32 csr0 = CSR0_TPE | CSR0_RPE; + int ret; + + ravb_write(ndev, csr0 & ~mask, CSR0); + ret = ravb_wait(ndev, CSR0, mask, 0); + if (!ret) + ravb_write(ndev, val, reg); + + ravb_write(ndev, csr0, CSR0); + + return ret; +} + static int ravb_set_features_gbeth(struct net_device *ndev, netdev_features_t features) { - /* Place holder */ - return 0; + netdev_features_t changed = ndev->features ^ features; + struct ravb_private *priv = netdev_priv(ndev); + unsigned long flags; + int ret = 0; + u32 val; + + spin_lock_irqsave(&priv->lock, flags); + if (changed & NETIF_F_RXCSUM) { + if (features & NETIF_F_RXCSUM) + val = CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4; + else + val = 0; + + ret = ravb_endisable_csum_gbeth(ndev, CSR2, val, CSR0_RPE); + if (ret) + goto done; + } + + ndev->features = features; +done: + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; } static int ravb_set_features_rcar(struct net_device *ndev, @@ -2593,6 +2677,8 @@ static const struct ravb_hw_info gbeth_hw_info = { .emac_init = ravb_emac_init_gbeth, .gstrings_stats = ravb_gstrings_stats_gbeth, .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), + .net_hw_features = NETIF_F_RXCSUM, + .net_features = NETIF_F_RXCSUM, .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN), .tccr_mask = TCCR_TSRQ0, From patchwork Wed May 29 08:14:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678298 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7AE5C27C44 for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:12 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 22/33] ravb: Add Tx checksum offload support for GbEth Date: Wed, 29 May 2024 11:14:23 +0300 Message-Id: <20240529081434.639519-23-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:17 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16050 From: Biju Das commit 6c8e2803ef36d3c0c20c7019a19c668c3b0ac1d1 upstream. TOE has hardware support for calculating IP header and TCP/UDP/ICMP checksum for both IPv4 and IPv6. Add Tx checksum offload supported by TOE for IPv4 and TCP/UDP. For Tx, the result of checksum calculation is set to the checksum field of each IPv4 Header/TCP/UDP/ICMP of ethernet frames. For the unsupported frames, those fields are not changed. If a transmission frame is an UDPv4 frame and its checksum value in the UDP header field is 0x0000, TOE does not calculate checksum for UDP part of this frame as it is optional function as per standards. We can test this functionality by the below commands ethtool -K eth0 tx on --> to turn on Tx checksum offload ethtool -K eth0 tx off --> to turn off Tx checksum offload Signed-off-by: Biju Das Reviewed-by: Sergey Shtylyov Link: https://lore.kernel.org/r/20240207092838.160627-3-biju.das.jz@bp.renesas.com Signed-off-by: Jakub Kicinski Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb.h | 15 +++++ drivers/net/ethernet/renesas/ravb_main.c | 71 +++++++++++++++++++++--- 2 files changed, 79 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index b98677c7c8e1..35e642fc4b2a 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -208,6 +208,7 @@ enum ravb_reg { /* TOE registers (RZ/G2L only) */ CSR0 = 0x0800, + CSR1 = 0x0804, CSR2 = 0x0808, }; @@ -981,6 +982,20 @@ enum CSR0_BIT { CSR0_RPE = 0x00000020, }; +enum CSR1_BIT { + CSR1_TIP4 = 0x00000001, + CSR1_TTCP4 = 0x00000010, + CSR1_TUDP4 = 0x00000020, + CSR1_TICMP4 = 0x00000040, + CSR1_TTCP6 = 0x00100000, + CSR1_TUDP6 = 0x00200000, + CSR1_TICMP6 = 0x00400000, + CSR1_THOP = 0x01000000, + CSR1_TROUT = 0x02000000, + CSR1_TAHD = 0x04000000, + CSR1_TDHD = 0x08000000, +}; + enum CSR2_BIT { CSR2_RIP4 = 0x00000001, CSR2_RTCP4 = 0x00000010, diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index d5d660edd481..548bd436c51a 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "ravb.h" @@ -516,16 +517,28 @@ static int ravb_ring_init(struct net_device *ndev, int q) static void ravb_csum_init_gbeth(struct net_device *ndev) { - if (!(ndev->features & NETIF_F_RXCSUM)) + bool tx_enable = ndev->features & NETIF_F_HW_CSUM; + bool rx_enable = ndev->features & NETIF_F_RXCSUM; + + if (!(tx_enable || rx_enable)) goto done; ravb_write(ndev, 0, CSR0); - if (ravb_wait(ndev, CSR0, CSR0_RPE, 0)) { + if (ravb_wait(ndev, CSR0, CSR0_TPE | CSR0_RPE, 0)) { netdev_err(ndev, "Timeout enabling hardware checksum\n"); - ndev->features &= ~NETIF_F_RXCSUM; + + if (tx_enable) + ndev->features &= ~NETIF_F_HW_CSUM; + + if (rx_enable) + ndev->features &= ~NETIF_F_RXCSUM; } else { - ravb_write(ndev, CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4, - CSR2); + if (tx_enable) + ravb_write(ndev, CSR1_TIP4 | CSR1_TTCP4 | CSR1_TUDP4, CSR1); + + if (rx_enable) + ravb_write(ndev, CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4, + CSR2); } done: @@ -2073,6 +2086,36 @@ static void ravb_tx_timeout_work(struct work_struct *work) rtnl_unlock(); } +static bool ravb_can_tx_csum_gbeth(struct sk_buff *skb) +{ + struct iphdr *ip = ip_hdr(skb); + + /* TODO: Need to add support for VLAN tag 802.1Q */ + if (skb_vlan_tag_present(skb)) + return false; + + /* TODO: Need to add hardware checksum for IPv6 */ + if (skb->protocol != htons(ETH_P_IP)) + return false; + + switch (ip->protocol) { + case IPPROTO_TCP: + break; + case IPPROTO_UDP: + /* If the checksum value in the UDP header field is 0, TOE does + * not calculate checksum for UDP part of this frame as it is + * optional function as per standards. + */ + if (udp_hdr(skb)->check == 0) + return false; + break; + default: + return false; + } + + return true; +} + /* Packet transmit function for Ethernet AVB */ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) { @@ -2088,6 +2131,9 @@ static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) u32 entry; u32 len; + if (skb->ip_summed == CHECKSUM_PARTIAL && !ravb_can_tx_csum_gbeth(skb)) + skb_checksum_help(skb); + spin_lock_irqsave(&priv->lock, flags); if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * num_tx_desc) { @@ -2493,6 +2539,17 @@ static int ravb_set_features_gbeth(struct net_device *ndev, goto done; } + if (changed & NETIF_F_HW_CSUM) { + if (features & NETIF_F_HW_CSUM) + val = CSR1_TIP4 | CSR1_TTCP4 | CSR1_TUDP4; + else + val = 0; + + ret = ravb_endisable_csum_gbeth(ndev, CSR1, val, CSR0_TPE); + if (ret) + goto done; + } + ndev->features = features; done: spin_unlock_irqrestore(&priv->lock, flags); @@ -2677,8 +2734,8 @@ static const struct ravb_hw_info gbeth_hw_info = { .emac_init = ravb_emac_init_gbeth, .gstrings_stats = ravb_gstrings_stats_gbeth, .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), - .net_hw_features = NETIF_F_RXCSUM, - .net_features = NETIF_F_RXCSUM, + .net_hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, + .net_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN), .tccr_mask = TCCR_TSRQ0, From patchwork Wed May 29 08:14:24 2024 Content-Type: text/plain; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:13 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 23/33] net: ravb: Get rid of the temporary variable irq Date: Wed, 29 May 2024 11:14:24 +0300 Message-Id: <20240529081434.639519-24-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:17 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16051 From: Claudiu Beznea commit a260f080660ef8bac97404dd0b9ddbe35a608426 upstream. The 4th argument of ravb_setup_irq() is used to save the IRQ number that will be further used by the driver code. Not all ravb_setup_irqs() calls need to save the IRQ number. The previous code used to pass a dummy variable as the 4th argument in case the IRQ is not needed for further usage. That is not necessary as the code from ravb_setup_irq() can detect by itself if the IRQ needs to be saved. Thus, get rid of the code that is not needed. Reported-by: Sergey Shtylyov Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: David S. Miller Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 29 +++++++++++++----------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 548bd436c51a..e206b5b21ffd 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2767,24 +2767,27 @@ static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, struct device *dev = &pdev->dev; const char *dev_name; unsigned long flags; - int error; + int error, irq_num; if (irq_name) { dev_name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); if (!dev_name) return -ENOMEM; - *irq = platform_get_irq_byname(pdev, irq_name); + irq_num = platform_get_irq_byname(pdev, irq_name); flags = 0; } else { dev_name = ndev->name; - *irq = platform_get_irq(pdev, 0); + irq_num = platform_get_irq(pdev, 0); flags = IRQF_SHARED; } - if (*irq < 0) - return *irq; + if (irq_num < 0) + return irq_num; + + if (irq) + *irq = irq_num; - error = devm_request_irq(dev, *irq, handler, flags, dev_name, ndev); + error = devm_request_irq(dev, irq_num, handler, flags, dev_name, ndev); if (error) netdev_err(ndev, "cannot request IRQ %s\n", dev_name); @@ -2796,7 +2799,7 @@ static int ravb_setup_irqs(struct ravb_private *priv) const struct ravb_hw_info *info = priv->info; struct net_device *ndev = priv->ndev; const char *irq_name, *emac_irq_name; - int error, irq; + int error; if (!info->multi_irqs) return ravb_setup_irq(priv, NULL, NULL, &ndev->irq, ravb_interrupt); @@ -2819,28 +2822,28 @@ static int ravb_setup_irqs(struct ravb_private *priv) return error; if (info->err_mgmt_irqs) { - error = ravb_setup_irq(priv, "err_a", "err_a", &irq, ravb_multi_interrupt); + error = ravb_setup_irq(priv, "err_a", "err_a", NULL, ravb_multi_interrupt); if (error) return error; - error = ravb_setup_irq(priv, "mgmt_a", "mgmt_a", &irq, ravb_multi_interrupt); + error = ravb_setup_irq(priv, "mgmt_a", "mgmt_a", NULL, ravb_multi_interrupt); if (error) return error; } - error = ravb_setup_irq(priv, "ch0", "ch0:rx_be", &irq, ravb_be_interrupt); + error = ravb_setup_irq(priv, "ch0", "ch0:rx_be", NULL, ravb_be_interrupt); if (error) return error; - error = ravb_setup_irq(priv, "ch1", "ch1:rx_nc", &irq, ravb_nc_interrupt); + error = ravb_setup_irq(priv, "ch1", "ch1:rx_nc", NULL, ravb_nc_interrupt); if (error) return error; - error = ravb_setup_irq(priv, "ch18", "ch18:tx_be", &irq, ravb_be_interrupt); + error = ravb_setup_irq(priv, "ch18", "ch18:tx_be", NULL, ravb_be_interrupt); if (error) return error; - return ravb_setup_irq(priv, "ch19", "ch19:tx_nc", &irq, ravb_nc_interrupt); + return ravb_setup_irq(priv, "ch19", "ch19:tx_nc", NULL, ravb_nc_interrupt); } static int ravb_probe(struct platform_device *pdev) From patchwork Wed May 29 08:14:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678300 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8A1EC25B75 for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:15 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 24/33] net: ravb: Keep the reverse order of operations in ravb_close() Date: Wed, 29 May 2024 11:14:25 +0300 Message-Id: <20240529081434.639519-25-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:27 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16052 From: Claudiu Beznea commit a5f149a97d09cc9340d8fb4e22a3074a7bc1e02d upstream. Keep the reverse order of operations in ravb_close() when compared with ravb_open(). This is the recommended configuration sequence. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: David S. Miller Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index e206b5b21ffd..ea741fcab46c 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2341,6 +2341,14 @@ static int ravb_close(struct net_device *ndev) ravb_write(ndev, 0, RIC2); ravb_write(ndev, 0, TIC); + /* PHY disconnect */ + if (ndev->phydev) { + phy_stop(ndev->phydev); + phy_disconnect(ndev->phydev); + if (of_phy_is_fixed_link(np)) + of_phy_deregister_fixed_link(np); + } + /* Stop PTP Clock driver */ if (info->gptp || info->ccc_gac) ravb_ptp_stop(ndev); @@ -2359,14 +2367,6 @@ static int ravb_close(struct net_device *ndev) } } - /* PHY disconnect */ - if (ndev->phydev) { - phy_stop(ndev->phydev); - phy_disconnect(ndev->phydev); - if (of_phy_is_fixed_link(np)) - of_phy_deregister_fixed_link(np); - } - cancel_work_sync(&priv->work); if (info->nc_queues) From patchwork Wed May 29 08:14:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A5DEC27C44 for ; Wed, 29 May 2024 08:15:28 +0000 (UTC) Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by mx.groups.io with SMTP id smtpd.web11.8696.1716970518626306762 for ; Wed, 29 May 2024 01:15:18 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=kQFRtFSg; spf=pass (domain: tuxon.dev, ip: 209.85.128.45, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-42120e3911eso12067525e9.0 for ; Wed, 29 May 2024 01:15:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970517; x=1717575317; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HO0X9jNoxwJfBZX16rch2LjhZ/J4q4jPUaEye07frbs=; b=kQFRtFSg3r4IspZ9nZfItz2vKfoK4MkwssVys3+wbDWyoXto+2RdepD99tAufeQcS4 py3rTpLR9gVh//t9r86FjtXGFsxlDIT1l3xRT53bqVL3YO1VjqyPiFDRJOKb2KgKXopm Tc85LH4PmVALitCEZsFG9QTFWqJCpbMyYh4nno4twnz9oyTcq5yGgfxhHIQW1XRPmLeZ NBgWkJvcEhGxFWlU21k06dThfqWF2PrJeYxWxYFagwzHfalm4N0I205SYVPTQV+adHEO psHSswteDCBZdsL2F/XlS4hp6WdoxXj9AnxBrBfgWWXoj9B48zpnXGjeBNIh1xLJXHyq ojRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970517; x=1717575317; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HO0X9jNoxwJfBZX16rch2LjhZ/J4q4jPUaEye07frbs=; b=V/GNfNkdg2Bz5SNGqxhhzBUFZeyYb/zyso5JtjsbKnz0qg0HM9upiser5+cFFdxXYK PnRp471GaUQG/yqeAXLT+i8+l9hdbP2MpZpSujNjaogy7sGcsYb8nDW5Tn4g8WxOlYN/ PlZfM9jyJ9dswDfouQjtZ0YN90UZMHTouXLDpvkzZXycsh5AXWkzSfnZ11dHpTRkHYg5 MH2z9sJ0I61NR1qNzoZlZzwCFwgHb6Y9d45TIDpnMmhxdXWoWUA/mHcJYsKwi28q42by aT3MI397LAET1ZOtPJ0A+Vus5cKg2GoTwu1baJMnqVBC3rPt4q7gcC+Tx4McKVetbwul LJcA== X-Gm-Message-State: AOJu0Yy9fKIpP/LlFKjvL/tpiuFHsGKIQTKkAT4cdt1lu5jHC2u15YHe zpHyIUc9o4J76NjFrgEDxdt5FH0usz3uJQJSv04Sa7crKwD19xkhlV5pwKjqkj4= X-Google-Smtp-Source: AGHT+IGxHV+njv86lakbyK/lotwnrcLfMTPn9Mnsr/oXBfI6jXhcVdBKGO50mM0AXlw91+asBalscA== X-Received: by 2002:a05:600c:1c9f:b0:41b:b07a:c54c with SMTP id 5b1f17b1804b1-421089ccfa1mr101215985e9.9.1716970517155; Wed, 29 May 2024 01:15:17 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:16 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 25/33] net: ravb: Return cached statistics if the interface is down Date: Wed, 29 May 2024 11:14:26 +0300 Message-Id: <20240529081434.639519-26-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:28 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16053 From: Claudiu Beznea commit bbf2345fa6582c5292bc5c537e7a29aad918be0c upstream. Return the cached statistics in case the interface is down. There should be no drawback to this, as cached statistics are updated in ravb_close(). In order to avoid accessing the IP registers while the IP is runtime suspended pm_runtime_active() check was introduced. The device runtime PM usage counter has been incremented to avoid disabling the device clocks while the check is in progress (if any). The commit prepares the code for the addition of runtime PM support. Suggested-by: Sergey Shtylyov Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: David S. Miller Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index ea741fcab46c..6494f72ff79f 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2268,8 +2268,15 @@ static struct net_device_stats *ravb_get_stats(struct net_device *ndev) struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; struct net_device_stats *nstats, *stats0, *stats1; + struct device *dev = &priv->pdev->dev; nstats = &ndev->stats; + + pm_runtime_get_noresume(dev); + + if (!pm_runtime_active(dev)) + goto out_rpm_put; + stats0 = &priv->stats[RAVB_BE]; if (info->tx_counters) { @@ -2311,6 +2318,8 @@ static struct net_device_stats *ravb_get_stats(struct net_device *ndev) nstats->rx_over_errors += stats1->rx_over_errors; } +out_rpm_put: + pm_runtime_put_noidle(dev); return nstats; } @@ -2378,6 +2387,9 @@ static int ravb_close(struct net_device *ndev) if (info->nc_queues) ravb_ring_free(ndev, RAVB_NC); + /* Update statistics. */ + ravb_get_stats(ndev); + /* Set reset mode. */ return ravb_set_opmode(ndev, CCC_OPC_RESET); } From patchwork Wed May 29 08:14:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678301 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8A91C41513 for ; Wed, 29 May 2024 08:15:27 +0000 (UTC) Received: from mail-lj1-f181.google.com (mail-lj1-f181.google.com [209.85.208.181]) by mx.groups.io with SMTP id smtpd.web11.8699.1716970520767565730 for ; Wed, 29 May 2024 01:15:21 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=DTWaUFwn; spf=pass (domain: tuxon.dev, ip: 209.85.208.181, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lj1-f181.google.com with SMTP id 38308e7fff4ca-2e9684e0288so22497481fa.1 for ; Wed, 29 May 2024 01:15:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970519; x=1717575319; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wqzWoSDOULDEsM/8Jro50TsKViK1Pp1ecyRqoNxEOM0=; b=DTWaUFwntUPmdlOJnn9jrJ6hN2iEclzG+cFeLdPJWnVsOIj0/5AnRsNQVf4KV7+64Q rfjSRfOwxcn7w4n5TlS8CHAATWDCkKmbNjcAXlYT+gqcSA3OVwCZ+mtZGMVXaprWMngD 9zymygGP+c7amZTGrYXzou+THg73EscvRJ6q1BJ9Vja5Tcm7TUv+/R2MZBqdgk/Fq7Ju IRtjdKKQd3ostQt7Tk5pQh/sqsxvSXxhcOacX9VzWewIeR4AEnXUf/KrPNmAQOYPkKru gN6a8i297pQ26PVgjhuGqczcNuBQjBA+lXKXNUnKuepvPSM/zcN0BnO4NbeeWD9n6gcE LC+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970519; x=1717575319; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wqzWoSDOULDEsM/8Jro50TsKViK1Pp1ecyRqoNxEOM0=; b=W8jHoIUJscUXspziel+JZ/O+sarwNo3grnASyBUhgBt/Y3yWC4ipalce3FnDHMqlJ8 9nX1kcdvnJeTCKBFEOHAjT/1v9EYXhFthmebea9JSZUoQT6ZY28pVK/z6MJemLYY2DEu sY9f7PHoQIVCboM3nmuF1ricnQTwqpjt2UYapB2SLOkeUu5PJkni0m//fd3KekzHPNLM 90h/fagaiwsCYlM9MDYU1X1IwTuSzno8HUMjI8NkcKPRqTRjv9hFtyrzMtRqIvQeHuRD dk6PuRQ0eBpV3kDXaxx0LL/wAF6nfn2/hIbH4Xsu+g69v1VpkvwJKsw+L11aK/+kfIu8 VEaw== X-Gm-Message-State: AOJu0YynxDXbRSRFkowidpjxUcu8YcXKdkwRgCZLkOhwBfF9qX62mFI3 QCJeG680d2V47r4VfC+p0DyybX0NSazcg7BLeFo8sLmUt/YccS79C4/mfxu1A14= X-Google-Smtp-Source: AGHT+IGN9e43QIyvyLviXP4GTM/m1WswahPZqyicqmbi7WUr8wUCHwkgbyMkLuS0nORsfn+iE0HJRw== X-Received: by 2002:a2e:9c94:0:b0:2e2:a85f:f222 with SMTP id 38308e7fff4ca-2e95b042c1dmr142834061fa.10.1716970518943; Wed, 29 May 2024 01:15:18 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:18 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 26/33] net: ravb: Move the update of ndev->features to ravb_set_features() Date: Wed, 29 May 2024 11:14:27 +0300 Message-Id: <20240529081434.639519-27-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:27 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16054 From: Claudiu Beznea commit 7bddccc9911cdff377e16b9a5a386721279b4438 upstream. Commit c2da9408579d ("ravb: Add Rx checksum offload support for GbEth") introduced support for setting GbEth features. With this the IP-specific features update functions update the ndev->features individually. Next commits add runtime PM support for the ravb driver. The runtime PM implementation will enable/disable the IP clocks on the ravb_open()/ravb_close() functions. Accessing the IP registers with clocks disabled blocks the system. The ravb_set_features() function could be executed when the Ethernet interface is closed so we need to ensure we don't access IP registers while the interface is down when runtime PM support will be in place. For these, move the update of ndev->features to ravb_set_features(). In this way we update the ndev->features only when the IP-specific features set function returns success and we can avoid code duplication when introducing runtime PM registers protection. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: David S. Miller Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 6494f72ff79f..49607ab981ab 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2562,7 +2562,6 @@ static int ravb_set_features_gbeth(struct net_device *ndev, goto done; } - ndev->features = features; done: spin_unlock_irqrestore(&priv->lock, flags); @@ -2577,8 +2576,6 @@ static int ravb_set_features_rcar(struct net_device *ndev, if (changed & NETIF_F_RXCSUM) ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); - ndev->features = features; - return 0; } @@ -2587,8 +2584,15 @@ static int ravb_set_features(struct net_device *ndev, { struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; + int ret; + + ret = info->set_feature(ndev, features); + if (ret) + return ret; - return info->set_feature(ndev, features); + ndev->features = features; + + return 0; } static const struct net_device_ops ravb_netdev_ops = { From patchwork Wed May 29 08:14:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0161DC25B7E for ; Wed, 29 May 2024 08:15:28 +0000 (UTC) Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.groups.io with SMTP id smtpd.web10.8736.1716970521772927696 for ; Wed, 29 May 2024 01:15:22 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=k3Wu34Zm; spf=pass (domain: tuxon.dev, ip: 209.85.128.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-42120fc8cbfso11580935e9.2 for ; Wed, 29 May 2024 01:15:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970520; x=1717575320; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gSj9oYMXBLVUiXIDHIb/ZIKKGc+KUGEEzQtbT3H6vk4=; b=k3Wu34ZmbkV8jLHfBfGF9xSqudvvy9FLieVTq/dp9ab3PceoiLT6VvERbMVbxb2RkW 7loBrKM9hQyA0A7KW0ycHt2TALCq60Q16C+ZKR8c1jXScaIJ7BFDyrqeetjHOG1+vgBv BzUTgxcKTr8MjsVGT9I0XUbG4djecIWL1KeKRVjlK75NqMNXHlkcz2qzlxUHGkXI4zNd m1YQ9KZdB4ewEyB4J+b6iFDPtEtwRe8fICMeUAuFiuFmuuRusE8Te3Xjuzz32CxeF1tm oNP9v9Pxe0M9BT29VI+Moe8aMgDau9sSFEQyBCtS5I2BYzR4L8sGFnWhkIwU3YpqLtzX BXiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970520; x=1717575320; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gSj9oYMXBLVUiXIDHIb/ZIKKGc+KUGEEzQtbT3H6vk4=; b=vwtCLCeLhB1mXITv6CjXlYDvNWHDKNURCA1f6ZIpidgAlyhjMISl9zB+P08exAJmQE XAukz6zH/gDbhLdsGMYrTzMQjhz9TfQyCzFvAFY8gpck2GkJIGJB9FoDgpuBJoDPFkPN N1OCRG+kkCDn8v9ZSQAouyHlIGfVsVBu41Bxhbe+r+EnFm7L+uXzmuNgmb63B+WB/ljv 4uRkBqWimZbqVOlje9xxgUWRCUAIslkOQIRkkk+a1ZXQZcOgEeN78I+sOmWt/59NRAXW UfJVzKQCM9xU7or05OXjWWqCioVNuv1RSYSCEaB/cy58U1rmt8tn6Cgcc5DlV6Jt0HJ0 o23A== X-Gm-Message-State: AOJu0YxKIvPxVQbijaXu6efBuCoH8TSJqDInCV9LTeCrwH1v3fXY0qxf xuPLMvVb3o8yz1ikwlnzmq2DWaiuhOEKNiyr0WawZxgrohk8BTYBDCKbLgQ6Ozw= X-Google-Smtp-Source: AGHT+IFCBgI8VbNV0TOsiG1tnWI165e/LutZDX4QsGTQh1ks3lHDlUAY7hcoutbkgUTM4Ok7mxWQjQ== X-Received: by 2002:a05:600c:6b1a:b0:418:ed23:a9f0 with SMTP id 5b1f17b1804b1-421089dc44cmr111110385e9.18.1716970520332; Wed, 29 May 2024 01:15:20 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:19 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 27/33] net: ravb: Do not apply features to hardware if the interface is down Date: Wed, 29 May 2024 11:14:28 +0300 Message-Id: <20240529081434.639519-28-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:28 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16055 From: Claudiu Beznea commit a71a50e391bf00fdc88bb13a867620c59ad744da upstream. Do not apply features to hardware if the interface is down. In case runtime PM is enabled, and while the interface is down, the IP will be in reset mode (as for some platforms disabling the clocks will switch the IP to reset mode, which will lead to losing register contents) and applying settings in reset mode is not an option. Instead, cache the features and apply them in ravb_open() through ravb_emac_init(). To avoid accessing the hardware while the interface is down pm_runtime_active() check was introduced. Along with it the device runtime PM usage counter has been incremented to avoid disabling the device clocks while the check is in progress (if any). Commit prepares for the addition of runtime PM. Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: David S. Miller Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 49607ab981ab..a9adf5f67d8b 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2584,9 +2584,18 @@ static int ravb_set_features(struct net_device *ndev, { struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; + struct device *dev = &priv->pdev->dev; int ret; - ret = info->set_feature(ndev, features); + pm_runtime_get_noresume(dev); + + if (pm_runtime_active(dev)) + ret = info->set_feature(ndev, features); + else + ret = 0; + + pm_runtime_put_noidle(dev); + if (ret) return ret; From patchwork Wed May 29 08:14:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10E51C25B7C for ; Wed, 29 May 2024 08:15:28 +0000 (UTC) Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) by mx.groups.io with SMTP id smtpd.web10.8737.1716970523798817253 for ; Wed, 29 May 2024 01:15:24 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=XK9lQqdM; spf=pass (domain: tuxon.dev, ip: 209.85.128.44, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-42108739ed8so21282625e9.0 for ; Wed, 29 May 2024 01:15:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970522; x=1717575322; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=96bl+9LhPvuZnxppNjKplTrxYcU7Jo/nTvttXBYjZes=; b=XK9lQqdMb2yOKYAmumVjtF6VW7PX24rxJfJ0BLtPXS1Z23oy3GOb7TPXRULsibchIh reuTSE5aM/LgbMfQNrBci+ZiKX0HDTVxxygWKRghpD60UI20KX3HKgbLbbPN/XJ4I3a/ mWme5MlFIf+nMtkXePQVNAGlNQOcCRRiOG99X8p1eslUwZVO8t9pS/mx9GACZnxUlGZY xkFVpadlD9Jt190aegtuQ3XpeyVCBgQJetiYSjh40K2uUubEqXPhtofZzqjl21mjrUSY WbPGVvf6uobHag4UMoCwHj5GLDteBALt4QdaqZjD9IsIuty4BDIwVAHOALfpHrvShqEX XnYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970522; x=1717575322; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=96bl+9LhPvuZnxppNjKplTrxYcU7Jo/nTvttXBYjZes=; b=wHrCgtTYLcUVECHr62ZGiRdjVkccYpdySH1yq4FNAIDkvHHgCCgn5wZ38C3AfXu5wo M8mh/4QgsHfeZyyJLRmbyyJ+u3F6J+5wem2dt4RVbkRFUd/VI5th+mjuRgLgVO7m3SUp 0j7ghCY1Jygz1lIoDbm9QOARWy2Jim7jZJZH1RCmnn1t93BGAX3l8OecNHCEEoIjA8/X sYhSVxJLNU4v5XObUWvreFn1u8Najais66KD7OzQ3cXur2T0Aye2VicR2UmQxND39K0W DnILWvJ8b2fF6IVLKhtZswDeN4/FWJHrT+FxAcXvbpjcsV1HzMqbwIobLfYr3+a0TslX 6WBA== X-Gm-Message-State: AOJu0Yxp35bWGpDQhHHf2vk2Jcsb4ZyDHGh9uzsLfI8rbXzise6vO+xR ond3KygzfGOSVst9NjnlJr9iIsGVzogVWgz36EtmoX063rKIurtHs2q97tA0i2o= X-Google-Smtp-Source: AGHT+IFzGWnuN1qLGt7E8qyupeSQYkeWde/F3WSkvty4jyEck2tioE4FtGr6dv4RmToE2fkShfInUg== X-Received: by 2002:a05:600c:19d0:b0:421:20ac:1244 with SMTP id 5b1f17b1804b1-42120ac12d2mr37114875e9.22.1716970522284; Wed, 29 May 2024 01:15:22 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:21 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 28/33] net: ravb: Add runtime PM support Date: Wed, 29 May 2024 11:14:29 +0300 Message-Id: <20240529081434.639519-29-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:28 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16056 From: Claudiu Beznea commit 48f894ab07c444b9b26a0913d2032de663f4aecb upstream. Add runtime PM support for the ravb driver. As the driver is used by different IP variants, with different behaviors, to be able to have the runtime PM support available for all devices, the preparatory commits moved all the resources parsing and allocations in the driver's probe function and kept the settings for ravb_open(). This is due to the fact that on some IP variants-platforms tuples disabling/enabling the clocks will switch the IP to the reset operation mode where register contents is lost and reconfiguration needs to be done. For this the rabv_open() function enables the clocks, switches the IP to configuration mode, applies all the register settings and switches the IP to the operational mode. At the end of ravb_open() IP is ready to send/receive data. In ravb_close() necessary reverts are done (compared with ravb_open()), the IP is switched to reset mode and clocks are disabled. The ethtool APIs or IOCTLs that might execute while the interface is down are either cached (and applied in ravb_open()) or rejected (as at that time the IP is in reset mode). Keeping the IP in the reset mode also increases the power saved (according to the hardware manual). Signed-off-by: Claudiu Beznea Reviewed-by: Sergey Shtylyov Signed-off-by: David S. Miller [claudiu.beznea: return error in case pm_runtime_resume_and_get() call from ravb_remove() fails] Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 54 ++++++++++++++++++++++-- 1 file changed, 50 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index a9adf5f67d8b..892912716488 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1959,16 +1959,21 @@ static int ravb_open(struct net_device *ndev) { struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; + struct device *dev = &priv->pdev->dev; int error; napi_enable(&priv->napi[RAVB_BE]); if (info->nc_queues) napi_enable(&priv->napi[RAVB_NC]); + error = pm_runtime_resume_and_get(dev); + if (error < 0) + goto out_napi_off; + /* Set AVB config mode */ error = ravb_set_config_mode(ndev); if (error) - goto out_napi_off; + goto out_rpm_put; ravb_set_delay_mode(ndev); ravb_write(ndev, priv->desc_bat_dma, DBAT); @@ -2002,6 +2007,9 @@ static int ravb_open(struct net_device *ndev) ravb_stop_dma(ndev); out_set_reset: ravb_set_opmode(ndev, CCC_OPC_RESET); +out_rpm_put: + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); out_napi_off: if (info->nc_queues) napi_disable(&priv->napi[RAVB_NC]); @@ -2342,6 +2350,8 @@ static int ravb_close(struct net_device *ndev) struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; struct ravb_tstamp_skb *ts_skb, *ts_skb2; + struct device *dev = &priv->pdev->dev; + int error; netif_tx_stop_all_queues(ndev); @@ -2391,7 +2401,14 @@ static int ravb_close(struct net_device *ndev) ravb_get_stats(ndev); /* Set reset mode. */ - return ravb_set_opmode(ndev, CCC_OPC_RESET); + error = ravb_set_opmode(ndev, CCC_OPC_RESET); + if (error) + return error; + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return 0; } static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) @@ -2946,6 +2963,8 @@ static int ravb_probe(struct platform_device *pdev) clk_prepare(priv->refclk); platform_set_drvdata(pdev, ndev); + pm_runtime_set_autosuspend_delay(&pdev->dev, 100); + pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_enable(&pdev->dev); error = pm_runtime_resume_and_get(&pdev->dev); if (error < 0) @@ -3051,6 +3070,9 @@ static int ravb_probe(struct platform_device *pdev) netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); + return 0; out_napi_del: @@ -3068,6 +3090,7 @@ static int ravb_probe(struct platform_device *pdev) pm_runtime_put(&pdev->dev); out_rpm_disable: pm_runtime_disable(&pdev->dev); + pm_runtime_dont_use_autosuspend(&pdev->dev); clk_unprepare(priv->refclk); out_reset_assert: reset_control_assert(rstc); @@ -3081,6 +3104,12 @@ static int ravb_remove(struct platform_device *pdev) struct net_device *ndev = platform_get_drvdata(pdev); struct ravb_private *priv = netdev_priv(ndev); const struct ravb_hw_info *info = priv->info; + struct device *dev = &priv->pdev->dev; + int error; + + error = pm_runtime_resume_and_get(dev); + if (error < 0) + return error; unregister_netdev(ndev); if (info->nc_queues) @@ -3092,8 +3121,9 @@ static int ravb_remove(struct platform_device *pdev) dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, priv->desc_bat_dma); - pm_runtime_put_sync(&pdev->dev); + pm_runtime_put_sync_suspend(&pdev->dev); pm_runtime_disable(&pdev->dev); + pm_runtime_dont_use_autosuspend(dev); clk_unprepare(priv->refclk); reset_control_assert(priv->rstc); free_netdev(ndev); @@ -3177,6 +3207,10 @@ static int __maybe_unused ravb_suspend(struct device *dev) if (ret) return ret; + ret = pm_runtime_force_suspend(&priv->pdev->dev); + if (ret) + return ret; + reset_assert: return reset_control_assert(priv->rstc); } @@ -3199,16 +3233,28 @@ static int __maybe_unused ravb_resume(struct device *dev) ret = ravb_wol_restore(ndev); if (ret) return ret; + } else { + ret = pm_runtime_force_resume(dev); + if (ret) + return ret; } /* Reopening the interface will restore the device to the working state. */ ret = ravb_open(ndev); if (ret < 0) - return ret; + goto out_rpm_put; ravb_set_rx_mode(ndev); netif_device_attach(ndev); + return 0; + +out_rpm_put: + if (!priv->wol_enabled) { + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + } + return ret; } From patchwork Wed May 29 08:14:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678306 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24F68C41513 for ; Wed, 29 May 2024 08:15:38 +0000 (UTC) Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by mx.groups.io with SMTP id smtpd.web10.8739.1716970525281164728 for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:23 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 29/33] net: ravb: Fix registered interrupt names Date: Wed, 29 May 2024 11:14:30 +0300 Message-Id: <20240529081434.639519-30-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:38 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16057 From: Geert Uytterhoeven commit 0c81ea5a8e231fa120e3f76aa9ea99fa3950cc59 upstream. As interrupts are now requested from ravb_probe(), before calling register_netdev(), ndev->name still contains the template "eth%d", leading to funny names in /proc/interrupts. E.g. on R-Car E3: 89: 0 0 GICv2 93 Level eth%d:ch22:multi 90: 0 3 GICv2 95 Level eth%d:ch24:emac 91: 0 23484 GICv2 71 Level eth%d:ch0:rx_be 92: 0 0 GICv2 72 Level eth%d:ch1:rx_nc 93: 0 13735 GICv2 89 Level eth%d:ch18:tx_be 94: 0 0 GICv2 90 Level eth%d:ch19:tx_nc Worse, on platforms with multiple RAVB instances (e.g. R-Car V4H), all interrupts have similar names. Fix this by using the device name instead, like is done in several other drivers: 89: 0 0 GICv2 93 Level e6800000.ethernet:ch22:multi 90: 0 1 GICv2 95 Level e6800000.ethernet:ch24:emac 91: 0 28578 GICv2 71 Level e6800000.ethernet:ch0:rx_be 92: 0 0 GICv2 72 Level e6800000.ethernet:ch1:rx_nc 93: 0 14044 GICv2 89 Level e6800000.ethernet:ch18:tx_be 94: 0 0 GICv2 90 Level e6800000.ethernet:ch19:tx_nc Rename the local variable dev_name, as it shadows the dev_name() function, and pre-initialize it, to simplify the code. Fixes: 32f012b8c01ca9fd ("net: ravb: Move getting/requesting IRQs in the probe() method") Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Reviewed-by: Sergey Shtylyov Reviewed-by: Claudiu Beznea Tested-by: Claudiu Beznea # on RZ/G3S Link: https://lore.kernel.org/r/cde67b68adf115b3cf0b44c32334ae00b2fbb321.1713944647.git.geert+renesas@glider.be Signed-off-by: Jakub Kicinski Signed-off-by: Claudiu Beznea --- drivers/net/ethernet/renesas/ravb_main.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 892912716488..dda7fb410657 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2807,19 +2807,18 @@ static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, struct platform_device *pdev = priv->pdev; struct net_device *ndev = priv->ndev; struct device *dev = &pdev->dev; - const char *dev_name; + const char *devname = dev_name(dev); unsigned long flags; int error, irq_num; if (irq_name) { - dev_name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); - if (!dev_name) + devname = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", devname, ch); + if (!devname) return -ENOMEM; irq_num = platform_get_irq_byname(pdev, irq_name); flags = 0; } else { - dev_name = ndev->name; irq_num = platform_get_irq(pdev, 0); flags = IRQF_SHARED; } @@ -2829,9 +2828,9 @@ static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, if (irq) *irq = irq_num; - error = devm_request_irq(dev, irq_num, handler, flags, dev_name, ndev); + error = devm_request_irq(dev, irq_num, handler, flags, devname, ndev); if (error) - netdev_err(ndev, "cannot request IRQ %s\n", dev_name); + netdev_err(ndev, "cannot request IRQ %s\n", devname); return error; } From patchwork Wed May 29 08:14:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678304 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CFCBC27C50 for ; Wed, 29 May 2024 08:15:28 +0000 (UTC) Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) by mx.groups.io with SMTP id smtpd.web11.8701.1716970526981396620 for ; Wed, 29 May 2024 01:15:27 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=kiYeB6cs; spf=pass (domain: tuxon.dev, ip: 209.85.128.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-421140314d5so14315485e9.0 for ; Wed, 29 May 2024 01:15:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970525; x=1717575325; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5IDTuuUmMn75Lwct81/xNe16cbwwQxJv0yqy2cX1aHk=; b=kiYeB6csE2QdRASiwfNrVJHOoBtV7kHftDlftudEHASaQoeSeWgIdDaQh+WitTmvH/ xPD7MAUTUsuR18OWLcSck3zhpIY6t2CLwECmupCypsuvecul2bNJxQtAQBxKtlAON5eG O8U2AF559of94OUXyVLWa0hg8zyMhQOrXEeHndkA03EuVZ6RayYVSIV2e92/GfhgpgcG x+9On0CctsGjHKbUmvwi/cYfM5fb2JuNXKmtsvrLKwE8za2HgfukJ1SQ5tMgOy8EO6jt N6chUz9LBm3v2us+DEIZ5+/8kgfqPuoATI4/YzT8qeOCldcr3ihHmKU8THmivmRg6FLp 9PFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970525; x=1717575325; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5IDTuuUmMn75Lwct81/xNe16cbwwQxJv0yqy2cX1aHk=; b=sn2w1npYVPjQtin0nSXDgf6dSAZ/moa4j+8Yl1caaxjcbkOxMs7h9or8BL0pIhzv7I jngELFfknZFp1CHq5cFCMUV62rJak/n5u66pmSWEicdifUrIRBt98mAOKToAEgCUMS0R V8Bhz8ybv2nmh6jxFzyDCsKimYUBF/0PuJiiV4Wv+ZjHDRd5KfapdrZrE97jC6YZ7S6L +4YuUgzsdRhlS0mLXrbZmJCLw7gQo0XEqUedxXq7YYJ9FOWxSuMcpu99xYtgdOekX9v0 sR4/iAi7HVg9NERRly27GswpG9xa0QOFALC5aSd0oP0FNiiZS+2SU2+dBOQqRmw2fJ02 Ji6A== X-Gm-Message-State: AOJu0Yw6GEW9cse+TBUhJgBvTTOzqRyNRFx81rt3Y6aepbCqPs0GLR4t +l3M1TOai2002cPjxLe0yYnDAq0oTIo6JjvcagTImmgkCGSV/Sl8fmFfeOGJeBw= X-Google-Smtp-Source: AGHT+IGq/iklyaHgHanAFhacaBnjjBcl8Z3S0DCFShYa1urYKsYuVI8TX7gmKAXdXaWVZrDiunawZw== X-Received: by 2002:a05:600c:5110:b0:421:15f:186a with SMTP id 5b1f17b1804b1-42108a12b4fmr99744735e9.39.1716970525433; Wed, 29 May 2024 01:15:25 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:24 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 30/33] arm64: dts: renesas: r9a08g045: Add Ethernet nodes Date: Wed, 29 May 2024 11:14:31 +0300 Message-Id: <20240529081434.639519-31-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:28 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16058 From: Claudiu Beznea commit aefd220c5791ea3471fc920feba380aacd2dcfa7 upstream. Add the Ethernet nodes available on RZ/G3S (R9A08G045). Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-10-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 6c7b29b69d0e..aaab5739c134 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -149,6 +149,44 @@ sdhi2: mmc@11c20000 { status = "disabled"; }; + eth0: ethernet@11c30000 { + compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>, + <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A08G045_ETH0_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth1: ethernet@11c40000 { + compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; + reg = <0 0x11c40000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>, + <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A08G045_ETH1_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@12400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From patchwork Wed May 29 08:14:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678308 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32A91C25B7E for ; Wed, 29 May 2024 08:15:38 +0000 (UTC) Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by mx.groups.io with SMTP id smtpd.web10.8740.1716970528237232882 for ; Wed, 29 May 2024 01:15:28 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=SiEox9A7; spf=pass (domain: tuxon.dev, ip: 209.85.128.46, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-42011507a54so3475035e9.0 for ; Wed, 29 May 2024 01:15:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970527; x=1717575327; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0+R7AZabC2j7Eqa8GxbK2zoq/iJA7/S2Tp64qTSI1+w=; b=SiEox9A76Kyuu0e7Z0H+qrClZC7fxK6/r126Txd2pGXHVVRZ0c0J/TDjF6RtgYqhT/ djxlf6VgSId6O07K6aOma+YMgXx5fN+8IetLPXgpHe9/d1Cr/l3YEgu/MOHX1mOZmzM2 BQgUanmDVhb0d+Ai8duSrSgx88JrZCItSGOaNKZR621AUB7OEG5leXof4hVRsAOmnpKz v2g5moUE2aW0La86wkjVjgw/ZcXtMmKKf/aMEw8TvtbKvWynttEm5wv/eUYBokDc+lVv 9+8bVyq+Ai/j6hljzk1j+V4xyj/gD7rHZOQk/u8paQ3mp2P8Fyc9KDsvLPT1KtWBz5qs Zf0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970527; x=1717575327; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0+R7AZabC2j7Eqa8GxbK2zoq/iJA7/S2Tp64qTSI1+w=; b=nusrqXdmoFXe7nwy3ZU0krmKX1z7opkoyGwAjLLlLRBU2OUoAR86aVAOY2bZVLMl/l Dk7Zfr2RA3V8NMMxIZqnw6R6NH87yEN656cVCJ05BGtug7B33Kxh50T7+IxeJSsRFVzX ErW9Vn8M0DvAgJKQBAq5gS7TBa/JhQonopc5nEQY/r6DoXSLUvO3XeaAUpnhd1ZFPFmb I7AzswHNqNobCVWVZt47O3dLmQ5MmdznxrOh1OYIx3/17MmtOfbe9SPmPuMpHD6VIZcR qxipwQMnHezXlNA6JrlyYN9wntlIiMsYXE+l5jXo3aTf09QD2NX3SwGAL+nD1aIK5o+R 6yJw== X-Gm-Message-State: AOJu0YyJJWuXnAFzjfr3svLZE4CWnvCEl0GdRgubHqMLWzjaiDma+khn hu2e3jhkVDf5Eh6MnDN+l76puPQNOMXnMAtfflKq1+vr0uz2VXv9SK82K7RmYNnkN4ZLylefSIt rJXI= X-Google-Smtp-Source: AGHT+IGY14JxJdUbCkwxWF0bv7DgWc14qu3IFrqe8167ikXg4OX+uDW6PdHaFoLMV1kt0/VlVZJaOA== X-Received: by 2002:a05:600c:5103:b0:41f:9edf:de50 with SMTP id 5b1f17b1804b1-42122b274c7mr10331625e9.15.1716970526726; Wed, 29 May 2024 01:15:26 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:26 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 31/33] arm64: dts: renesas: rzg3s-smarc-som: Use switches' names to select on-board functionalities Date: Wed, 29 May 2024 11:14:32 +0300 Message-Id: <20240529081434.639519-32-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:38 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16059 From: Claudiu Beznea commit 447765986dbfc321e37b13d7c276b106a469ec0b upstream. The intention of the SW_SD0_DEV_SEL and SW_SD2_EN macros was to reflect the state of the SW_CONFIG individual switches available on the RZ/G3S Smarc Module, and at the same time to have a descriptive name for the switches themselves. Each individual switch is associated with a signal name, which might be active-low or not on the board. Using signal names instead of SW_CONFIG switch names may be confusing for a user who just playes with switches to select individual functionalities, but also for an advanced user who looks at the schematics. To avoid even further confusion, use the switches' names here and instantiate them with an ON/OFF state. This should be simpler, even though the name of the switches is not that intuitive. The switches' names documentation reflects the switches' purposes. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-11-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 34 ++++++++++++------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 01a4a9da7afc..f59094701a4a 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -9,23 +9,31 @@ #include /* - * Signals of SW_CONFIG switches: - * @SW_SD0_DEV_SEL: - * 0 - SD0 is connected to eMMC - * 1 - SD0 is connected to uSD0 card - * @SW_SD2_EN: - * 0 - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC - * 1 - SD2 is connected to SoC + * On-board switches' states: + * @SW_OFF: switch's state is OFF + * @SW_ON: switch's state is ON */ -#define SW_SD0_DEV_SEL 1 -#define SW_SD2_EN 1 +#define SW_OFF 0 +#define SW_ON 1 + +/* + * SW_CONFIG[x] switches' states: + * @SW_CONFIG2: + * SW_OFF - SD0 is connected to eMMC + * SW_ON - SD0 is connected to uSD0 card + * @SW_CONFIG3: + * SW_OFF - SD2 is connected to SoC + * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC + */ +#define SW_CONFIG2 SW_ON +#define SW_CONFIG3 SW_OFF / { compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; aliases { mmc0 = &sdhi0; -#if SW_SD2_EN +#if SW_CONFIG3 == SW_OFF mmc2 = &sdhi2; #endif }; @@ -50,7 +58,7 @@ vcc_sdhi0: regulator0 { enable-active-high; }; -#if SW_SD0_DEV_SEL +#if SW_CONFIG2 == SW_ON vccq_sdhi0: regulator1 { compatible = "regulator-gpio"; regulator-name = "SDHI0 VccQ"; @@ -85,7 +93,7 @@ &extal_clk { clock-frequency = <24000000>; }; -#if SW_SD0_DEV_SEL +#if SW_CONFIG2 == SW_ON /* SD0 slot */ &sdhi0 { pinctrl-0 = <&sdhi0_pins>; @@ -116,7 +124,7 @@ &sdhi0 { }; #endif -#if SW_SD2_EN +#if SW_CONFIG3 == SW_OFF &sdhi2 { pinctrl-0 = <&sdhi2_pins>; pinctrl-names = "default"; From patchwork Wed May 29 08:14:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24F2FC25B75 for ; Wed, 29 May 2024 08:15:38 +0000 (UTC) Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) by mx.groups.io with SMTP id smtpd.web11.8703.1716970530044064352 for ; Wed, 29 May 2024 01:15:30 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=aoIFuRv5; spf=pass (domain: tuxon.dev, ip: 209.85.128.52, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-420180b5898so14221425e9.2 for ; Wed, 29 May 2024 01:15:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1716970528; x=1717575328; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Jy0JzQKtDy1pYtA9NTXZluynHW5V8Nkmn5JCqCnSOxM=; b=aoIFuRv5QouB9bGuGzBxgUfWRzsf2jXlaBedTfKmLJCVIMdMNFtHf/xs/Taks9uGK+ 8pDTKKWmXXMnc0B4bQZh8piVMs8CgEWzz3OT/1cBEY0mj7XB3u8s6rQ8WK7EFMHo3m8l 9BE0i49GS7N+RV6woXIuqojKSa5UBhYk42VBxIKQ++RCpHnc6i0wD8BMas9B9IsJWjqK NbQSv+8wxey9obVAXYv1L+nhxdCT7f583DrOpPqne1FmqDJmeZAS+4rkSvDipzC1kLaG eju+QcHekMkoVaV6UPJfkThMb6rZ7+91mH2Dq/DWbdRHZbS7faHkIhfOJvdjDLEgzztC O6Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716970528; x=1717575328; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Jy0JzQKtDy1pYtA9NTXZluynHW5V8Nkmn5JCqCnSOxM=; b=qyA7NgVj8e/Ifyx57XQOYDtXvnzj4pMz+ACmUKqxJgsVEvLhM74jhnB7n0Byg79GUG zym//TvfoQC3AKI3aOJbPkJgcJXTRb570Jv4ph3HA+28N8gYZfxD1cSbvPlukC2Q5OAE kiOF7FSYNeeHe0uOUCp619EKkLrMRGQ6g8pzThVHw2ul+OVDkO30CuHbgNAvnbyCOu5l DIYczpXyP8pdjFzfOfaFH/fcCrDntZySac/f1HR4y5qQJ2RcYVkvc/iW9HEuBOseVryc vs/+rDThTojOakmCKO8bJmK/HD+IJw7+MNgVB3w8pztLKfPOA/OvWP+ht4ci+Y4lLtvw gmag== X-Gm-Message-State: AOJu0YwZHlN0zfeMdvpNR7AgwBrQlNIb5lLmc4ddY8BSwtFALj/qSgz2 nvvi4rMz1D0DLrajMLHFOryWVRlZYXwDAykn1MrZ6k6AjCYY+qkKksBhWW4be+w= X-Google-Smtp-Source: AGHT+IF2EL0cr5G1CX/r8ft6YWobHhMoDqINVyoJ08s7u/49KNmfb8UGxOT+nopTERbFsrhdlc2JdQ== X-Received: by 2002:a05:600c:3553:b0:418:29d4:1964 with SMTP id 5b1f17b1804b1-4210895dd5emr104338245e9.0.1716970528606; Wed, 29 May 2024 01:15:28 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:27 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 32/33] arm64: dts: renesas: rzg3s-smarc-som: Enable the Ethernet interfaces Date: Wed, 29 May 2024 11:14:33 +0300 Message-Id: <20240529081434.639519-33-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:38 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16060 From: Claudiu Beznea commit 932ff0c802c678bb6c7a98740eff930dad41fece upstream. The RZ/G3S Smarc Module has Ethernet PHYs (KSZ9131) connected to each Ethernet IP. For this, add proper DT descriptions to enable Ethernet communication through these PHYs. The interface b/w PHYs and MACs is RGMII. The skew settings were set to zero as based on phy-mode (rgmii-id) the KSZ9131 driver enables internal DLL, which adds a 2ns delay b/w clocks (TX/RX) and data signals. Different pin settings were applied to TXC and TX_CTL compared with the rest of the RGMII pins to comply with requirements for these pins imposed by HW manual of RZ/G3S (see chapters "Ether Ch0 Voltage Mode Control Register (ETH0_POC)", "Ether Ch1 Voltage Mode Control Register (ETH1_POC)", for power source selection, "Ether MII/RGMII Mode Control Register (ETH_MODE)" for output-enable and "Input Enable Control Register (IEN_m)" for input-enable configurations). Also enable the Ethernet interfaces by selecting SW_CONFIG3 = SW_ON. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231207070700.4156557-12-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 141 +++++++++++++++++- 1 file changed, 140 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index f59094701a4a..f062d4ad78b7 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -26,7 +26,7 @@ * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC */ #define SW_CONFIG2 SW_ON -#define SW_CONFIG3 SW_OFF +#define SW_CONFIG3 SW_ON / { compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; @@ -35,6 +35,9 @@ aliases { mmc0 = &sdhi0; #if SW_CONFIG3 == SW_OFF mmc2 = &sdhi2; +#else + eth0 = ð0; + eth1 = ð1; #endif }; @@ -89,6 +92,60 @@ vcc_sdhi2: regulator2 { }; }; +#if SW_CONFIG3 == SW_ON +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@7 { + reg = <7>; + interrupt-parent = <&pinctrl>; + interrupts = ; + rxc-skew-psec = <0>; + txc-skew-psec = <0>; + rxdv-skew-psec = <0>; + txen-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + +ð1 { + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy1: ethernet-phy@7 { + reg = <7>; + interrupt-parent = <&pinctrl>; + interrupts = ; + rxc-skew-psec = <0>; + txc-skew-psec = <0>; + rxdv-skew-psec = <0>; + txen-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; +#endif + &extal_clk { clock-frequency = <24000000>; }; @@ -136,6 +193,88 @@ &sdhi2 { #endif &pinctrl { + eth0-phy-irq-hog { + gpio-hog; + gpios = ; + input; + line-name = "eth0-phy-irq"; + }; + + eth0_pins: eth0 { + txc { + pinmux = ; /* ET0_TXC */ + power-source = <1800>; + output-enable; + input-enable; + drive-strength-microamp = <5200>; + }; + + tx_ctl { + pinmux = ; /* ET0_TX_CTL */ + power-source = <1800>; + output-enable; + drive-strength-microamp = <5200>; + }; + + mux { + pinmux = , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + , /* ET0_RXD3 */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + ; /* ET0_LINKSTA */ + power-source = <1800>; + }; + }; + + eth1-phy-irq-hog { + gpio-hog; + gpios = ; + input; + line-name = "eth1-phy-irq"; + }; + + eth1_pins: eth1 { + txc { + pinmux = ; /* ET1_TXC */ + power-source = <1800>; + output-enable; + input-enable; + drive-strength-microamp = <5200>; + }; + + tx_ctl { + pinmux = ; /* ET1_TX_CTL */ + power-source = <1800>; + output-enable; + drive-strength-microamp = <5200>; + }; + + mux { + pinmux = , /* ET1_TXD0 */ + , /* ET1_TXD1 */ + , /* ET1_TXD2 */ + , /* ET1_TXD3 */ + , /* ET1_RXC */ + , /* ET1_RX_CTL */ + , /* ET1_RXD0 */ + , /* ET1_RXD1 */ + , /* ET1_RXD2 */ + , /* ET1_RXD3 */ + , /* ET1_MDC */ + , /* ET1_MDIO */ + ; /* ET1_LINKSTA */ + power-source = <1800>; + }; + }; + sdhi0_pins: sd0 { data { pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; From patchwork Wed May 29 08:14:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13678309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40F49C25B7C for ; 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([82.78.167.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-421089711e8sm171803935e9.18.2024.05.29.01.15.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 May 2024 01:15:29 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com, paul.barker.ct@bp.renesas.com Subject: [PATCH 6.1.y-cip 33/33] arm64: dts: renesas: rzg3s-smarc-som: Guard Ethernet IRQ GPIO hogs Date: Wed, 29 May 2024 11:14:34 +0300 Message-Id: <20240529081434.639519-34-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> References: <20240529081434.639519-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Wed, 29 May 2024 08:15:38 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16061 From: Claudiu Beznea commit 150d81f7a260f36c118cbec253fdd493c671dc29 upstream. Ethernet IRQ GPIOs are marked as GPIO hogs. Thus, these GPIOs are requested at probe time without considering if there are other peripherals that need them. The Ethernet IRQ GPIOs are shared with SDHI2. Selection between Ethernet and SDHI2 is done through a hardware switch. To avoid scenarios where one wants to boot with SDHI2 support and some SDHI pins are not propertly configured because of the GPIO hogs, guard the Ethernet IRQ GPIO hogs with the proper build flag. Fixes: 932ff0c802c6 ("arm64: dts: renesas: rzg3s-smarc-som: Enable the Ethernet interfaces") Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240208124300.2740313-13-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index f062d4ad78b7..d33ab4c88787 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -193,12 +193,14 @@ &sdhi2 { #endif &pinctrl { +#if SW_CONFIG3 == SW_ON eth0-phy-irq-hog { gpio-hog; gpios = ; input; line-name = "eth0-phy-irq"; }; +#endif eth0_pins: eth0 { txc { @@ -234,12 +236,14 @@ mux { }; }; +#if SW_CONFIG3 == SW_ON eth1-phy-irq-hog { gpio-hog; gpios = ; input; line-name = "eth1-phy-irq"; }; +#endif eth1_pins: eth1 { txc {