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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id m26sm3561637lji.22.2019.02.27.09.47.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Feb 2019 09:47:42 -0800 (PST) From: Marcin Wojtas To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org Subject: [net: PATCH] net: mvpp2: disable link IRQ waiting for IDLE frames Date: Wed, 27 Feb 2019 18:47:32 +0100 Message-Id: <1551289652-7377-1-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190227_094748_409304_B72B87C3 X-CRM114-Status: GOOD ( 11.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: antoine.tenart@bootlin.com, jaz@semihalf.com, gregory.clement@bootlin.com, linux@armlinux.org.uk, nadavh@marvell.com, thomas.petazzoni@bootlin.com, tn@semihalf.com, stefanc@marvell.com, mw@semihalf.com, davem@davemloft.net MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Current version of the driver was configuring XLG MAC in a way to wait 3 IDLE frames before allowing for the link-up interrupt to be triggered. This resulted in an issue, preventing to detect the link change during RX traffic on the interface. Fix that. Fixes: 4bb043262878 ("net: mvpp2: phylink support") Signed-off-by: Marcin Wojtas --- drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c index 16066c2..f1378f9 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c @@ -4532,8 +4532,7 @@ static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC; - ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC | - MVPP22_XLG_CTRL4_EN_IDLE_CHECK; + ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC; writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG); writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG);