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[87.16.233.11]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a63570e5d0esm217427966b.214.2024.05.30.03.11.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 03:11:50 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta , Conor Dooley , Krzysztof Kozlowski Subject: [PATCH v5 1/4] dt-bindings: arm: bcm: Add BCM2712 SoC support Date: Thu, 30 May 2024 12:11:58 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240530_031154_617130_BD0DA2FF X-CRM114-Status: GOOD ( 10.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The BCM2712 SoC is found on Raspberry Pi 5. Add compatible string to acknowledge its new chipset. Signed-off-by: Andrea della Porta Reviewed-by: Stefan Wahren Acked-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml index 162a39dab218..e4ff71f006b8 100644 --- a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml @@ -23,6 +23,12 @@ properties: - raspberrypi,4-model-b - const: brcm,bcm2711 + - description: BCM2712 based Boards + items: + - enum: + - raspberrypi,5-model-b + - const: brcm,bcm2712 + - description: BCM2835 based Boards items: - enum: From patchwork Thu May 30 10:11:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea della Porta X-Patchwork-Id: 13680116 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0F38BC25B7E for ; Thu, 30 May 2024 10:12:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JVKsxmwBeJxpQNlCj9uwGQtDgjp+L22BkZsoP/SbMj0=; b=MBn80Vs2qaJZ6U K9qwCyy3B9O9TZqj9BZGvYv2muVgyURp1OMW06it8YqXAsLRLLViJeLiSpzj2qxSr6XlKuSMFlqEh wNj3m+0ZlmuVeahWyfYixFRJu0Gkm1MHE3Cv7UJaf7RJAgrMLrefup4t2Yf2vYeH/IZScy4nO5xsP umFN+WliGjTnmdEakk0zmUF1Zf84HTIrkCjE+XlEaiHoNKTZdY/hIqI0XXFKe5g6iGrZWN76zB6rx PsGg3XKTPjXTAagQYICn86XQOfX7z+2KNC762EVf0iekT0+v+RbuF27zcY4OqWa0AnDC9SCVouoA5 3rBJF2nOY0XAMtUrLHew==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sCclf-00000006wkS-1TuQ; Thu, 30 May 2024 10:12:19 +0000 Received: from mail-lf1-x130.google.com ([2a00:1450:4864:20::130]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sCclI-00000006wXw-0835 for linux-arm-kernel@lists.infradead.org; Thu, 30 May 2024 10:11:58 +0000 Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-5295e488248so685128e87.2 for ; Thu, 30 May 2024 03:11:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1717063913; x=1717668713; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r4ruLk9Ftm9+QjaAcWOvP48LMnKLjWaDjJj5/jKtjp0=; b=MRfA4N45EdMBT0CqvTS04wfAQpT1TgyYOKA9thok9Myfv4mwEcGiIn7/Q8rcLKAmyS poj5cMtfxu2H1MHxTFjfubvWI2yPmtqSKspdU3i2tgG6/9CqN3v+gsJUbpqpUSR2AMhD ASn+zL80sT84d8KIb6S4U4doOPWkB9G5zndIoZulJjY82UPjMWjJxUN9w0AcNarSVIV6 TuXXc5o+9LR/Wq2HwnU7qZJa5oRrLJoYW2v/GG37vquWaD/xwk+n74s8QLWe3a2xnL3U Gfy1fxC2Ksk1Wm8P2BT6fkJAjR+ujTs9fB8aTimeyg9/UmlO8staBoemy7Xu4d3YGXfC jDrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717063913; x=1717668713; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r4ruLk9Ftm9+QjaAcWOvP48LMnKLjWaDjJj5/jKtjp0=; b=Vv9/c93zHG37EgVX+RZ6uYedpto8x9mcO5w0MMPFmpepm4yt59Ak5+BsOoqVT+m/1j mNvRdENr4AHcYPJQPvsUyfb3Yiv6oKWpJW/jW9z6FtJqBxbFksb9Agcn0oJLICVB5Bjl QSR0U6gBEa60vhW+KjacrMtZ9140wx8aaHggUuRtY0Gt1ioSu/tK7JZTQQDEsXjrl5F5 g4jpSDqWsB/58fCvYTMCqaTJ6DQhfY/k29t3AZ6vhrZO4KYPamkLG8qcM0eCWANl+rq1 ZyX3jRPlhU4N+HH37SYauhQo5C8HgFfzMSvPVORnkrjQti+e8byDLY5N7G+2ez5W8024 yXcw== X-Forwarded-Encrypted: i=1; AJvYcCXTz5sxwDRGB9/yGHnBxiXhPu908yJcE3ZAzJ4da1dJePrtdSgR+K33Ut4Ha4wr6BP3r46n4Qi+I6njdzgTEdauyyM8AYO2TnouuL3GaZnC2y8MeCM= X-Gm-Message-State: AOJu0YzVrZ4qPLpf8iLNpagBd+IiRdIDxlLnot8pOAxoevD6QUeLctTx uq0t8mP3QGvcBoNoxMOgcUUFBXBi+c3ZUkmg8xmOWe0wqtzyO+zUGkcxru6HVVE= X-Google-Smtp-Source: AGHT+IHKELWEC1v/nerdFhSEuhPemYySFWzIWZQFDT3Ps3RHOrqqWa9HWxlgaztorNoQN9pOQkFXRQ== X-Received: by 2002:ac2:5496:0:b0:529:1dd4:3e76 with SMTP id 2adb3069b0e04-52b7d480865mr883981e87.59.1717063912908; Thu, 30 May 2024 03:11:52 -0700 (PDT) Received: from localhost (host-87-16-233-11.retail.telecomitalia.it. [87.16.233.11]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57a22aa3f8bsm530025a12.22.2024.05.30.03.11.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 03:11:52 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta , Krzysztof Kozlowski Subject: [PATCH v5 2/4] dt-bindings: mmc: Add support for BCM2712 SD host controller Date: Thu, 30 May 2024 12:11:59 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240530_031157_051904_95CF8562 X-CRM114-Status: GOOD ( 10.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The BCM2712 has an SDHCI capable host interface similar to the one found in other STB chipsets. Add the relevant compatible string. Signed-off-by: Andrea della Porta Reviewed-by: Stefan Wahren Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml index cbd3d6c6c77f..eee6be7a7867 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml @@ -20,6 +20,7 @@ properties: - const: brcm,sdhci-brcmstb - items: - enum: + - brcm,bcm2712-sdhci - brcm,bcm74165b0-sdhci - brcm,bcm7445-sdhci - brcm,bcm7425-sdhci From patchwork Thu May 30 10:12:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea della Porta X-Patchwork-Id: 13680115 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81C8BC25B74 for ; Thu, 30 May 2024 10:12:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hItyBJ7chFR0PRQGSJCP9S6jS2f9PpLjy1MuCXadNhE=; b=AQYqMDxb2DoDrl a/pxQWApEiygU3OEzX6O5mt3oLqVfuFqk1j2hDKsxLOp4gWp3n3ZpHTUz3Vcf44+ZKFQkU5fjqCau BkA+j3zA2uaqzBlsx6b1WHv4QehM7ZIuBv3exFPjLrCy8LeCTM2/2uaZcnSf3iFLKmZkklYl58JmS vRotVJnU6oFAZ+30BvO0Yl3Qt9wOe2BK+w2jVVRXREAUPv/+wwLC9PHENfwUDDnr88Jpf6XxrQLmH KpT28giqgxShamVcV3jNVVg6mZz5zcAB3PG1T6LSHZiRe5H5DJ+LQT9Yh5ofcnoPm2hO/piWaTqIw AK7eTii0+cMtaCcJwD/Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sCclg-00000006wlc-2MZW; Thu, 30 May 2024 10:12:20 +0000 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sCclJ-00000006wYe-1PAp for linux-arm-kernel@lists.infradead.org; Thu, 30 May 2024 10:12:00 +0000 Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-57a1fe6392eso501942a12.0 for ; Thu, 30 May 2024 03:11:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1717063914; x=1717668714; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dcRXedB2L/K4Z2DKMFe1HwvDzR0/ipx5LpIH3TLEmVs=; b=KujqazpShK2VXmuU0hpQUKntn8CcaoR7HtnRX16UqfDAijNYUZWo7NxVWAF4a5er4i l9SQrPX+3bsgFsHLpsxknwWWKnBIgtOG8rzS9HstSnS04aCb4jAZaCr25skWStf2jX5W gie/ZAu1dn8jeYV4KE0HChfVUZ9Xlxi8dIqEeLUB3jvor2cNyRAetxK62Av3aPil4Sq9 cGhEmYFgbfbR5xYmdWXtvIRcdePxrKMVZ2I7qSfnVD1lB5OIDkv/zyB9SQ83B8Msyl4g 1m0TxE1UM1ll4kIzr9uUUrCfy8SZlDvBYIAIr4ldVv3PO74O+avF+WV27nWzGEe5OK1W IG/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717063914; x=1717668714; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dcRXedB2L/K4Z2DKMFe1HwvDzR0/ipx5LpIH3TLEmVs=; b=cuGt/+hVqiRJb6IEplV1buqO4Ez7DZD0i9TlDoSwVI4YdSvraDLSCZzEFUd4Qxmcru jiOsgKZMAyMBX1cMDdeQ+WWqOZOHKoFhyDdNINDo44+qpCpAqR22wKdcXtMIXdMdPpIN qCTdc8L4ZYOQESazlVWIR3EIGDbT/BJGgMmRb9XDHOx4VSwLLfNyacpVVcvTYVZZ9ryU P7YR+d+ez5T1Ec8M8zS/ju6Jugo/PNT2Gqw/NXzfdrBvQ18LJ33L5FNFMGn0WxFImESc JbEaIQRrD90hcW6UkxD6+xkYyKFJMhwsizAT12j4IPFMnTyzvBnc+qd2P7Bcur0S7604 Wa1g== X-Forwarded-Encrypted: i=1; AJvYcCWYWvuRpO6d7D3InuoRtLOJhEkRvRvOvq5v0VQvo193A73nTqA0TNRb+ntgds0QOuoZtW/HjI9+Hmke9JuIfjghVXLkG7WTPYbpfiivwbjIGR05elE= X-Gm-Message-State: AOJu0YyoFK8geIoiTqf5CTGue7oXacqrNdFZppk7/TYvCpoaXWqceRsg 7CxYI7kybkJedR7nvjIdehSVzyFqiqK4Wa+uPmjRudNWzKrjJ8W/ZQRicBOCX0s= X-Google-Smtp-Source: AGHT+IEWYcNoqLpEebhmlHEI02E4bUTWw3UCMc2lMorAyO49bD2UFIdo4HXmbVIbm2kIcWz8uAGOeA== X-Received: by 2002:a50:d69b:0:b0:57a:2ae5:70e7 with SMTP id 4fb4d7f45d1cf-57a2ae57134mr31613a12.7.1717063914160; Thu, 30 May 2024 03:11:54 -0700 (PDT) Received: from localhost (host-87-16-233-11.retail.telecomitalia.it. [87.16.233.11]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-579c2026406sm6815197a12.37.2024.05.30.03.11.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 03:11:53 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta Subject: [PATCH v5 3/4] mmc: sdhci-brcmstb: Add BCM2712 support Date: Thu, 30 May 2024 12:12:00 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240530_031157_633093_6F24C075 X-CRM114-Status: GOOD ( 20.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Broadcom BCM2712 SoC has an SDHCI card controller using the SDIO CFG register block present on other STB chips. Add support for BCM2712 SD capabilities of this chipset. The silicon is SD Express capable but this driver port does not currently include that feature yet. Based on downstream driver by raspberry foundation maintained kernel. Signed-off-by: Andrea della Porta Reviewed-by: Stefan Wahren Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-brcmstb.c | 60 ++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index 9053526fa212..db1c7f5cd5fd 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -30,6 +30,21 @@ #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 +#define SDIO_CFG_CQ_CAPABILITY 0x4c +#define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) + +#define SDIO_CFG_CTRL 0x0 +#define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31) +#define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30) + +#define SDIO_CFG_MAX_50MHZ_MODE 0x1ac +#define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31) +#define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0) + +#define MMC_CAP_HSE_MASK (MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V) +/* Select all SD UHS type I SDR speed above 50MB/s */ +#define MMC_CAP_UHS_I_SDR_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104) + struct sdhci_brcmstb_priv { void __iomem *cfg_regs; unsigned int flags; @@ -38,6 +53,7 @@ struct sdhci_brcmstb_priv { }; struct brcmstb_match_priv { + void (*cfginit)(struct sdhci_host *host); void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); struct sdhci_ops *ops; const unsigned int flags; @@ -168,6 +184,33 @@ static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); } +static void sdhci_brcmstb_cfginit_2712(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host); + u32 reg; + + /* + * If we support a speed that requires tuning, + * then select the delay line PHY as the clock source. + */ + if ((host->mmc->caps & MMC_CAP_UHS_I_SDR_MASK) || (host->mmc->caps2 & MMC_CAP_HSE_MASK)) { + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); + reg &= ~SDIO_CFG_MAX_50MHZ_MODE_ENABLE; + reg |= SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE; + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); + } + + if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || + (host->mmc->caps & MMC_CAP_NEEDS_POLL)) { + /* Force presence */ + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); + reg &= ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV; + reg |= SDIO_CFG_CTRL_SDCD_N_TEST_EN; + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); + } +} + static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) { sdhci_dumpregs(mmc_priv(mmc)); @@ -200,6 +243,14 @@ static struct sdhci_ops sdhci_brcmstb_ops = { .set_uhs_signaling = sdhci_set_uhs_signaling, }; +static struct sdhci_ops sdhci_brcmstb_ops_2712 = { + .set_clock = sdhci_set_clock, + .set_power = sdhci_set_power_and_bus_voltage, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, +}; + static struct sdhci_ops sdhci_brcmstb_ops_7216 = { .set_clock = sdhci_brcmstb_set_clock, .set_bus_width = sdhci_set_bus_width, @@ -214,6 +265,11 @@ static struct sdhci_ops sdhci_brcmstb_ops_74165b0 = { .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling, }; +static const struct brcmstb_match_priv match_priv_2712 = { + .cfginit = sdhci_brcmstb_cfginit_2712, + .ops = &sdhci_brcmstb_ops_2712, +}; + static struct brcmstb_match_priv match_priv_7425 = { .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT | BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, @@ -238,6 +294,7 @@ static struct brcmstb_match_priv match_priv_74165b0 = { }; static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = { + { .compatible = "brcm,bcm2712-sdhci", .data = &match_priv_2712 }, { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 }, @@ -370,6 +427,9 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) (host->mmc->caps2 & MMC_CAP2_HS400_ES)) host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es; + if (match_priv->cfginit) + match_priv->cfginit(host); + /* * Supply the existing CAPS, but clear the UHS modes. This * will allow these modes to be specified by device tree From patchwork Thu May 30 10:12:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea della Porta X-Patchwork-Id: 13680117 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3048EC25B74 for ; Thu, 30 May 2024 10:12:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NP8SsVMopi5LllBOmNsF6+qcI48ieTG0+2r6WcIrMOo=; b=pNL84Z6n1j0Wro BSw1AY6TK/dydB1MuEmFbgymnkjZzOnxi1efrFD7axCiaJMZYHK/V+CgeMn5ojvlr88w1zFYgrPo9 ny0cxXh8t/Elszn5O8FmT7Gadj6YNUA65KyuNH68e2/p9XcKUXds0WXw0FOPDgBcAT6wph/Z0QVVp g3Bw2XpfIn11zc7jiAJ7ZddlPVSIDxz0K74X/FJaNpuxL+K1a6kcUh5qqDYsJbW5+1hEI7MKVe+5q FoZo8FUHmeRa38ndHxrS6Y0LGIxF20mgxol+TsDkwNiok/rhAZLFHYxqkSPbi9CA/MW1qxAFe5ffQ UX3vRLocmfOyDNeXq0MA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sCclw-00000006wum-2ftz; Thu, 30 May 2024 10:12:36 +0000 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sCclK-00000006wZ8-2F9Q for linux-arm-kernel@lists.infradead.org; Thu, 30 May 2024 10:12:01 +0000 Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-a6303e13ffeso60710566b.3 for ; Thu, 30 May 2024 03:11:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1717063916; x=1717668716; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MTw3IRZEjtj9X2tzd7G8IPucKzFK90zRS9yH1RupvFc=; b=RQLsgbcvHcbGt5oL4quFlbq6Ws2/VAENeGOWCK8sgiPFOoDd1d4pgZPccGz/MgIbpc /8271T7WYDaUREyJK0ct8W3hmhqRU4nt9zkdvN2yN7724wZJnEKewYycYO2IbIOFwqD1 ronzVo45V9v1AER0R61ks4UbEOJtJ9lggydy+wdpvRk3yTCWlqBH3iFjcScUWqfE9YJk uQOKpw8eOoRoFxOkv4AeTg5qvDDDjWwP/STICqYz07BKQl42ev7hKIdiVbqd4Z/I5x9C FN7lcqR2oe3o5YOSL+z9aQ1Xn4C/9DkdlLN1Jg/SMhV6uUnv9D+pNtQv5HUmYUOLelti tjVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717063916; x=1717668716; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MTw3IRZEjtj9X2tzd7G8IPucKzFK90zRS9yH1RupvFc=; b=XZVU8/MR4wr02t3VvSBN0ESEZdnSnueI33s5qjfAkgMlbaxJDIxllvzewBk3sPUvjt +MZJrJATS+RqfF6o2m8Cqyrp0bQe50vBaei7697AKdfK/nvLUx08nxSSKIAW4jhjQ1cO 40x39+or/59o4YhvHAD34+vU5oo9jKR6FTXSc3iB/p4B8ZczARiWm+MwFJ4KKKDNTYTS v2S9hru51mxAeYnOPpgqnG/RL7KMyT+oBNATUmkOxnOHIefkhA98VTcn6UzL9aMud15F xYfHQ1O0kFaMJD+MM/QTzc4wbRHZfZ+yXvT7LZZaB3SRdQ+5GGQlJ+S54+ci6rk+Ponv r31A== X-Forwarded-Encrypted: i=1; AJvYcCWg85rkbOKav1deVAEIaBXbQNE1XfYy0FcTjF85n6mnvTTFIlIKmmj8tr0NHwXttZSRBdG3OY+hZWh3EwZxgyn+WqC3hVYguvKX1nIFTx9/VKu7L68= X-Gm-Message-State: AOJu0Yx4jW0CIiPP4UMrUy69728IRedTCkOuqKE79+AiQDLIPqhyfu1D Jk48JwJ95WeS+BtbueWHLUXProzTe91ps4Jo5Cj3rGVIfPJXCsUP/zFzK6+e1/A= X-Google-Smtp-Source: AGHT+IGfd02sPfoD2nHto0/+98rMdUOtDd+kXq4ityc75IOcyDbJ04Gttkzd5fJAys86Uj9NOEIipA== X-Received: by 2002:a17:906:32cf:b0:a59:cff:2cfa with SMTP id a640c23a62f3a-a65e923ef00mr110889666b.67.1717063915791; Thu, 30 May 2024 03:11:55 -0700 (PDT) Received: from localhost (host-87-16-233-11.retail.telecomitalia.it. [87.16.233.11]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a626cda4151sm801020466b.197.2024.05.30.03.11.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 03:11:55 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta Subject: [PATCH v5 4/4] arm64: dts: broadcom: Add minimal support for Raspberry Pi 5 Date: Thu, 30 May 2024 12:12:01 +0200 Message-ID: <874589f6c621036620cca944986e5be7238b4784.1717061147.git.andrea.porta@suse.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240530_031158_646479_548ED641 X-CRM114-Status: GOOD ( 21.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The BCM2712 SoC family can be found on Raspberry Pi 5. Add minimal SoC and board (Rpi5 specific) dts file to be able to boot from SD card and use console on debug UART. Signed-off-by: Andrea della Porta Reviewed-by: Stefan Wahren --- arch/arm64/boot/dts/broadcom/Makefile | 1 + .../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 64 ++++ arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 283 ++++++++++++++++++ 3 files changed, 348 insertions(+) create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712.dtsi diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index 8b4591ddd27c..92565e9781ad 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -6,6 +6,7 @@ DTC_FLAGS := -@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \ bcm2711-rpi-4-b.dtb \ bcm2711-rpi-cm4-io.dtb \ + bcm2712-rpi-5-b.dtb \ bcm2837-rpi-3-a-plus.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts new file mode 100644 index 000000000000..2bdbb6780242 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/dts-v1/; + +#include +#include "bcm2712.dtsi" + +/ { + compatible = "raspberrypi,5-model-b", "brcm,bcm2712"; + model = "Raspberry Pi 5"; + + aliases { + serial10 = &uart10; + }; + + chosen: chosen { + stdout-path = "serial10:115200n8"; + }; + + /* Will be filled by the bootloader */ + memory@0 { + device_type = "memory"; + reg = <0 0 0 0x28000000>; + }; + + sd_io_1v8_reg: sd-io-1v8-reg { + compatible = "regulator-gpio"; + regulator-name = "vdd-sd-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-settling-time-us = <5000>; + gpios = <&gio_aon 3 GPIO_ACTIVE_HIGH>; + states = <1800000 1>, + <3300000 0>; + }; + + sd_vcc_reg: sd-vcc-reg { + compatible = "regulator-fixed"; + regulator-name = "vcc-sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>; + }; +}; + +/* The Debug UART, on Rpi5 it's on JST-SH 1.0mm 3-pin connector + * labeled "UART", i.e. the interface with the system console. + */ +&uart10 { + status = "okay"; +}; + +/* SDIO1 is used to drive the SD card */ +&sdio1 { + vqmmc-supply = <&sd_io_1v8_reg>; + vmmc-supply = <&sd_vcc_reg>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi new file mode 100644 index 000000000000..bccb7318ce7e --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +#include + +/ { + compatible = "brcm,bcm2712"; + + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gicv2>; + + clocks { + /* The oscillator is the root of the clock tree. */ + clk_osc: clk-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "osc"; + clock-frequency = <54000000>; + }; + + clk_vpu: clk-vpu { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <750000000>; + clock-output-names = "vpu-clock"; + }; + + clk_uart: clk-uart { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <9216000>; + clock-output-names = "uart-clock"; + }; + + clk_emmc2: clk-emmc2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "emmc2-clock"; + }; + }; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + + /* Source for L1 d/i cache-line-size, cache-sets, cache-size + * https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en + * Source for L2 cache-line-size and cache-sets: + * https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en + * and for cache-size: + * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 + */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x000>; + enable-method = "psci"; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + next-level-cache = <&l2_cache_l0>; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <128>; + cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x100>; + enable-method = "psci"; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + next-level-cache = <&l2_cache_l1>; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <128>; + cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x200>; + enable-method = "psci"; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + next-level-cache = <&l2_cache_l2>; + + l2_cache_l2: l2-cache-l2 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <128>; + cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x300>; + enable-method = "psci"; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set + next-level-cache = <&l2_cache_l3>; + + l2_cache_l3: l2-cache-l3 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <128>; + cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + }; + + /* Source for cache-line-size and cache-sets: + * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en + * Source for cache-size: + * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 + */ + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set + cache-level = <3>; + cache-unified; + }; + }; + + psci { + method = "smc"; + compatible = "arm,psci-1.0", "arm,psci-0.2"; + }; + + rmem: reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + atf@0 { + reg = <0x0 0x0 0x0 0x80000>; + no-map; + }; + + cma: linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x4000000>; /* 64MB */ + reusable; + linux,cma-default; + alloc-ranges = <0x0 0x00000000 0x0 0x40000000>; + }; + }; + + soc: soc@107c000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0x10 0x00000000 0x80000000>; + #address-cells = <1>; + #size-cells = <1>; + + sdio1: mmc@fff000 { + compatible = "brcm,bcm2712-sdhci", + "brcm,sdhci-brcmstb"; + reg = <0x00fff000 0x260>, + <0x00fff400 0x200>; + reg-names = "host", "cfg"; + interrupts = ; + clocks = <&clk_emmc2>; + clock-names = "sw_sdio"; + mmc-ddr-3_3v; + }; + + system_timer: timer@7c003000 { + compatible = "brcm,bcm2835-system-timer"; + reg = <0x7c003000 0x1000>; + interrupts = , + , + , + ; + clock-frequency = <1000000>; + }; + + mailbox: mailbox@7c013880 { + compatible = "brcm,bcm2835-mbox"; + reg = <0x7c013880 0x40>; + interrupts = ; + #mbox-cells = <0>; + }; + + local_intc: local-intc@7cd00000 { + compatible = "brcm,bcm2836-l1-intc"; + reg = <0x7cd00000 0x100>; + }; + + uart10: serial@7d001000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x7d001000 0x200>; + interrupts = ; + clocks = <&clk_uart>, <&clk_vpu>; + clock-names = "uartclk", "apb_pclk"; + arm,primecell-periphid = <0x00241011>; + status = "disabled"; + }; + + interrupt-controller@7d517000 { + compatible = "brcm,bcm7271-l2-intc"; + reg = <0x7d517000 0x10>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gio_aon: gpio@7d517c00 { + compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + reg = <0x7d517c00 0x40>; + gpio-controller; + #gpio-cells = <2>; + brcm,gpio-bank-widths = <17 6>; + /* The lack of 'interrupt-controller' property here is intended: + * don't use GIO_AON as an interrupt controller because it will + * clash with the firmware monitoring the PMIC interrupt via the VPU. + */ + }; + + gicv2: interrupt-controller@7fff9000 { + compatible = "arm,gic-400"; + reg = <0x7fff9000 0x1000>, + <0x7fffa000 0x2000>, + <0x7fffc000 0x2000>, + <0x7fffe000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + }; +};