From patchwork Fri May 31 23:05:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 13682257 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD106824BD; Fri, 31 May 2024 23:06:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717196765; cv=none; b=YzFijysqpXhlecwPWHZ/Yv7JGbXE6n68jJK7HxIJlwYcAKZQEudRxHxONN2fFC7qxTlmNW4MWcGd++tmtvmU3Qd8QTFSMIQHs1VM91l7e/ltFp3I9U64wmBj/Wfdp6xL8Mgo3FcSP7E7GjiCu0ffOGxVJDEGQb0lTDE75glZQ9I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717196765; c=relaxed/simple; bh=O35Z+GxicxEFnCVSzyl7cYoaf/7XaXGGKvt/g+NqZLw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=gdkCyXv93raYLwCjZhWbXC7HfmUxfLirJMpRPovVzfDkz5e51RrEJfXTtKh1sSlIDC2e4Pi22tKfFLbi3mCn4jxVrBfwgWdOZTR7T8rXwI0hh88U3/EJguc6eDQvkMVLywrj9zvNnXFnTati28hIcXaBAc7UZ1Sf/EjVySVXXnk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=roeck-us.net; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=BddmrbTd; arc=none smtp.client-ip=209.85.210.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=roeck-us.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BddmrbTd" Received: by mail-pf1-f172.google.com with SMTP id d2e1a72fcca58-70109d34a16so2400900b3a.2; Fri, 31 May 2024 16:06:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1717196763; x=1717801563; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:from:to:cc:subject:date :message-id:reply-to; bh=o/1/w+2qvpM05PxKueeUmEk2b81CeESoYWlX6Sv0NZ8=; b=BddmrbTd97+TeKlCESgP6FoJ839XPf/w5BY+vwW/EYNLj+B2HfNcuoFAu4yB0cmUrN RLCJ6buvcLKUVPs9+I0yBOQMYrseliGQLspDvPOPIFOBBzGIlPvMzrnkb46Z+tZZhRKt V7w4I3LUjk9BnIqvd7s5Ej0x0GwDhAZwZ8RMr1lqnzZ1ZYI4spJc16HYq1DWeDXTiV1L Ecs1UEYNy6WOUEswDD/Rvcj9/+5YLWQHiPBsUP99K5UP1ZEs+3V5xhrEi5g1LPLQZ6do PipYN2709cA73OtAo4vSoNxI5X+0w9cZzmqgs8tbfiu99YFe8x5V/L3odyjL55mE6y4n GOYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717196763; x=1717801563; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:sender:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=o/1/w+2qvpM05PxKueeUmEk2b81CeESoYWlX6Sv0NZ8=; b=YcSuaQO7BoAFfEjnybwgA2p7gTsHDKl6b3UXWbw3HOyk/avCL6xyC5H+bBrbweK62b 8EVKuyD6jAtj+qkaObxvx/ke8fVQN/5OBE7JnKr0Xb7cyTWk3mw4fhZxUcgoRn/+o8en BFB/whrm7WlvNnMVu8HX0uoRPRDd7uW/je2xoinFyPLtfrxwVbD3WrnV+H0h5p9MLVHh nNBGDYGa3y9J1/GDS4MY4TeRM87hxJxxTjHOa456Q8MAZp5h/Oq1QlEvrltkKnqro5wV tOzsK9wafbpInxTvIP+wljWbvfxw8ppnlOIYa2gELvijm7rA9HjQox/VgZuKEhJ+hD9+ 2RQw== X-Forwarded-Encrypted: i=1; AJvYcCXZSKWbNIK9k4wPwowLS4be2H6PrJ4f3vODjoj70W+P0AkU8h0jraAZYWDRdTQoQWVVGNUoTkzODKry5WpOYu5IRWi7PzU5fqE2kJAN X-Gm-Message-State: AOJu0YwrtgfcHWbK5p1zi5kazf3s90wlcnDWzBi00TIom+RY3XOK4Imh c3KAnjhnKcxyt91EzideSXw/nqGsL2IAjQSaMFnvEa5f9bfRM/fr7SjkGw== X-Google-Smtp-Source: AGHT+IGmPkGewLx6fr/GPQQDemgJ9DbOHn0kMGdSyhINfj77xWhPsbH6v8h6A1CCP4gKxT87R1B63g== X-Received: by 2002:a05:6a20:7284:b0:1b2:1de2:7dfa with SMTP id adf61e73a8af0-1b26f1b5be1mr3894641637.22.1717196762565; Fri, 31 May 2024 16:06:02 -0700 (PDT) Received: from server.roeck-us.net ([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-702423da731sm1871863b3a.61.2024.05.31.16.06.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 May 2024 16:06:02 -0700 (PDT) Sender: Guenter Roeck From: Guenter Roeck To: linux-hwmon@vger.kernel.org Cc: devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org, Armin Wolf , =?utf-8?q?Thomas?= =?utf-8?q?_Wei=C3=9Fschuh?= , =?utf-8?q?Ren=C3=A9_Reb?= =?utf-8?q?e?= , Wolfram Sang , Guenter Roeck Subject: [PATCH v3 1/4] dt-bindings: trivial-devices: Add jedec,spd5118 Date: Fri, 31 May 2024 16:05:53 -0700 Message-Id: <20240531230556.1409532-2-linux@roeck-us.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240531230556.1409532-1-linux@roeck-us.net> References: <20240531230556.1409532-1-linux@roeck-us.net> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add bindings for the SPD hub present in DDR5 modules. (https://www.jedec.org/standards-documents/docs/jesd300-5b01). Signed-off-by: Guenter Roeck Acked-by: Krzysztof Kozlowski --- v3: Drop explicit bindings file; add binding to trivial devices instead Documentation/devicetree/bindings/trivial-devices.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 0a419453d183..1d19e67de2a1 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -168,6 +168,8 @@ properties: - isil,isl69269 # Intersil ISL76682 Ambient Light Sensor - isil,isl76682 + # JEDEC JESD300 (SPD5118) Hub and Serial Presence Detect + - jedec,spd5118 # Linear Technology LTC2488 - lineartechnology,ltc2488 # 5 Bit Programmable, Pulse-Width Modulator From patchwork Fri May 31 23:05:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 13682258 Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0246312F5B1; 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Fri, 31 May 2024 16:06:04 -0700 (PDT) Received: from server.roeck-us.net ([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-702425d8a5fsm1876557b3a.76.2024.05.31.16.06.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 May 2024 16:06:03 -0700 (PDT) Sender: Guenter Roeck From: Guenter Roeck To: linux-hwmon@vger.kernel.org Cc: devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org, Armin Wolf , =?utf-8?q?Thomas?= =?utf-8?q?_Wei=C3=9Fschuh?= , =?utf-8?q?Ren=C3=A9_Reb?= =?utf-8?q?e?= , Wolfram Sang , Guenter Roeck Subject: [PATCH v3 2/4] hwmon: Add support for SPD5118 compliant temperature sensors Date: Fri, 31 May 2024 16:05:54 -0700 Message-Id: <20240531230556.1409532-3-linux@roeck-us.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240531230556.1409532-1-linux@roeck-us.net> References: <20240531230556.1409532-1-linux@roeck-us.net> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for SPD5118 (Jedec JESD300) compliant temperature sensors. Such sensors are typically found on DDR5 memory modules. Cc: René Rebe Cc: Thomas Weißschuh Reviewed-by: Thomas Weißschuh Tested-by: Thomas Weißschuh Signed-off-by: Guenter Roeck Tested-by: Armin Wolf Reviewed-by: Armin Wolf --- v3: Shorten JESD300-5B.01 to JESD300; 5B.01 refers to the version of the standard Drop unnecessary 'attr' parameter from spd5118_{read,write}_enable() v2: Drop PEC property documentation Add note indicating that alarm attributes are sticky until read to documentation Fix detect function Fix misspelling in Makefile (CONFIG_SENSORS_SPD5118->CONFIG_SENSORS_SPD5118) Documentation/hwmon/index.rst | 1 + Documentation/hwmon/spd5118.rst | 55 ++++ drivers/hwmon/Kconfig | 12 + drivers/hwmon/Makefile | 1 + drivers/hwmon/spd5118.c | 481 ++++++++++++++++++++++++++++++++ 5 files changed, 550 insertions(+) create mode 100644 Documentation/hwmon/spd5118.rst create mode 100644 drivers/hwmon/spd5118.c diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst index 03d313af469a..6e7b8726b60c 100644 --- a/Documentation/hwmon/index.rst +++ b/Documentation/hwmon/index.rst @@ -215,6 +215,7 @@ Hardware Monitoring Kernel Drivers smsc47m192 smsc47m1 sparx5-temp + spd5118 stpddc60 surface_fan sy7636a-hwmon diff --git a/Documentation/hwmon/spd5118.rst b/Documentation/hwmon/spd5118.rst new file mode 100644 index 000000000000..a15d75aa2066 --- /dev/null +++ b/Documentation/hwmon/spd5118.rst @@ -0,0 +1,55 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Kernel driver spd5118 +===================== + +Supported chips: + + * SPD5118 (JEDEC JESD300) compliant temperature sensor chips + + JEDEC standard download: + https://www.jedec.org/standards-documents/docs/jesd300-5b01 + (account required) + + + Prefix: 'spd5118' + + Addresses scanned: I2C 0x50 - 0x57 + +Author: + Guenter Roeck + + +Description +----------- + +This driver implements support for SPD5118 (JEDEC JESD300) compliant temperature +sensors, which are used on many DDR5 memory modules. Some systems use the sensor +to prevent memory overheating by automatically throttling the memory controller. + +The driver auto-detects SPD5118 compliant chips, but can also be instantiated +using devicetree/firmware nodes. + +A SPD5118 compliant chip supports a single temperature sensor. Critical minimum, +minimum, maximum, and critical temperature can be configured. There are alarms +for low critical, low, high, and critical thresholds. + + +Hardware monitoring sysfs entries +--------------------------------- + +======================= ================================== +temp1_input Temperature (RO) +temp1_lcrit Low critical high temperature (RW) +temp1_min Minimum temperature (RW) +temp1_max Maximum temperature (RW) +temp1_crit Critical high temperature (RW) + +temp1_lcrit_alarm Temperature low critical alarm +temp1_min_alarm Temperature low alarm +temp1_max_alarm Temperature high alarm +temp1_crit_alarm Temperature critical alarm +======================= ================================== + +Alarm attributes are sticky until read and will be cleared afterwards +unless the alarm condition still applies. diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index e14ae18a973b..d0fb5fe1b2ac 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -2181,6 +2181,18 @@ config SENSORS_INA3221 This driver can also be built as a module. If so, the module will be called ina3221. +config SENSORS_SPD5118 + tristate "SPD5118 Compliant Temperature Sensors" + depends on I2C + select REGMAP_I2C + help + If you say yes here you get support for SPD5118 (JEDEC JESD300) + compliant temperature sensors. Such sensors are found on DDR5 memory + modules. + + This driver can also be built as a module. If so, the module + will be called spd5118. + config SENSORS_TC74 tristate "Microchip TC74" depends on I2C diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index e3f25475d1f0..6574ca67d761 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -207,6 +207,7 @@ obj-$(CONFIG_SENSORS_SMSC47B397)+= smsc47b397.o obj-$(CONFIG_SENSORS_SMSC47M1) += smsc47m1.o obj-$(CONFIG_SENSORS_SMSC47M192)+= smsc47m192.o obj-$(CONFIG_SENSORS_SPARX5) += sparx5-temp.o +obj-$(CONFIG_SENSORS_SPD5118) += spd5118.o obj-$(CONFIG_SENSORS_STTS751) += stts751.o obj-$(CONFIG_SENSORS_SURFACE_FAN)+= surface_fan.o obj-$(CONFIG_SENSORS_SY7636A) += sy7636a-hwmon.o diff --git a/drivers/hwmon/spd5118.c b/drivers/hwmon/spd5118.c new file mode 100644 index 000000000000..d3fc0ae17743 --- /dev/null +++ b/drivers/hwmon/spd5118.c @@ -0,0 +1,481 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Driver for Jedec 5118 compliant temperature sensors + * + * Derived from https://github.com/Steve-Tech/SPD5118-DKMS + * Originally from T/2 driver at https://t2sde.org/packages/linux + * Copyright (c) 2023 René Rebe, ExactCODE GmbH; Germany. + * + * Copyright (c) 2024 Guenter Roeck + * + * Inspired by ee1004.c and jc42.c. + * + * SPD5118 compliant temperature sensors are typically used on DDR5 + * memory modules. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Addresses to scan */ +static const unsigned short normal_i2c[] = { + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, I2C_CLIENT_END }; + +/* SPD5118 registers. */ +#define SPD5118_REG_TYPE 0x00 /* MR0:MR1 */ +#define SPD5118_REG_REVISION 0x02 /* MR2 */ +#define SPD5118_REG_VENDOR 0x03 /* MR3:MR4 */ +#define SPD5118_REG_CAPABILITY 0x05 /* MR5 */ +#define SPD5118_REG_I2C_LEGACY_MODE 0x0B /* MR11 */ +#define SPD5118_REG_TEMP_CLR 0x13 /* MR19 */ +#define SPD5118_REG_ERROR_CLR 0x14 /* MR20 */ +#define SPD5118_REG_TEMP_CONFIG 0x1A /* MR26 */ +#define SPD5118_REG_TEMP_MAX 0x1c /* MR28:MR29 */ +#define SPD5118_REG_TEMP_MIN 0x1e /* MR30:MR31 */ +#define SPD5118_REG_TEMP_CRIT 0x20 /* MR32:MR33 */ +#define SPD5118_REG_TEMP_LCRIT 0x22 /* MR34:MR35 */ +#define SPD5118_REG_TEMP 0x31 /* MR49:MR50 */ +#define SPD5118_REG_TEMP_STATUS 0x33 /* MR51 */ + +#define SPD5118_TEMP_STATUS_HIGH BIT(0) +#define SPD5118_TEMP_STATUS_LOW BIT(1) +#define SPD5118_TEMP_STATUS_CRIT BIT(2) +#define SPD5118_TEMP_STATUS_LCRIT BIT(3) + +#define SPD5118_CAP_TS_SUPPORT BIT(1) /* temperature sensor support */ + +#define SPD5118_TS_DISABLE BIT(0) /* temperature sensor disable */ + +/* Temperature unit in millicelsius */ +#define SPD5118_TEMP_UNIT (MILLIDEGREE_PER_DEGREE / 4) +/* Representable temperature range in millicelsius */ +#define SPD5118_TEMP_RANGE_MIN -256000 +#define SPD5118_TEMP_RANGE_MAX 255750 + +static int spd5118_temp_from_reg(u16 reg) +{ + int temp = sign_extend32(reg >> 2, 10); + + return temp * SPD5118_TEMP_UNIT; +} + +static u16 spd5118_temp_to_reg(long temp) +{ + temp = clamp_val(temp, SPD5118_TEMP_RANGE_MIN, SPD5118_TEMP_RANGE_MAX); + return (DIV_ROUND_CLOSEST(temp, SPD5118_TEMP_UNIT) & 0x7ff) << 2; +} + +static int spd5118_read_temp(struct regmap *regmap, u32 attr, long *val) +{ + int reg, err; + u8 regval[2]; + u16 temp; + + switch (attr) { + case hwmon_temp_input: + reg = SPD5118_REG_TEMP; + break; + case hwmon_temp_max: + reg = SPD5118_REG_TEMP_MAX; + break; + case hwmon_temp_min: + reg = SPD5118_REG_TEMP_MIN; + break; + case hwmon_temp_crit: + reg = SPD5118_REG_TEMP_CRIT; + break; + case hwmon_temp_lcrit: + reg = SPD5118_REG_TEMP_LCRIT; + break; + default: + return -EOPNOTSUPP; + } + + err = regmap_bulk_read(regmap, reg, regval, 2); + if (err) + return err; + + temp = (regval[1] << 8) | regval[0]; + + *val = spd5118_temp_from_reg(temp); + return 0; +} + +static int spd5118_read_alarm(struct regmap *regmap, u32 attr, long *val) +{ + unsigned int mask, regval; + int err; + + switch (attr) { + case hwmon_temp_max_alarm: + mask = SPD5118_TEMP_STATUS_HIGH; + break; + case hwmon_temp_min_alarm: + mask = SPD5118_TEMP_STATUS_LOW; + break; + case hwmon_temp_crit_alarm: + mask = SPD5118_TEMP_STATUS_CRIT; + break; + case hwmon_temp_lcrit_alarm: + mask = SPD5118_TEMP_STATUS_LCRIT; + break; + default: + return -EOPNOTSUPP; + } + + err = regmap_read(regmap, SPD5118_REG_TEMP_STATUS, ®val); + if (err < 0) + return err; + *val = !!(regval & mask); + if (*val) + return regmap_write(regmap, SPD5118_REG_TEMP_CLR, mask); + return 0; +} + +static int spd5118_read_enable(struct regmap *regmap, long *val) +{ + u32 regval; + int err; + + err = regmap_read(regmap, SPD5118_REG_TEMP_CONFIG, ®val); + if (err < 0) + return err; + *val = !(regval & SPD5118_TS_DISABLE); + return 0; +} + +static int spd5118_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct regmap *regmap = dev_get_drvdata(dev); + + if (type != hwmon_temp) + return -EOPNOTSUPP; + + switch (attr) { + case hwmon_temp_input: + case hwmon_temp_max: + case hwmon_temp_min: + case hwmon_temp_crit: + case hwmon_temp_lcrit: + return spd5118_read_temp(regmap, attr, val); + case hwmon_temp_max_alarm: + case hwmon_temp_min_alarm: + case hwmon_temp_crit_alarm: + case hwmon_temp_lcrit_alarm: + return spd5118_read_alarm(regmap, attr, val); + case hwmon_temp_enable: + return spd5118_read_enable(regmap, val); + default: + return -EOPNOTSUPP; + } +} + +static int spd5118_write_temp(struct regmap *regmap, u32 attr, long val) +{ + u8 regval[2]; + u16 temp; + int reg; + + switch (attr) { + case hwmon_temp_max: + reg = SPD5118_REG_TEMP_MAX; + break; + case hwmon_temp_min: + reg = SPD5118_REG_TEMP_MIN; + break; + case hwmon_temp_crit: + reg = SPD5118_REG_TEMP_CRIT; + break; + case hwmon_temp_lcrit: + reg = SPD5118_REG_TEMP_LCRIT; + break; + default: + return -EOPNOTSUPP; + } + + temp = spd5118_temp_to_reg(val); + regval[0] = temp & 0xff; + regval[1] = temp >> 8; + + return regmap_bulk_write(regmap, reg, regval, 2); +} + +static int spd5118_write_enable(struct regmap *regmap, long val) +{ + if (val && val != 1) + return -EINVAL; + + return regmap_update_bits(regmap, SPD5118_REG_TEMP_CONFIG, + SPD5118_TS_DISABLE, + val ? 0 : SPD5118_TS_DISABLE); +} + +static int spd5118_temp_write(struct regmap *regmap, u32 attr, long val) +{ + switch (attr) { + case hwmon_temp_max: + case hwmon_temp_min: + case hwmon_temp_crit: + case hwmon_temp_lcrit: + return spd5118_write_temp(regmap, attr, val); + case hwmon_temp_enable: + return spd5118_write_enable(regmap, val); + default: + return -EOPNOTSUPP; + } +} + +static int spd5118_write(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long val) +{ + struct regmap *regmap = dev_get_drvdata(dev); + + switch (type) { + case hwmon_temp: + return spd5118_temp_write(regmap, attr, val); + default: + return -EOPNOTSUPP; + } +} + +static umode_t spd5118_is_visible(const void *_data, enum hwmon_sensor_types type, + u32 attr, int channel) +{ + if (type != hwmon_temp) + return 0; + + switch (attr) { + case hwmon_temp_input: + return 0444; + case hwmon_temp_min: + case hwmon_temp_max: + case hwmon_temp_lcrit: + case hwmon_temp_crit: + case hwmon_temp_enable: + return 0644; + case hwmon_temp_min_alarm: + case hwmon_temp_max_alarm: + case hwmon_temp_crit_alarm: + case hwmon_temp_lcrit_alarm: + return 0444; + default: + return 0; + } +} + +static inline bool spd5118_parity8(u8 w) +{ + w ^= w >> 4; + return (0x6996 >> (w & 0xf)) & 1; +} + +/* + * Bank and vendor id are 8-bit fields with seven data bits and odd parity. + * Vendor IDs 0 and 0x7f are invalid. + * See Jedec standard JEP106BJ for details and a list of assigned vendor IDs. + */ +static bool spd5118_vendor_valid(u8 bank, u8 id) +{ + if (!spd5118_parity8(bank) || !spd5118_parity8(id)) + return false; + + id &= 0x7f; + return id && id != 0x7f; +} + +/* Return 0 if detection is successful, -ENODEV otherwise */ +static int spd5118_detect(struct i2c_client *client, struct i2c_board_info *info) +{ + struct i2c_adapter *adapter = client->adapter; + int regval; + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | + I2C_FUNC_SMBUS_WORD_DATA)) + return -ENODEV; + + regval = i2c_smbus_read_word_swapped(client, SPD5118_REG_TYPE); + if (regval != 0x5118) + return -ENODEV; + + regval = i2c_smbus_read_word_data(client, SPD5118_REG_VENDOR); + if (regval < 0 || !spd5118_vendor_valid(regval & 0xff, regval >> 8)) + return -ENODEV; + + regval = i2c_smbus_read_byte_data(client, SPD5118_REG_CAPABILITY); + if (regval < 0) + return -ENODEV; + if (!(regval & SPD5118_CAP_TS_SUPPORT) || (regval & 0xfc)) + return -ENODEV; + + regval = i2c_smbus_read_byte_data(client, SPD5118_REG_TEMP_CLR); + if (regval) + return -ENODEV; + regval = i2c_smbus_read_byte_data(client, SPD5118_REG_ERROR_CLR); + if (regval) + return -ENODEV; + + regval = i2c_smbus_read_byte_data(client, SPD5118_REG_REVISION); + if (regval < 0 || (regval & 0xc1)) + return -ENODEV; + + regval = i2c_smbus_read_byte_data(client, SPD5118_REG_TEMP_CONFIG); + if (regval < 0) + return -ENODEV; + if (regval & ~SPD5118_TS_DISABLE) + return -ENODEV; + + strscpy(info->type, "spd5118", I2C_NAME_SIZE); + return 0; +} + +static const struct hwmon_channel_info *spd5118_info[] = { + HWMON_CHANNEL_INFO(chip, + HWMON_C_REGISTER_TZ), + HWMON_CHANNEL_INFO(temp, + HWMON_T_INPUT | + HWMON_T_LCRIT | HWMON_T_LCRIT_ALARM | + HWMON_T_MIN | HWMON_T_MIN_ALARM | + HWMON_T_MAX | HWMON_T_MAX_ALARM | + HWMON_T_CRIT | HWMON_T_CRIT_ALARM | + HWMON_T_ENABLE), + NULL +}; + +static const struct hwmon_ops spd5118_hwmon_ops = { + .is_visible = spd5118_is_visible, + .read = spd5118_read, + .write = spd5118_write, +}; + +static const struct hwmon_chip_info spd5118_chip_info = { + .ops = &spd5118_hwmon_ops, + .info = spd5118_info, +}; + +static bool spd5118_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case SPD5118_REG_TEMP_CLR: + case SPD5118_REG_TEMP_CONFIG: + case SPD5118_REG_TEMP_MAX: + case SPD5118_REG_TEMP_MAX + 1: + case SPD5118_REG_TEMP_MIN: + case SPD5118_REG_TEMP_MIN + 1: + case SPD5118_REG_TEMP_CRIT: + case SPD5118_REG_TEMP_CRIT + 1: + case SPD5118_REG_TEMP_LCRIT: + case SPD5118_REG_TEMP_LCRIT + 1: + return true; + default: + return false; + } +} + +static bool spd5118_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case SPD5118_REG_TEMP_CLR: + case SPD5118_REG_ERROR_CLR: + case SPD5118_REG_TEMP: + case SPD5118_REG_TEMP + 1: + case SPD5118_REG_TEMP_STATUS: + return true; + default: + return false; + } +} + +static const struct regmap_config spd5118_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = SPD5118_REG_TEMP_STATUS, + .writeable_reg = spd5118_writeable_reg, + .volatile_reg = spd5118_volatile_reg, + .cache_type = REGCACHE_MAPLE, +}; + +static int spd5118_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + unsigned int regval, revision, vendor, bank; + struct device *hwmon_dev; + struct regmap *regmap; + int err; + + regmap = devm_regmap_init_i2c(client, &spd5118_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "regmap init failed\n"); + + err = regmap_read(regmap, SPD5118_REG_CAPABILITY, ®val); + if (err) + return err; + if (!(regval & SPD5118_CAP_TS_SUPPORT)) + return -ENODEV; + + err = regmap_read(regmap, SPD5118_REG_REVISION, &revision); + if (err) + return err; + + err = regmap_read(regmap, SPD5118_REG_VENDOR, &bank); + if (err) + return err; + err = regmap_read(regmap, SPD5118_REG_VENDOR + 1, &vendor); + if (err) + return err; + if (!spd5118_vendor_valid(bank, vendor)) + return -ENODEV; + + hwmon_dev = devm_hwmon_device_register_with_info(dev, "spd5118", + regmap, &spd5118_chip_info, + NULL); + if (IS_ERR(hwmon_dev)) + return PTR_ERR(hwmon_dev); + + /* + * From JESD300-5B + * MR2 bits [5:4]: Major revision, 1..4 + * MR2 bits [3:1]: Minor revision, 0..8? Probably a typo, assume 1..8 + */ + dev_info(dev, "DDR5 temperature sensor: vendor 0x%02x:0x%02x revision %d.%d\n", + bank & 0x7f, vendor, ((revision >> 4) & 0x03) + 1, ((revision >> 1) & 0x07) + 1); + + return 0; +} + +static const struct i2c_device_id spd5118_id[] = { + { "spd5118", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, spd5118_id); + +static const struct of_device_id spd5118_of_ids[] = { + { .compatible = "jedec,spd5118", }, + { } +}; +MODULE_DEVICE_TABLE(of, spd5118_of_ids); + +static struct i2c_driver spd5118_driver = { + .class = I2C_CLASS_HWMON, + .driver = { + .name = "spd5118", + .of_match_table = spd5118_of_ids, + }, + .probe = spd5118_probe, + .id_table = spd5118_id, + .detect = spd5118_detect, + .address_list = normal_i2c, +}; + +module_i2c_driver(spd5118_driver); + +MODULE_AUTHOR("René Rebe "); +MODULE_AUTHOR("Guenter Roeck "); +MODULE_DESCRIPTION("SPD 5118 driver"); +MODULE_LICENSE("GPL"); From patchwork Fri May 31 23:05:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 13682259 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BE0A12FB3C; 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Fri, 31 May 2024 16:06:06 -0700 (PDT) Received: from server.roeck-us.net ([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f632408348sm21996885ad.258.2024.05.31.16.06.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 May 2024 16:06:05 -0700 (PDT) Sender: Guenter Roeck From: Guenter Roeck To: linux-hwmon@vger.kernel.org Cc: devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org, Armin Wolf , =?utf-8?q?Thomas?= =?utf-8?q?_Wei=C3=9Fschuh?= , =?utf-8?q?Ren=C3=A9_Reb?= =?utf-8?q?e?= , Wolfram Sang , Guenter Roeck Subject: [PATCH RFT v3 3/4] hwmon: (spd5118) Add suspend/resume support Date: Fri, 31 May 2024 16:05:55 -0700 Message-Id: <20240531230556.1409532-4-linux@roeck-us.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240531230556.1409532-1-linux@roeck-us.net> References: <20240531230556.1409532-1-linux@roeck-us.net> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add suspend/resume support to ensure that limit and configuration registers are updated and synchronized after a suspend/resume cycle. Cc: Armin Wolf Signed-off-by: Guenter Roeck Tested-by: Armin Wolf --- v3: No change v2: New patch RFT: I tested the patch through a suspend/resume cycle, and it seems to work, but I am not sure if that had any effect because, after all, the memory is still active during suspend/resume. I was unable to test a hibernation cycle with my system. drivers/hwmon/spd5118.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/hwmon/spd5118.c b/drivers/hwmon/spd5118.c index d3fc0ae17743..baa315172298 100644 --- a/drivers/hwmon/spd5118.c +++ b/drivers/hwmon/spd5118.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -432,6 +433,8 @@ static int spd5118_probe(struct i2c_client *client) if (!spd5118_vendor_valid(bank, vendor)) return -ENODEV; + dev_set_drvdata(dev, regmap); + hwmon_dev = devm_hwmon_device_register_with_info(dev, "spd5118", regmap, &spd5118_chip_info, NULL); @@ -449,6 +452,31 @@ static int spd5118_probe(struct i2c_client *client) return 0; } +static int spd5118_suspend(struct device *dev) +{ + struct regmap *regmap = dev_get_drvdata(dev); + + regcache_cache_bypass(regmap, true); + regmap_update_bits(regmap, SPD5118_REG_TEMP_CONFIG, SPD5118_TS_DISABLE, + SPD5118_TS_DISABLE); + regcache_cache_bypass(regmap, false); + + regcache_cache_only(regmap, true); + regcache_mark_dirty(regmap); + + return 0; +} + +static int spd5118_resume(struct device *dev) +{ + struct regmap *regmap = dev_get_drvdata(dev); + + regcache_cache_only(regmap, false); + return regcache_sync(regmap); +} + +static DEFINE_SIMPLE_DEV_PM_OPS(spd5118_pm_ops, spd5118_suspend, spd5118_resume); + static const struct i2c_device_id spd5118_id[] = { { "spd5118", 0 }, { } @@ -466,6 +494,7 @@ static struct i2c_driver spd5118_driver = { .driver = { .name = "spd5118", .of_match_table = spd5118_of_ids, + .pm = pm_sleep_ptr(&spd5118_pm_ops), }, .probe = spd5118_probe, .id_table = spd5118_id, From patchwork Fri May 31 23:05:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guenter Roeck X-Patchwork-Id: 13682260 Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A9A31311A8; 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Fri, 31 May 2024 16:06:07 -0700 (PDT) Received: from server.roeck-us.net ([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c1a776f526sm4024943a91.13.2024.05.31.16.06.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 May 2024 16:06:07 -0700 (PDT) Sender: Guenter Roeck From: Guenter Roeck To: linux-hwmon@vger.kernel.org Cc: devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org, Armin Wolf , =?utf-8?q?Thomas?= =?utf-8?q?_Wei=C3=9Fschuh?= , =?utf-8?q?Ren=C3=A9_Reb?= =?utf-8?q?e?= , Wolfram Sang , Guenter Roeck Subject: [PATCH RFT v3 4/4] hwmon: (spd5118) Add support for reading SPD data Date: Fri, 31 May 2024 16:05:56 -0700 Message-Id: <20240531230556.1409532-5-linux@roeck-us.net> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240531230556.1409532-1-linux@roeck-us.net> References: <20240531230556.1409532-1-linux@roeck-us.net> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for reading SPD NVRAM data from SPD5118 (Jedec JESD300) compliant memory modules. NVRAM write operation is not supported. Signed-off-by: Guenter Roeck --- v3: New patch RFT: I'd like to get some more test coverage before moving forward with this patch. decode-dimms doesn't recognize the 'spd5118' driver. Documentation/hwmon/spd5118.rst | 8 ++ drivers/hwmon/spd5118.c | 146 +++++++++++++++++++++++++++++++- 2 files changed, 150 insertions(+), 4 deletions(-) diff --git a/Documentation/hwmon/spd5118.rst b/Documentation/hwmon/spd5118.rst index a15d75aa2066..ef7338f46575 100644 --- a/Documentation/hwmon/spd5118.rst +++ b/Documentation/hwmon/spd5118.rst @@ -53,3 +53,11 @@ temp1_crit_alarm Temperature critical alarm Alarm attributes are sticky until read and will be cleared afterwards unless the alarm condition still applies. + + +SPD (Serial Presence Detect) support +------------------------------------ + +The driver also supports reading the SPD NVRAM on SPD5118 compatible chips. +SPD data is available from the 'eeprom' binary attribute file attached to the +chip's I2C device. diff --git a/drivers/hwmon/spd5118.c b/drivers/hwmon/spd5118.c index baa315172298..131002290ff3 100644 --- a/drivers/hwmon/spd5118.c +++ b/drivers/hwmon/spd5118.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include #include #include #include @@ -53,12 +55,31 @@ static const unsigned short normal_i2c[] = { #define SPD5118_TS_DISABLE BIT(0) /* temperature sensor disable */ +#define SPD5118_LEGACY_MODE_ADDR BIT(3) +#define SPD5118_LEGACY_PAGE_MASK GENMASK(2, 0) +#define SPD5118_LEGACY_MODE_MASK (SPD5118_LEGACY_MODE_ADDR | SPD5118_LEGACY_PAGE_MASK) + + +#define SPD5118_NUM_PAGES 8 +#define SPD5118_PAGE_SIZE 128 +#define SPD5118_PAGE_SHIFT 7 +#define SPD5118_PAGE_MASK GENMASK(6, 0) +#define SPD5118_EEPROM_BASE 0x80 +#define SPD5118_EEPROM_SIZE (SPD5118_PAGE_SIZE * SPD5118_NUM_PAGES) + /* Temperature unit in millicelsius */ #define SPD5118_TEMP_UNIT (MILLIDEGREE_PER_DEGREE / 4) /* Representable temperature range in millicelsius */ #define SPD5118_TEMP_RANGE_MIN -256000 #define SPD5118_TEMP_RANGE_MAX 255750 +struct spd5118_data { + struct regmap *regmap; + struct mutex nvmem_lock; +}; + +/* hwmon */ + static int spd5118_temp_from_reg(u16 reg) { int temp = sign_extend32(reg >> 2, 10); @@ -360,9 +381,111 @@ static const struct hwmon_chip_info spd5118_chip_info = { .info = spd5118_info, }; +/* nvmem */ + +static int spd5118_nvmem_set_page(struct regmap *regmap, int page) +{ + unsigned int old_page; + int err; + + err = regmap_read(regmap, SPD5118_REG_I2C_LEGACY_MODE, &old_page); + if (err) + return err; + + if (page != (old_page & SPD5118_LEGACY_MODE_MASK)) { + /* Update page and explicitly select 1-byte addressing */ + err = regmap_update_bits(regmap, SPD5118_REG_I2C_LEGACY_MODE, + SPD5118_LEGACY_MODE_MASK, page); + if (err) + return err; + + /* Selected new NVMEM page, drop cached data */ + regcache_drop_region(regmap, SPD5118_EEPROM_BASE, 0xff); + } + + return 0; +} + +static ssize_t spd5118_nvmem_read_page(struct regmap *regmap, char *buf, + unsigned int offset, size_t count) +{ + int err; + + err = spd5118_nvmem_set_page(regmap, offset >> SPD5118_PAGE_SHIFT); + if (err) + return err; + + offset &= SPD5118_PAGE_MASK; + + /* Can't cross page boundaries */ + if (offset + count > SPD5118_PAGE_SIZE) + count = SPD5118_PAGE_SIZE - offset; + + err = regmap_bulk_read(regmap, SPD5118_EEPROM_BASE + offset, buf, count); + if (err) + return err; + + return count; +} + +static int spd5118_nvmem_read(void *priv, unsigned int off, void *val, size_t count) +{ + struct spd5118_data *data = priv; + char *buf = val; + int ret; + + if (unlikely(!count)) + return count; + + if (off + count > SPD5118_EEPROM_SIZE) + return -EINVAL; + + mutex_lock(&data->nvmem_lock); + + while (count) { + ret = spd5118_nvmem_read_page(data->regmap, buf, off, count); + if (ret < 0) { + mutex_unlock(&data->nvmem_lock); + return ret; + } + buf += ret; + off += ret; + count -= ret; + } + mutex_unlock(&data->nvmem_lock); + return 0; +} + +static int spd5118_nvmem_init(struct device *dev, struct spd5118_data *data) +{ + struct nvmem_config nvmem_config = { + .type = NVMEM_TYPE_EEPROM, + .name = dev_name(dev), + .id = NVMEM_DEVID_AUTO, + .dev = dev, + .base_dev = dev, + .read_only = true, + .root_only = false, + .owner = THIS_MODULE, + .compat = true, + .reg_read = spd5118_nvmem_read, + .priv = data, + .stride = 1, + .word_size = 1, + .size = SPD5118_EEPROM_SIZE, + }; + struct nvmem_device *nvmem; + + nvmem = devm_nvmem_register(dev, &nvmem_config); + return PTR_ERR_OR_ZERO(nvmem); +} + +/* regmap */ + static bool spd5118_writeable_reg(struct device *dev, unsigned int reg) { switch (reg) { + case SPD5118_REG_I2C_LEGACY_MODE: case SPD5118_REG_TEMP_CLR: case SPD5118_REG_TEMP_CONFIG: case SPD5118_REG_TEMP_MAX: @@ -396,7 +519,7 @@ static bool spd5118_volatile_reg(struct device *dev, unsigned int reg) static const struct regmap_config spd5118_regmap_config = { .reg_bits = 8, .val_bits = 8, - .max_register = SPD5118_REG_TEMP_STATUS, + .max_register = 0xff, .writeable_reg = spd5118_writeable_reg, .volatile_reg = spd5118_volatile_reg, .cache_type = REGCACHE_MAPLE, @@ -406,10 +529,15 @@ static int spd5118_probe(struct i2c_client *client) { struct device *dev = &client->dev; unsigned int regval, revision, vendor, bank; + struct spd5118_data *data; struct device *hwmon_dev; struct regmap *regmap; int err; + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + regmap = devm_regmap_init_i2c(client, &spd5118_regmap_config); if (IS_ERR(regmap)) return dev_err_probe(dev, PTR_ERR(regmap), "regmap init failed\n"); @@ -433,7 +561,15 @@ static int spd5118_probe(struct i2c_client *client) if (!spd5118_vendor_valid(bank, vendor)) return -ENODEV; - dev_set_drvdata(dev, regmap); + data->regmap = regmap; + mutex_init(&data->nvmem_lock); + dev_set_drvdata(dev, data); + + err = spd5118_nvmem_init(dev, data); + if (err) { + dev_err_probe(dev, err, "failed to register nvmem\n"); + return err; + } hwmon_dev = devm_hwmon_device_register_with_info(dev, "spd5118", regmap, &spd5118_chip_info, @@ -454,7 +590,8 @@ static int spd5118_probe(struct i2c_client *client) static int spd5118_suspend(struct device *dev) { - struct regmap *regmap = dev_get_drvdata(dev); + struct spd5118_data *data = dev_get_drvdata(dev); + struct regmap *regmap = data->regmap; regcache_cache_bypass(regmap, true); regmap_update_bits(regmap, SPD5118_REG_TEMP_CONFIG, SPD5118_TS_DISABLE, @@ -469,7 +606,8 @@ static int spd5118_suspend(struct device *dev) static int spd5118_resume(struct device *dev) { - struct regmap *regmap = dev_get_drvdata(dev); + struct spd5118_data *data = dev_get_drvdata(dev); + struct regmap *regmap = data->regmap; regcache_cache_only(regmap, false); return regcache_sync(regmap);