From patchwork Tue Jun 4 01:11:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 13684520 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 148FFB676; Tue, 4 Jun 2024 01:13:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717463599; cv=none; b=HlzIU8/KGcD1VQiJywtr0IGjRWdpmIkIlEJDPrE+epPsQhV74BXpd6I/VTWFTFRmpleGw0goyAuoIblImrox5dcBga827gfKHySld+WcJETmILDOQBLXRHvjHJMqiqFksQkLPKlbo1/Mz658m8axXfslDIKFIRTRmNAfDquMT0U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717463599; c=relaxed/simple; bh=jztKnnlHdZ0d5U7J26a873QAPkRWX0J2JKqleIiDpXI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YYIlJObi9iEG+08iMKQ8ixYhwb98VRndoajqCDDhsvfZ67DDvnZH2k4leLuFiaBFi71/Q5MbQBSlOK3mavNixG0EIIbawl/d3Rdgh5zaiF/1R66VlDx6Jsc/PeDzRcEOI3LyukDHTYoluEb4WEWi8tuQVE0IvddgJ8Ak+FJ+LAQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=lUXSKbLJ; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="lUXSKbLJ" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 453CGM3E028674; Tue, 4 Jun 2024 01:13:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= qgu+d5dPRwrokhzDKM/ctW6lufP8HCeLXFdMNcJSK+I=; b=lUXSKbLJRM2Co1Nh q7GApxKpWeCsPdtmhV8ZJeiVmnGTkP4AYRuoknImPbOsW7if02vxZPDBTlPbYjT5 6957l3o55huJ2Rz5NY8I2f4U7d9HSr6TngWIAszRda3cw/zzBH/sz8IeUYh9nqOR nYhdA2IlH4aSbd+YHPrm1xMDReilrq+HHmEqeECVK9hByr0nw2i4PaHbbbl0wadh AsSU/qaxn89nRRgXaPRYRTlIO4VgnU2x3MdfGQpc71vq13MW1ZpzOnyx3J2C2GPe 06KfKIQPrH91PtNCYWIHA971mcFtSw9Qxdsa7gj3y7dtgh0Vh5ZlllAUHCnxI+jL 484RGg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3yfw5t55j9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Jun 2024 01:13:13 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4541DCrp012450 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 4 Jun 2024 01:13:12 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 3 Jun 2024 18:13:07 -0700 From: Sibi Sankar To: , , , , , CC: , , , , , , , , , Subject: [PATCH 1/4] dt-bindings: interconnect: qcom,msm8998-bwmon: Add X1E80100 BWMON instances Date: Tue, 4 Jun 2024 06:41:54 +0530 Message-ID: <20240604011157.2358019-2-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604011157.2358019-1-quic_sibis@quicinc.com> References: <20240604011157.2358019-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: QHaZdCR_blpBm4C63wfQ2rnQZEAJhwJZ X-Proofpoint-GUID: QHaZdCR_blpBm4C63wfQ2rnQZEAJhwJZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-06-03_17,2024-05-30_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 spamscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 malwarescore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406040008 Document X1E80100 BWMONs, which has multiple (one per cluster) BWMONv4 instances for the CPU->LLCC path and one BWMONv5 instance for LLCC->DDR path. Signed-off-by: Sibi Sankar Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml index 05067e197abe..05f6bd348138 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -35,6 +35,7 @@ properties: - qcom,sm8250-cpu-bwmon - qcom,sm8550-cpu-bwmon - qcom,sm8650-cpu-bwmon + - qcom,x1e80100-cpu-bwmon - const: qcom,sdm845-bwmon # BWMON v4, unified register space - items: - enum: @@ -44,6 +45,7 @@ properties: - qcom,sm8250-llcc-bwmon - qcom,sm8550-llcc-bwmon - qcom,sm8650-llcc-bwmon + - qcom,x1e80100-llcc-bwmon - const: qcom,sc7280-llcc-bwmon - const: qcom,sc7280-llcc-bwmon # BWMON v5 - const: qcom,sdm845-llcc-bwmon # BWMON v5 From patchwork Tue Jun 4 01:11:55 2024 Content-Type: text/plain; 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Mark them are shared to allow for re-use across instances. Signed-off-by: Sibi Sankar --- drivers/soc/qcom/icc-bwmon.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c index fb323b3364db..d69e0797eeda 100644 --- a/drivers/soc/qcom/icc-bwmon.c +++ b/drivers/soc/qcom/icc-bwmon.c @@ -783,7 +783,8 @@ static int bwmon_probe(struct platform_device *pdev) bwmon_disable(bwmon); ret = devm_request_threaded_irq(dev, bwmon->irq, bwmon_intr, bwmon_intr_thread, - IRQF_ONESHOT, dev_name(dev), bwmon); + IRQF_ONESHOT | IRQF_SHARED, + dev_name(dev), bwmon); if (ret) return dev_err_probe(dev, ret, "failed to request IRQ\n"); From patchwork Tue Jun 4 01:11:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 13684522 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AC6B18EAF; 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Tue, 04 Jun 2024 01:13:24 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4541DNhf023372 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 4 Jun 2024 01:13:23 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 3 Jun 2024 18:13:18 -0700 From: Sibi Sankar To: , , , , , CC: , , , , , , , , , Subject: [PATCH 3/4] arm64: dts: qcom: x1e80100: Add BWMONs Date: Tue, 4 Jun 2024 06:41:56 +0530 Message-ID: <20240604011157.2358019-4-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604011157.2358019-1-quic_sibis@quicinc.com> References: <20240604011157.2358019-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 18uscrXsqX-CN_9yCd2j9tn6Djfb0JcD X-Proofpoint-GUID: 18uscrXsqX-CN_9yCd2j9tn6Djfb0JcD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-06-03_17,2024-05-30_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 phishscore=0 malwarescore=0 priorityscore=1501 mlxscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 mlxlogscore=823 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406040008 Add the CPU and LLCC BWMONs on X1E80100 SoCs. Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 169 +++++++++++++++++++++++++ 1 file changed, 169 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 1929c34ae70a..d86c4d3be126 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5329,6 +5329,175 @@ cpu_scp_lpri1: scp-sram-section@200 { }; }; + pmu@24091000 { + compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0 0x24091000 0 0x1000>; + + interrupts = ; + + interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <800000>; + }; + + opp-1 { + opp-peak-kBps = <2188000>; + }; + + opp-2 { + opp-peak-kBps = <3072000>; + }; + + opp-3 { + opp-peak-kBps = <6220800>; + }; + + opp-4 { + opp-peak-kBps = <6835200>; + }; + + opp-5 { + opp-peak-kBps = <8371200>; + }; + + opp-6 { + opp-peak-kBps = <10944000>; + }; + + opp-7 { + opp-peak-kBps = <12748800>; + }; + + opp-8 { + opp-peak-kBps = <14745600>; + }; + + opp-9 { + opp-peak-kBps = <16896000>; + }; + }; + }; + + pmu@240b3400 { + compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x240b3400 0 0x600>; + + interrupts = ; + + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; + operating-points-v2 = <&cpu0_bwmon_opp_table>; + + cpu0_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-1 { + opp-peak-kBps = <4800000>; + }; + + opp-2 { + opp-peak-kBps = <7464000>; + }; + + opp-3 { + opp-peak-kBps = <9600000>; + }; + + opp-4 { + opp-peak-kBps = <12896000>; + }; + + opp-5 { + opp-peak-kBps = <14928000>; + }; + + opp-6 { + opp-peak-kBps = <17064000>; + }; + }; + }; + + pmu@240b5400 { + compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x240b5400 0 0x600>; + + interrupts = ; + + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; + operating-points-v2 = <&cpu8_bwmon_opp_table>; + + cpu8_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-1 { + opp-peak-kBps = <4800000>; + }; + + opp-2 { + opp-peak-kBps = <7464000>; + }; + + opp-3 { + opp-peak-kBps = <9600000>; + }; + + opp-4 { + opp-peak-kBps = <12896000>; + }; + + opp-5 { + opp-peak-kBps = <14928000>; + }; + + opp-6 { + opp-peak-kBps = <17064000>; + }; + }; + }; + + pmu@240b6400 { + compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x240b6400 0 0x600>; + + interrupts = ; + + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; + operating-points-v2 = <&cpu4_bwmon_opp_table>; + + cpu4_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-1 { + opp-peak-kBps = <4800000>; + }; + + opp-2 { + opp-peak-kBps = <7464000>; + }; + + opp-3 { + opp-peak-kBps = <9600000>; + }; + + opp-4 { + opp-peak-kBps = <12896000>; + }; + + opp-5 { + opp-peak-kBps = <14928000>; + }; + + opp-6 { + opp-peak-kBps = <17064000>; + }; + }; + }; + system-cache-controller@25000000 { compatible = "qcom,x1e80100-llcc"; reg = <0 0x25000000 0 0x200000>, From patchwork Tue Jun 4 01:11:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 13684523 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2552524A08; Tue, 4 Jun 2024 01:13:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717463613; cv=none; b=u6+TvU97Ub0bHyLJY93BjJFnFQX7MB0s/fDpKMdUd2zEHzw2CM7M5eiDBqpsXrawL6OeWYf8ih8t95LAXO2wUhY7DROCrp/2XPVYRZt/xBuPg7RuZpP6+qzoHOXDBayJ3PdgR4XRNzEKMR4NIaj0aZMu1VSszKYqqlOoxf4LoCE= ARC-Message-Signature: i=1; a=rsa-sha256; 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Tue, 4 Jun 2024 01:13:28 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 3 Jun 2024 18:13:23 -0700 From: Sibi Sankar To: , , , , , CC: , , , , , , , , , Subject: [PATCH 4/4] arm64: dts: qcom: x1e80100: Add fastrpc nodes Date: Tue, 4 Jun 2024 06:41:57 +0530 Message-ID: <20240604011157.2358019-5-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240604011157.2358019-1-quic_sibis@quicinc.com> References: <20240604011157.2358019-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: jTKPC6OOZy6OgkCht_WT-68_F8nO_quL X-Proofpoint-GUID: jTKPC6OOZy6OgkCht_WT-68_F8nO_quL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-06-03_17,2024-05-30_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 spamscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 malwarescore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=725 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406040008 Add fastrpc nodes for ADSP and CDSP on X1E80100 SoC. Signed-off-by: Sibi Sankar --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 156 +++++++++++++++++++++++++ 1 file changed, 156 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index d86c4d3be126..4edabe0ff592 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5567,6 +5567,55 @@ IPCC_MPROC_SIGNAL_GLINK_QMP label = "lpass"; qcom,remote-pid = <2>; + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1063 0x0>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1064 0x0>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1065 0x0>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1066 0x0>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x80>, + <&apps_smmu 0x1067 0x0>; + dma-coherent; + }; + }; + gpr { compatible = "qcom,gpr"; qcom,glink-channels = "adsp_apps"; @@ -5656,6 +5705,113 @@ IPCC_MPROC_SIGNAL_GLINK_QMP label = "cdsp"; qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0c01 0x20>, + <&apps_smmu 0x0c21 0x20>; + dma-coherent; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0c02 0x20>, + <&apps_smmu 0x0c22 0x20>; + dma-coherent; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0c03 0x20>, + <&apps_smmu 0x0c23 0x20>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x0c04 0x20>, + <&apps_smmu 0x0c24 0x20>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x0c05 0x20>, + <&apps_smmu 0x0c25 0x20>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x0c06 0x20>, + <&apps_smmu 0x0c26 0x20>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x0c07 0x20>, + <&apps_smmu 0x0c27 0x20>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x0c08 0x20>, + <&apps_smmu 0x0c28 0x20>; + dma-coherent; + }; + + /* note: compute-cb@9 is secure */ + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <10>; + iommus = <&apps_smmu 0x0c0c 0x20>, + <&apps_smmu 0x0c2c 0x20>; + dma-coherent; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + iommus = <&apps_smmu 0x0c0d 0x20>, + <&apps_smmu 0x0c2d 0x20>; + dma-coherent; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&apps_smmu 0x0c0e 0x20>, + <&apps_smmu 0x0c2e 0x20>; + dma-coherent; + }; + + compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&apps_smmu 0x0c0f 0x20>, + <&apps_smmu 0x0c2f 0x20>; + dma-coherent; + }; + }; }; }; };