From patchwork Wed Jun 5 12:15:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13686737 Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B70441B1409 for ; Wed, 5 Jun 2024 12:15:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717589742; cv=none; b=UBx3Pi/8bfKbnKmgXWyDzFP3HbDxyrasbKkY+DHU2AkYe5cFLyzIeANhT2wzCcZp9MwRbdLB6xVnPfbTmsfyyHRspYnsX6TcWxdg9UZTqB42VY/PAmeNmq4lnJ5QV7RvoilaaCIQ1F1Z1aUfxta5KGTg4agBeWslhFbvFBUSnqE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717589742; c=relaxed/simple; bh=hTmtsdXYiGBOLJKJx4/m17z57Knu5252Lz/eRo2JFWI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=HI/+o4XN9B6qdTGzLTk4KLDhDIlFszGLDuUbtJQKUDUl7e9lZTzJNIGgtxfE/hOUKTCvmAalbhJDBIJSt1AWpIMDCAMyyRYT2xh31gjAyNJgm/jegGSxGZjzTiGHEqTlCuT+aMU9Xo+YIfEl96PxPqxHp0057p1GLfJzyqAwd8c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=UDhwyHgP; arc=none smtp.client-ip=209.85.210.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="UDhwyHgP" Received: by mail-pf1-f175.google.com with SMTP id d2e1a72fcca58-70276322ad8so2005252b3a.1 for ; Wed, 05 Jun 2024 05:15:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717589740; x=1718194540; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=M6DDIEotd8EWgMMcCZznOzCPmVBacRxZ1YaVEsFTRqc=; b=UDhwyHgPpWAaVxQKTTVkYKghXtatBoosfgNf5Qj1AeEyBbAD8kumMCFCZAQay4BDx9 7KG9uioFFCmQ7n/dPaKE0M8H9u6ewES6wyge6sJQCIZHq6ZkEF23AulF+9h6webjFuQ3 neJHZU0fYs9ybdF77bhXaqBbsbtQBOdIKv/hlc402Cxcwt4+ZmtxFIObarHRox8bCNu0 20qLcLKiIjyLRxg8A9OUr19IRMdzbZGfmpxlCtmC5LpvUed290N1Vw4WIQxTMdFy/fVj vMB076wOOTurfbHJDRv1nVcqzCGXuWWGOfLNRQ77bHy3aKzjEY39CAbMViIdOh4f5c07 a1qQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717589740; x=1718194540; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=M6DDIEotd8EWgMMcCZznOzCPmVBacRxZ1YaVEsFTRqc=; b=ArKvJF8E+fqpYfm+IBSyD91kxnDpVm93kCNNVAD0saSXrWWcjgTUrSomCbvX1SY1jo pxpAdc8lbzOaAMw5WKWRKbNNYtqpvOOsVIlewExSm0GWayFPxXLMaz1yZhXnZD/Gh+i7 cqTaNqKyba7fSMyL+UHXg7YjF68VmS9gLnUZv8grTVtFC/70jhRpGc9xgygkYvvhRt9q xWHWKbfbCxG7yqRDoV05tfc1Ce3Zye4jvD8u8EiqCY1Ss7H/9xp4LjGHcM/ZfOPavPUf jpo/WvWzX6JGIatWHp83gn808qLxqctPEWKjCb3425Ccv2QwGgZ7NrXqP4SI/3iYRSNK +P1A== X-Forwarded-Encrypted: i=1; AJvYcCVTOPs+pibRMJgTZ1TeWPR510wsNoSpJ3rPGhc1XIRMeDL2AdaK+O6MSqbIsi66wNSknE8ZuByxQo2cNAqX0pjqgaaz X-Gm-Message-State: AOJu0Yyc7Gxvdh6OUv/AlJ7erkYEUYsqCvK3cIanFz3YvPKAlpekLrzW mz451nPOr2cKHdjA9+hAyKf2Wdq0dBdio4hIZZHB/0uxc6q8/raV+OH13qvXwYc= X-Google-Smtp-Source: AGHT+IH3nqH0HygTrtx132GmRiIh9ksqvzFGs1AgXrG45C29IYpnZlxfse4GWma8yLnINlc5RX1TYA== X-Received: by 2002:a05:6a00:b4b:b0:703:ee76:6e5a with SMTP id d2e1a72fcca58-703ee7670c1mr1282317b3a.0.1717589739980; Wed, 05 Jun 2024 05:15:39 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703ee672fb3sm885379b3a.216.2024.06.05.05.15.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 05:15:39 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: apatel@ventanamicro.com, alex@ghiti.fr, ajones@ventanamicro.com, greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Jinyu Tang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Conor Dooley , Mayuresh Chitale , Atish Patra , wchen , Samuel Ortiz , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Evan Green , Xiao Wang , Alexandre Ghiti , Andrew Morton , "Mike Rapoport (IBM)" , Kemeng Shi , Samuel Holland , Jisheng Zhang , Charlie Jenkins , "Matthew Wilcox (Oracle)" , Leonardo Bras Subject: [PATCH v5 1/4] RISC-V: Add Svade and Svadu Extensions Support Date: Wed, 5 Jun 2024 20:15:07 +0800 Message-Id: <20240605121512.32083-2-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240605121512.32083-1-yongxuan.wang@sifive.com> References: <20240605121512.32083-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Svade and Svadu extensions represent two schemes for managing the PTE A/D bits. When the PTE A/D bits need to be set, Svade extension intdicates that a related page fault will be raised. In contrast, the Svadu extension supports hardware updating of PTE A/D bits. Since the Svade extension is mandatory and the Svadu extension is optional in RVA23 profile, by default the M-mode firmware will enable the Svadu extension in the menvcfg CSR when only Svadu is present in DT. This patch detects Svade and Svadu extensions from DT and adds arch_has_hw_pte_young() to enable optimization in MGLRU and __wp_page_copy_user() when we have the PTE A/D bits hardware updating support. Co-developed-by: Jinyu Tang Signed-off-by: Jinyu Tang Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/include/asm/pgtable.h | 14 +++++++++++++- arch/riscv/kernel/cpufeature.c | 2 ++ 5 files changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b94176e25be1..dbfe2be99bf9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -36,6 +36,7 @@ config RISCV select ARCH_HAS_PMEM_API select ARCH_HAS_PREPARE_SYNC_CORE_CMD select ARCH_HAS_PTE_SPECIAL + select ARCH_HAS_HW_PTE_YOUNG select ARCH_HAS_SET_DIRECT_MAP if MMU select ARCH_HAS_SET_MEMORY if MMU select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 25966995da04..524cd4131c71 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -195,6 +195,7 @@ /* xENVCFG flags */ #define ENVCFG_STCE (_AC(1, ULL) << 63) #define ENVCFG_PBMTE (_AC(1, ULL) << 62) +#define ENVCFG_ADUE (_AC(1, ULL) << 61) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) #define ENVCFG_CBIE_SHIFT 4 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e17d0078a651..35d7aa49785d 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,8 @@ #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 +#define RISCV_ISA_EXT_SVADE 75 +#define RISCV_ISA_EXT_SVADU 76 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index aad8b8ca51f1..7287ea4a6160 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -120,6 +120,7 @@ #include #include #include +#include #define __page_val_to_pfn(_val) (((_val) & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT) @@ -288,7 +289,6 @@ static inline pte_t pud_pte(pud_t pud) } #ifdef CONFIG_RISCV_ISA_SVNAPOT -#include static __always_inline bool has_svnapot(void) { @@ -624,6 +624,18 @@ static inline pgprot_t pgprot_writecombine(pgprot_t _prot) return __pgprot(prot); } +/* + * Both Svade and Svadu control the hardware behavior when the PTE A/D bits need to be set. By + * default the M-mode firmware enables the hardware updating scheme when only Svadu is present in + * DT. + */ +#define arch_has_hw_pte_young arch_has_hw_pte_young +static inline bool arch_has_hw_pte_young(void) +{ + return riscv_has_extension_unlikely(RISCV_ISA_EXT_SVADU) && + !riscv_has_extension_likely(RISCV_ISA_EXT_SVADE); +} + /* * THP functions */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 5ef48cb20ee1..58565798cea0 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -301,6 +301,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), + __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), + __RISCV_ISA_EXT_DATA(svadu, RISCV_ISA_EXT_SVADU), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), From patchwork Wed Jun 5 12:15:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13686738 Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3A5A1B14FE for ; Wed, 5 Jun 2024 12:15:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717589748; cv=none; b=UFxT4sziinTHfNQKoHELE7LJ3N4guSI7DhhvK5m0Gf2TqLIdJrJfZRHUai2i074bCIkleLiP+Mnu9HTuSTM0KfTpkuc1EQRkFer5bilAc3IMnCfXFpoBGAp5QaT/adbzawsirqiAGjFPTYglV6ZduNc05UT5wOANGB3zh0rLyZ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717589748; c=relaxed/simple; bh=7vv9BIxOlTAnkVcmOEbkz5pJ3DyqNEvdcN47CRhSbiU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=q02P3LOvo6XkoVPUAGbp8ukqDLA9nHy4Sd3Qe7dkpqOWzLtbwxj3GQBFfbtGSFdp90TkA+qAEyJu4L07J3NOP3Q8S/oCL7z44eNMSaiAvwDC+HWz54enHy6IkIWNpxqOP60EoRdwNPXUiP4T/9zsTnSasBfsCtAHqbTYJH32PP0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=iAZOCUTk; arc=none smtp.client-ip=209.85.210.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="iAZOCUTk" Received: by mail-pf1-f182.google.com with SMTP id d2e1a72fcca58-70259bdcf7cso3142728b3a.0 for ; Wed, 05 Jun 2024 05:15:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717589746; x=1718194546; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=GpvzkiCxKozJEFTOhtS0qkQgzMcSqTc8pxD/W7VEhXs=; b=iAZOCUTk8lI8+n+8mWwcJ0NmiEDHnk1vcO8fqJcwNa0tQM5nv5fkI+3Jy8YP29dF81 D8Ah6eBR6hqtGY6jF+B0ABj2UMKQ+19NoS/ElCSdkB/CF1so69yUqThKEprEROcAeorn jkikUg9Yk0U4yWWGRVYcRBiHwUWfUpXGYIAzH1Zk4zTT8JuPjvpieLXJ1WRZUDRwRtyy 9HAZUfiPtVB/BVhCMJ3gA+qIxKvHporUhrs9oAYtD2vWfvU2/JtUX+x6Hy5yWDddL9yu d0jjyMjXhHH8SZPRiBBooR5p5w47z3QLpyx4u54qsryesmJVdYyn5BfqYstzeKFJs/jZ SLiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717589746; x=1718194546; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=GpvzkiCxKozJEFTOhtS0qkQgzMcSqTc8pxD/W7VEhXs=; b=Zb9Kgf7OW5J1J0Fj0qBGWbaGd0jK5UduVO/V9GK52VGBTG4cCftf1DT90F2IAMZJod 32gd+GovlHqNHmU4p5DUhoBUfjeeiYfx9srPSYFFJhitdjjWaKnuCD2LkayEeRzYgzl4 BO9pedrPP1lCqtbMYS8xzFslZoXwOqqVFHN1enENOYCiUCuZ/OXf6+F9j9V5FHS9yyd9 zhuPWJQn7RF+VbUBjbLIGfTEPG+kFYA0lb4oIzQ+xWq3UY7J/XRlBinkaf+orXMlfh9G Z6qtC6+9augnAqj8vXftN7LX4u0feQTmJkP94s/hnlk9vd7Ftz7FElj0EKqYt/SPidpw pZJQ== X-Forwarded-Encrypted: i=1; AJvYcCVSAcdGWtITi0rFPR0QoCITG2pDV0uxi8IOS/KKMXshV/u6Mec0J+jx7SjeA3/yW5ANYkgikn1Hv7OK05OA8286Tp56 X-Gm-Message-State: AOJu0YwPJo3PNHecAavxu0/OJX3Pq0jBWQh8+nowTDwSz/+Aapzrh8gA HRpcJ55AK/vyfMHixZVsjxskxacLTwjU2JQUy9Oa95neD4LKhO74krBkFQsaK2U= X-Google-Smtp-Source: AGHT+IHxvvSw4LHcVUp46xf5eLnBwmt4LaRfb4YBe++3w64DoItEt1ztOFnT7PyaQMcSTm6fON3nVA== X-Received: by 2002:a05:6a00:1991:b0:6ed:de6e:dd24 with SMTP id d2e1a72fcca58-703e597aa21mr2623604b3a.16.1717589744922; Wed, 05 Jun 2024 05:15:44 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703ee672fb3sm885379b3a.216.2024.06.05.05.15.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 05:15:44 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: apatel@ventanamicro.com, alex@ghiti.fr, ajones@ventanamicro.com, greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , devicetree@vger.kernel.org Subject: [PATCH v5 2/4] dt-bindings: riscv: Add Svade and Svadu Entries Date: Wed, 5 Jun 2024 20:15:08 +0800 Message-Id: <20240605121512.32083-3-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240605121512.32083-1-yongxuan.wang@sifive.com> References: <20240605121512.32083-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Add entries for the Svade and Svadu extensions to the riscv,isa-extensions property. Signed-off-by: Yong-Xuan Wang --- .../devicetree/bindings/riscv/extensions.yaml | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 468c646247aa..1e30988826b9 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -153,6 +153,36 @@ properties: ratified at commit 3f9ed34 ("Add ability to manually trigger workflow. (#2)") of riscv-time-compare. + - const: svade + description: | + The standard Svade supervisor-level extension for raising page-fault + exceptions when PTE A/D bits need be set as ratified in the 20240213 + version of the privileged ISA specification. + + Both Svade and Svadu extensions control the hardware behavior when + the PTE A/D bits need to be set. The default behavior for the four + possible combinations of these extensions in the device tree are: + 1. Neither svade nor svadu in DT: default to svade. + 2. Only svade in DT: use svade. + 3. Only svadu in DT: use svadu. + 4. Both svade and svadu in DT: default to svade (Linux can switch to + svadu once the SBI FWFT extension is available). + + - const: svadu + description: | + The standard Svadu supervisor-level extension for hardware updating + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request + #25 from ved-rivos/ratified") of riscv-svadu. + + Both Svade and Svadu extensions control the hardware behavior when + the PTE A/D bits need to be set. The default behavior for the four + possible combinations of these extensions in the device tree are: + 1. Neither svade nor svadu in DT: default to svade. + 2. Only svade in DT: use svade. + 3. Only svadu in DT: use svadu. + 4. Both svade and svadu in DT: default to svade (Linux can switch to + svadu once the SBI FWFT extension is available). + - const: svinval description: The standard Svinval supervisor-level extension for fine-grained From patchwork Wed Jun 5 12:15:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13686739 Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0D361B151F for ; Wed, 5 Jun 2024 12:15:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717589752; cv=none; b=R41zTNu0tV/hjwb6C61XE+HTU9XcwfV3Q/e9jWGzAvOsAAoF/7F0SU5OAdiNMLn2YHxyfieJZ9ZCcsY3v7X3DnwJ4V++0GEGFhVLKvIOPHB6HlTBrlkTA+lW1O3VtK5x10QGq5pNlN5NO0rdXJmbM2BuHOQdsSRxwm/Xrfo5yb0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717589752; c=relaxed/simple; bh=CRu+PRCiIUbcgK7k+OALzNd3CLHlGYyDDJJ1/w/c3G0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=IlcVgViUHlQM1mr/H3CG9lmO1mY8hrQPJsPBhVMxxC9clc2ooOAuWOsxJWOcHqOMJuW5p5IvlX2tBGmiYifH6GLFnP7u97XU3dUwlauUUZMZ9pnASdoytgC5WNm48Rhvv8ZSI7iNnlszlDixhfKOFH/02qMdzbvWCPOTKdx+0zM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=TdXZ+kdV; arc=none smtp.client-ip=209.85.210.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="TdXZ+kdV" Received: by mail-pf1-f173.google.com with SMTP id d2e1a72fcca58-7025b253f64so3097544b3a.3 for ; Wed, 05 Jun 2024 05:15:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717589750; x=1718194550; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=C9yGW+vb+251DuCHvQ6eWHokjrDaPZ1CHdh15Wr7+D4=; b=TdXZ+kdVAYeqgf6FzrHoOcCipHaldgDwM/fSwuj5BsxAeA3j2UOuE6q55DCelFKbjh Lp97yCa0oHXKisVjjsxb5p/4OuM/weATVjS7bJmlCyakg8R/Lq3MELYNB7yfAeo9resh EnGTAFRW6KQQIRk6ImmTYvV6l/D1aYljinGQO23JG6qBsxKBoGJHFKwrxQr5ekrIIMcH /cTiTVl7HUD9an23rhSAWyXx2BfH3dZAE/JgUdP9M7cBtJKoQ9//GqyQLBJmM6Scf9R0 UHn9PIgtmTxvPKO2lAm+56eUrk3B4QWgtCSdMpX5rPZ+TZaIw8yonyS1h8sXXh6I9+Ri IuoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717589750; x=1718194550; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=C9yGW+vb+251DuCHvQ6eWHokjrDaPZ1CHdh15Wr7+D4=; b=iLH4IT/JgiqhM5glowfuHWHmugFROU3CzgYjfVVA82tfrYm6gNWnvd1Mst2X9g93Gm 4STgnD2veTmhdbi2oBTgwoFUUt7kc9voBwksd1TZAj90V8oVLanf7pfHvAh5e2Xl4X1g bgiHxebHjJ9LDQxX6+wsqDXlbDuUL3ozpvDSMeCDDUyYC1cvli978WV/p7z3HbVpiuyx pIzKRcyFSJZwNTKQ/SDEFGuMKeGtttnLOJxY3nHCQ5JBIs3eh6ICPw58eBUA5mPwTBkM UjgxJi4H9OttckG6vU7c8LB1YJobD7kch6x1BGzh9Wr8kHHNZhUAGzJg+m4d2ptihh+Q Z9cQ== X-Forwarded-Encrypted: i=1; AJvYcCXF758MDZi9XvBAfEICnHu3t0PvkG5PTE9sX7ffORNjohXSKwfX8OyO6r3x/AnBfcJhRW4WSvxSf6Lo5X5l2Y+WYWg4 X-Gm-Message-State: AOJu0Yw+pevfy6zjVkmDgFPHDNAFn/szw3Q4y4JciAbSIuq7oiRUMHgy vWpOhdIzVB2fPfQSjzlSFwYeMhg7Z1myocXxZgWHboQCzrRbTDqPzi4FW2CPi4k= X-Google-Smtp-Source: AGHT+IHuMhXVgloS9T7u/eogW1nwS9cEhCJiBxA9pyATWrWX01kMIqq28iggOkL5AgJrH0kuilEjvg== X-Received: by 2002:a05:6a00:18a0:b0:6e6:98bf:7b62 with SMTP id d2e1a72fcca58-703e594abe7mr2644243b3a.8.1717589749923; Wed, 05 Jun 2024 05:15:49 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703ee672fb3sm885379b3a.216.2024.06.05.05.15.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 05:15:49 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: apatel@ventanamicro.com, alex@ghiti.fr, ajones@ventanamicro.com, greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou Subject: [PATCH v5 3/4] RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM Date: Wed, 5 Jun 2024 20:15:09 +0800 Message-Id: <20240605121512.32083-4-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240605121512.32083-1-yongxuan.wang@sifive.com> References: <20240605121512.32083-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: We extend the KVM ISA extension ONE_REG interface to allow VMM tools to detect and enable Svade and Svadu extensions for Guest/VM. Since the henvcfg.ADUE is read-only zero if the menvcfg.ADUE is zero, the Svadu extension is available for Guest/VM only when arch_has_hw_pte_young() is true. Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones --- arch/riscv/include/uapi/asm/kvm.h | 2 ++ arch/riscv/kvm/vcpu.c | 6 ++++++ arch/riscv/kvm/vcpu_onereg.c | 6 ++++++ 3 files changed, 14 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index e878e7cc3978..a5e0c35d7e9a 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -168,6 +168,8 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZTSO, KVM_RISCV_ISA_EXT_ZACAS, KVM_RISCV_ISA_EXT_SSCOFPMF, + KVM_RISCV_ISA_EXT_SVADE, + KVM_RISCV_ISA_EXT_SVADU, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 17e21df36cc1..21edd60c4756 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -540,6 +540,12 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu) if (riscv_isa_extension_available(isa, ZICBOZ)) cfg->henvcfg |= ENVCFG_CBZE; + if (riscv_isa_extension_available(isa, SVADU)) + cfg->henvcfg |= ENVCFG_ADUE; + + if (riscv_isa_extension_available(isa, SVADE)) + cfg->henvcfg &= ~ENVCFG_ADUE; + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) { cfg->hstateen0 |= SMSTATEEN0_HSENVCFG; if (riscv_isa_extension_available(isa, SSAIA)) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index c676275ea0a0..06e930f1e206 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #define KVM_RISCV_BASE_ISA_MASK GENMASK(25, 0) @@ -38,6 +39,8 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSCOFPMF), KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVADE), + KVM_ISA_EXT_ARR(SVADU), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), @@ -105,6 +108,9 @@ static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext) return __riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSAIA); case KVM_RISCV_ISA_EXT_V: return riscv_v_vstate_ctrl_user_allowed(); + case KVM_RISCV_ISA_EXT_SVADU: + /* The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero. */ + return arch_has_hw_pte_young(); default: break; } From patchwork Wed Jun 5 12:15:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13686740 Received: from mail-pf1-f170.google.com (mail-pf1-f170.google.com [209.85.210.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 517731B29CD for ; Wed, 5 Jun 2024 12:15:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717589756; cv=none; b=f82E0LhAzzpKTA81gRqCxOK8cM7aI8j75AAI/b7evsDiPS4mTViY2RKBcIywoxiQViNJig1CE6vxDle6S0WW2nLe4ILAyzk7QnicYJ2BhqpaBo105Fq/bAFFbzjYbAjtHXHlOvTRd3tdPqgX0k8oO+qbx6B+3E1Tb4HN+8O1BSo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717589756; c=relaxed/simple; bh=jTQnCjAYiOnyg83RQMSJJfcBlJdwMJJeulbs10TuFN0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=dkLLRIBYBLvs5UGDgEcLEfZyKviFnkND2vWquVo4ZzHHmu8KE/+yKlpuAy9wL4hLHbLNhQUb5Bq0sD00ZHmlrVkELPiHpAw87u5cBHS+yo8nB/kFK7Cs8PjHwvApLi2KFeeT3mngS9i5zwf6Cr9A+N3dcgommpaO6DUl4ixby+M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=CBitWUsR; arc=none smtp.client-ip=209.85.210.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="CBitWUsR" Received: by mail-pf1-f170.google.com with SMTP id d2e1a72fcca58-70260814b2dso757127b3a.1 for ; Wed, 05 Jun 2024 05:15:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1717589755; x=1718194555; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=s1s067gNcLroY85Io7X9j2HhTsy4/JNlR/TnSjjDyVA=; b=CBitWUsR33hB9HOopjBrDaBMynnxWxj9jsJptpQQEiMRYqcDTNOrzWqgU12T6nM/if Js42uzlCtjQ54l343H/Qt6ze3cksIGBBpN3P85Eu9VQg8F3J8rkPF7wr3jdciHklWuN7 LpqsnFHlIKWARFzMcHv95e3qd5iT1U88MdTD19Noi6zqiitE6BJY+DzB8FVAQL17neoe FHIV14Orizcq46ErCe3sEfnfdJwVLMbYHHHvcF/ZI684TX7hIvmosQNFCuTq0JQCKSPl gu6lrE2kQfKaf0IHv1QfA94jGI9yeJQQSKzFsOj87i1oolHhpvndPscP647SKDNs4ol1 qcwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717589755; x=1718194555; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=s1s067gNcLroY85Io7X9j2HhTsy4/JNlR/TnSjjDyVA=; b=GWSLD38lTidlRdLaju5x744sGnwAui6Lazh5L3507Rl2OMux87WN/esjm8n2x+P0l6 WbaHSsI2UAl3O2pn6kzzHs3HhNqjXhDHf5+SRxxRqP/HDQUbadvop8PZEw0UNFfCtRbc 0zQ0+60F2bJo3aY2hOwI/Fk+wWxhCn7KVe/jOtiPHp+qhkqCFJxWLKr7+hE1OLikfIQz aQqcEZMrqLVmmn2vmsJhj2qqf66TNvFVGpE9bhrrgxGnOCgk5w9cnN3w3cNHVGPuWnK6 Lj+1XwjjlPU9QMVGoaetdHz94qKG9wHp6EdL3MjJSgkrMfHGDu/6g4zhqq4zs2h1942+ CQaA== X-Forwarded-Encrypted: i=1; AJvYcCUtoT0l8hBcxEfw8vIxG+g9UOw1Q8VuK5Gv+j48vMB8vwo31vlmnTgn/BhUpfDOHTR0RdfokVV+JBYGIu9ksFKgS4jy X-Gm-Message-State: AOJu0YyQjVJ8WGeDhaoD0OLzPK2QNNnzv04eZEYdOfWPEyTvm6GpvYjp yCWAhfNlvgpx5qE2eDM+4fjxQn84LCOl4UKIEcJ8qRbPtsCWGyUUrRBLFdGs7vw= X-Google-Smtp-Source: AGHT+IE2uyoTxe3pUNkQoaQt0ajX+GBn9F8zoOHdbUYCJhav/6GYlnkgU9F3LAFV0i5BxmNjeJ1V1Q== X-Received: by 2002:a05:6a00:6082:b0:702:5514:4cb8 with SMTP id d2e1a72fcca58-7027fba0d23mr6188351b3a.4.1717589754693; Wed, 05 Jun 2024 05:15:54 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-703ee672fb3sm885379b3a.216.2024.06.05.05.15.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 05:15:54 -0700 (PDT) From: Yong-Xuan Wang To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: apatel@ventanamicro.com, alex@ghiti.fr, ajones@ventanamicro.com, greentime.hu@sifive.com, vincent.chen@sifive.com, Yong-Xuan Wang , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-kselftest@vger.kernel.org Subject: [PATCH v5 4/4] KVM: riscv: selftests: Add Svade and Svadu Extension to get-reg-list test Date: Wed, 5 Jun 2024 20:15:10 +0800 Message-Id: <20240605121512.32083-5-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240605121512.32083-1-yongxuan.wang@sifive.com> References: <20240605121512.32083-1-yongxuan.wang@sifive.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Update the get-reg-list test to test the Svade and Svadu Extensions are available for guest OS. Signed-off-by: Yong-Xuan Wang Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 222198dd6d04..1d32351ad55e 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -45,6 +45,8 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSCOFPMF: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADE: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADU: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT: @@ -411,6 +413,8 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSCOFPMF), KVM_ISA_EXT_ARR(SSTC), + KVM_ISA_EXT_ARR(SVADE), + KVM_ISA_EXT_ARR(SVADU), KVM_ISA_EXT_ARR(SVINVAL), KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), @@ -935,6 +939,8 @@ KVM_ISA_EXT_SIMPLE_CONFIG(h, H); KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN); KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF); KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC); +KVM_ISA_EXT_SIMPLE_CONFIG(svade, SVADE); +KVM_ISA_EXT_SIMPLE_CONFIG(svadu, SVADU); KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL); KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT); KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT); @@ -991,6 +997,8 @@ struct vcpu_reg_list *vcpu_configs[] = { &config_smstateen, &config_sscofpmf, &config_sstc, + &config_svade, + &config_svadu, &config_svinval, &config_svnapot, &config_svpbmt,