From patchwork Wed Jun 5 17:20:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Morgan X-Patchwork-Id: 13687170 Received: from mail-oo1-f49.google.com (mail-oo1-f49.google.com [209.85.161.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60E5E5380F; Wed, 5 Jun 2024 17:20:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717608059; cv=none; b=khZ/leO8OvazTUZupY+U+KppDpNJ2jhcXs5XQ7UpylUlXuJ6MYe2R10hjKfd1KuRZZeFDEduZsg8nx7KDnfOzXjfniPYEICEwYS7MvoNCVOrpovuq5o5csaEqPd//Nl3k5o22yQHpVqaE1KnzNZCen4fJ8T7u8yY1dPT4uQ2xeU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717608059; c=relaxed/simple; bh=cBU3yekOXtlhNWdWpyG2xf0kFZVmOK5W2mTTLEsUAFk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bIS5qqeAaGhRGYspzWLVg9Wil41Z4NmxSE7lWqZ31eFIYa4HHWKZ6hen4WJWmDbdBJENzokrI3qC/C0nHm8kT4xJphZ+YLdsQVpGbHDSBHGyGzr4VOya7w16ZLPaoNDTkbZX2AeFFmiDgNH4fbSXXbdwLJ+84FI66OEz7NywIkI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=fDEQ7Wo0; arc=none smtp.client-ip=209.85.161.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fDEQ7Wo0" Received: by mail-oo1-f49.google.com with SMTP id 006d021491bc7-5ba33b08550so2321193eaf.2; Wed, 05 Jun 2024 10:20:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1717608055; x=1718212855; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iycGYFzd3F+df0p/qsCILVl1cIBvCeHnsWMgOkKCQP4=; b=fDEQ7Wo04zJOoc9WWoQqh9GiOiYlVfN+3cnfDoOwQ+jT/n8pl3CMEDZl5LGcFzgo03 egxt+wJdiEDjmXfZsja7/o9KELsYBm1CFe/CG9G5o0RGSw5K6inoPYnOzhymobiEQtZ6 FsuHtnLo3D3ao4Z6Z8Q0fuhtdDTXHmxXMq2mlwiWZ4HUHRmIeV8X61JRzCcuMrzXFfs+ umYZYD2eQQOe1ddijZyyhM2hVuRGD8yCypS1+L68a3ha5UJmQTvcyI6Na+MibPmjo2uh SJIkozj18mcwXmSKgtzoOsBAAr2ai3dhRxSTyxX3jdTFUTnMl6MZ+uULPafGsdRI+r+U DvxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717608055; x=1718212855; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iycGYFzd3F+df0p/qsCILVl1cIBvCeHnsWMgOkKCQP4=; b=All+8lZYEpXV4Os6QOt/fXs51YVTh0E1tA79dAnVXNtsAhjL2sXu4ZbxR/pHO4IAM3 8QCAOGWCDHhVqw/sAtsPm/sUQuYhwePBIATbKgxciacaBG5silH7H/DrG0zgMFDKtaEs wMkVXWd1tj3KOlmZpUyqhn4L5UTHqEVfzSnOx3Q4MDhjMdACqiCJMkEfqnPPLv/RFHxS e3nZ+n8ubc0lVnB+DXaFL0s8UcjccfdeHMM0dTifltzfS4S4zjuNyMa3La+849o4X4zk HinAHi6/6gUiE24TfekGxMTYyaPkiBp8ulOYStB1ArInugKuNRE8WVlC3yClT3lautmt flgA== X-Forwarded-Encrypted: i=1; AJvYcCVGUUa1XEzRo9nEgG+I6Qh7oBKeYN18iQrRG+DHPJbuhQRO8Ts2cZJyBwJ7crxtyAN3PH8sSpUPWDHxb7hjbc3meQG9DB+ZDcP3ldM0tWVkYG4QWUXaaiA7ivanZQ/iGkTlZONBvA== X-Gm-Message-State: AOJu0YxdQJ0DfRqSUILvjhzF7Jb+RW8rAxrLqoHQHEt0c9AaaA4uDj3b EQllPiJ9zLdjgi7LDfQ7pjo14FEHJcB6VszizvvzAmWjnfJ+tKIX X-Google-Smtp-Source: AGHT+IGLosO08ZXKoA1XuLlmpddoc2V3y6CwKOw/IuAQwj1zCJCa9l6+oWIoh8BDD8IE8Pbo6tjJnQ== X-Received: by 2002:a05:6820:62a:b0:5b9:f351:3f8b with SMTP id 006d021491bc7-5ba78d42decmr3790153eaf.0.1717608055299; Wed, 05 Jun 2024 10:20:55 -0700 (PDT) Received: from localhost.localdomain ([75.28.21.198]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5ba72cb44f4sm586124eaf.40.2024.06.05.10.20.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 10:20:55 -0700 (PDT) From: Chris Morgan To: linux-sunxi@lists.linux.dev Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, p.zabel@pengutronix.de, sboyd@kernel.org, mturquette@baylibre.com, samuel@sholland.org, jernej.skrabec@gmail.com, wens@csie.org, conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org, Chris Morgan Subject: [PATCH V2 1/4] dt-bindings: clock: sun50i-h616-ccu: Add GPADC clocks Date: Wed, 5 Jun 2024 12:20:46 -0500 Message-Id: <20240605172049.231108-2-macroalpha82@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240605172049.231108-1-macroalpha82@gmail.com> References: <20240605172049.231108-1-macroalpha82@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chris Morgan Add the required clock bindings for the GPADC. Signed-off-by: Chris Morgan Acked-by: Conor Dooley --- include/dt-bindings/clock/sun50i-h616-ccu.h | 1 + include/dt-bindings/reset/sun50i-h616-ccu.h | 1 + 2 files changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h index 6f8f01e67628..ebb146ab7f8c 100644 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h @@ -112,5 +112,6 @@ #define CLK_HDCP 126 #define CLK_BUS_HDCP 127 #define CLK_PLL_SYSTEM_32K 128 +#define CLK_BUS_GPADC 129 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h index 1bd8bb0a11be..ed177c04afdd 100644 --- a/include/dt-bindings/reset/sun50i-h616-ccu.h +++ b/include/dt-bindings/reset/sun50i-h616-ccu.h @@ -66,5 +66,6 @@ #define RST_BUS_TVE0 57 #define RST_BUS_HDCP 58 #define RST_BUS_KEYADC 59 +#define RST_BUS_GPADC 60 #endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */ From patchwork Wed Jun 5 17:20:47 2024 Content-Type: text/plain; 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Signed-off-by: Chris Morgan --- drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 5 +++++ drivers/clk/sunxi-ng/ccu-sun50i-h616.h | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c index 45aae1ae5178..64f476c46f5b 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c @@ -489,6 +489,8 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0, static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0); +static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0); + static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0); static const char * const audio_parents[] = { "pll-audio-1x", "pll-audio-2x", @@ -807,6 +809,7 @@ static struct ccu_common *sun50i_h616_ccu_clks[] = { &bus_emac1_clk.common, &ts_clk.common, &bus_ts_clk.common, + &bus_gpadc_clk.common, &bus_ths_clk.common, &spdif_clk.common, &bus_spdif_clk.common, @@ -940,6 +943,7 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = { [CLK_BUS_EMAC1] = &bus_emac1_clk.common.hw, [CLK_TS] = &ts_clk.common.hw, [CLK_BUS_TS] = &bus_ts_clk.common.hw, + [CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw, [CLK_BUS_THS] = &bus_ths_clk.common.hw, [CLK_SPDIF] = &spdif_clk.common.hw, [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, @@ -1021,6 +1025,7 @@ static struct ccu_reset_map sun50i_h616_ccu_resets[] = { [RST_BUS_EMAC0] = { 0x97c, BIT(16) }, [RST_BUS_EMAC1] = { 0x97c, BIT(17) }, [RST_BUS_TS] = { 0x9bc, BIT(16) }, + [RST_BUS_GPADC] = { 0x9ec, BIT(16) }, [RST_BUS_THS] = { 0x9fc, BIT(16) }, [RST_BUS_SPDIF] = { 0xa2c, BIT(16) }, [RST_BUS_DMIC] = { 0xa4c, BIT(16) }, diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.h b/drivers/clk/sunxi-ng/ccu-sun50i-h616.h index fdd2f4d5103f..a75803b49f6a 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.h +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.h @@ -51,6 +51,6 @@ #define CLK_BUS_DRAM 56 -#define CLK_NUMBER (CLK_PLL_SYSTEM_32K + 1) +#define CLK_NUMBER (CLK_BUS_GPADC + 1) #endif /* _CCU_SUN50I_H616_H_ */ From patchwork Wed Jun 5 17:20:48 2024 Content-Type: text/plain; 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Reviewed-by: Andre Przywara Signed-off-by: Chris Morgan --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index 921d5f61d8d6..30ebc0d23760 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -589,6 +589,17 @@ spdif: spdif@5093000 { status = "disabled"; }; + gpadc: adc@5070000 { + compatible = "allwinner,sun50i-h616-gpadc", + "allwinner,sun20i-d1-gpadc"; + reg = <0x05070000 0x400>; + clocks = <&ccu CLK_BUS_GPADC>; + resets = <&ccu RST_BUS_GPADC>; + interrupts = ; + status = "disabled"; + #io-channel-cells = <1>; + }; + ths: thermal-sensor@5070400 { compatible = "allwinner,sun50i-h616-ths"; reg = <0x05070400 0x400>; From patchwork Wed Jun 5 17:20:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Morgan X-Patchwork-Id: 13687171 Received: from mail-oo1-f54.google.com (mail-oo1-f54.google.com [209.85.161.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE2712770E; 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Wed, 05 Jun 2024 10:20:57 -0700 (PDT) Received: from localhost.localdomain ([75.28.21.198]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5ba72cb44f4sm586124eaf.40.2024.06.05.10.20.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 10:20:57 -0700 (PDT) From: Chris Morgan To: linux-sunxi@lists.linux.dev Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, p.zabel@pengutronix.de, sboyd@kernel.org, mturquette@baylibre.com, samuel@sholland.org, jernej.skrabec@gmail.com, wens@csie.org, conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org, Chris Morgan Subject: [PATCH V2 4/4] arm64: dts: allwinner: anbernic-rg35xx-h: Add ADC joysticks Date: Wed, 5 Jun 2024 12:20:49 -0500 Message-Id: <20240605172049.231108-5-macroalpha82@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240605172049.231108-1-macroalpha82@gmail.com> References: <20240605172049.231108-1-macroalpha82@gmail.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Chris Morgan Add support for the ADC joysticks found on the Anbernic RG35XX-H. The joysticks use one channel of the GPADC which is muxed 4 ways by an ADC mux. Signed-off-by: Chris Morgan --- .../sun50i-h700-anbernic-rg35xx-h.dts | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts index 63036256917f..ff453336eab1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h700-anbernic-rg35xx-h.dts @@ -9,6 +9,78 @@ / { model = "Anbernic RG35XX H"; compatible = "anbernic,rg35xx-h", "allwinner,sun50i-h700"; + + adc-joystick { + compatible = "adc-joystick"; + io-channels = <&adc_mux 0>, + <&adc_mux 1>, + <&adc_mux 2>, + <&adc_mux 3>; + pinctrl-0 = <&joy_mux_pin>; + pinctrl-names = "default"; + poll-interval = <60>; + #address-cells = <1>; + #size-cells = <0>; + + axis@0 { + reg = <0>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <4096 0>; + linux,code = ; + }; + + axis@1 { + reg = <1>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <0 4096>; + linux,code = ; + }; + + axis@2 { + reg = <2>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <0 4096>; + linux,code = ; + }; + + axis@3 { + reg = <3>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <4096 0>; + linux,code = ; + }; + }; + + adc_mux: adc-mux { + compatible = "io-channel-mux"; + channels = "left_x", "left_y", "right_x", "right_y"; + #io-channel-cells = <1>; + io-channels = <&gpadc 0>; + io-channel-names = "parent"; + mux-controls = <&gpio_mux>; + settle-time-us = <100>; + }; + + gpio_mux: mux-controller { + compatible = "gpio-mux"; + mux-gpios = <&pio 8 1 GPIO_ACTIVE_LOW>, + <&pio 8 2 GPIO_ACTIVE_LOW>; + #mux-control-cells = <0>; + }; +}; + +&gpadc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@0 { + reg = <0>; + }; }; &gpio_keys_gamepad { @@ -34,3 +106,10 @@ &ehci1 { &ohci1 { status = "okay"; }; + +&pio { + joy_mux_pin: joy-mux-pin { + pins = "PI0"; + function = "gpio_out"; + }; +};