From patchwork Thu Jun 6 11:15:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13688316 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F2182C25B75 for ; Thu, 6 Jun 2024 11:16:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7DB9710E8EE; Thu, 6 Jun 2024 11:16:14 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="EX/RX0tz"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 387D710E8EE for ; Thu, 6 Jun 2024 11:16:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717672573; x=1749208573; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6oSQBAhOAErlWSQp3E5acchQsTJmWax9lcEcVvgUGFk=; b=EX/RX0tzog1V49Mm6ve66eeC+Q5TiB+qIWK8GQXPWaXw3kZ4FAmCrToe 5FtgKg1q1k5MCsbcg6cf6G8Mv53yXb2dpVTaCPDwGekMNcNFinW/y1c3/ kW70xfKNRt+LSBaw6JRpUczWN64GhywNuTRMWL9ovKCnqgvXczYgXyhbT Id0ptNXh/ATIYUNb7DOtFd7MDFzvhsIzfC9scnDfEf8uqt8Y9QIZ/gfPw zxC7Ch76aaSk4rTfP1rBJaOzQeD84js43SnaLfHfVPbbfoogjsRlnkgHF LqjihbjGntWFXcop67ZARxC8uV0VtDcUKYZKsCXaIoZv2jMOQRKmpTVtr A==; X-CSE-ConnectionGUID: XIkZTak7QcOwRNtHpnvMNA== X-CSE-MsgGUID: wWz7Ei0MR/er6i5X+4t98A== X-IronPort-AV: E=McAfee;i="6600,9927,11094"; a="17265506" X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="17265506" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:13 -0700 X-CSE-ConnectionGUID: Xb9eGwMpRVuZQuz1PGzuXQ== X-CSE-MsgGUID: 2R4Sok0iQ6eAfPX5XkWsSw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="38046772" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:12 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, Matt Roper Subject: [PATCH v2 01/14] drm/i915/wm: rename intel_get_cxsr_latency -> pnv_get_cxsr_latency Date: Thu, 6 Jun 2024 14:15:53 +0300 Message-Id: <584010ddd2da8956212eff5e60c1b7568b7acf79.1717672515.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Clarify that the function is specific to PNV, making subsequent changes slightly easier to grasp. Reviewed-by: Matt Roper Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_wm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c index 628e7192ebc9..8657ec0abd2d 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.c +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c @@ -70,7 +70,7 @@ static const struct cxsr_latency cxsr_latency_table[] = { {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ }; -static const struct cxsr_latency *intel_get_cxsr_latency(struct drm_i915_private *i915) +static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *i915) { int i; @@ -635,7 +635,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv) u32 reg; unsigned int wm; - latency = intel_get_cxsr_latency(dev_priv); + latency = pnv_get_cxsr_latency(dev_priv); if (!latency) { drm_dbg_kms(&dev_priv->drm, "Unknown FSB/MEM found, disable CxSR\n"); @@ -4022,7 +4022,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv) g4x_setup_wm_latency(dev_priv); dev_priv->display.funcs.wm = &g4x_wm_funcs; } else if (IS_PINEVIEW(dev_priv)) { - if (!intel_get_cxsr_latency(dev_priv)) { + if (!pnv_get_cxsr_latency(dev_priv)) { drm_info(&dev_priv->drm, "failed to find known CxSR latency " "(found ddr%s fsb freq %d, mem freq %d), " From patchwork Thu Jun 6 11:15:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13688317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C47C7C25B75 for ; Thu, 6 Jun 2024 11:16:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2F3DE10E8F3; Thu, 6 Jun 2024 11:16:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="WG18fcu6"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5F05710E8F3 for ; Thu, 6 Jun 2024 11:16:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717672576; x=1749208576; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KGWh5nAoRiryOPfY/UO+MgJK+3vymcf5YMVa+FPJl20=; b=WG18fcu6yNyIOnwQJ9s8+9pehJ+NixwecUaET7SgtSN5e680v/vm28Bg SCJrzVkJ9QVlVjYTZy26YkSLLDbr+B5UBVwcYvdrzuG/J2YwrinFJAm1w u4xOOOCRKm7WTAuZnvDrL72GRivjiBDB+mgtZmL4JMfHhlz5kKPm0LwYK Kl2+NjGWbsYwcQYkqgRJXQ9v7Kv0y4eVxUO4LUs2uXpIN4OTn+KJdWMd3 x/+n5Vhfav7mARr/IYMZpFIjVjm2i3HeHqKKk0BeXGL8KjfTvlaG/55KD KmgC2hVxl2/gGiVmeNQQuapMUyw4jlii8KxlTPzoRoe1efkcmCMruxumc A==; X-CSE-ConnectionGUID: hKIqWGt/SXSSUMYCoKCiWQ== X-CSE-MsgGUID: VPu3LfT8QQ+YXK/k4PsIaw== X-IronPort-AV: E=McAfee;i="6600,9927,11094"; a="17265514" X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="17265514" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:16 -0700 X-CSE-ConnectionGUID: iBLEmm3eS7mb9e3CYV5oKg== X-CSE-MsgGUID: HRf0nCZcTE+xeer7gSiXCg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="38046780" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:15 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH v2 02/14] drm/i915/wm: clarify logging on not finding CxSR latency config Date: Thu, 6 Jun 2024 14:15:54 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Clarify and unify the logging on not finding PNV CxSR latency config. Just let the i915->fsb_freq == 0 || i915->mem_freq == 0 case go through the table instead of checking for it separately. v2: Do not check for fsb == 0 || mem == 0 separately (Matt) Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_wm.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c index 8657ec0abd2d..a63ecd5cf3b5 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.c +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c @@ -74,9 +74,6 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private * { int i; - if (i915->fsb_freq == 0 || i915->mem_freq == 0) - return NULL; - for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { const struct cxsr_latency *latency = &cxsr_latency_table[i]; bool is_desktop = !IS_MOBILE(i915); @@ -88,7 +85,9 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private * return latency; } - drm_dbg_kms(&i915->drm, "Unknown FSB/MEM found, disable CxSR\n"); + drm_dbg_kms(&i915->drm, + "Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u MHz\n", + i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq); return NULL; } @@ -637,8 +636,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv) latency = pnv_get_cxsr_latency(dev_priv); if (!latency) { - drm_dbg_kms(&dev_priv->drm, - "Unknown FSB/MEM found, disable CxSR\n"); + drm_dbg_kms(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n"); intel_set_memory_cxsr(dev_priv, false); return; } @@ -4023,12 +4021,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv) dev_priv->display.funcs.wm = &g4x_wm_funcs; } else if (IS_PINEVIEW(dev_priv)) { if (!pnv_get_cxsr_latency(dev_priv)) { - drm_info(&dev_priv->drm, - "failed to find known CxSR latency " - "(found ddr%s fsb freq %d, mem freq %d), " - "disabling CxSR\n", - (dev_priv->is_ddr3 == 1) ? "3" : "2", - dev_priv->fsb_freq, dev_priv->mem_freq); + drm_info(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n"); /* Disable CxSR and never update its watermark again */ intel_set_memory_cxsr(dev_priv, false); dev_priv->display.funcs.wm = &nop_funcs; From patchwork Thu Jun 6 11:15:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13688318 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D4545C27C54 for ; Thu, 6 Jun 2024 11:16:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5DF3B10E8F4; Thu, 6 Jun 2024 11:16:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Nv9GoHJr"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6943310E8F4 for ; Thu, 6 Jun 2024 11:16:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717672580; x=1749208580; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w+kl0piwzeO91MGT5ylCfSw/zbFxBOl1C7oOvL2BR/s=; b=Nv9GoHJrqOpwFHY0soh49CG7p8rInIDFyaFN5NAHoHrTznJZcKPdLirx oSdMM/XwAcaQDhhzZgmojjfihIch1kBE2c5mbd4XS7tl77hEyqJ+sv0TC 1xVp+FRSLTviiKSpQNLz/pZpgrwFUe/dORUh1hrfx7ndSHKnNvWs7urUt qq5RLn33ROHefOLLRtHU51OCWrBG1Ke8NrOLhuicMQNDpIyCqzfsX/A+Y iMjkLWImB46SvzqVoWxZiW9BkY3OaHllIMOB4fgilBILFE637/SwsjU/O TzQvNyewBTMM+FI9zv2vVUnp2n8J32FfBIEVC/kTjPmwOc6oFi856opXL w==; X-CSE-ConnectionGUID: 7MI5FkJBRr2oaFwCFqqamA== X-CSE-MsgGUID: 2WlwieUERB2bSCC/gYlf/A== X-IronPort-AV: E=McAfee;i="6600,9927,11094"; a="14468043" X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="14468043" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:20 -0700 X-CSE-ConnectionGUID: HMI5XRviRO+smZnfBGL2Kw== X-CSE-MsgGUID: ioSMFkjkQS654Mc/CiE7fw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="38003782" Received: from unknown (HELO localhost) ([10.237.66.160]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:19 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, Matt Roper Subject: [PATCH v2 03/14] drm/i915/dram: separate fsb freq detection from mem freq Date: Thu, 6 Jun 2024 14:15:55 +0300 Message-Id: <751af8b3cf9a571da16ae6727053974fe4544ddb.1717672515.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To simplify further changes, add separate functions for reading the fsb frequency. This ends up reading CLKCFG register twice, but it's not a big deal. Reviewed-by: Matt Roper Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/soc/intel_dram.c | 106 +++++++++++++++----------- 1 file changed, 60 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index 18a879e98f03..3dce9b9a2c5e 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -49,21 +49,6 @@ static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv) tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG); - switch (tmp & CLKCFG_FSB_MASK) { - case CLKCFG_FSB_533: - dev_priv->fsb_freq = 533; /* 133*4 */ - break; - case CLKCFG_FSB_800: - dev_priv->fsb_freq = 800; /* 200*4 */ - break; - case CLKCFG_FSB_667: - dev_priv->fsb_freq = 667; /* 167*4 */ - break; - case CLKCFG_FSB_400: - dev_priv->fsb_freq = 400; /* 100*4 */ - break; - } - switch (tmp & CLKCFG_MEM_MASK) { case CLKCFG_MEM_533: dev_priv->mem_freq = 533; @@ -83,7 +68,7 @@ static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv) static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv) { - u16 ddrpll, csipll; + u16 ddrpll; ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1); switch (ddrpll & 0xff) { @@ -105,36 +90,6 @@ static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv) dev_priv->mem_freq = 0; break; } - - csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0); - switch (csipll & 0x3ff) { - case 0x00c: - dev_priv->fsb_freq = 3200; - break; - case 0x00e: - dev_priv->fsb_freq = 3733; - break; - case 0x010: - dev_priv->fsb_freq = 4266; - break; - case 0x012: - dev_priv->fsb_freq = 4800; - break; - case 0x014: - dev_priv->fsb_freq = 5333; - break; - case 0x016: - dev_priv->fsb_freq = 5866; - break; - case 0x018: - dev_priv->fsb_freq = 6400; - break; - default: - drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", - csipll & 0x3ff); - dev_priv->fsb_freq = 0; - break; - } } static void chv_detect_mem_freq(struct drm_i915_private *i915) @@ -192,6 +147,64 @@ static void detect_mem_freq(struct drm_i915_private *i915) drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq); } +static unsigned int pnv_fsb_freq(struct drm_i915_private *i915) +{ + u32 fsb; + + fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK; + + switch (fsb) { + case CLKCFG_FSB_400: + return 400; + case CLKCFG_FSB_533: + return 533; + case CLKCFG_FSB_667: + return 667; + case CLKCFG_FSB_800: + return 800; + } + + return 0; +} + +static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv) +{ + u16 fsb; + + fsb = intel_uncore_read16(&dev_priv->uncore, CSIPLL0) & 0x3ff; + + switch (fsb) { + case 0x00c: + return 3200; + case 0x00e: + return 3733; + case 0x010: + return 4266; + case 0x012: + return 4800; + case 0x014: + return 5333; + case 0x016: + return 5866; + case 0x018: + return 6400; + default: + drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", fsb); + return 0; + } +} + +static void detect_fsb_freq(struct drm_i915_private *i915) +{ + if (GRAPHICS_VER(i915) == 5) + i915->fsb_freq = ilk_fsb_freq(i915); + else if (IS_PINEVIEW(i915)) + i915->fsb_freq = pnv_fsb_freq(i915); + + if (i915->fsb_freq) + drm_dbg(&i915->drm, "FSB frequency: %d MHz\n", i915->fsb_freq); +} + static int intel_dimm_num_devices(const struct dram_dimm_info *dimm) { return dimm->ranks * 64 / (dimm->width ?: 1); @@ -661,6 +674,7 @@ void intel_dram_detect(struct drm_i915_private *i915) struct dram_info *dram_info = &i915->dram_info; int ret; + detect_fsb_freq(i915); detect_mem_freq(i915); if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915)) From patchwork Thu Jun 6 11:15:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13688319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB9E4C25B75 for ; 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X-CSE-ConnectionGUID: ffJQVRCjRhe7PYEXO6AmjA== X-CSE-MsgGUID: Z2LLmCyWSNKfmnOtLE+NZQ== X-IronPort-AV: E=McAfee;i="6600,9927,11094"; a="18123374" X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="18123374" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:24 -0700 X-CSE-ConnectionGUID: 7/7VGe/rT+OE5Eu6xWrN5Q== X-CSE-MsgGUID: d+uSc5lHTiahHOPziRkLsg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="42862865" Received: from unknown (HELO localhost) ([10.237.66.160]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:23 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, Matt Roper Subject: [PATCH v2 04/14] drm/i915/dram: split out pnv DDR3 detection Date: Thu, 6 Jun 2024 14:15:56 +0300 Message-Id: <5cea7f6e36182367027e10a1e027220beb954857.1717672515.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Split out the PNV DDR3 detection to a distinct step instead of conflating it with mem freq detection. Reviewed-by: Matt Roper Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/soc/intel_dram.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index 3dce9b9a2c5e..1a4db52ac258 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -43,6 +43,11 @@ static const char *intel_dram_type_str(enum intel_dram_type type) #undef DRAM_TYPE_STR +static bool pnv_is_ddr3(struct drm_i915_private *i915) +{ + return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3; +} + static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv) { u32 tmp; @@ -60,10 +65,6 @@ static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv) dev_priv->mem_freq = 800; break; } - - /* detect pineview DDR3 setting */ - tmp = intel_uncore_read(&dev_priv->uncore, CSHRDDR3CTL); - dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; } static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv) @@ -143,6 +144,9 @@ static void detect_mem_freq(struct drm_i915_private *i915) else if (IS_VALLEYVIEW(i915)) vlv_detect_mem_freq(i915); + if (IS_PINEVIEW(i915)) + i915->is_ddr3 = pnv_is_ddr3(i915); + if (i915->mem_freq) drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq); } From patchwork Thu Jun 6 11:15:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13688320 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F00BC25B75 for ; Thu, 6 Jun 2024 11:16:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1A31A10E8F7; Thu, 6 Jun 2024 11:16:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="NWoWXDr/"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9EEF410E8F6 for ; Thu, 6 Jun 2024 11:16:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717672587; x=1749208587; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=t41aQwOaZuXlaWJR/Op72xnj72a21vj1tZevFvPMEGM=; b=NWoWXDr/IXUk23PHl5hRvxbk4RHubqu5xbZX7x0D0yF19F2WipQmb8mi c5nMDcRAkYKJTWLmQmSN9qV1mZ6lLVVW6wZQWm/DtpI7cHqJeSiVntvAC 4SIoiu2t2+SiiJcIOm56j77ORbQiDw1MKbXnGot6SkX3ck5jqrvZLt9Hg j1GUKCfRE+CZVIOEm/a8T7pNN8B2hjMNTPck2/sfUfEIHMCfSRYb1M+JU 0MAYPJlRvWFyfP/yQrE7W5GQBcEsXZqRKJF16UuTOChryMcRl4AlzbP1a iscFVdKaQqDb21eXJiY7RLhaJ8Pz0gCeEnFeKrebxyHQg2JOvupEQzuhk g==; X-CSE-ConnectionGUID: 8Z85pkFcS8uJhGakiQaqLQ== X-CSE-MsgGUID: aFI1oAO/QM2HOn24PzN1Vw== X-IronPort-AV: E=McAfee;i="6600,9927,11094"; a="18123376" X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="18123376" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:27 -0700 X-CSE-ConnectionGUID: LEb+FmgrQrqQmQU7hzGJLw== X-CSE-MsgGUID: bGvmxN5MRqqZyt2dVjYtjw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="42862881" Received: from unknown (HELO localhost) ([10.237.66.160]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:27 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, Matt Roper Subject: [PATCH v2 05/14] drm/i915/dram: rearrange mem freq init Date: Thu, 6 Jun 2024 14:15:57 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Follow the same style in mem freq init as in fsb freq init, returning the value instead of assigning in multiple places. Reviewed-by: Matt Roper Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/soc/intel_dram.c | 59 ++++++++++++--------------- 1 file changed, 25 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index 1a4db52ac258..266ed6cfa485 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -48,7 +48,7 @@ static bool pnv_is_ddr3(struct drm_i915_private *i915) return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3; } -static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv) +static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv) { u32 tmp; @@ -56,44 +56,38 @@ static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv) switch (tmp & CLKCFG_MEM_MASK) { case CLKCFG_MEM_533: - dev_priv->mem_freq = 533; - break; + return 533; case CLKCFG_MEM_667: - dev_priv->mem_freq = 667; - break; + return 667; case CLKCFG_MEM_800: - dev_priv->mem_freq = 800; - break; + return 800; } + + return 0; } -static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv) +static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv) { u16 ddrpll; ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1); switch (ddrpll & 0xff) { case 0xc: - dev_priv->mem_freq = 800; - break; + return 800; case 0x10: - dev_priv->mem_freq = 1066; - break; + return 1066; case 0x14: - dev_priv->mem_freq = 1333; - break; + return 1333; case 0x18: - dev_priv->mem_freq = 1600; - break; + return 1600; default: drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n", ddrpll & 0xff); - dev_priv->mem_freq = 0; - break; + return 0; } } -static void chv_detect_mem_freq(struct drm_i915_private *i915) +static unsigned int chv_mem_freq(struct drm_i915_private *i915) { u32 val; @@ -103,15 +97,13 @@ static void chv_detect_mem_freq(struct drm_i915_private *i915) switch ((val >> 2) & 0x7) { case 3: - i915->mem_freq = 2000; - break; + return 2000; default: - i915->mem_freq = 1600; - break; + return 1600; } } -static void vlv_detect_mem_freq(struct drm_i915_private *i915) +static unsigned int vlv_mem_freq(struct drm_i915_private *i915) { u32 val; @@ -122,27 +114,26 @@ static void vlv_detect_mem_freq(struct drm_i915_private *i915) switch ((val >> 6) & 3) { case 0: case 1: - i915->mem_freq = 800; - break; + return 800; case 2: - i915->mem_freq = 1066; - break; + return 1066; case 3: - i915->mem_freq = 1333; - break; + return 1333; } + + return 0; } static void detect_mem_freq(struct drm_i915_private *i915) { if (IS_PINEVIEW(i915)) - pnv_detect_mem_freq(i915); + i915->mem_freq = pnv_mem_freq(i915); else if (GRAPHICS_VER(i915) == 5) - ilk_detect_mem_freq(i915); + i915->mem_freq = ilk_mem_freq(i915); else if (IS_CHERRYVIEW(i915)) - chv_detect_mem_freq(i915); + i915->mem_freq = chv_mem_freq(i915); else if (IS_VALLEYVIEW(i915)) - vlv_detect_mem_freq(i915); + i915->mem_freq = vlv_mem_freq(i915); if (IS_PINEVIEW(i915)) i915->is_ddr3 = pnv_is_ddr3(i915); From patchwork Thu Jun 6 11:15:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13688321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65112C25B75 for ; Thu, 6 Jun 2024 11:16:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DCBAC10E8F9; Thu, 6 Jun 2024 11:16:32 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Z7yuM9u8"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3F94F10E8F9 for ; Thu, 6 Jun 2024 11:16:31 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="38003800" Received: from unknown (HELO localhost) ([10.237.66.160]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:30 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH v2 06/14] drm/i915/gt: remove mem freq from gt debugfs Date: Thu, 6 Jun 2024 14:15:58 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" It's a bit out of place, and only printed for VLV/CHV. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c index 4fcba42cfe34..c1ce6258e55c 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c @@ -367,7 +367,6 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p) vlv_punit_put(i915); drm_printf(p, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); - drm_printf(p, "DDR freq: %d MHz\n", i915->mem_freq); drm_printf(p, "actual GPU freq: %d MHz\n", intel_gpu_freq(rps, (freq_sts >> 8) & 0xff)); From patchwork Thu Jun 6 11:15:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13688322 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A3B5C25B75 for ; Thu, 6 Jun 2024 11:16:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B88D510E8F6; Thu, 6 Jun 2024 11:16:35 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="UYBPClKS"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id D315110E8FA for ; Thu, 6 Jun 2024 11:16:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717672595; x=1749208595; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZydT6WMssmier0flDB0A7VHD7hLRIGY0hqaa7imBYfc=; b=UYBPClKSeg0fr7RH+Y9zldhj3NiBaKVXpELJGuV2786K9Nh1+dMkYDs1 d84yBaM2s+Rch2deZzhnTuIOtvH6UksEk8eETXwCiONguirLkcV8u8j8c Z8FCFPQEPb6qsFvkmyLRtmvJQaFL99ZQHV1RlGvUGsjkCmHob/Pto1Bcl 54rAJbg8MBaaetPO7sYSohL3U1I1yCx0wnUpo4Z8JhwRSy49xuOIzCrR/ 0m8CEeZ4QkbcS+PJIAVLRgwhRyoyCwFfh2cAQMI3s4pUIWYLTOBhuyhMA 2MniIbkRHiBYPe0RPOCnIWIiJU8OnQ1GBC1nUxwxgjkXYJ3MxrzTH9y4m g==; X-CSE-ConnectionGUID: pcyu0LcDSlyRB6cmJulYgw== X-CSE-MsgGUID: n7w8CBViTWOag/yRkzBvtg== X-IronPort-AV: E=McAfee;i="6600,9927,11094"; a="18123389" X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="18123389" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:34 -0700 X-CSE-ConnectionGUID: 5uD3KXMgTc6PkwlAfSY6Fw== X-CSE-MsgGUID: aXymmYZPSx+hDAsZyFeTlw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="42862928" Received: from unknown (HELO localhost) ([10.237.66.160]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:34 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, Matt Roper Subject: [PATCH v2 07/14] drm/i915: convert fsb_freq and mem_freq to kHz Date: Thu, 6 Jun 2024 14:15:59 +0300 Message-Id: <1e3df6485c36998340dfbbfa643550c04f1a92f5.1717672515.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We'll want to use fsb frequency for deriving GT clock and rawclk frequencies in the future. Increase the accuracy by converting to kHz. Do the same for mem freq to be aligned. Round the frequencies ending in 666 to 667. v2: Also handle mem_freq in gen5_rps_init() (Ville) Reviewed-by: Matt Roper Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_wm.c | 6 ++-- drivers/gpu/drm/i915/gt/intel_rps.c | 11 +++--- drivers/gpu/drm/i915/soc/intel_dram.c | 50 +++++++++++++------------- 3 files changed, 34 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c index a63ecd5cf3b5..9e39c1afda7b 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.c +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c @@ -80,13 +80,13 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private * if (is_desktop == latency->is_desktop && i915->is_ddr3 == latency->is_ddr3 && - i915->fsb_freq == latency->fsb_freq && - i915->mem_freq == latency->mem_freq) + DIV_ROUND_CLOSEST(i915->fsb_freq, 1000) == latency->fsb_freq && + DIV_ROUND_CLOSEST(i915->mem_freq, 1000) == latency->mem_freq) return latency; } drm_dbg_kms(&i915->drm, - "Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u MHz\n", + "Could not find CxSR latency for DDR%s, FSB %u kHz, MEM %u kHz\n", i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq); return NULL; diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 70176be269d3..fa304ea088e4 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -265,10 +265,10 @@ static const struct cparams { u16 c; } cparams[] = { { 1, 1333, 301, 28664 }, - { 1, 1066, 294, 24460 }, + { 1, 1067, 294, 24460 }, { 1, 800, 294, 25192 }, { 0, 1333, 276, 27605 }, - { 0, 1066, 276, 27605 }, + { 0, 1067, 276, 27605 }, { 0, 800, 231, 23784 }, }; @@ -280,15 +280,16 @@ static void gen5_rps_init(struct intel_rps *rps) u32 rgvmodectl; int c_m, i; - if (i915->fsb_freq <= 3200) + if (i915->fsb_freq <= 3200000) c_m = 0; - else if (i915->fsb_freq <= 4800) + else if (i915->fsb_freq <= 4800000) c_m = 1; else c_m = 2; for (i = 0; i < ARRAY_SIZE(cparams); i++) { - if (cparams[i].i == c_m && cparams[i].t == i915->mem_freq) { + if (cparams[i].i == c_m && + cparams[i].t == DIV_ROUND_CLOSEST(i915->mem_freq, 1000)) { rps->ips.m = cparams[i].m; rps->ips.c = cparams[i].c; break; diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index 266ed6cfa485..ace9372244a4 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -56,11 +56,11 @@ static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv) switch (tmp & CLKCFG_MEM_MASK) { case CLKCFG_MEM_533: - return 533; + return 533333; case CLKCFG_MEM_667: - return 667; + return 666667; case CLKCFG_MEM_800: - return 800; + return 800000; } return 0; @@ -73,13 +73,13 @@ static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv) ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1); switch (ddrpll & 0xff) { case 0xc: - return 800; + return 800000; case 0x10: - return 1066; + return 1066667; case 0x14: - return 1333; + return 1333333; case 0x18: - return 1600; + return 1600000; default: drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n", ddrpll & 0xff); @@ -97,9 +97,9 @@ static unsigned int chv_mem_freq(struct drm_i915_private *i915) switch ((val >> 2) & 0x7) { case 3: - return 2000; + return 2000000; default: - return 1600; + return 1600000; } } @@ -114,11 +114,11 @@ static unsigned int vlv_mem_freq(struct drm_i915_private *i915) switch ((val >> 6) & 3) { case 0: case 1: - return 800; + return 800000; case 2: - return 1066; + return 1066667; case 3: - return 1333; + return 1333333; } return 0; @@ -139,7 +139,7 @@ static void detect_mem_freq(struct drm_i915_private *i915) i915->is_ddr3 = pnv_is_ddr3(i915); if (i915->mem_freq) - drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq); + drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq); } static unsigned int pnv_fsb_freq(struct drm_i915_private *i915) @@ -150,13 +150,13 @@ static unsigned int pnv_fsb_freq(struct drm_i915_private *i915) switch (fsb) { case CLKCFG_FSB_400: - return 400; + return 400000; case CLKCFG_FSB_533: - return 533; + return 533333; case CLKCFG_FSB_667: - return 667; + return 666667; case CLKCFG_FSB_800: - return 800; + return 800000; } return 0; @@ -170,19 +170,19 @@ static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv) switch (fsb) { case 0x00c: - return 3200; + return 3200000; case 0x00e: - return 3733; + return 3733333; case 0x010: - return 4266; + return 4266667; case 0x012: - return 4800; + return 4800000; case 0x014: - return 5333; + return 5333333; case 0x016: - return 5866; + return 5866667; case 0x018: - return 6400; + return 6400000; default: drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", fsb); return 0; @@ -197,7 +197,7 @@ static void detect_fsb_freq(struct drm_i915_private *i915) i915->fsb_freq = pnv_fsb_freq(i915); if (i915->fsb_freq) - drm_dbg(&i915->drm, "FSB frequency: %d MHz\n", i915->fsb_freq); + drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq); } static int intel_dimm_num_devices(const struct dram_dimm_info *dimm) From patchwork Thu Jun 6 11:16:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13688323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5576C25B75 for ; Thu, 6 Jun 2024 11:16:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5BD8810E8FB; Thu, 6 Jun 2024 11:16:39 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Axyf41aP"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 532ED10E8FA for ; Thu, 6 Jun 2024 11:16:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717672598; x=1749208598; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iTvKIgt9oaAK0ATe4kz9O57rPc7GsvaUqwWetIBJ8yM=; b=Axyf41aPXofaZApRTawdHqtcoBKrv9dajQlXc8xF9xi6BKj6jQMIAhkR UbeK3QTiPXMMhOgz+MSlY6q7xqXclcyY6aqbAyQ+8jeX+Skm+gOMXKLyj /Kk1ent/fMycyuHt1X4J1/XqhH9IDiKzoZSuAJgNRB2HSkWHqtpN/PaEf 0mPRqkegmSt13yS31BuCbsN5/6MwviNxfCBUh2vKA0RDVC0p19RILfJ9Y SJvFmAo7orgTgf64PYJaM5/NRbZ8Nz6vFgAY266vEchnj08iVHK1RwHOg 2TDN+iLGmQxBVlgrSL5l3fUyW1ygP3pe9k7qLL/tfIHENtsVBLxuCjPer Q==; X-CSE-ConnectionGUID: YBA0p8nmRbuAG+CkKDww/A== X-CSE-MsgGUID: kDkhS3tyRImoHClS33jdMg== X-IronPort-AV: E=McAfee;i="6600,9927,11094"; a="14468067" X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="14468067" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:38 -0700 X-CSE-ConnectionGUID: qReUJ3c+R0eSyQivmrdphw== X-CSE-MsgGUID: YXC1MJxxRKq+HRQR9R6uiQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="38003819" Received: from unknown (HELO localhost) ([10.237.66.160]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:37 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH v2 08/14] drm/i915: extend the fsb_freq initialization to more platforms Date: Thu, 6 Jun 2024 14:16:00 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Initialize fsb frequency for more platforms to be able to use it for GT clock and rawclk frequency initialization. Note: There's a discrepancy between existing pnv_fsb_freq() and i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is mobile. Default to 1333 MHz for unknown values, similar to i9xx_hrawclk(). v2: - Add MISSING_CASE() (Ville) - Default to the same frequency for both branches (Ville) Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/soc/intel_dram.c | 55 ++++++++++++++++++++------- 1 file changed, 41 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index ace9372244a4..1b01e5130f79 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -142,24 +142,51 @@ static void detect_mem_freq(struct drm_i915_private *i915) drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq); } -static unsigned int pnv_fsb_freq(struct drm_i915_private *i915) +static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915) { u32 fsb; fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK; - switch (fsb) { - case CLKCFG_FSB_400: - return 400000; - case CLKCFG_FSB_533: - return 533333; - case CLKCFG_FSB_667: - return 666667; - case CLKCFG_FSB_800: - return 800000; + if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) { + switch (fsb) { + case CLKCFG_FSB_400: + return 400000; + case CLKCFG_FSB_533: + return 533333; + case CLKCFG_FSB_667: + return 666667; + case CLKCFG_FSB_800: + return 800000; + case CLKCFG_FSB_1067: + return 1066667; + case CLKCFG_FSB_1333: + return 1333333; + default: + MISSING_CASE(fsb); + return 1333333; + } + } else { + switch (fsb) { + case CLKCFG_FSB_400_ALT: + return 400000; + case CLKCFG_FSB_533: + return 533333; + case CLKCFG_FSB_667: + return 666667; + case CLKCFG_FSB_800: + return 800000; + case CLKCFG_FSB_1067_ALT: + return 1066667; + case CLKCFG_FSB_1333_ALT: + return 1333333; + case CLKCFG_FSB_1600_ALT: + return 1600000; + default: + MISSING_CASE(fsb); + return 1333333; + } } - - return 0; } static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv) @@ -193,8 +220,8 @@ static void detect_fsb_freq(struct drm_i915_private *i915) { if (GRAPHICS_VER(i915) == 5) i915->fsb_freq = ilk_fsb_freq(i915); - else if (IS_PINEVIEW(i915)) - i915->fsb_freq = pnv_fsb_freq(i915); + else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4) + i915->fsb_freq = i9xx_fsb_freq(i915); if (i915->fsb_freq) drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq); From patchwork Thu Jun 6 11:16:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13688324 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 558D0C25B75 for ; Thu, 6 Jun 2024 11:16:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D2BE410E8FA; Thu, 6 Jun 2024 11:16:43 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; 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a="14556686" X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="14556686" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:42 -0700 X-CSE-ConnectionGUID: FqRFW5p1SnS305kl0uPI1Q== X-CSE-MsgGUID: DMm1WLAxTZq8ChXdzdEWmg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="38494535" Received: from unknown (HELO localhost) ([10.237.66.160]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:40 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH v2 09/14] drm/i915: use i9xx_fsb_freq() for GT clock frequency Date: Thu, 6 Jun 2024 14:16:01 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Reuse i9xx_fsb_freq() for GT clock frequency initialization instead of depending on rawclk_freq. Note: If the init order was changed, we could use i915->fsb_freq directly. However, GT clock initialization is done in i915_driver_mmio_probe(), but intel_dram_detect() later in i915_driver_hw_probe(), with a dependency on intel_pcode_init(). Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 3 ++- drivers/gpu/drm/i915/soc/intel_dram.c | 2 +- drivers/gpu/drm/i915/soc/intel_dram.h | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c index 7c9be4fd1c8c..6e63505fe478 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c @@ -9,6 +9,7 @@ #include "intel_gt_clock_utils.h" #include "intel_gt_print.h" #include "intel_gt_regs.h" +#include "soc/intel_dram.h" static u32 read_reference_ts_freq(struct intel_uncore *uncore) { @@ -151,7 +152,7 @@ static u32 gen4_read_clock_frequency(struct intel_uncore *uncore) * * Testing on actual hardware has shown there is no /16. */ - return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000; + return DIV_ROUND_CLOSEST(i9xx_fsb_freq(uncore->i915), 4) * 1000; } static u32 read_clock_frequency(struct intel_uncore *uncore) diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index 1b01e5130f79..dac39b41fa51 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -142,7 +142,7 @@ static void detect_mem_freq(struct drm_i915_private *i915) drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq); } -static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915) +unsigned int i9xx_fsb_freq(struct drm_i915_private *i915) { u32 fsb; diff --git a/drivers/gpu/drm/i915/soc/intel_dram.h b/drivers/gpu/drm/i915/soc/intel_dram.h index 4ba13c13162c..a10136eda674 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.h +++ b/drivers/gpu/drm/i915/soc/intel_dram.h @@ -10,5 +10,6 @@ struct drm_i915_private; void intel_dram_edram_detect(struct drm_i915_private *i915); void intel_dram_detect(struct drm_i915_private *i915); +unsigned int i9xx_fsb_freq(struct drm_i915_private *i915); #endif /* __INTEL_DRAM_H__ */ From patchwork Thu Jun 6 11:16:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13688325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8E7CC27C55 for ; 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X-CSE-ConnectionGUID: IBv49jVNQgGd2z+HWB2Kyg== X-CSE-MsgGUID: k4bJO8iWQS2EcirArpWx4Q== X-IronPort-AV: E=McAfee;i="6600,9927,11094"; a="14468072" X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="14468072" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:45 -0700 X-CSE-ConnectionGUID: 6NT2+11DQb+4rZDJCdNrdQ== X-CSE-MsgGUID: 0XQOX4x4SBuAEeQtpjp2uQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="38003833" Received: from unknown (HELO localhost) ([10.237.66.160]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:44 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH v2 10/14] drm/i915/cdclk: use i9xx_fsb_freq() for rawclk_freq initialization Date: Thu, 6 Jun 2024 14:16:02 +0300 Message-Id: <8117cc078ec43e91eb3b2f626f02f8399306e570.1717672515.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Instead of duplicating the CLKCFG parsing, reuse i9xx_fsb_freq() to figure out rawclk_freq where applicable. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cdclk.c | 46 ++-------------------- 1 file changed, 3 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 7ef8dcb1601a..7e93984eba11 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -23,6 +23,7 @@ #include +#include "soc/intel_dram.h" #include "hsw_ips.h" #include "i915_reg.h" #include "intel_atomic.h" @@ -3539,10 +3540,8 @@ static int vlv_hrawclk(struct drm_i915_private *dev_priv) CCK_DISPLAY_REF_CLOCK_CONTROL); } -static int i9xx_hrawclk(struct drm_i915_private *dev_priv) +static int i9xx_hrawclk(struct drm_i915_private *i915) { - u32 clkcfg; - /* * hrawclock is 1/4 the FSB frequency * @@ -3553,46 +3552,7 @@ static int i9xx_hrawclk(struct drm_i915_private *dev_priv) * don't know which registers have that information, * and all the relevant docs have gone to bit heaven :( */ - clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; - - if (IS_MOBILE(dev_priv)) { - switch (clkcfg) { - case CLKCFG_FSB_400: - return 100000; - case CLKCFG_FSB_533: - return 133333; - case CLKCFG_FSB_667: - return 166667; - case CLKCFG_FSB_800: - return 200000; - case CLKCFG_FSB_1067: - return 266667; - case CLKCFG_FSB_1333: - return 333333; - default: - MISSING_CASE(clkcfg); - return 133333; - } - } else { - switch (clkcfg) { - case CLKCFG_FSB_400_ALT: - return 100000; - case CLKCFG_FSB_533: - return 133333; - case CLKCFG_FSB_667: - return 166667; - case CLKCFG_FSB_800: - return 200000; - case CLKCFG_FSB_1067_ALT: - return 266667; - case CLKCFG_FSB_1333_ALT: - return 333333; - case CLKCFG_FSB_1600_ALT: - return 400000; - default: - return 133333; - } - } + return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4); } /** From patchwork Thu Jun 6 11:16:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13688326 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EAEDDC27C54 for ; Thu, 6 Jun 2024 11:16:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 42E8E10E8F8; Thu, 6 Jun 2024 11:16:50 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="GeCpPVOV"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id B29F010E8F8 for ; Thu, 6 Jun 2024 11:16:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717672609; x=1749208609; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YMKUufCMbLazXrghgwvNa0mnMZFNnm6yTWphataPkzw=; b=GeCpPVOV+s0KrCLZvsVZC7FcJXc4WIoGn6pdeQhtZUqD7yTlwqLA6cVB tA/j4yHyCTlABsnW+23lQfv974cD0F2lQ8hGtWpjERacX8ehAcC3erAGW EDoDz26haqCTn8mnDMYN8B92Cx5ZwAuKvamtsPh8TusRRC3VJ/M9Ezxuc +xlVs1Ci9s5b7oaYnn4ighzDb7K8bmYgJXEHuHq0efauLcxTiz9ZKPaHZ h/4025GJat5U3iTl3gR0rZZkkAm8aFaK3FfU2smJxmxfCAySjy9t+36ba ZndC8HUKhe/+ig52aUbbmzHJdELzI6alEuH1g4YaXpMeAPHsiSFMcU2Pr g==; X-CSE-ConnectionGUID: 3pBCCWM5Rvux4PqayNxlZQ== X-CSE-MsgGUID: 6wBBvTwMShKhiH6n5J6FVA== X-IronPort-AV: E=McAfee;i="6600,9927,11094"; a="14556694" X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="14556694" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:48 -0700 X-CSE-ConnectionGUID: D0e8OfbLSZWZAx8Pam36UQ== X-CSE-MsgGUID: n04sj7qgTCCa0efnYc2TIA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="38494564" Received: from unknown (HELO localhost) ([10.237.66.160]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:47 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH v2 11/14] drm/i915: move rawclk init to intel_cdclk_init() Date: Thu, 6 Jun 2024 14:16:03 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The rawclk initialization is a bit out of place in intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a bit of refactoring on intel_read_rawclk(). Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++----------- drivers/gpu/drm/i915/display/intel_cdclk.h | 1 - drivers/gpu/drm/i915/intel_device_info.c | 4 ---- 3 files changed, 11 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 7e93984eba11..cfb7d4e2f05e 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -3228,6 +3228,8 @@ int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joi return intel_atomic_lock_global_state(&cdclk_state->base); } +static void intel_rawclk_init(struct drm_i915_private *dev_priv); + int intel_cdclk_init(struct drm_i915_private *dev_priv) { struct intel_cdclk_state *cdclk_state; @@ -3239,6 +3241,8 @@ int intel_cdclk_init(struct drm_i915_private *dev_priv) intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, &cdclk_state->base, &intel_cdclk_funcs); + intel_rawclk_init(dev_priv); + return 0; } @@ -3555,16 +3559,13 @@ static int i9xx_hrawclk(struct drm_i915_private *i915) return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4); } -/** - * intel_read_rawclk - Determine the current RAWCLK frequency - * @dev_priv: i915 device - * - * Determine the current RAWCLK frequency. RAWCLK is a fixed - * frequency clock so this needs to done only once. +/* + * Initialize the current RAWCLK frequency. RAWCLK is a fixed frequency clock so + * this needs to done only once. */ -u32 intel_read_rawclk(struct drm_i915_private *dev_priv) +static void intel_rawclk_init(struct drm_i915_private *dev_priv) { - u32 freq; + u32 freq = 0; if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL) /* @@ -3583,11 +3584,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) freq = vlv_hrawclk(dev_priv); else if (DISPLAY_VER(dev_priv) >= 3) freq = i9xx_hrawclk(dev_priv); - else - /* no rawclk on other platforms, or no need to know it */ - return 0; - return freq; + RUNTIME_INFO(dev_priv)->rawclk_freq = freq; + drm_dbg_kms(&dev_priv->drm, "rawclk rate: %d kHz\n", freq); } static int i915_cdclk_info_show(struct seq_file *m, void *unused) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index cfdcdec07a4d..a3f950d5a366 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -64,7 +64,6 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915); void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); void intel_update_max_cdclk(struct drm_i915_private *dev_priv); void intel_update_cdclk(struct drm_i915_private *dev_priv); -u32 intel_read_rawclk(struct drm_i915_private *dev_priv); bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b); int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915, diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index d26de37719a7..365bb7a10030 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -370,10 +370,6 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) "Disabling ppGTT for VT-d support\n"); runtime->ppgtt_type = INTEL_PPGTT_NONE; } - - runtime->rawclk_freq = intel_read_rawclk(dev_priv); - drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); - } /* From patchwork Thu Jun 6 11:16:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13688327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1C121C25B75 for ; Thu, 6 Jun 2024 11:16:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D1E010E8FC; Thu, 6 Jun 2024 11:16:53 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="blFA0A20"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4306110E902 for ; Thu, 6 Jun 2024 11:16:52 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="38020196" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:50 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH v2 12/14] drm/i915: move rawclk from runtime to display runtime info Date: Thu, 6 Jun 2024 14:16:04 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" It's mostly about display, so move it under display. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_backlight.c | 10 +++++----- drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- drivers/gpu/drm/i915/display/intel_display_device.c | 2 ++ drivers/gpu/drm/i915/display/intel_display_device.h | 2 ++ .../gpu/drm/i915/display/intel_display_power_well.c | 4 ++-- drivers/gpu/drm/i915/display/intel_dp_aux.c | 4 ++-- drivers/gpu/drm/i915/display/intel_pps.c | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 1 - drivers/gpu/drm/i915/intel_device_info.h | 2 -- 9 files changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c index 071668bfe5d1..66ee925287c2 100644 --- a/drivers/gpu/drm/i915/display/intel_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_backlight.c @@ -1011,7 +1011,7 @@ static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) { struct drm_i915_private *i915 = to_i915(connector->base.dev); - return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq), + return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq), pwm_freq_hz); } @@ -1073,7 +1073,7 @@ static u32 pch_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) { struct drm_i915_private *i915 = to_i915(connector->base.dev); - return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq), + return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq), pwm_freq_hz * 128); } @@ -1091,7 +1091,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) int clock; if (IS_PINEVIEW(i915)) - clock = KHz(RUNTIME_INFO(i915)->rawclk_freq); + clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq); else clock = KHz(i915->display.cdclk.hw.cdclk); @@ -1109,7 +1109,7 @@ static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) int clock; if (IS_G4X(i915)) - clock = KHz(RUNTIME_INFO(i915)->rawclk_freq); + clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq); else clock = KHz(i915->display.cdclk.hw.cdclk); @@ -1133,7 +1133,7 @@ static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) clock = MHz(25); mul = 16; } else { - clock = KHz(RUNTIME_INFO(i915)->rawclk_freq); + clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq); mul = 128; } diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index cfb7d4e2f05e..17d04353b2b0 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -3585,7 +3585,7 @@ static void intel_rawclk_init(struct drm_i915_private *dev_priv) else if (DISPLAY_VER(dev_priv) >= 3) freq = i9xx_hrawclk(dev_priv); - RUNTIME_INFO(dev_priv)->rawclk_freq = freq; + DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq = freq; drm_dbg_kms(&dev_priv->drm, "rawclk rate: %d kHz\n", freq); } diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index b35422da7f6c..f10996b0b41d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -1511,6 +1511,8 @@ void intel_display_device_info_print(const struct intel_display_device_info *inf drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp)); drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc)); drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc)); + + drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq); } /* diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index e1d9947394dc..2dcfdcdf69bd 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -201,6 +201,8 @@ struct intel_display_runtime_info { u16 step; } ip; + u32 rawclk_freq; + u8 pipe_mask; u8 cpu_transcoder_mask; u16 port_mask; diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 83f616097a29..a6b156c4388e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -1176,9 +1176,9 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); intel_de_write(dev_priv, CBR1_VLV, 0); - drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0); + drm_WARN_ON(&dev_priv->drm, DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq == 0); intel_de_write(dev_priv, RAWCLK_FREQ_VLV, - DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, + DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq, 1000)); } diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index b8a53bb174da..cbc817bb0cc3 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -83,7 +83,7 @@ static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) * The clock divider is based off the hrawclk, and would like to run at * 2MHz. So, take the hrawclk value and divide by 2000 and use that */ - return DIV_ROUND_CLOSEST(RUNTIME_INFO(i915)->rawclk_freq, 2000); + return DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq, 2000); } static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) @@ -103,7 +103,7 @@ static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) if (dig_port->aux_ch == AUX_CH_A) freq = i915->display.cdclk.hw.cdclk; else - freq = RUNTIME_INFO(i915)->rawclk_freq; + freq = DISPLAY_RUNTIME_INFO(i915)->rawclk_freq; return DIV_ROUND_CLOSEST(freq, 2000); } diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 73046ef58d8e..8ca2800f614c 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -1468,7 +1468,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u32 pp_on, pp_off, port_sel = 0; - int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000; + int div = DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq / 1000; struct pps_registers regs; enum port port = dp_to_dig_port(intel_dp)->base.port; const struct edp_power_seq *seq = &intel_dp->pps.pps_delays; diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 365bb7a10030..91acbf99574c 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -124,7 +124,6 @@ void intel_device_info_print(const struct intel_device_info *info, #undef PRINT_FLAG drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu)); - drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq); } #define ID(id) (id) diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index d1a2abc7e513..fb8a08623eb0 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -204,8 +204,6 @@ struct intel_runtime_info { u16 device_id; - u32 rawclk_freq; - struct intel_step_info step; unsigned int page_sizes; /* page sizes supported by the HW */ From patchwork Thu Jun 6 11:16:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13688328 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7116AC25B75 for ; Thu, 6 Jun 2024 11:17:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EC95710E8FE; Thu, 6 Jun 2024 11:17:00 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mNv6sA56"; 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d="scan'208";a="14556707" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:55 -0700 X-CSE-ConnectionGUID: 11UkGo2IT6mXftDMxDdKWg== X-CSE-MsgGUID: +SmXX58bT6aMK29W0vL2UA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="38494571" Received: from unknown (HELO localhost) ([10.237.66.160]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:54 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH v2 13/14] drm/xe/display: drop unused rawclk_freq and RUNTIME_INFO() Date: Thu, 6 Jun 2024 14:16:05 +0300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With rawclk_freq moved to display runtime info, xe has no users left for them. Signed-off-by: Jani Nikula --- drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 - drivers/gpu/drm/xe/xe_device_types.h | 6 ------ 2 files changed, 7 deletions(-) diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index cd4632276141..6c5830875091 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -181,7 +181,6 @@ struct i915_sched_attr { intel_runtime_pm_put((rpm), (wf)), (wf) = 0) #define pdev_to_i915 pdev_to_xe_device -#define RUNTIME_INFO(xe) (&(xe)->info.i915_runtime) #define FORCEWAKE_ALL XE_FORCEWAKE_ALL diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index f1c09824b145..bb24384b10a2 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -290,12 +290,6 @@ struct xe_device { u8 has_atomic_enable_pte_bit:1; /** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */ u8 has_device_atomics_on_smem:1; - -#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) - struct { - u32 rawclk_freq; - } i915_runtime; -#endif } info; /** @irq: device interrupt state */ From patchwork Thu Jun 6 11:16:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13688329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5FB8CC25B75 for ; Thu, 6 Jun 2024 11:17:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E717A10E900; Thu, 6 Jun 2024 11:17:17 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="oFkxDsLV"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id BBFC210E900 for ; Thu, 6 Jun 2024 11:17:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1717672636; x=1749208636; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZOgEAiHEWiyAbTzpi8HJDXU3VSU9aBW5O3T3mfOUm/0=; b=oFkxDsLVEQK6y43C+9yqF5fr7Fu9oZP5FMwkbyE+sLuP83TX+Z+nHw0l 9qe9AKpZw6oZQ0EFr/NhbU9LP5DJDO0OSyAzX7yC0Qh6Tls0GAWkdWvXN AmftoCG2D8547rbFdb3dydAc87yogYsbcGZrHPyU+l5knnST6fY5FJxeQ vGdU7fTL8c+54ffmuc3jGxoXt4LfctyDRqglGr3zBz9qTyUFNXo2PhY/W XK/+O/E75JFHTmVAAFE7Z2RlsYEB8pDDNJ5GxvoNqqyLeDMEPOkVEEjuV wMOBpzCmG+LEXFE+bVVjHP/KUh7ucAEyULa1xrCl7Di1B0kGvPmWS0hfh w==; X-CSE-ConnectionGUID: YWzM0RQSTZG47D6UQPSZ2g== X-CSE-MsgGUID: A8jbQeqmRKaNVX878qdXsg== X-IronPort-AV: E=McAfee;i="6600,9927,11094"; a="14137202" X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="14137202" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:58 -0700 X-CSE-ConnectionGUID: fw87b37sS0uavViXmUQEfQ== X-CSE-MsgGUID: deAS37eXRY2/gUZiBEllwA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,219,1712646000"; d="scan'208";a="38020204" Received: from unknown (HELO localhost) ([10.237.66.160]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2024 04:16:57 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com, =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= Subject: [PATCH v2 14/14] drm/i915: move comments about FSB straps to proper place Date: Thu, 6 Jun 2024 14:16:06 +0300 Message-Id: <58eda13ef17b14f5d497944f76d9692442ce099d.1717672515.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Move the comment about FSB straps to where the relevant register is read. Suggested-by: Ville Syrjälä Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +---------- drivers/gpu/drm/i915/soc/intel_dram.c | 8 ++++++++ 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 17d04353b2b0..5336c8846d89 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -3546,16 +3546,7 @@ static int vlv_hrawclk(struct drm_i915_private *dev_priv) static int i9xx_hrawclk(struct drm_i915_private *i915) { - /* - * hrawclock is 1/4 the FSB frequency - * - * Note that this only reads the state of the FSB - * straps, not the actual FSB frequency. Some BIOSen - * let you configure each independently. Ideally we'd - * read out the actual FSB frequency but sadly we - * don't know which registers have that information, - * and all the relevant docs have gone to bit heaven :( - */ + /* hrawclock is 1/4 the FSB frequency */ return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4); } diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index dac39b41fa51..4aba47bccc63 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -146,6 +146,14 @@ unsigned int i9xx_fsb_freq(struct drm_i915_private *i915) { u32 fsb; + /* + * Note that this only reads the state of the FSB + * straps, not the actual FSB frequency. Some BIOSen + * let you configure each independently. Ideally we'd + * read out the actual FSB frequency but sadly we + * don't know which registers have that information, + * and all the relevant docs have gone to bit heaven :( + */ fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK; if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {