From patchwork Fri Jun 7 14:08:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13690047 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 033E3C27C5F for ; Fri, 7 Jun 2024 14:09:11 +0000 (UTC) Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) by mx.groups.io with SMTP id smtpd.web10.42747.1717769341174338313 for ; Fri, 07 Jun 2024 07:09:01 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=q2Pcwghq; spf=pass (domain: tuxon.dev, ip: 209.85.218.50, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-a6266ffdba8so210553166b.1 for ; Fri, 07 Jun 2024 07:09:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1717769339; x=1718374139; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v0Z0wGNebP5DPlfQfOSdLhCl1ppkwfUAo5GYzgtQ0wA=; b=q2PcwghquHY52MeObbhSwU219AjxGhMn+d654v4O7syfuM8GOzpZnf0LptQLpz1lMN RaWslEjUhMslzacvOKdsCy1ZNHR8AoWrSHwobDz/dOC/15eIuMBJkbqWbC5t2WkoVIUR I6YC+aoJOW/cOlhDhe/e8yUjmq4yqZqKXEm+PjqjZErtoSLktvrq3K6mQfow0ZPVjULL la0fRQW0sWVBIN48nkSAmdZN6I6gcN9qUnlvRt1r/KN8Yp8Bqp2M3paJLawNxmy+Lu23 U4jvQUttJr5bcv4NtumwL/fnVOmziTumSmgJ+ttETajUol8tvG/xnaPFCdfSY1ds/HdF NAXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717769339; x=1718374139; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v0Z0wGNebP5DPlfQfOSdLhCl1ppkwfUAo5GYzgtQ0wA=; b=Vh6e/o2O6YpOSAMygPN3LVezWdQQk3Rob7MQKFav8gsOHJVcN4QRRvMT2e05gfz0jB pfmI9EgtxBOvhebjiDqROjtegDiru+4PPXwoDkOlJIHUrIQmBePXe48gLvqEmdsGI91e G3dSpACdGUqzhHfpE9CYnL8jv6rUyS6W/15MlyXhcVC95mfa6CJVpdkU/1fk9jxutzg9 RSwEMLKNUGuQyormK86Ow0v0YCHYJUsc9sRgfphdvMo9XCAzGMSIpEQ/IXqxbbKor0Dj 5y1zqJYM0VUc7mtQydFvvlz7IwW4GchwR1IUmuETlATEuA4ms1PGwtjwdbtGsBRD2hoQ 0eug== X-Gm-Message-State: AOJu0YyaBvdMMBR6dmOLQ53MSDjW/sqf27aQtunLkqlVSgCGXOtIunRp bsujheEbsP/XaG3ve0yWX3CMkGMEmVkXrxS/d1R8tXpszHV8/68ZkIr5fKrDSs8= X-Google-Smtp-Source: AGHT+IGFV/M+/VbAFpE9Seh+x2xEhnYaBG+wcQPMMoYGUrcxEGqBfRnryPnR6aRu1IAkEWrWR6e0bg== X-Received: by 2002:a17:906:478c:b0:a68:e58b:2c35 with SMTP id a640c23a62f3a-a6cd6660cbemr235237166b.31.1717769339704; Fri, 07 Jun 2024 07:08:59 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.08.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:08:59 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 01/17] clk: renesas: r9a08g045: Add IA55 pclk and its reset Date: Fri, 7 Jun 2024 17:08:40 +0300 Message-Id: <20240607140856.2497508-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:11 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16162 From: Claudiu Beznea commit 755cb955e2e7a2ef65e7a782925585ef1cce53b6 upstream. An IA55 interrupt controller is available on the RZ/G3S SoC. Add the IA55 pclk and its reset. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231120111820.87398-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a08g045-cpg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index a6d3bea968c0..2582ba95256e 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -190,6 +190,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0), + DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0), DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1), DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0), DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), @@ -217,6 +218,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0), DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1), + DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0), DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2), @@ -230,6 +232,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = { static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A08G045_GIC600_GICCLK, + MOD_CLK_BASE + R9A08G045_IA55_PCLK, MOD_CLK_BASE + R9A08G045_IA55_CLK, MOD_CLK_BASE + R9A08G045_DMAC_ACLK, }; From patchwork Fri Jun 7 14:08:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13690050 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2884CC27C75 for ; Fri, 7 Jun 2024 14:09:11 +0000 (UTC) Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) by mx.groups.io with SMTP id smtpd.web11.43039.1717769343249075063 for ; Fri, 07 Jun 2024 07:09:03 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=GwKAZz3O; spf=pass (domain: tuxon.dev, ip: 209.85.167.42, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f42.google.com with SMTP id 2adb3069b0e04-52bbdb15dd5so798270e87.3 for ; Fri, 07 Jun 2024 07:09:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1717769341; x=1718374141; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KSHkEWYYpFN2gEe1WBEPlS/X35QGVe9hjuaMhfDNB+0=; b=GwKAZz3O6sJXmJOQTypNzXTHhemBfj4rssce/D6ica57a1hBCjhEwv8aVtlHjePaWC fBNeCIqUYnqQT0S6oI5Ec082sXr+9bVVxn8UN1xz3jJS1V0w1blrTlN8vzwKaTylgzBa q1HupMBdEfuQQEVi+nOCd1tNtnNe+KK486ZAWcWoRJOzpGai2Ek0lsQsTIlILFwzXYiv Cv5yGydCEJZVtp0eYP8gopLqYHdJbvdZ6iijeZBmkD+gJOtXdmmLpwF4BNK3OuiM+sSB CtZpRld2XXWc76XxEpcBEk58WGKLUSmYotnRaKZYafMMl7BK3Q0EtJjuxdsk1vfTt6G1 jrGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717769341; x=1718374141; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KSHkEWYYpFN2gEe1WBEPlS/X35QGVe9hjuaMhfDNB+0=; b=VFe8uTXpCakTtci/USxvTB8TiiN3B4jJHeTD1SQhwME+Jdp0E3Ojf9+PiuNjeUQsGY Md0mTTD3dykLi8Mwu5MtzHIPZMDNW2mpFoRGG6VUq/+bBe6ycf2Bt8aJgp6JPIhrfUsD U94Lyq8GPgWfoM8oiyxcbJ1ee9rzrybDGmnYtv35AiqUhtUSaWpMatIli16xxtDcH2jS UQzlYDq611sZ4ctMLXocxMN52wPf+bri1xoU2HIp3RgWJU89J2IxAJNs3ww9D/Qfu0QU CiRn/EbzFW4Rx00REEROz0/Q+lLSmW9UJGfH7TRw9obwHMHbhy7RSMXlC8pUG13DMgxH yM+g== X-Gm-Message-State: AOJu0YyFjlGTRlFYCS4upc8FHPSV9kTXHJxuWHmKeTFniNun0SVp58I2 9cWaJGSkeh5N+lq6s3OlKiZq44sCWGMdkqKDmCG2Jo0EAqHxMln8jn5KFvjVn0C/+9azAW8q5Y/ i X-Google-Smtp-Source: AGHT+IG5u2q6NtdbXK4N0MqBOg0fnPMQ/UJHsi+qKbLpqJW9mbuviLxbdrF60NGuRUNeUrNkDKl45w== X-Received: by 2002:a05:6512:220a:b0:52b:f6ab:6f75 with SMTP id 2adb3069b0e04-52bf6ab71b4mr95534e87.29.1717769341371; Fri, 07 Jun 2024 07:09:01 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.08.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:09:00 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 02/17] bitfield: add FIELD_PREP_CONST() Date: Fri, 7 Jun 2024 17:08:41 +0300 Message-Id: <20240607140856.2497508-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:11 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16163 From: Johannes Berg commit e2192de59e457aef8d1f055a452131f0b3e5d097 upstream. Neither FIELD_PREP() nor *_encode_bits() can be used in constant contexts (such as initializers), but we don't want to define shift constants for all masks just for use in initializers, and having checks that the values fit is also useful. Therefore, add FIELD_PREP_CONST() which is a smaller version of FIELD_PREP() that can only take constant arguments and has less friendly (but not less strict) error checks, and expands to a constant value. Signed-off-by: Johannes Berg Link: https://lore.kernel.org/r/20230118142652.53f20593504b.Iaeea0aee77a6493d70e573b4aa55c91c00e01e4b@changeid Signed-off-by: Johannes Berg Signed-off-by: Claudiu Beznea --- include/linux/bitfield.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h index c9be1657f03d..ebfa12f69501 100644 --- a/include/linux/bitfield.h +++ b/include/linux/bitfield.h @@ -115,6 +115,32 @@ ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ }) +#define __BF_CHECK_POW2(n) BUILD_BUG_ON_ZERO(((n) & ((n) - 1)) != 0) + +/** + * FIELD_PREP_CONST() - prepare a constant bitfield element + * @_mask: shifted mask defining the field's length and position + * @_val: value to put in the field + * + * FIELD_PREP_CONST() masks and shifts up the value. The result should + * be combined with other fields of the bitfield using logical OR. + * + * Unlike FIELD_PREP() this is a constant expression and can therefore + * be used in initializers. Error checking is less comfortable for this + * version, and non-constant masks cannot be used. + */ +#define FIELD_PREP_CONST(_mask, _val) \ + ( \ + /* mask must be non-zero */ \ + BUILD_BUG_ON_ZERO((_mask) == 0) + \ + /* check if value fits */ \ + BUILD_BUG_ON_ZERO(~((_mask) >> __bf_shf(_mask)) & (_val)) + \ + /* check if mask is contiguous */ \ + __BF_CHECK_POW2((_mask) + (1ULL << __bf_shf(_mask))) + \ + /* and create the value */ \ + (((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask)) \ + ) + /** * FIELD_GET() - extract a bitfield element * @_mask: shifted mask defining the field's length and position From patchwork Fri Jun 7 14:08:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13690051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36200C27C6F for ; Fri, 7 Jun 2024 14:09:11 +0000 (UTC) Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) by mx.groups.io with SMTP id smtpd.web11.43041.1717769344078965696 for ; Fri, 07 Jun 2024 07:09:04 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=UdCuG0m6; spf=pass (domain: tuxon.dev, ip: 209.85.218.54, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-a63359aaacaso335699466b.1 for ; Fri, 07 Jun 2024 07:09:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1717769342; x=1718374142; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aqcG+ymHJNoMet1clzOb6REmt+cDiyCH63M+6JaG0aI=; b=UdCuG0m63BiVdo4xBdYrPbPEt6KPJiFqLPLOuJzjXgvPxgIMX14dsPKmb4rY2rX8/3 VwTRV2eG2RoJfKmBMwsNAqFgqaOq/RZK/lQtTPWrnig/19aST75mbCBisVniF3d0nMoo 6HUAY3nZZnXVmTRBIgwphZiH0bZREMkk1yw1An7I9JGS6tKgcKnO6ZPHtJfcEnoAWMuC f0b8KJO+HJfWH/xmAAiaIVRFiszn9e2Isp92qU2b6pHNnJ94XqMLH/OOWgCs9AUedjyD OLnrXEB+FQtzSSN6kpYOGsXA47TjNBylTlCnLqXD3vfOwPx77ujbiv07805Zes+zTiqY pXtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717769342; x=1718374142; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aqcG+ymHJNoMet1clzOb6REmt+cDiyCH63M+6JaG0aI=; b=ehHVaCfTuQDt4GRyoQ2OHfPrV5FPIpWgD6r3PGno3EsVBx3MkFgAzd/a5vwU5Kpqwk MW5U3mEoa4b+P218n79VIDwzSFxTrOiOMcmUMbd0Tq9TrGh8pYX8RqDKjbTvsIfJntKx Jyc630RK6ULoVvqhQqMueUcVF5BH5O4HkAb6tT+faZOrTW2WXwNeQCKdTaNoTAomLw9t JdkeSgMEGW387moOaLnCCx8bqOzPz/t8rzLgv9GLws5SWeAi+kiyy60ouS70evgjAbTP 9TFzSEh4ctgkWBFNBfsIv7tUgecKdcb4/JDKTSZIF/SqC9osXauwWeXm81XQVPf2/Rxe BzdA== X-Gm-Message-State: AOJu0YyyG+ymrAJsQr2JHxbHA0RLwXCXuRdrWUO4mghGxAfZJzNmixiK 9SzUQCQeSRyWn9cVZY0lyIBC8hPlBN2uk//5McxygtIqFdgZP6mklZCtTvp+YU4= X-Google-Smtp-Source: AGHT+IG+a+2ZirM4nxWVxe4dhbcYBQ/i8R0QIhapaYRewNTR19IB/+L4GGlBrhiRTclZ2F1SvJZwpg== X-Received: by 2002:a17:906:1305:b0:a68:ad0d:bae6 with SMTP id a640c23a62f3a-a6cd561e522mr182858166b.3.1717769342467; Fri, 07 Jun 2024 07:09:02 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.09.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:09:02 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 03/17] pinctrl: renesas: rzg2l: Improve code for readability Date: Fri, 7 Jun 2024 17:08:42 +0300 Message-Id: <20240607140856.2497508-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:11 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16164 From: Lad Prabhakar commit 04d231b90e66fc013a85f556e4dbf19a2c3ef7ea upstream. As the RZ/G2L pinctrl driver is extensively utilized by numerous SoCs and has experienced substantial growth, enhance code readability by incorporating FIELD_PREP_CONST/FIELD_GET macros wherever necessary. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240129135556.63466-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 44 ++++++++++++++----------- 1 file changed, 25 insertions(+), 19 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index c0d5bdd3a9c9..c748238d6274 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -5,6 +5,7 @@ * Copyright (C) 2021 Renesas Electronics Corporation. */ +#include #include #include #include @@ -37,8 +38,6 @@ */ #define MUX_PIN_ID_MASK GENMASK(15, 0) #define MUX_FUNC_MASK GENMASK(31, 16) -#define MUX_FUNC_OFFS 16 -#define MUX_FUNC(pinconf) (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS) /* PIN capabilities */ #define PIN_CFG_IOLH_A BIT(0) @@ -80,8 +79,12 @@ * n indicates number of pins in the port, a is the register index * and f is pin configuration capabilities supported. */ -#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) -#define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) +#define PIN_CFG_PIN_CNT_MASK GENMASK(30, 28) +#define PIN_CFG_PIN_REG_MASK GENMASK(27, 20) +#define PIN_CFG_MASK GENMASK(19, 0) +#define RZG2L_GPIO_PORT_PACK(n, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_CNT_MASK, (n)) | \ + FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ + FIELD_PREP_CONST(PIN_CFG_MASK, (f))) /* * BIT(31) indicates dedicated pin, p is the register index while @@ -89,14 +92,17 @@ * (b * 8) and f is the pin configuration capabilities supported. */ #define RZG2L_SINGLE_PIN BIT(31) +#define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK(30, 24) +#define RZG2L_SINGLE_PIN_BITS_MASK GENMASK(22, 20) + #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ - ((p) << 24) | ((b) << 20) | (f)) -#define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) + FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \ + FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \ + FIELD_PREP_CONST(PIN_CFG_MASK, (f))) -#define RZG2L_PIN_CFG_TO_CAPS(cfg) ((cfg) & GENMASK(19, 0)) #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ - (((cfg) & GENMASK(30, 24)) >> 24) : \ - (((cfg) & GENMASK(26, 20)) >> 20)) + FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \ + FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg))) #define P(off) (0x0000 + (off)) #define PM(off) (0x0100 + (off) * 2) @@ -431,8 +437,8 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, ret = of_property_read_u32_index(np, "pinmux", i, &value); if (ret) goto done; - pins[i] = value & MUX_PIN_ID_MASK; - psel_val[i] = MUX_FUNC(value); + pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value); + psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value); } if (parent) { @@ -559,7 +565,7 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, u32 cfg, u32 port, u8 bit) { - u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg); + u8 pincount = FIELD_GET(PIN_CFG_PIN_CNT_MASK, cfg); u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); u32 data; @@ -865,9 +871,9 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, return -EINVAL; off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); - cfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data); + cfg = FIELD_GET(PIN_CFG_MASK, *pin_data); if (*pin_data & RZG2L_SINGLE_PIN) { - bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); + bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); } else { bit = RZG2L_PIN_ID_TO_PIN(_pin); @@ -969,9 +975,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, return -EINVAL; off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); - cfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data); + cfg = FIELD_GET(PIN_CFG_MASK, *pin_data); if (*pin_data & RZG2L_SINGLE_PIN) { - bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); + bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); } else { bit = RZG2L_PIN_ID_TO_PIN(_pin); @@ -1607,12 +1613,12 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_ bit = virq % 8; if (port >= data->n_ports || - bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port])) + bit >= FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[port])) return -EINVAL; gpioint = bit; for (i = 0; i < port; i++) - gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]); + gpioint += FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[i]); return gpioint; } @@ -1787,7 +1793,7 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, bit = offset % 8; if (port >= pctrl->data->n_ports || - bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port])) + bit >= FIELD_GET(PIN_CFG_PIN_CNT_MASK, pctrl->data->port_pin_configs[port])) clear_bit(offset, valid_mask); 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([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.09.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:09:03 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 04/17] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro Date: Fri, 7 Jun 2024 17:08:43 +0300 Message-Id: <20240607140856.2497508-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:11 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16165 From: Lad Prabhakar commit 15e4ae4f9ae74433e96331164e96f744769c0f8e upstream. Currently we assume all the port pins are sequential ie always PX_0 to PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to P28_5 which have holes in them, for example only one pin on port19 is available and that is P19_1 and not P19_0. So to handle such cases include pinmap for each port which would indicate the pin availability on each port. As the pincount can be calculated based on pinmap drop this from RZG2L_GPIO_PORT_PACK() macro. Previously we had a max of 7 pins on each port but on RZ/Five Port-20 has 8 pins, so move the single pin configuration to BIT(63). Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240129135556.63466-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven [claudiu.beznea: fixed conflict in rzg2l_pinctrl_set_mux() function] Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 56 +++++++++++++------------ 1 file changed, 29 insertions(+), 27 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index c748238d6274..e05d4e3bd9c4 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -79,19 +79,20 @@ * n indicates number of pins in the port, a is the register index * and f is pin configuration capabilities supported. */ -#define PIN_CFG_PIN_CNT_MASK GENMASK(30, 28) +#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(35, 28) #define PIN_CFG_PIN_REG_MASK GENMASK(27, 20) #define PIN_CFG_MASK GENMASK(19, 0) -#define RZG2L_GPIO_PORT_PACK(n, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_CNT_MASK, (n)) | \ + +#define RZG2L_GPIO_PORT_PACK(n, a, f) ((((1ULL << (n)) - 1) << 28) | \ FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ FIELD_PREP_CONST(PIN_CFG_MASK, (f))) /* - * BIT(31) indicates dedicated pin, p is the register index while + * BIT(63) indicates dedicated pin, p is the register index while * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits * (b * 8) and f is the pin configuration capabilities supported. */ -#define RZG2L_SINGLE_PIN BIT(31) +#define RZG2L_SINGLE_PIN BIT_ULL(63) #define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK(30, 24) #define RZG2L_SINGLE_PIN_BITS_MASK GENMASK(22, 20) @@ -194,12 +195,12 @@ struct rzg2l_hwcfg { struct rzg2l_dedicated_configs { const char *name; - u32 config; + u64 config; }; struct rzg2l_pinctrl_data { const char * const *port_pins; - const u32 *port_pin_configs; + const u64 *port_pin_configs; unsigned int n_ports; const struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; @@ -300,7 +301,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, pins = group->pins; for (i = 0; i < group->num_pins; i++) { - unsigned int *pin_data = pctrl->desc.pins[pins[i]].drv_data; + u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); @@ -563,13 +564,13 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, } static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, - u32 cfg, u32 port, u8 bit) + u64 cfg, u32 port, u8 bit) { - u8 pincount = FIELD_GET(PIN_CFG_PIN_CNT_MASK, cfg); + u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); - u32 data; + u64 data; - if (bit >= pincount || port >= pctrl->data->n_port_pins) + if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins) return -EINVAL; data = pctrl->data->port_pin_configs[port]; @@ -861,7 +862,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, enum pin_config_param param = pinconf_to_config_param(*config); const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; - unsigned int *pin_data = pin->drv_data; + u64 *pin_data = pin->drv_data; unsigned int arg = 0; u32 off, cfg; int ret; @@ -964,7 +965,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; - unsigned int *pin_data = pin->drv_data; + u64 *pin_data = pin->drv_data; enum pin_config_param param; unsigned int i, arg, index; u32 cfg, off; @@ -1169,7 +1170,7 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - u32 *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u32 port = RZG2L_PIN_ID_TO_PORT(offset); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); @@ -1201,7 +1202,7 @@ static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, bool output) { const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); unsigned long flags; @@ -1222,7 +1223,7 @@ static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); @@ -1253,7 +1254,7 @@ static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); unsigned long flags; @@ -1286,7 +1287,7 @@ static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); u16 reg16; @@ -1371,7 +1372,7 @@ static const char * const rzg2l_gpio_names[] = { "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", }; -static const u32 r9a07g044_gpio_configs[] = { +static const u64 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), @@ -1423,7 +1424,7 @@ static const u32 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), }; -static const u32 r9a07g043_gpio_configs[] = { +static const u64 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), @@ -1445,7 +1446,7 @@ static const u32 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), }; -static const u32 r9a08g045_gpio_configs[] = { +static const u64 r9a08g045_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH0)) | @@ -1613,12 +1614,12 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_ bit = virq % 8; if (port >= data->n_ports || - bit >= FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[port])) + bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port]))) return -EINVAL; gpioint = bit; for (i = 0; i < port; i++) - gpioint += FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[i]); + gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i])); return gpioint; } @@ -1629,7 +1630,7 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); unsigned long flags; @@ -1656,7 +1657,7 @@ static void rzg2l_gpio_irq_enable(struct irq_data *d) struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); unsigned long flags; @@ -1793,7 +1794,8 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, bit = offset % 8; if (port >= pctrl->data->n_ports || - bit >= FIELD_GET(PIN_CFG_PIN_CNT_MASK, pctrl->data->port_pin_configs[port])) + bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, + pctrl->data->port_pin_configs[port]))) clear_bit(offset, valid_mask); } } @@ -1875,7 +1877,7 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; struct pinctrl_pin_desc *pins; unsigned int i, j; - u32 *pin_data; + u64 *pin_data; int ret; pctrl->desc.name = DRV_NAME; From patchwork Fri Jun 7 14:08:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13690052 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 121EAC27C53 for ; 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([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.09.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:09:04 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 05/17] pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 Date: Fri, 7 Jun 2024 17:08:44 +0300 Message-Id: <20240607140856.2497508-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:11 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16166 From: Lad Prabhakar commit fea58424e2523376ece6f734479e63061e17ad7f upstream. Add the missing port pins P19 to P28 for RZ/Five SoC. These additional pins provide expanded capabilities and are exclusive to the RZ/Five SoC. Couple of port pins have different configuration and are not identical for the complete port so introduce struct rzg2l_variable_pin_cfg to handle such cases and introduce the PIN_CFG_VARIABLE macro. The actual pin config is then assigned in rzg2l_pinctrl_get_variable_pin_cfg(). Add an additional check in rzg2l_gpio_get_gpioint() to only allow GPIO pins which support interrupt facility. While at define RZG2L_GPIO_PORT_PACK() using RZG2L_GPIO_PORT_SPARSE_PACK(). Update the gpio-ranges property in the RZ/Five SoC DTSI, as it must match the driver. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240129135556.63466-4-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/r/20240129135556.63466-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 + drivers/pinctrl/renesas/pinctrl-rzg2l.c | 213 +++++++++++++++++++- 2 files changed, 208 insertions(+), 9 deletions(-) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index b0796015e36b..e68a91c9fe77 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -42,6 +42,10 @@ cpu0_intc: interrupt-controller { }; }; +&pinctrl { + gpio-ranges = <&pinctrl 0 0 232>; +}; + &soc { dma-noncoherent; interrupt-parent = <&plic>; diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index e05d4e3bd9c4..336b7313e108 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -56,6 +56,8 @@ #define PIN_CFG_IOLH_C BIT(13) #define PIN_CFG_SOFT_PS BIT(14) #define PIN_CFG_OEN BIT(15) +#define PIN_CFG_VARIABLE BIT(16) +#define PIN_CFG_NOGPIO_INT BIT(17) #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ (PIN_CFG_IOLH_##group | \ @@ -75,17 +77,23 @@ PIN_CFG_FILNUM | \ PIN_CFG_FILCLKSEL) -/* - * n indicates number of pins in the port, a is the register index - * and f is pin configuration capabilities supported. - */ #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(35, 28) #define PIN_CFG_PIN_REG_MASK GENMASK(27, 20) #define PIN_CFG_MASK GENMASK(19, 0) -#define RZG2L_GPIO_PORT_PACK(n, a, f) ((((1ULL << (n)) - 1) << 28) | \ - FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ - FIELD_PREP_CONST(PIN_CFG_MASK, (f))) +/* + * m indicates the bitmap of supported pins, a is the register index + * and f is pin configuration capabilities supported. + */ +#define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \ + FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ + FIELD_PREP_CONST(PIN_CFG_MASK, (f))) + +/* + * n indicates number of pins in the port, a is the register index + * and f is pin configuration capabilities supported. + */ +#define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f)) /* * BIT(63) indicates dedicated pin, p is the register index while @@ -198,6 +206,18 @@ struct rzg2l_dedicated_configs { u64 config; }; +/** + * struct rzg2l_variable_pin_cfg - pin data cfg + * @cfg: port pin configuration + * @port: port number + * @pin: port pin + */ +struct rzg2l_variable_pin_cfg { + u32 cfg:20; + u32 port:5; + u32 pin:3; +}; + struct rzg2l_pinctrl_data { const char * const *port_pins; const u64 *port_pin_configs; @@ -206,6 +226,8 @@ struct rzg2l_pinctrl_data { unsigned int n_port_pins; unsigned int n_dedicated_pins; const struct rzg2l_hwcfg *hwcfg; + const struct rzg2l_variable_pin_cfg *variable_pin_cfg; + unsigned int n_variable_pin_cfg; }; /** @@ -241,6 +263,143 @@ struct rzg2l_pinctrl { static const u16 available_ps[] = { 1800, 2500, 3300 }; +#ifdef CONFIG_RISCV +static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, + u64 pincfg, + unsigned int port, + u8 pin) +{ + unsigned int i; + + for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) { + if (pctrl->data->variable_pin_cfg[i].port == port && + pctrl->data->variable_pin_cfg[i].pin == pin) + return (pincfg & ~PIN_CFG_VARIABLE) | pctrl->data->variable_pin_cfg[i].cfg; + } + + return 0; +} + +static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = { + { + .port = 20, + .pin = 0, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 1, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 2, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 3, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 4, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 5, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 6, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 7, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 23, + .pin = 1, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT + }, + { + .port = 23, + .pin = 2, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 23, + .pin = 3, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 23, + .pin = 4, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 23, + .pin = 5, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 0, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 1, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 2, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 3, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 4, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 5, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_NOGPIO_INT, + }, +}; +#endif + static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { @@ -1444,6 +1603,25 @@ static const u64 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), +#ifdef CONFIG_RISCV + /* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */ + RZG2L_GPIO_PORT_PACK(8, 0x07, PIN_CFG_VARIABLE), /* P20 */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */ + RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x3e, 0x0a, PIN_CFG_VARIABLE), /* P23 */ + RZG2L_GPIO_PORT_PACK(6, 0x0b, PIN_CFG_VARIABLE), /* P24 */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF | + PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_NOGPIO_INT), /* P25 */ + 0x0, /* P26 */ + 0x0, /* P27 */ + RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO_INT), /* P28 */ +#endif }; static const u64 r9a08g045_gpio_configs[] = { @@ -1604,12 +1782,18 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { PIN_CFG_IO_VMC_SD1)) }, }; -static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data) +static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) { + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; + const struct rzg2l_pinctrl_data *data = pctrl->data; + u64 *pin_data = pin_desc->drv_data; unsigned int gpioint; unsigned int i; u32 port, bit; + if (*pin_data & PIN_CFG_NOGPIO_INT) + return -EINVAL; + port = virq / 8; bit = virq % 8; @@ -1719,7 +1903,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, unsigned long flags; int gpioint, irq; - gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data); + gpioint = rzg2l_gpio_get_gpioint(child, pctrl); if (gpioint < 0) return gpioint; @@ -1905,6 +2089,13 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) if (i && !(i % RZG2L_PINS_PER_PORT)) j++; pin_data[i] = pctrl->data->port_pin_configs[j]; +#ifdef CONFIG_RISCV + if (pin_data[i] & PIN_CFG_VARIABLE) + pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl, + pin_data[i], + j, + i % RZG2L_PINS_PER_PORT); +#endif pins[i].drv_data = &pin_data[i]; } @@ -2056,6 +2247,10 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), .hwcfg = &rzg2l_hwcfg, +#ifdef CONFIG_RISCV + .variable_pin_cfg = r9a07g043f_variable_pin_cfg, + .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg), +#endif }; static struct rzg2l_pinctrl_data r9a07g044_data = { From patchwork Fri Jun 7 14:08:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13690049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20830C27C6E for ; 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([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.09.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:09:05 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 06/17] pinctrl: renesas: rzg2l: Configure interrupt input mode Date: Fri, 7 Jun 2024 17:08:45 +0300 Message-Id: <20240607140856.2497508-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:11 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16167 From: Biju Das commit 2fd4fe19d01507369cef18a037d84f3439dd5ab2 upstream. Configure GPIO interrupt as input mode. Also if the bootloader sets gpio interrupt pin as function, override it as gpio. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240206135115.151218-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 37 +++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 336b7313e108..245eb41aa05a 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1893,6 +1893,26 @@ static const struct irq_chip rzg2l_gpio_irqchip = { GPIOCHIP_IRQ_RESOURCE_HELPERS, }; +static int rzg2l_gpio_interrupt_input_mode(struct gpio_chip *chip, unsigned int offset) +{ + struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; + u64 *pin_data = pin_desc->drv_data; + u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); + u8 bit = RZG2L_PIN_ID_TO_PIN(offset); + u8 reg8; + int ret; + + reg8 = readb(pctrl->base + PMC(off)); + if (reg8 & BIT(bit)) { + ret = rzg2l_gpio_request(chip, offset); + if (ret) + return ret; + } + + return rzg2l_gpio_direction_input(chip, offset); +} + static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, unsigned int child, unsigned int child_type, @@ -1902,16 +1922,24 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); unsigned long flags; int gpioint, irq; + int ret; gpioint = rzg2l_gpio_get_gpioint(child, pctrl); if (gpioint < 0) return gpioint; + ret = rzg2l_gpio_interrupt_input_mode(gc, child); + if (ret) + return ret; + spin_lock_irqsave(&pctrl->bitmap_lock, flags); irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); - if (irq < 0) - return -ENOSPC; + if (irq < 0) { + ret = -ENOSPC; + goto err; + } + pctrl->hwirq[irq] = child; irq += RZG2L_TINT_IRQ_START_INDEX; @@ -1919,6 +1947,10 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, *parent_type = IRQ_TYPE_LEVEL_HIGH; *parent = RZG2L_PACK_HWIRQ(gpioint, irq); return 0; + +err: + rzg2l_gpio_free(gc, child); + return ret; } static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, @@ -1951,6 +1983,7 @@ static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int v for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { if (pctrl->hwirq[i] == hwirq) { + rzg2l_gpio_free(gc, hwirq); spin_lock_irqsave(&pctrl->bitmap_lock, flags); bitmap_release_region(pctrl->tint_slot, i, get_order(1)); spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); From patchwork Fri Jun 7 14:08:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13690048 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03414C41513 for ; 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([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.09.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:09:07 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 07/17] pinctrl: renesas: rzg2l: Simplify rzg2l_gpio_irq_{en,dis}able() Date: Fri, 7 Jun 2024 17:08:46 +0300 Message-Id: <20240607140856.2497508-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:11 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16168 From: Biju Das commit d3c49299339051b17ae3f2fe70fa5af7bbb82011 upstream. Simplify rzg2l_gpio_irq_{en,dis}able() by adding a helper function rzg2l_gpio_irq_endisable(). Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240206135115.151218-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 40 ++++++++++--------------- 1 file changed, 16 insertions(+), 24 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 245eb41aa05a..514aebc3fc8e 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1808,11 +1808,9 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl return gpioint; } -static void rzg2l_gpio_irq_disable(struct irq_data *d) +static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, + unsigned int hwirq, bool enable) { - struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); - unsigned int hwirq = irqd_to_hwirq(d); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); @@ -1820,8 +1818,6 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) unsigned long flags; void __iomem *addr; - irq_chip_disable_parent(d); - addr = pctrl->base + ISEL(off); if (bit >= 4) { bit -= 4; @@ -1829,9 +1825,21 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) } spin_lock_irqsave(&pctrl->lock, flags); - writel(readl(addr) & ~BIT(bit * 8), addr); + if (enable) + writel(readl(addr) | BIT(bit * 8), addr); + else + writel(readl(addr) & ~BIT(bit * 8), addr); spin_unlock_irqrestore(&pctrl->lock, flags); +} +static void rzg2l_gpio_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); + unsigned int hwirq = irqd_to_hwirq(d); + + irq_chip_disable_parent(d); + rzg2l_gpio_irq_endisable(pctrl, hwirq, false); gpiochip_disable_irq(gc, hwirq); } @@ -1840,25 +1848,9 @@ static void rzg2l_gpio_irq_enable(struct irq_data *d) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); - const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; - u64 *pin_data = pin_desc->drv_data; - u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); - u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); - unsigned long flags; - void __iomem *addr; gpiochip_enable_irq(gc, hwirq); - - addr = pctrl->base + ISEL(off); - if (bit >= 4) { - bit -= 4; - addr += 4; - } - - spin_lock_irqsave(&pctrl->lock, flags); - writel(readl(addr) | BIT(bit * 8), addr); - spin_unlock_irqrestore(&pctrl->lock, flags); - + rzg2l_gpio_irq_endisable(pctrl, hwirq, true); irq_chip_enable_parent(d); } From patchwork Fri Jun 7 14:08:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13690054 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36292C27C53 for ; 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([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.09.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:09:09 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 08/17] pinctrl: renesas: rzg2l: Avoid configuring ISEL in gpio_irq_{en,dis}able*( Date: Fri, 7 Jun 2024 17:08:47 +0300 Message-Id: <20240607140856.2497508-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:21 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16169 From: Biju Das commit 1d2da79708cb4e23ec3d19c6c5b528753ca08e67 upstream. Currently on irq_disable(), we are disabling gpio interrupt enable(ISEL). That means the pin is just gpio input and not gpio input interrupt any more. So, move configuring ISEL in rzg2l_gpio_child_to_parent_hwirq()/ rzg2l_gpio_irq_domain_free() so that the pin will be gpioint always even during irq_disable(). Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240206135318.165426-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 514aebc3fc8e..38cff01a5852 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1835,22 +1835,18 @@ static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl, static void rzg2l_gpio_irq_disable(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); irq_chip_disable_parent(d); - rzg2l_gpio_irq_endisable(pctrl, hwirq, false); gpiochip_disable_irq(gc, hwirq); } static void rzg2l_gpio_irq_enable(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); gpiochip_enable_irq(gc, hwirq); - rzg2l_gpio_irq_endisable(pctrl, hwirq, true); irq_chip_enable_parent(d); } @@ -1932,6 +1928,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, goto err; } + rzg2l_gpio_irq_endisable(pctrl, child, true); pctrl->hwirq[irq] = child; irq += RZG2L_TINT_IRQ_START_INDEX; @@ -1975,6 +1972,7 @@ static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int v for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { if (pctrl->hwirq[i] == hwirq) { + rzg2l_gpio_irq_endisable(pctrl, hwirq, false); rzg2l_gpio_free(gc, hwirq); spin_lock_irqsave(&pctrl->bitmap_lock, flags); bitmap_release_region(pctrl->tint_slot, i, get_order(1)); From patchwork Fri Jun 7 14:08:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13690059 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EB04C41513 for ; Fri, 7 Jun 2024 14:09:21 +0000 (UTC) Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) by mx.groups.io with SMTP id smtpd.web11.43052.1717769353276573751 for ; Fri, 07 Jun 2024 07:09:13 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=kSQo50E5; spf=pass (domain: tuxon.dev, ip: 209.85.167.47, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-52bc335e49aso299141e87.3 for ; Fri, 07 Jun 2024 07:09:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1717769351; x=1718374151; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cA3EPoGWGBugroqTalIpgl/f3/OmNU9egTQ61XzBNeI=; b=kSQo50E5BPluAATuXNLTaapniwcDqzUHQkEGSBY6X1uNh/wHgNmp6vy3aYFAobIMwj TWYeKMkDXu9yjQ6mVPoVIiM9d+w0XTTDBxf1u/K3oEtxPNmfJLlPl1+lOlgu8f9MkdTB DH4iwMB9s6itzVHHDt86muMYGODz7Hkm2No8b1MvbhcdHkOsCtayHBVo/OinoU/19sNU 9HrrftOmQzWN5o037icx4BpjoTowNqBuomnZ3kBjSLrpPR6sGDiIfSgKRihPh8g+hfEz f/WfrogIJ+Tov/exsiSjb3vu59SvXvIll/ZmZfd3R7SrMZTDgU9wvQSkrinEo44LvriQ VSuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717769351; x=1718374151; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cA3EPoGWGBugroqTalIpgl/f3/OmNU9egTQ61XzBNeI=; b=gIqIvbImi30PKIJoNrfFpVgTHXQwMX3yAmyez9MQ6UNBWKae6Wa1Qy2TR7jsPZXGFh rTA9/o1oFvcfDRClpXWvKRVE+CIe3X4MbL7UXmcNpgerhJay2b5mW+/d9OC72X5DPV/U 8VRwPXAlt5yR3E4PmdtBPTCu75t7SWsb+9tNeUJg4p5tATeAsQR3PWUnR/i+Tr0nMQB9 AYR5xwb1KKUh35MIsWphHexi24P6GLuK5MjHZQANqbeyCi3aXbvodwO+nXQZHgqKu0bC LaA3ITNc1BTyVZLnj2N42GoDhQXFSYBLQtKPfAT/KqGkyzJHtGnBYz/rBD6QySZRtU87 lIMQ== X-Gm-Message-State: AOJu0Yz1QjQrrDU6oLx6600id2C7WvnNFO4Kx/DaCxtBTUTyL3MBPtqo 96S9NzwA7ZigqwSbpA1C4YqYtXPxQqJDb9jgfZxxz4GelHnLZclrmcV1qp7BSWM= X-Google-Smtp-Source: AGHT+IESvVV0LkjhvDqLItjlu0gaj4nR7NtOZ7Z7eO93TuuqUw5TpyWVBaIdEC2Ti1Rtmio1JtDmoQ== X-Received: by 2002:a19:ac07:0:b0:52b:360f:ceb4 with SMTP id 2adb3069b0e04-52bb9f755c6mr1709819e87.17.1717769351456; Fri, 07 Jun 2024 07:09:11 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.09.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:09:10 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 09/17] pinctrl: renesas: rzg2l: Add suspend/resume support Date: Fri, 7 Jun 2024 17:08:48 +0300 Message-Id: <20240607140856.2497508-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:21 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16170 From: Claudiu Beznea commit 254203f9a94cf8f8f406e241a11f38b8e4701d91 upstream. pinctrl-rzg2l driver is used on RZ/G3S which support deep sleep states where power to most of the SoC components is turned off. For this add suspend/resume support. This involves saving and restoring configured registers along with disabling clock in case there is no pin configured as wakeup sources. To save/restore registers 2 caches were allocated: one for GPIO pins and one for dedicated pins. On suspend path the pin controller registers are saved and if none of the pins are configured as wakeup sources the pinctrl clock is disabled. Otherwise it remains on. On resume path the configuration is done as follows: 1/ setup PFCs by writing to registers on pin based accesses 2/ setup GPIOs by writing to registers on port based accesses and following configuration steps specified in hardware manual 3/ setup dedicated pins by writing to registers on port based accesses 4/ setup interrupts. Because interrupt signals are routed to IA55 interrupt controller and IA55 interrupt controller resumes before pin controller, patch restores also the configured interrupts just after pin settings are restored to avoid invalid interrupts while resuming. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240215124112.2259103-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 408 +++++++++++++++++++++++- 1 file changed, 404 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 38cff01a5852..6f49da4bd327 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -148,6 +148,33 @@ #define RZG2L_TINT_IRQ_START_INDEX 9 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) +/* Read/write 8 bits register */ +#define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \ + do { \ + if (_read) \ + _val = readb(_addr); \ + else \ + writeb(_val, _addr); \ + } while (0) + +/* Read/write 16 bits register */ +#define RZG2L_PCTRL_REG_ACCESS16(_read, _addr, _val) \ + do { \ + if (_read) \ + _val = readw(_addr); \ + else \ + writew(_val, _addr); \ + } while (0) + +/* Read/write 32 bits register */ +#define RZG2L_PCTRL_REG_ACCESS32(_read, _addr, _val) \ + do { \ + if (_read) \ + _val = readl(_addr); \ + else \ + writel(_val, _addr); \ + } while (0) + /** * struct rzg2l_register_offsets - specific register offsets * @pwpr: PWPR register offset @@ -240,6 +267,32 @@ struct rzg2l_pinctrl_pin_settings { u16 drive_strength_ua; }; +/** + * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume) + * @p: P registers cache + * @pm: PM registers cache + * @pmc: PMC registers cache + * @pfc: PFC registers cache + * @iolh: IOLH registers cache + * @ien: IEN registers cache + * @sd_ch: SD_CH registers cache + * @eth_poc: ET_POC registers cache + * @eth_mode: ETH_MODE register cache + * @qspi: QSPI registers cache + */ +struct rzg2l_pinctrl_reg_cache { + u8 *p; + u16 *pm; + u8 *pmc; + u32 *pfc; + u32 *iolh[2]; + u32 *ien[2]; + u8 sd_ch[2]; + u8 eth_poc[2]; + u8 eth_mode; + u8 qspi; +}; + struct rzg2l_pinctrl { struct pinctrl_dev *pctl; struct pinctrl_desc desc; @@ -249,6 +302,8 @@ struct rzg2l_pinctrl { void __iomem *base; struct device *dev; + struct clk *clk; + struct gpio_chip gpio_chip; struct pinctrl_gpio_range gpio_range; DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); @@ -259,6 +314,9 @@ struct rzg2l_pinctrl { struct mutex mutex; /* serialize adding groups and functions */ struct rzg2l_pinctrl_pin_settings *settings; + struct rzg2l_pinctrl_reg_cache *cache; + struct rzg2l_pinctrl_reg_cache *dedicated_cache; + atomic_t wakeup_path; }; static const u16 available_ps[] = { 1800, 2500, 3300 }; @@ -1867,6 +1925,28 @@ static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) seq_printf(p, dev_name(gc->parent)); } +static int rzg2l_gpio_irq_set_wake(struct irq_data *data, unsigned int on) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); + int ret; + + /* It should not happen. */ + if (!data->parent_data) + return -EOPNOTSUPP; + + ret = irq_chip_set_wake_parent(data, on); + if (ret) + return ret; + + if (on) + atomic_inc(&pctrl->wakeup_path); + else + atomic_dec(&pctrl->wakeup_path); + + return 0; +} + static const struct irq_chip rzg2l_gpio_irqchip = { .name = "rzg2l-gpio", .irq_disable = rzg2l_gpio_irq_disable, @@ -1877,6 +1957,7 @@ static const struct irq_chip rzg2l_gpio_irqchip = { .irq_eoi = rzg2l_gpio_irqc_eoi, .irq_print_chip = rzg2l_gpio_irq_print_chip, .irq_set_affinity = irq_chip_set_affinity_parent, + .irq_set_wake = rzg2l_gpio_irq_set_wake, .flags = IRQCHIP_IMMUTABLE, GPIOCHIP_IRQ_RESOURCE_HELPERS, }; @@ -1957,6 +2038,35 @@ static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, return 0; } +static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) +{ + struct irq_domain *domain = pctrl->gpio_chip.irq.domain; + + for (unsigned int i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { + struct irq_data *data; + unsigned int virq; + + if (!pctrl->hwirq[i]) + continue; + + virq = irq_find_mapping(domain, pctrl->hwirq[i]); + if (!virq) { + dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n", + pctrl->hwirq[i]); + continue; + } + + data = irq_domain_get_irq_data(domain, virq); + if (!data) { + dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq); + continue; + } + + if (!irqd_irq_disabled(data)) + rzg2l_gpio_irq_enable(data); + } +} + static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs) { @@ -2007,6 +2117,68 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, } } +static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl) +{ + u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; + struct rzg2l_pinctrl_reg_cache *cache, *dedicated_cache; + + cache = devm_kzalloc(pctrl->dev, sizeof(*cache), GFP_KERNEL); + if (!cache) + return -ENOMEM; + + dedicated_cache = devm_kzalloc(pctrl->dev, sizeof(*dedicated_cache), GFP_KERNEL); + if (!dedicated_cache) + return -ENOMEM; + + cache->p = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->p), GFP_KERNEL); + if (!cache->p) + return -ENOMEM; + + cache->pm = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pm), GFP_KERNEL); + if (!cache->pm) + return -ENOMEM; + + cache->pmc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pmc), GFP_KERNEL); + if (!cache->pmc) + return -ENOMEM; + + cache->pfc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pfc), GFP_KERNEL); + if (!cache->pfc) + return -ENOMEM; + + for (u8 i = 0; i < 2; i++) { + u32 n_dedicated_pins = pctrl->data->n_dedicated_pins; + + cache->iolh[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->iolh[i]), + GFP_KERNEL); + if (!cache->iolh[i]) + return -ENOMEM; + + cache->ien[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->ien[i]), + GFP_KERNEL); + if (!cache->ien[i]) + return -ENOMEM; + + /* Allocate dedicated cache. */ + dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, + sizeof(*dedicated_cache->iolh[i]), + GFP_KERNEL); + if (!dedicated_cache->iolh[i]) + return -ENOMEM; + + dedicated_cache->ien[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins, + sizeof(*dedicated_cache->ien[i]), + GFP_KERNEL); + if (!dedicated_cache->ien[i]) + return -ENOMEM; + } + + pctrl->cache = cache; + pctrl->dedicated_cache = dedicated_cache; + + return 0; +} + static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) { struct device_node *np = pctrl->dev->of_node; @@ -2147,6 +2319,10 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) } } + ret = rzg2l_pinctrl_reg_cache_alloc(pctrl); + if (ret) + return ret; + ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, &pctrl->pctl); if (ret) { @@ -2172,7 +2348,6 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) static int rzg2l_pinctrl_probe(struct platform_device *pdev) { struct rzg2l_pinctrl *pctrl; - struct clk *clk; int ret; BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT > @@ -2198,14 +2373,16 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) if (IS_ERR(pctrl->base)) return PTR_ERR(pctrl->base); - clk = devm_clk_get_enabled(pctrl->dev, NULL); - if (IS_ERR(clk)) - return dev_err_probe(pctrl->dev, PTR_ERR(clk), + pctrl->clk = devm_clk_get_enabled(pctrl->dev, NULL); + if (IS_ERR(pctrl->clk)) { + return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->clk), "failed to enable GPIO clk\n"); + } spin_lock_init(&pctrl->lock); spin_lock_init(&pctrl->bitmap_lock); mutex_init(&pctrl->mutex); + atomic_set(&pctrl->wakeup_path, 0); platform_set_drvdata(pdev, pctrl); @@ -2217,6 +2394,224 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) return 0; } +static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspend) +{ + u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; + struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; + + for (u32 port = 0; port < nports; port++) { + bool has_iolh, has_ien; + u32 off, caps; + u8 pincnt; + u64 cfg; + + cfg = pctrl->data->port_pin_configs[port]; + off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); + pincnt = hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg)); + + caps = FIELD_GET(PIN_CFG_MASK, cfg); + has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); + has_ien = !!(caps & PIN_CFG_IEN); + + if (suspend) + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]); + + /* + * Now cache the registers or set them in the order suggested by + * HW manual (section "Operation for GPIO Function"). + */ + RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]); + if (has_iolh) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), + cache->iolh[0][port]); + if (pincnt >= 4) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4, + cache->iolh[1][port]); + } + } + + RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]); + RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]); + + if (has_ien) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), + cache->ien[0][port]); + if (pincnt >= 4) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4, + cache->ien[1][port]); + } + } + } +} + +static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend) +{ + struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; + + /* + * Make sure entries in pctrl->data->n_dedicated_pins[] having the same + * port offset are close together. + */ + for (u32 i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) { + bool has_iolh, has_ien; + u32 off, next_off = 0; + u64 cfg, next_cfg; + u8 pincnt; + + cfg = pctrl->data->dedicated_pins[i].config; + off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); + if (i + 1 < pctrl->data->n_dedicated_pins) { + next_cfg = pctrl->data->dedicated_pins[i + 1].config; + next_off = RZG2L_PIN_CFG_TO_PORT_OFFSET(next_cfg); + } + + if (off == next_off) { + /* Gather caps of all port pins. */ + caps |= FIELD_GET(PIN_CFG_MASK, cfg); + continue; + } + + /* And apply them in a single shot. */ + has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)); + has_ien = !!(caps & PIN_CFG_IEN); + pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg)); + + if (has_iolh) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off), + cache->iolh[0][i]); + } + if (has_ien) { + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off), + cache->ien[0][i]); + } + + if (pincnt >= 4) { + if (has_iolh) { + RZG2L_PCTRL_REG_ACCESS32(suspend, + pctrl->base + IOLH(off) + 4, + cache->iolh[1][i]); + } + if (has_ien) { + RZG2L_PCTRL_REG_ACCESS32(suspend, + pctrl->base + IEN(off) + 4, + cache->ien[1][i]); + } + } + caps = 0; + } +} + +static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl) +{ + u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT; + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; + const struct rzg2l_register_offsets *regs = &hwcfg->regs; + + /* Set the PWPR register to allow PFC register to write. */ + writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ + writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */ + + /* Restore port registers. */ + for (u32 port = 0; port < nports; port++) { + unsigned long pinmap; + u8 pmc = 0, max_pin; + u32 off, pfc = 0; + u64 cfg; + u16 pm; + u8 pin; + + cfg = pctrl->data->port_pin_configs[port]; + off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); + pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); + max_pin = fls(pinmap); + + pm = readw(pctrl->base + PM(off)); + for_each_set_bit(pin, &pinmap, max_pin) { + struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; + + /* Nothing to do if PFC was not configured before. */ + if (!(cache->pmc[port] & BIT(pin))) + continue; + + /* Set pin to 'Non-use (Hi-Z input protection)' */ + pm &= ~(PM_MASK << (pin * 2)); + writew(pm, pctrl->base + PM(off)); + + /* Temporarily switch to GPIO mode with PMC register */ + pmc &= ~BIT(pin); + writeb(pmc, pctrl->base + PMC(off)); + + /* Select Pin function mode. */ + pfc &= ~(PFC_MASK << (pin * 4)); + pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4))); + writel(pfc, pctrl->base + PFC(off)); + + /* Switch to Peripheral pin function. */ + pmc |= BIT(pin); + writeb(pmc, pctrl->base + PMC(off)); + } + } + + /* Set the PWPR register to be write-protected. */ + writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */ + writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */ +} + +static int rzg2l_pinctrl_suspend_noirq(struct device *dev) +{ + struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; + const struct rzg2l_register_offsets *regs = &hwcfg->regs; + struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; + + rzg2l_pinctrl_pm_setup_regs(pctrl, true); + rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true); + + for (u8 i = 0; i < 2; i++) { + cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); + cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); + } + + cache->qspi = readb(pctrl->base + QSPI); + cache->eth_mode = readb(pctrl->base + ETH_MODE); + + if (!atomic_read(&pctrl->wakeup_path)) + clk_disable_unprepare(pctrl->clk); + else + device_set_wakeup_path(dev); + + return 0; +} + +static int rzg2l_pinctrl_resume_noirq(struct device *dev) +{ + struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev); + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; + const struct rzg2l_register_offsets *regs = &hwcfg->regs; + struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; + int ret; + + if (!atomic_read(&pctrl->wakeup_path)) { + ret = clk_prepare_enable(pctrl->clk); + if (ret) + return ret; + } + + writeb(cache->qspi, pctrl->base + QSPI); + writeb(cache->eth_mode, pctrl->base + ETH_MODE); + for (u8 i = 0; i < 2; i++) { + writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); + writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); + } + + rzg2l_pinctrl_pm_setup_pfc(pctrl); + rzg2l_pinctrl_pm_setup_regs(pctrl, false); + rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false); + rzg2l_gpio_irq_restore(pctrl); + + return 0; +} + static const struct rzg2l_hwcfg rzg2l_hwcfg = { .regs = { .pwpr = 0x3014, @@ -2313,10 +2708,15 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = { { /* sentinel */ } }; +static const struct dev_pm_ops rzg2l_pinctrl_pm_ops = { + NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg2l_pinctrl_suspend_noirq, rzg2l_pinctrl_resume_noirq) +}; + static struct platform_driver rzg2l_pinctrl_driver = { .driver = { .name = DRV_NAME, .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table), + .pm = pm_sleep_ptr(&rzg2l_pinctrl_pm_ops), }, .probe = rzg2l_pinctrl_probe, }; From patchwork Fri Jun 7 14:08:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13690056 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B8EBC27C6F for ; Fri, 7 Jun 2024 14:09:21 +0000 (UTC) Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) by mx.groups.io with SMTP id smtpd.web10.42761.1717769354673788753 for ; Fri, 07 Jun 2024 07:09:14 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=oEPb9Mpz; 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([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.09.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:09:12 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 10/17] pinctrl: renesas: rzg2l: Select GPIOLIB_IRQCHIP and IRQ_DOMAIN_HIERARCHY Date: Fri, 7 Jun 2024 17:08:49 +0300 Message-Id: <20240607140856.2497508-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:21 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16171 From: Claudiu Beznea commit fda5edd7d66f091770b600f789dd4190ce6a7907 upstream. The pinctrl-rzg2l driver accesses gpio_chip.irq, which is available only if CONFIG_GPIOLIB_IRQCHIP=y, and uses APIs that are defined only if CONFIG_IRQ_DOMAIN_HIERARCHY=y (irq_chip_*_parent() APIs). On ARCH_RZG2L, CONFIG_IRQ_DOMAIN_HIERARCHY is selected anyway, e.g. by CONFIG_ARM_GIC_V3, but CONFIG_GPIOLIB_IRQCHIP is not (it is on R-Car). Make this explicit at the driver level for a clearer view of the dependencies. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240215124112.2259103-2-claudiu.beznea.uj@bp.renesas.com [geert: select GPIOLIB_IRQCHIP, too] Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- drivers/pinctrl/renesas/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 1ef875980261..5fc190fa2f68 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -192,9 +192,11 @@ config PINCTRL_RZG2L bool "pin control support for RZ/{G2L,G2UL,V2L}" if COMPILE_TEST depends on OF select GPIOLIB + select GPIOLIB_IRQCHIP select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF + select IRQ_DOMAIN_HIERARCHY help This selects GPIO and pinctrl driver for Renesas RZ/{G2L,G2UL,V2L} platforms. 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([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.09.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:09:13 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 11/17] irqchip/renesas-rzg2l: Add support for suspend to RAM Date: Fri, 7 Jun 2024 17:08:50 +0300 Message-Id: <20240607140856.2497508-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:21 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16172 From: Claudiu Beznea commit 74d2ef5f6f4b2437e6292ab2502400e8048db4aa upstream. The irqchip-renesas-rzg2l driver is used on RZ/G3S SoC. RZ/G3S can go into deep sleep states where power to different SoC's parts is cut off and RAM is switched to self-refresh. The resume from these states is done with the help of the bootloader. The IA55 IRQ controller needs to be reconfigured when resuming from deep sleep state. For this the IA55 registers are cached in suspend and restored in resume. The IA55 IRQ controller is connected to GPIO controller and GIC as follows: ┌──────────┐ ┌──────────┐ │ │ SPIX │ │ │ ├─────────►│ │ │ │ │ │ │ │ │ │ ┌────────┐IRQ0-7 │ IA55 │ │ GIC │ Pin0 ───────►│ ├─────────────►│ │ │ │ │ │ │ │ PPIY │ │ ... │ GPIO │ │ ├─────────►│ │ │ │GPIOINT0-127 │ │ │ │ PinN ───────►│ ├─────────────►│ │ │ │ └────────┘ └──────────┘ └──────────┘ where: - Pin0 is the first GPIO controller pin - PinN is the last GPIO controller pin - SPIX is the SPI interrupt with identifier X - PPIY is the PPI interrupt with identifier Y Implement suspend/resume functionality with syscore_ops to be able to cache/restore the registers after/before the GPIO controller suspend/resume functions are invoked. As the syscore_ops suspend/resume functions do not take any argument make the driver private data static so it can be accessed from the suspend/resume functions. The IA55 interrupt controller is resumed before the GPIO controller. As GPIO pins could be in an a state which causes spurious interrupts, the reconfiguration of the interrupt controller is restricted to restore the interrupt type and leave them disabled. An eventually required interrupt enable operation will be done as part of the GPIO controller resume function after restoring the GPIO state. [ tglx: Massaged changelog ] Signed-off-by: Claudiu Beznea Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20231120111820.87398-8-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 68 ++++++++++++++++++++++++----- 1 file changed, 57 insertions(+), 11 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 9b0a748ea2cb..ae67fec2ab46 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -18,6 +18,7 @@ #include #include #include +#include #define IRQC_IRQ_START 1 #define IRQC_IRQ_COUNT 8 @@ -55,17 +56,29 @@ #define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) +/** + * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume) + * @iitsr: IITSR register + * @titsr: TITSR registers + */ +struct rzg2l_irqc_reg_cache { + u32 iitsr; + u32 titsr[2]; +}; + /** * struct rzg2l_irqc_priv - IRQ controller private data structure * @base: Controller's base address * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers + * @cache: Registers cache for suspend/resume */ -struct rzg2l_irqc_priv { +static struct rzg2l_irqc_priv { void __iomem *base; struct irq_fwspec fwspec[IRQC_NUM_IRQ]; raw_spinlock_t lock; -}; + struct rzg2l_irqc_reg_cache cache; +} *rzg2l_irqc_data; static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) { @@ -282,6 +295,38 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } +static int rzg2l_irqc_irq_suspend(void) +{ + struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; + void __iomem *base = rzg2l_irqc_data->base; + + cache->iitsr = readl_relaxed(base + IITSR); + for (u8 i = 0; i < 2; i++) + cache->titsr[i] = readl_relaxed(base + TITSR(i)); + + return 0; +} + +static void rzg2l_irqc_irq_resume(void) +{ + struct rzg2l_irqc_reg_cache *cache = &rzg2l_irqc_data->cache; + void __iomem *base = rzg2l_irqc_data->base; + + /* + * Restore only interrupt type. TSSRx will be restored at the + * request of pin controller to avoid spurious interrupts due + * to invalid PIN states. + */ + for (u8 i = 0; i < 2; i++) + writel_relaxed(cache->titsr[i], base + TITSR(i)); + writel_relaxed(cache->iitsr, base + IITSR); +} + +static struct syscore_ops rzg2l_irqc_syscore_ops = { + .suspend = rzg2l_irqc_irq_suspend, + .resume = rzg2l_irqc_irq_resume, +}; + static const struct irq_chip irqc_chip = { .name = "rzg2l-irqc", .irq_eoi = rzg2l_irqc_eoi, @@ -367,7 +412,6 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) struct irq_domain *irq_domain, *parent_domain; struct platform_device *pdev; struct reset_control *resetn; - struct rzg2l_irqc_priv *priv; int ret; pdev = of_find_device_by_node(node); @@ -380,15 +424,15 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) return -ENODEV; } - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) + rzg2l_irqc_data = devm_kzalloc(&pdev->dev, sizeof(*rzg2l_irqc_data), GFP_KERNEL); + if (!rzg2l_irqc_data) return -ENOMEM; - priv->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); + if (IS_ERR(rzg2l_irqc_data->base)) + return PTR_ERR(rzg2l_irqc_data->base); - ret = rzg2l_irqc_parse_interrupts(priv, node); + ret = rzg2l_irqc_parse_interrupts(rzg2l_irqc_data, node); if (ret) { dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret); return ret; @@ -411,17 +455,19 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) goto pm_disable; } - raw_spin_lock_init(&priv->lock); + raw_spin_lock_init(&rzg2l_irqc_data->lock); irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ, node, &rzg2l_irqc_domain_ops, - priv); + rzg2l_irqc_data); if (!irq_domain) { dev_err(&pdev->dev, "failed to add irq domain\n"); ret = -ENOMEM; goto pm_put; } + register_syscore_ops(&rzg2l_irqc_syscore_ops); + return 0; pm_put: From patchwork Fri Jun 7 14:08:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13690055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42CF4C27C6E for ; Fri, 7 Jun 2024 14:09:21 +0000 (UTC) Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) by mx.groups.io with SMTP id smtpd.web11.43056.1717769357906680559 for ; Fri, 07 Jun 2024 07:09:18 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=C+Tbo9IU; spf=pass (domain: tuxon.dev, ip: 209.85.218.46, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-a68e7538cfaso275795866b.0 for ; Fri, 07 Jun 2024 07:09:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1717769356; x=1718374156; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WuFrhNWP6t8VQyXp9dFcTbfifanXPHZ8V/2rNC+tFpM=; b=C+Tbo9IUk8Sg3Tns3Fb0JMUXq8KQpzzpW7/7UpDvvFzilU+a4E4spyURJlPbDQuYhc WRK3ZbZ52Tm6XLfctyVvXEBJDywrB4pBLB9asDFg1HeRDzD86ucpLX86YDeG27jlE4Zu 8LH2Oljjkurz/Tt4FhZF5eBGveSlu/Dbi6HYPTwMTGN9foTUVRKe9XbYsrGvfcy4cCIP e0JxCiQwZSHZqwfN0cHimJsVG9RvyG3ozDd2tZn3Mhc9tMqxSFnl8OiVDfGpwGZn44qx eU6jkHXlGPJ5DSwYCDDut7KrXfrPPk7/Cnq8cdKdiyB6eDrq+Llvi00zEAUZLX+UMi3/ kT+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717769356; x=1718374156; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WuFrhNWP6t8VQyXp9dFcTbfifanXPHZ8V/2rNC+tFpM=; b=uGZ11uQK7tqBFy4hxE/04rIz9+a5HTfYEmCJEaIA8xhf9AyJi/HZO3N8nEsVMd7gvK gd0hYT2Og/Eq1H262WTqb/1n9qTFHt54m1gTpBKFTnHO18q5/bD1ttTfzT/133qoEmKr CWu78g6e0j3c+Pe80nb8RcCHD0P0UM2/8CjS+0kfva7Wl/zKHynu93XHIrts833Va8Ib I23J8aWFq4KCXSwvgcVuynh2w9bBKsvba9oEDCBKx9m7wI8lI/h2DYjKLutIpXnXR5w9 h3mZHoXha0b7ZjaDweZ/etYhb8C65/lL1mJSdDNDoGs90fSph4eyYzWE5vv47QR832qq DFQQ== X-Gm-Message-State: AOJu0YxWCv4AAncLKfOb4xCCiSD/PS/h2Z4/XRivmPzeLbqYPEO7R6mC aFpsxAnikDWgpeFKZ5m997BipWoD3hxcebqm8l6xQRht/GR2R282g4SmI3HSv6P3J949mMB9Zqp g X-Google-Smtp-Source: AGHT+IHzOvIwJDB7+5uGVB/Yw3EMZgoLFZriQg/Pzp4mM+Yvxu116zYAT6RmBDiOKG9mgCD6wjHrLg== X-Received: by 2002:a17:906:70d0:b0:a6e:2a27:5669 with SMTP id a640c23a62f3a-a6e2a2766admr110913766b.23.1717769356375; Fri, 07 Jun 2024 07:09:16 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.09.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:09:15 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 12/17] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC Date: Fri, 7 Jun 2024 17:08:51 +0300 Message-Id: <20240607140856.2497508-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:21 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16173 From: Lad Prabhakar commit db712c0089bd8e9e47c286ed772d86fb187d0854 upstream. Document RZ/G2UL (R9A07G043U) IRQC bindings. The IRQC block on RZ/G2UL SoC is almost identical to one found on the RZ/G2L SoC the only difference being it can support BUS_ERR_INT for which it has additional registers. Hence new generic compatible string "renesas,r9a07g043u-irqc" is added for RZ/G2UL SoC. Now that we have additional interrupt for RZ/G2UL and RZ/Five SoC interrupt-names property is added so that we can parse them based on names. While at it updated the example node to four spaces and added interrupt-names property. Signed-off-by: Lad Prabhakar Reviewed-by: Rob Herring Reviewed-by: Geert Uytterhoeven Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20231006121058.13890-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Claudiu Beznea --- .../renesas,rzg2l-irqc.yaml | 225 +++++++++++++----- 1 file changed, 170 insertions(+), 55 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml index ea7db3618b23..2ef3081eaaf3 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml @@ -19,13 +19,11 @@ description: | - NMI edge select (NMI is not treated as NMI exception and supports fall edge and stand-up edge detection interrupts) -allOf: - - $ref: /schemas/interrupt-controller.yaml# - properties: compatible: items: - enum: + - renesas,r9a07g043u-irqc # RZ/G2UL - renesas,r9a07g044-irqc # RZ/G2{L,LC} - renesas,r9a07g054-irqc # RZ/V2L - const: renesas,rzg2l-irqc @@ -45,7 +43,96 @@ properties: maxItems: 1 interrupts: - maxItems: 41 + minItems: 41 + items: + - description: NMI interrupt + - description: IRQ0 interrupt + - description: IRQ1 interrupt + - description: IRQ2 interrupt + - description: IRQ3 interrupt + - description: IRQ4 interrupt + - description: IRQ5 interrupt + - description: IRQ6 interrupt + - description: IRQ7 interrupt + - description: GPIO interrupt, TINT0 + - description: GPIO interrupt, TINT1 + - description: GPIO interrupt, TINT2 + - description: GPIO interrupt, TINT3 + - description: GPIO interrupt, TINT4 + - description: GPIO interrupt, TINT5 + - description: GPIO interrupt, TINT6 + - description: GPIO interrupt, TINT7 + - description: GPIO interrupt, TINT8 + - description: GPIO interrupt, TINT9 + - description: GPIO interrupt, TINT10 + - description: GPIO interrupt, TINT11 + - description: GPIO interrupt, TINT12 + - description: GPIO interrupt, TINT13 + - description: GPIO interrupt, TINT14 + - description: GPIO interrupt, TINT15 + - description: GPIO interrupt, TINT16 + - description: GPIO interrupt, TINT17 + - description: GPIO interrupt, TINT18 + - description: GPIO interrupt, TINT19 + - description: GPIO interrupt, TINT20 + - description: GPIO interrupt, TINT21 + - description: GPIO interrupt, TINT22 + - description: GPIO interrupt, TINT23 + - description: GPIO interrupt, TINT24 + - description: GPIO interrupt, TINT25 + - description: GPIO interrupt, TINT26 + - description: GPIO interrupt, TINT27 + - description: GPIO interrupt, TINT28 + - description: GPIO interrupt, TINT29 + - description: GPIO interrupt, TINT30 + - description: GPIO interrupt, TINT31 + - description: Bus error interrupt + + interrupt-names: + minItems: 41 + items: + - const: nmi + - const: irq0 + - const: irq1 + - const: irq2 + - const: irq3 + - const: irq4 + - const: irq5 + - const: irq6 + - const: irq7 + - const: tint0 + - const: tint1 + - const: tint2 + - const: tint3 + - const: tint4 + - const: tint5 + - const: tint6 + - const: tint7 + - const: tint8 + - const: tint9 + - const: tint10 + - const: tint11 + - const: tint12 + - const: tint13 + - const: tint14 + - const: tint15 + - const: tint16 + - const: tint17 + - const: tint18 + - const: tint19 + - const: tint20 + - const: tint21 + - const: tint22 + - const: tint23 + - const: tint24 + - const: tint25 + - const: tint26 + - const: tint27 + - const: tint28 + - const: tint29 + - const: tint30 + - const: tint31 + - const: bus-err clocks: maxItems: 2 @@ -73,6 +160,23 @@ required: - power-domains - resets +allOf: + - $ref: /schemas/interrupt-controller.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,r9a07g043u-irqc + then: + properties: + interrupts: + minItems: 42 + interrupt-names: + minItems: 42 + required: + - interrupt-names + unevaluatedProperties: false examples: @@ -81,55 +185,66 @@ examples: #include irqc: interrupt-controller@110a0000 { - compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc"; - reg = <0x110a0000 0x10000>; - #interrupt-cells = <2>; - #address-cells = <0>; - interrupt-controller; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, - <&cpg CPG_MOD R9A07G044_IA55_PCLK>; - clock-names = "clk", "pclk"; - power-domains = <&cpg>; - resets = <&cpg R9A07G044_IA55_RESETN>; + compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc"; + reg = <0x110a0000 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31"; + clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, + <&cpg CPG_MOD R9A07G044_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_IA55_RESETN>; }; From patchwork Fri Jun 7 14:08:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13690057 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50B6FC27C5F for ; Fri, 7 Jun 2024 14:09:21 +0000 (UTC) Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) by mx.groups.io with SMTP id smtpd.web11.43057.1717769358907338412 for ; Fri, 07 Jun 2024 07:09:19 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=m9NpajpM; spf=pass (domain: tuxon.dev, ip: 209.85.208.54, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-57aa64c6bbfso2303374a12.3 for ; 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([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.09.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:09:17 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 13/17] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S Date: Fri, 7 Jun 2024 17:08:52 +0300 Message-Id: <20240607140856.2497508-14-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:21 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16174 From: Claudiu Beznea commit 1cf0697a24ef60b3ce8be47090a6e8e79329d962 upstream. Document the RZ/G3S (R9108G045) interrupt controller. This has few extra functionalities compared with RZ/G2UL but the already existing driver can still be used. Signed-off-by: Claudiu Beznea Signed-off-by: Thomas Gleixner Reviewed-by: Geert Uytterhoeven Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20231120111820.87398-9-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Claudiu Beznea --- .../bindings/interrupt-controller/renesas,rzg2l-irqc.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml index 2ef3081eaaf3..d3b5aec0a3f7 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043u-irqc # RZ/G2UL - renesas,r9a07g044-irqc # RZ/G2{L,LC} - renesas,r9a07g054-irqc # RZ/V2L + - renesas,r9a08g045-irqc # RZ/G3S - const: renesas,rzg2l-irqc '#interrupt-cells': @@ -167,7 +168,9 @@ allOf: properties: compatible: contains: - const: renesas,r9a07g043u-irqc + enum: + - renesas,r9a07g043u-irqc + - renesas,r9a08g045-irqc then: properties: interrupts: From patchwork Fri Jun 7 14:08:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13690060 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CECBC27C53 for ; Fri, 7 Jun 2024 14:09:31 +0000 (UTC) Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) by mx.groups.io with SMTP id smtpd.web10.42765.1717769361378434212 for ; Fri, 07 Jun 2024 07:09:21 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=Y5bSbC+a; spf=pass (domain: tuxon.dev, ip: 209.85.218.43, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f43.google.com with SMTP id a640c23a62f3a-a68c5524086so253508966b.3 for ; Fri, 07 Jun 2024 07:09:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1717769360; x=1718374160; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TImLYVGwYaEIQ6UzmedMc1+86VLx/JtcipOBs6oz8lo=; b=Y5bSbC+abrPR1O9bLdTMrIS5p4g+54QAmlLo+HTF+a0LDGOS5YiEfb01FxzJp3mzAQ jJZBIM3FWRxNLhilL31U5JhOJp2OlYdA397ddb9JKE+9+RJCyiZ9d/rs7Vwxap2aHwgC hssywDcXhyIvqpQlNnrppy4c6LDzMBtuMpiX1y14yiCFa9YdFpw5ydXhGB7EjdaBeXf3 uElxXLoWmxrz5dxvbl6YSSt1nIZrRyLgd0jw2PC/3WQXx4YasbM8U38j7wOiF26StOUF I3ag0QZZ1ylGTFmTtr+dtIBUeFFmmCj/b3dvzO/M99mhjzA8XtdKCCZ84Q4URsnxrtVk k9mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717769360; x=1718374160; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TImLYVGwYaEIQ6UzmedMc1+86VLx/JtcipOBs6oz8lo=; b=btobFXSe+03ZUlBioQ9KVeFiR6AzbbHJOZ+Lw4gP97LcwsEaNvldv+uV0I4RSU01Nu B5TrWrLRP1GKGh6jaGuvxoqqclxBPB9CuKQat4MIrpV0aLz0r8zi5tYDmsNT1YjZ1SV+ /6LpSqOUKCkWVEDgf+mJWrJepLlQTTZ0MfXmJjK3y8QMmnSZ9AbFDPOHThVS8PNMtrUG 0RoPErjWtSmnBhQxaR2SNjXaYvYSrHs1klskXkwEzfUeHFfQBhAckW0Qvb1sLr9wR6CV OLJ8mFff7HfFKsB18Kz+kb90DKF3Mhelm15C54HPW1Pg9QJeIrwrEHmz94ppegm4QiAh fECg== X-Gm-Message-State: AOJu0Yy7jD8CQTRhx1kw7y8wVt5MkuNdMVbGrMYSbHzmyI6mzSgQYd/a 7yDZzO12anvwIODh7cqwFNwdnSXmByZ4vocVw1I4mv8XTvtFtqol8UNMZxdpEakA22uYWFwM3JU + X-Google-Smtp-Source: AGHT+IHpx8E0nSJAc6ruo/h8eRMyRPN0MWfe1dDR/nW6Byxar90eVYB6f+0V8og308iepP1dM+ZKpQ== X-Received: by 2002:a17:906:a08e:b0:a66:fb17:3567 with SMTP id a640c23a62f3a-a6cd561185dmr188859266b.2.1717769359819; Fri, 07 Jun 2024 07:09:19 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.09.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:09:18 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 14/17] arm64: dts: renesas: r9a08g045: Add IA55 interrupt controller node Date: Fri, 7 Jun 2024 17:08:53 +0300 Message-Id: <20240607140856.2497508-15-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:31 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16175 From: Claudiu Beznea commit 837918aa3fdd6ecdc24c9dbfaa4e5ed8151acc60 upstream. Add IA55 interrupt controller node and set it as interrupt parent for pin controller. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231120111820.87398-10-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index aaab5739c134..5facfad96158 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -96,6 +96,7 @@ pinctrl: pinctrl@11030000 { #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + interrupt-parent = <&irqc>; gpio-ranges = <&pinctrl 0 0 152>; clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; power-domains = <&cpg>; @@ -104,6 +105,73 @@ pinctrl: pinctrl@11030000 { <&cpg R9A08G045_GPIO_SPARE_RESETN>; }; + irqc: interrupt-controller@11050000 { + compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x11050000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "bus-err"; + clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>, + <&cpg CPG_MOD R9A08G045_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_IA55_RESETN>; + }; + sdhi0: mmc@11c00000 { compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; From patchwork Fri Jun 7 14:08:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13690061 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69ED7C41513 for ; Fri, 7 Jun 2024 14:09:31 +0000 (UTC) Received: from mail-lf1-f46.google.com (mail-lf1-f46.google.com [209.85.167.46]) by mx.groups.io with SMTP id smtpd.web11.43060.1717769362741526892 for ; Fri, 07 Jun 2024 07:09:23 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=joY+lB7T; spf=pass (domain: tuxon.dev, ip: 209.85.167.46, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-lf1-f46.google.com with SMTP id 2adb3069b0e04-52bc3130ae6so299662e87.3 for ; Fri, 07 Jun 2024 07:09:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1717769361; x=1718374161; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bflcX6nbdHaX857+csHfWNKFzZ2w80yYoNBs+5YjahU=; b=joY+lB7TcyBSiKsaqT0Or0nU2e+WsIr960MvW4FaM1YOXA36B0hrUGtY6k8IdVZeeH DvA2ig2mLWR/wUj163AxmadIt0FExNTIRTiXRRo2hehe+93Xb07v+Rd+OxgB6wOfOE+Q QrgyecWOfXpBvImYC5W5sS5/0WKJX26/YWIfp3zgtYQ22Gb/R3KG1Zn0ieuN6Od9bTml vXjJZII916dqeoS/zrDbvNraogbRFyro2yeDsIBs3XwGGJ3qPmCx3/RMNX64jjTKa1g2 0MP500kky0As6s8nozU5lAMjtld/NjqI+UMhUhPa88SXHI011B/cC8BkXYf71qpWbsG+ HiEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717769361; x=1718374161; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bflcX6nbdHaX857+csHfWNKFzZ2w80yYoNBs+5YjahU=; b=pd3g7K0HjmOOHtvlFbQRGOiGG3y6XP9ju+IjMTtLEK47MMxGPmK+RktG9CO/asnRL9 jUlu/n93ofHsM9qj7MVw2EzDBUpN5kG3SCyOMijroFgot7FbUqQcEs1x7+AVHtQ+QUeg FCeJICSMYEI3MJPxwyMNV5WIhEBEvwJR4EbNufnYB9GUejNj+p50tfgcK93ZDE8VSRoB CPyqqz36RVm+TZerSfE+qJ8Wyv0pf+RT0tIxd6X4S/q7G2+BXHxUpOWPiF1SyNIAj1S2 MdIHxWlU5SKRPoI6VyvO9/+ZAXZDBuCGlA5bl8lEaxBVB5sRkwuSHjdwlt3jLdjHVUBx 6Q3A== X-Gm-Message-State: AOJu0YzYmsGCpTi85/Lb4ulAnXH6ehD8p+0PMMr+uZ5oz30KUFD6WX7c SBT21+LLsteBT8HD7BAG2n1ZiqBAS9Zhcrij/UhHj5Vjg7sQPNbbEg/ZjS+GUZMllLvv4xh3ozM R X-Google-Smtp-Source: AGHT+IGGJwDkMQThQ52iCL4BWP5nikO1MaLubvQJUJNjQNrhw7FPqHqZHz7QljUh/aAFjLiSK1Ngeg== X-Received: by 2002:a05:6512:704:b0:52b:be6c:9bcd with SMTP id 2adb3069b0e04-52bbe6c9ffamr944532e87.6.1717769360924; Fri, 07 Jun 2024 07:09:20 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.09.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:09:20 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 15/17] arm64: dts: renesas: r9a08g045: Add PSCI support Date: Fri, 7 Jun 2024 17:08:54 +0300 Message-Id: <20240607140856.2497508-16-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:31 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16176 From: Claudiu Beznea commit 145f33d1f1db869da15beff664f2c787fc94541f upstream. Add PSCI support to enable suspend/resume with the help of TF-A. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240208135629.2840932-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 5facfad96158..02fd68b06eea 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -42,6 +42,11 @@ extal_clk: extal-clk { clock-frequency = <0>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; From patchwork Fri Jun 7 14:08:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13690062 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FCB9C27C6E for ; Fri, 7 Jun 2024 14:09:31 +0000 (UTC) Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) by mx.groups.io with SMTP id smtpd.web10.42769.1717769364128561761 for ; Fri, 07 Jun 2024 07:09:24 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=QUMvy6h+; spf=pass (domain: tuxon.dev, ip: 209.85.208.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-57a2f27090aso5434741a12.0 for ; Fri, 07 Jun 2024 07:09:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1717769362; x=1718374162; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8u9EFSWCFzBU6PBuVFaluzhvL7+pBPGLLnR+2pKY/QU=; b=QUMvy6h+wax9ddVo7aQ5uRpQkGejG+AsKFTJeTfPTJgEtEl6psZqiYNTkMyr3jCCgE z3s5VKx2P2AbKYTVHR7QZH3kU3Xxxq0FoRul1xwFBd10468M/vj6V+jPaJDCl51yIqQr nIwPHwMM91RHNITwnJ2Q7DKMbiArMrafCAah3FzpedjGoSaTpfHt2T6YSXNxXz55U5Lc 3hofG93ASjQaLuIgKWC8fGeGF2yHqDMoo8bZaI2xJIkEpm0c8WxOMEaejX4gK62rfBIo dmZfdlbXj+NlH29T/fyUIOkcDe1Az4OgeYaIXfB1ta5MtuxXn+9r4Niu5KzlRHkLgu4I BrNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717769362; x=1718374162; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8u9EFSWCFzBU6PBuVFaluzhvL7+pBPGLLnR+2pKY/QU=; b=JjiLfo31/oH62hI62s0nifIXd9p8no/SRaN3AB5J1rSImGL1hfqbSjwkx7AUxVHxY7 w/rG942keTmTiBVvAonNomOD4XMZ8qIqMWrpxQBkduPT6hrYCsSUB8ZQzOxoIHmOxbxB ATca0IrxNPsFI5TIPgNb5fGdThxJKqTv6VEjpRTv4m6iPMv1HrUN0LTb7eh4TpLvdzXU ha6GonP2rJ18rJjtiGJWnTY7II48P4JgmwnXEfd6IUvfGrhhM5hPvFgnVMFDbAskgQPk G6QmnqIkqTZwzoRZ6SoB7oY8bFHFp3CZRTvxepuI+SK4znvY2PIj2I58QHIWQ2ku0tvU AxMA== X-Gm-Message-State: AOJu0Ywdba/FnxkjvWBscLgriIDiA+ivFxKEFplCj0MnDqAVcW9mfiaA c9vSK6tVnr/Lym8WEDg8PS0zbgyobrGYpeYSPvhIMI9fT30KQ+grAK0APt0bYlk= X-Google-Smtp-Source: AGHT+IGsVT0CuBOlPF4mdCMxOLqtwos/kE3ap1Zid3/oHU1xdMBLO3dGXWuT2h9xTYCfU0iAOnSWVg== X-Received: by 2002:a17:906:c254:b0:a6c:70f3:de0f with SMTP id a640c23a62f3a-a6cbc6ca035mr236133066b.28.1717769362561; Fri, 07 Jun 2024 07:09:22 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.09.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:09:21 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 16/17] arm64: dts: renesas: rzg3s-smarc: Add gpio keys Date: Fri, 7 Jun 2024 17:08:55 +0300 Message-Id: <20240607140856.2497508-17-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:31 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16177 From: Claudiu Beznea commit 347c80f7c7b207ad8cb183822df75f70b7dc0773 upstream. RZ SMARC Carrier II board has 3 user buttons called USER_SW1, USER_SW2, USER_SW3. Add a DT node in device tree to propertly instantiate the gpio-keys driver for these buttons. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231227130810.2744550-1-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 53 ++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 214520137230..deb2ad37bb2e 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include / { @@ -14,6 +15,37 @@ aliases { mmc1 = &sdhi1; }; + keys { + compatible = "gpio-keys"; + + key-1 { + interrupts = ; + interrupt-parent = <&pinctrl>; + linux,code = ; + label = "USER_SW1"; + wakeup-source; + debounce-interval = <20>; + }; + + key-2 { + interrupts = ; + interrupt-parent = <&pinctrl>; + linux,code = ; + label = "USER_SW2"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + interrupts = ; + interrupt-parent = <&pinctrl>; + linux,code = ; + label = "USER_SW3"; + wakeup-source; + debounce-interval = <20>; + }; + }; + vcc_sdhi1: regulator-vcc-sdhi1 { compatible = "regulator-fixed"; regulator-name = "SDHI1 Vcc"; @@ -35,6 +67,27 @@ vccq_sdhi1: regulator-vccq-sdhi1 { }; &pinctrl { + key-1-gpio-hog { + gpio-hog; + gpios = ; + input; + line-name = "key-1-gpio-irq"; + }; + + key-2-gpio-hog { + gpio-hog; + gpios = ; + input; + line-name = "key-2-gpio-irq"; + }; + + key-3-gpio-hog { + gpio-hog; + gpios = ; + input; + line-name = "key-3-gpio-irq"; + }; + scif0_pins: scif0 { pinmux = , /* RXD */ ; /* TXD */ From patchwork Fri Jun 7 14:08:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13690063 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A869C27C5F for ; Fri, 7 Jun 2024 14:09:31 +0000 (UTC) Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) by mx.groups.io with SMTP id smtpd.web11.43062.1717769365911136097 for ; Fri, 07 Jun 2024 07:09:26 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@tuxon.dev header.s=google header.b=ZTKQw4tT; spf=pass (domain: tuxon.dev, ip: 209.85.218.49, mailfrom: claudiu.beznea@tuxon.dev) Received: by mail-ej1-f49.google.com with SMTP id a640c23a62f3a-a68a9a4e9a6so208871566b.3 for ; Fri, 07 Jun 2024 07:09:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1717769364; x=1718374164; darn=lists.cip-project.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/SPBI/PgK9GyReJZyefK3nQtExOWXPBhl2T9F+V3rjE=; b=ZTKQw4tTsGVsI4zjv2e/kdczM+kk/lGOk+7UenuoQCN04zywo3ty0sN0B9RPWO5w/2 iEwtM3GeMkvuUe6RXwMKH0/1WkOue+Hnuq2rwxMcL/n3G4wMheCvnIB2JmTUS9JrjXoP 4fQRNLG/xTA7nB0GS6h+0tgBWzm4LTkPlDrAQSpM9ks7+ysqpM5EU0qeSwS56uYrWSd6 /eoTG1QIUQTFh7YSYKC/B7y3RNA5tnEFmHix/vY4uP06ugDpXC8ROBFy3nde741c/tPd C+3S3GRZTUkbU7PGui/pp5+FXwC2V3PxWpecLL0Z2hQAS/938eKeAdADTsp/OLOhbJ0u Fwdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717769364; x=1718374164; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/SPBI/PgK9GyReJZyefK3nQtExOWXPBhl2T9F+V3rjE=; b=WpwI7bSHvy/OahUBZWRpta4iYNBBDcfmX/8FFevCU3tOSJr0wqthdWrbjjU84B0SwO zC/oH7tfENjeuQ2Fy2hgwt8stKQVPDL9fNEPgZOe8nJYeOqy9/7tcWE88JAL02fop1d1 /9nttwejtGFSPrsv1PjrUuRecasi9HyVlkAB0YufFMlqXk/auzb4dNZ9tOS+8qYp+m45 IpQxS5KHKarcgWsgxpM13HsHKA+PaDUXqCnw1BOKTNSVFWMgdKS44I1AEHcsKYcxagR6 8NWmiKB+oPWE8izdg78JiJ7V5XUKnXvFDKApfNqTbvsRPzKdyj42f5gEHGMY0dqzNhqI ICNw== X-Gm-Message-State: AOJu0YwvBnGffAqjEpYHZoGz3g45bWUfkrD+hsl5tljatCAPm9RZ/vdW 8VlQo7ulOO71l4HT6s5kj/a3/N+P3FWMabiaf0RcDhSEWlLx+VkGfG4caQHZ+uHqqfOQYU1+L2U M X-Google-Smtp-Source: AGHT+IGaEg+CdxQFy8PGgkYVnr11rwrvyBgd3vhziF1DdfRj1pbigfbqjLo1N+NGXGavI4BrhRXJpw== X-Received: by 2002:a17:906:84d:b0:a6c:717a:5112 with SMTP id a640c23a62f3a-a6cd665ca24mr221527566b.21.1717769364289; Fri, 07 Jun 2024 07:09:24 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c80581870sm251987466b.25.2024.06.07.07.09.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jun 2024 07:09:23 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: nobuhiro1.iwamatsu@toshiba.co.jp, pavel@denx.de Cc: cip-dev@lists.cip-project.org, biju.das.jz@bp.renesas.com, prabhakar.mahadev-lad.rj@bp.renesas.com Subject: [PATCH 6.1.y-cip 17/17] arm64: dts: renesas: r9a08g045: Add missing interrupts to IRQC node Date: Fri, 7 Jun 2024 17:08:56 +0300 Message-Id: <20240607140856.2497508-18-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> References: <20240607140856.2497508-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 List-Id: X-Webhook-Received: from li982-79.members.linode.com [45.33.32.79] by aws-us-west-2-korg-lkml-1.web.codeaurora.org with HTTPS for ; Fri, 07 Jun 2024 14:09:31 -0000 X-Groupsio-URL: https://lists.cip-project.org/g/cip-dev/message/16178 From: Lad Prabhakar commit bf7e37716d995c54630c30540db5642f58ea037a upstream. The IRQC block on the RZ/G3S (R9A08G045) SoC supports ECCRAM error interrupts too. Add those missing interrupts to the IRQC node. Fixes: 837918aa3fdd ("arm64: dts: renesas: r9a08g045: Add IA55 interrupt controller node") Signed-off-by: Lad Prabhakar Reviewed-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240205144421.51195-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 02fd68b06eea..aba6b0383778 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -157,7 +157,10 @@ irqc: interrupt-controller@11050000 { , , , - ; + , + , + , + ; interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3", "irq4", "irq5", "irq6", "irq7", @@ -169,7 +172,8 @@ irqc: interrupt-controller@11050000 { "tint20", "tint21", "tint22", "tint23", "tint24", "tint25", "tint26", "tint27", "tint28", "tint29", "tint30", "tint31", - "bus-err"; + "bus-err", "ec7tie1-0", "ec7tie2-0", + "ec7tiovf-0"; clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>, <&cpg CPG_MOD R9A08G045_IA55_PCLK>; clock-names = "clk", "pclk";