From patchwork Mon Jun 10 11:09:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13691904 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BD0E7C27C55 for ; Mon, 10 Jun 2024 11:10:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=s/BPYZ880ZbfrzdSFInAEFpLbujKTS4XY+rH0qD4heo=; b=0wNfj5GR/4YJhv cfpMmWwIF/0LBY9N24rqQOunaOhPg0dgiQMhxmaJSuQTx4oMzk+ZOy7oS+mW7oE77FRKr57vjy+wr NMhEBVJTCxD1XPh53oEUzeA0RsxeJyLRwDv9MYTmXeYsNqAq1yzVL67gJfwWfJmAUZDQGnfFvXJFM lWNyn9Ig/mMOLf6Hf4b5QvvV8FGhaPQcUDoBx/OEqXI4MYuO1zhSOhfdN+7oXrzDXq1V3dKgNBuf+ 48KpSHYlhoTCAnFvWZ4aUSrFsSZvWJSYWx7HiWj3+iNU+zXaR9lxsYSCRH1GzvLi2ofvE3KzckAJB Mq8r/m+txBoK1TKhkVAg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sGcus-00000004ls8-0qxB; Mon, 10 Jun 2024 11:10:22 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sGcuo-00000004lpf-2LDp for linux-riscv@lists.infradead.org; Mon, 10 Jun 2024 11:10:21 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1718017819; x=1749553819; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=K/+z8VTLNuGA5cW2ehTsz1bcNhKx95w02wSEQ6xTaY4=; b=iBkLdqHTomGHgxC8gryc0RCDMac4XLJELiATjAm+szfKlCYsNYPAEM4e EeYoQElBlSMQkZTwdHZMCfTv3kp7k6r7g9WsjRa5L5IREVBN/bEQI13CZ HR5+FHK5BD2gijSby8bkYfPkvsc4V61rh7nRZlEDwA3nLGwW3jcc4J6oF LQEqmDilF3T3AyOV7PR8fDg6LqS86f1gA30jOQO6Hpni/8AIY3CiwlnlJ YRNz9lJXd4N2Hpz7fN6uJGTLPZzDYJKxc2nIdawxT9D50nIAsAui2cwpU Rmqxv7ccSY7i1r+3HtFWK0itc3knhzs/l0iruaep/4uMHXdOd7S/TaQjd w==; X-CSE-ConnectionGUID: jk7quZmdTreuz9niASlBPQ== X-CSE-MsgGUID: 2i2zpMRCSdiJS1aM8SSDPQ== X-IronPort-AV: E=Sophos;i="6.08,227,1712646000"; d="scan'208";a="258054503" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jun 2024 04:10:18 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Jun 2024 04:09:37 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Jun 2024 04:09:35 -0700 From: Conor Dooley To: CC: , , Paul Walmsley , Palmer Dabbelt , "Daire McNamara" , Rob Herring , Krzysztof Kozlowski , Samuel Holland , Subject: [PATCH v1 1/5] cache: ccache: allow building for PolarFire Date: Mon, 10 Jun 2024 12:09:13 +0100 Message-ID: <20240610-mocker-ankle-d3ee407bb352@wendy> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240610-vertical-frugally-a92a55427dd9@wendy> References: <20240610-vertical-frugally-a92a55427dd9@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=703; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=K/+z8VTLNuGA5cW2ehTsz1bcNhKx95w02wSEQ6xTaY4=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGlp926q8hUsOnhjSdyy83mz0sxf8Sw4PYtrgcfTiMOrJZhZ 84MmdpSyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAiJ5QY/pf+WGrVf698kUmj+UuX9J NrOv45sep1Fnx9Py9kfdQNy9OMDMcs50jffOG8Umf9zhyhexYrI5LVTvse+pX5IXoZ+ydJBxYA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240610_041018_657188_E3560167 X-CRM114-Status: GOOD ( 10.75 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org There's a ccache on PolarFire SoC, so don't limit it to SIFIVE/STARFIVE SoCs only. Signed-off-by: Conor Dooley Reviewed-by: Emil Renner Berthing --- drivers/cache/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 9345ce4976d76..b2d525e540212 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -10,7 +10,7 @@ config AX45MP_L2_CACHE config SIFIVE_CCACHE bool "Sifive Composable Cache controller" - depends on ARCH_SIFIVE || ARCH_STARFIVE + depends on ARCH_MICROCHIP || ARCH_SIFIVE || ARCH_STARFIVE help Support for the composable cache controller on SiFive platforms. From patchwork Mon Jun 10 11:09:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13691907 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BD6ADC27C65 for ; Mon, 10 Jun 2024 11:10:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=eqjHGtHQQT0Ph4Fl/g4sRZIeRigN58co0yBVSQsLoKM=; b=Lmi5y6E28PAwc2 9oc9CLogyFInvb8wxMQ89QkSuZZvGNoQKN4n76+Fkt/FajxpxdYE9oiEo7ZQrUbOfvzc53t0mZePb 94r+1V8YTk39/6eReDBGAsE4OJuFO3Y3bZD8dmmuokDC512jnqSWj9Trjma0xDwu+VELPkw2RpmB/ EdviwFgNtGkFyH+fW+igIWnt0xd+/x98rYiAp5DD9yuOC2RrebjTNkJKxzS/L2cnorc3yQ878SXvF TTQEfx6uOfxjFoJ/duvuB/yg9k8goUfsjDSfXg4Rbm3R2OP3+a8vdvtohX5nSJGcM4XU9ixYN8AxK oRySBctE7rJYspLwNGmQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sGcuy-00000004lw4-0TqT; Mon, 10 Jun 2024 11:10:28 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sGcuu-00000004ltd-30WH for linux-riscv@lists.infradead.org; Mon, 10 Jun 2024 11:10:26 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1718017825; x=1749553825; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vSvSduSdlE5klA6zgVVnIIfs+4m+OglLLkCW0vt9e5c=; b=rRnkNiolLXw7r/ruLISbvp2bt3gCvrBNMLZJE9dKa6/kwrtSg0Slu7om hm0gLyf+wvfOvGED8iL8CbHHiKM31Wv4y9BR/mEiVtBEvCiytEGSkCITN fS2zw0+D/kbusXOCB4vmRHw71gPMxtpy96yrGkfQb4ayli9sC+bgpgJYX d+gSEQDSgIRnB9LXeOq0+bJdyTAdSru6y/p0K9wOsUOJNEUAVayah7oVT +jF8D9rDAcY/zA/9BAkP7h8xASoc7CXOdR4Ntsc0B6tDd+7Dx/vbmNWuE LjJmRnTlJt4//s5ry2BPgqvkw7Bbuiu3vdQLl+EPomUTl5M7WIPQNK3wr Q==; X-CSE-ConnectionGUID: lNoOtL5sTs6vJxiNFFwsDA== X-CSE-MsgGUID: URZVaOARQKKJLc7sUBGxdw== X-IronPort-AV: E=Sophos;i="6.08,227,1712646000"; d="scan'208";a="27204229" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jun 2024 04:10:25 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Jun 2024 04:09:39 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Jun 2024 04:09:37 -0700 From: Conor Dooley To: CC: , , Paul Walmsley , Palmer Dabbelt , "Daire McNamara" , Rob Herring , Krzysztof Kozlowski , Samuel Holland , Subject: [PATCH v1 2/5] cache: ccache: add mpfs to nonstandard cache ops list Date: Mon, 10 Jun 2024 12:09:14 +0100 Message-ID: <20240610-reenact-amicably-bd088724b3cb@wendy> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240610-vertical-frugally-a92a55427dd9@wendy> References: <20240610-vertical-frugally-a92a55427dd9@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=930; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=vSvSduSdlE5klA6zgVVnIIfs+4m+OglLLkCW0vt9e5c=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGlp925NCr74tNrk8tFqz6wS1b3LN8h+b/LeuuLAlplKp6yr /p061VHKwiDGwSArpsiSeLuvRWr9H5cdzj1vYeawMoEMYeDiFICJvHnC8M9c+5/G/R9v87vTNgic/l ymdGb6Rzc/aR+Wu7ccjl5ln1HOyHB9c3TqfcWr5n/3tYcyKihp9dZt5tEL+aat5XusUk4vlgsA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240610_041024_812320_853E31B3 X-CRM114-Status: GOOD ( 10.47 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On PolarFire SoC, for performance reasons, we want to use non-coherent DMA. Add it to the match table with the non-standard non-coherent cache ops requirement. Signed-off-by: Conor Dooley Reviewed-by: Emil Renner Berthing --- drivers/cache/sifive_ccache.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c index 6874b72ec59d8..277e66a61efdc 100644 --- a/drivers/cache/sifive_ccache.c +++ b/drivers/cache/sifive_ccache.c @@ -122,6 +122,8 @@ static const struct of_device_id sifive_ccache_ids[] = { { .compatible = "sifive,fu740-c000-ccache" }, { .compatible = "starfive,jh7100-ccache", .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS | QUIRK_BROKEN_DATA_UNCORR) }, + { .compatible = "microchip,mpfs-ccache", + .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS) }, { .compatible = "sifive,ccache0" }, { /* end of table */ } }; From patchwork Mon Jun 10 11:09:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13691908 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65A49C27C65 for ; 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d="scan'208";a="194602823" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jun 2024 04:10:25 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Jun 2024 04:09:41 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Jun 2024 04:09:39 -0700 From: Conor Dooley To: CC: , , Paul Walmsley , Palmer Dabbelt , "Daire McNamara" , Rob Herring , Krzysztof Kozlowski , Samuel Holland , Subject: [PATCH v1 3/5] RISC-V: Add an MPFS erratum for PCIe Date: Mon, 10 Jun 2024 12:09:15 +0100 Message-ID: <20240610-crux-unloaded-93b701646454@wendy> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240610-vertical-frugally-a92a55427dd9@wendy> References: <20240610-vertical-frugally-a92a55427dd9@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3432; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=RnUro+xV+qZjTj4M3EgsjQkilJTe+OeOdfJTP/zcJ8s=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGlp924tK2hYLtn78kiE5nIpTf/aM3Xbtu+fbDRd4GNP3Daj v4r/OkpZGMQ4GGTFFFkSb/e1SK3/47LDuectzBxWJpAhDFycAjCRRzkMfzgyjgYXnT0Qde7vhH8uum mG72e75ZR1zlV92lsl+lQ+/gwjw60vb9vOl68q8vA8emSZyuS7luz3pwvWMG9qnWf8/hZ/EwcA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240610_041026_712156_46DF1AF2 X-CRM114-Status: GOOD ( 16.95 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On PolarFire SoC the PCIe root port is limited to 32-bit addressing (both when acting as an AXI-Slave and as an AXI-Master) due to how it is connected to the processor core complex via a Fabric Interface Controller (FIC), rather than being part of the Microprocessor Subsystem (MSS) like the other hard peripherals. The AXI buses between the FIC and the MSS are true 64-bit buses, but the PCIe root port is (effectively) only attached to the lower 32-bits of each bus. As PolarFire SoC is an FPGA, several of Microchip's customers that did not want to suffer the penalty of bounce buffering inserted a "shim" in the FPGA fabric that would alter the address of the AXI-S transaction on the return path to the MSS (conceptually moving the 4GiB range that the root port can address via the AXI-S interface around 64-bit space to better cover where those customers had placed their DDR). PolarFire SoC has a memory map with various apertures into the physical DDR, and depending on the MSS' configuration, the FPGA design can control what physical memory addresses back each aperture. The main apertures, which are cached memory, lie at 0x10_0000_0000 and 0x8000_0000. There are also non-cached apertures at 0xC000_0000 and 0x14_0000_0000. The "default" configuration is to have each of apertures overlap. Some use-cases add a shim to the FPGA fabric that will re-route transactions from the 0x10_0000_0000 region to avoid bounce buffering for 64-bit addresses or because the aperture at 0x8000_0000 does not correspond to usable memory (perhaps an AMP context is using it or the designer chose not to place memory at the aperture's physical address). Other user-cases re-route them to the non-cached region at 0x14_0000_0000. If the latter is done, DMA for the PCIe root ports become non-coherent. Such a scheme is only possible because the SiFive ccache on PolarFire SoC can perform flush invalidation of the L1/L2 cache for these types of configuration. Add an Erratum to support this second type of configuration. Like the JH7100's non-coherent DMA option, this requires use of DMA_GLOBAL_POOL and is therefore incompatible with Zicbom. Signed-off-by: Conor Dooley Reviewed-by: Emil Renner Berthing --- arch/riscv/Kconfig.errata | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 2acc7d876e1fb..0a9e13efbe6b5 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -21,6 +21,25 @@ config ERRATA_ANDES_CMO If you don't know what to do here, say "Y". +config ERRATA_MICROCHIP + bool "Microchip errata" + depends on ARCH_MICROCHIP + help + All Microchip errata Kconfig options depend on this option. Disabling + this option will disable all Microchip errata. + +config ERRATA_POLARFIRE_SOC_DMA_NON_COHERENT + bool "Non-coherent DMA support for PolarFire SoC" + depends on NONPORTABLE + depends on ERRATA_MICROCHIP + select DMA_GLOBAL_POOL + select RISCV_NONSTANDARD_CACHE_OPS + help + Enable support for non-coherent DMA on PolarFire SoC. + This support is not required for any peripherals in the MSS, but may + be required for peripherals in the FPGA fabric and is required for + the PCI root port to operate correctly, due to addressing limitations. + config ERRATA_SIFIVE bool "SiFive errata" depends on RISCV_ALTERNATIVE From patchwork Mon Jun 10 11:09:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13691903 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 03A59C27C5E for ; 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d="scan'208";a="29623984" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jun 2024 04:10:07 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Jun 2024 04:09:43 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Jun 2024 04:09:41 -0700 From: Conor Dooley To: CC: , , Paul Walmsley , Palmer Dabbelt , "Daire McNamara" , Rob Herring , Krzysztof Kozlowski , Samuel Holland , Subject: [PATCH v1 4/5] riscv: dts: microchip: modify memory map & add dma-ranges for pcie on icicle Date: Mon, 10 Jun 2024 12:09:16 +0100 Message-ID: <20240610-unhealthy-squeamish-db1039449a32@wendy> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240610-vertical-frugally-a92a55427dd9@wendy> References: <20240610-vertical-frugally-a92a55427dd9@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6818; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=KLTX+FrN+/X5Pjo7hasr1G+U/5MVxG90GAbohrK1Lcw=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGlp925Pi7651timSFPqf4/U7bYL+3zZkuuYzhz9s2Xmussh m2aldJSyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAiZ9gY/nD/CV8a3LqWJTvgkcvL+n 0XnbySzC9crFMQ1HZ9d67t621Ghnm++wRuuEwS/djpdvFaXa3/nDvSukX2kt5Nf2cHzvppwAsA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240610_041014_792836_716B8D79 X-CRM114-Status: GOOD ( 13.79 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Since 2022/02, the main reference design for the Icicle Kit uses a non-coherent memory configuration for PCIe, and a shim in the FPGA fabric, in response to customer requests. As a result, the PCIe root port has not been usable in mainline since that point in time. The memory apertures on the reference design have been configured so that the base of each aperture is mapped to 0x0 in physical memory, a completely "overlaid" approach. This enables the PCIe root port to operate in a non-coherent manner (the CPUs/harts use the cached variant of a particular actual DDR address, the PCIe root port uses the non-cached variant of the same address. As an example, to access DDR location 0, the FIC, to which the PCIe rootport is attached, would use 14'0000'0000 and the CPUs would use 10'0000'0000. In this example, the FIC is responsible for the upper 32-bits of the AXI address and the root-port (as it is limited to 32-bits on the AXI-S interface) is responsible for the lower 32-bits of the AXI address. The FPGA designs utilizing this approach use a simple "shim" to statically set the upper 32-bits of all AXI-S addresses to '000'0014'. Describe some regions of non-cached memory (and immediately reserve them, as PolarFire SoC does not support atomics in non-cached memory) so that we can configure dma-ranges and dma-pools to support a "shim" that will shift addresses in AXI transactions from the PCIe root port into the 0x14_0000_0000 non-cached region of memory. The price paid for this is a reduction in the overall system memory. Signed-off-by: Conor Dooley --- .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 75 ++++++++++++------- .../boot/dts/microchip/mpfs-icicle-kit.dts | 44 +++++++++-- 2 files changed, 84 insertions(+), 35 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 1069134f2e12a..33e76db965bbc 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -26,33 +26,54 @@ i2c2: i2c@40000200 { status = "disabled"; }; - pcie: pcie@3000000000 { - compatible = "microchip,pcie-host-1.0"; - #address-cells = <0x3>; - #interrupt-cells = <0x1>; - #size-cells = <0x2>; - device_type = "pci"; - reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; - bus-range = <0x0 0x7f>; - interrupt-parent = <&plic>; - interrupts = <119>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - interrupt-map-mask = <0 0 0 7>; - clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>; - clock-names = "fic1", "fic3"; - ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>; - dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; - msi-parent = <&pcie>; - msi-controller; - status = "disabled"; - pcie_intc: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; + fabric-pcie-bus@3000000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, + <0x30 0x0 0x30 0x0 0x10 0x0>; + dma-ranges = <0x0 0x0 0x0 0x80000000 0x0 0x6000000>, + <0x0 0x6000000 0x0 0xc6000000 0x0 0x4000000>, + <0x0 0xa000000 0x0 0x8a000000 0x0 0x8000000>, + <0x0 0x12000000 0x14 0x12000000 0x0 0x10000000>, + <0x0 0x22000000 0x10 0x22000000 0x0 0x5e000000>; + + pcie: pcie@3000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + dma-noncoherent; + reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = <119>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>; + clock-names = "fic1", "fic3"; + ranges = <0x43000000 0x0 0x9000000 0x30 0x9000000 0x0 0xf000000>, + <0x1000000 0x0 0x8000000 0x30 0x8000000 0x0 0x1000000>, + <0x3000000 0x0 0x18000000 0x30 0x18000000 0x0 0x70000000>; + dma-ranges = <0x3000000 0x0 0x80000000 0x0 0x0 0x0 0x6000000>, + <0x3000000 0x0 0x86000000 0x0 0x6000000 0x0 0x4000000>, + <0x3000000 0x0 0x8a000000 0x0 0xa000000 0x0 0x8000000>, + <0x3000000 0x0 0x92000000 0x0 0x12000000 0x0 0x10000000>, + <0x3000000 0x0 0xa2000000 0x0 0x22000000 0x0 0x5e000000>; + msi-parent = <&pcie>; + msi-controller; + status = "disabled"; + + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; }; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index f80df225f72b4..6c9340992e9eb 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -54,16 +54,29 @@ led-4 { }; }; - ddrc_cache_lo: memory@80000000 { + memory@80000000 { device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; - status = "okay"; + reg = <0x0 0x80000000 0x0 0x6000000>; }; - ddrc_cache_hi: memory@1040000000 { + memory@8a000000 { device_type = "memory"; - reg = <0x10 0x40000000 0x0 0x40000000>; - status = "okay"; + reg = <0x0 0x8a000000 0x0 0x8000000>; + }; + + memory@c4000000 { + device_type = "memory"; + reg = <0x0 0xc6000000 0x0 0x4000000>; + }; + + memory@1022000000 { + device_type = "memory"; + reg = <0x10 0x22000000 0x0 0x5e000000>; + }; + + memory@1412000000 { + device_type = "memory"; + reg = <0x14 0x12000000 0x0 0x10000000>; }; reserved-memory { @@ -71,10 +84,25 @@ reserved-memory { #size-cells = <2>; ranges; - hss_payload: region@BFC00000 { - reg = <0x0 0xBFC00000 0x0 0x400000>; + hss_payload: region@103fc00000 { + reg = <0x10 0x3fc00000 0x0 0x400000>; no-map; }; + + non-cached-low-buffer { + compatible = "shared-dma-pool"; + size = <0x0 0x4000000>; + no-map; + alloc-ranges = <0x0 0xc6000000 0x0 0x4000000>; + }; + + non-cached-high-buffer { + compatible = "shared-dma-pool"; + size = <0x0 0x10000000>; + no-map; + linux,dma-default; + alloc-ranges = <0x14 0x12000000 0x0 0x10000000>; + }; }; }; From patchwork Mon Jun 10 11:09:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13691906 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D087C27C5E for ; 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d="scan'208";a="194602814" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Jun 2024 04:10:16 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Jun 2024 04:09:45 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Jun 2024 04:09:44 -0700 From: Conor Dooley To: CC: , , Paul Walmsley , Palmer Dabbelt , "Daire McNamara" , Rob Herring , Krzysztof Kozlowski , Samuel Holland , Subject: [PATCH v1 5/5] riscv: dts: microchip: update pcie reg properties Date: Mon, 10 Jun 2024 12:09:17 +0100 Message-ID: <20240610-panda-revenue-7248a5403dfc@wendy> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240610-vertical-frugally-a92a55427dd9@wendy> References: <20240610-vertical-frugally-a92a55427dd9@wendy> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3109; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=fpCXcSYLvaUiPvd8q8SOwFC8Rj+IsgRpPjmmEKBXl+s=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGlp925bebxoODiN4/DmTXsbS+7b2H7I3rRqP9PE2Ty7VTcG P3GP7ihlYRDjYJAVU2RJvN3XIrX+j8sO5563MHNYmUCGMHBxCsBEqroY/qneU5um2Flwxqld1MLu2L zvhw9YLf/vI7nF4PH10He9kzcwMnRonJw6x+B+W33ytJkmXAuklZdNvlzUxD+x8b7L12zBtewA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240610_041023_200239_2C7267BB X-CRM114-Status: GOOD ( 10.68 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Split the "apb" regions of memory on PolarFire SoC devicetrees PCIe nodes into two regions, so that it will be possible to distinguish between which root port instance is in use. Currently the "apb" region points to the base of the root port region and the Linux driver uses hard-coded offsets to find the "control" and "bridge" regions. The new method for describing these regions explicitly passes the base address for the two regions of interest. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 6 ++++-- arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi | 6 ++++-- arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi | 6 ++++-- 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 33e76db965bbc..f151aa2606d7b 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -45,8 +45,10 @@ pcie: pcie@3000000000 { #size-cells = <0x2>; device_type = "pci"; dma-noncoherent; - reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; + reg = <0x30 0x0 0x0 0x8000000>, + <0x0 0x43008000 0x0 0x00002000>, + <0x0 0x4300a000 0x0 0x00002000>; + reg-names = "cfg", "bridge", "ctrl"; bus-range = <0x0 0x7f>; interrupt-parent = <&plic>; interrupts = <119>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi index 8230f06ddf48a..f5036126f2654 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi @@ -20,8 +20,10 @@ pcie: pcie@2000000000 { #interrupt-cells = <0x1>; #size-cells = <0x2>; device_type = "pci"; - reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; + reg = <0x30 0x0 0x0 0x8000000>, + <0x0 0x43008000 0x0 0x00002000>, + <0x0 0x4300a000 0x0 0x00002000>; + reg-names = "cfg", "bridge", "ctrl"; bus-range = <0x0 0x7f>; interrupt-parent = <&plic>; interrupts = <119>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi index 9a56de7b91d64..121b13f9c8bf4 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi @@ -20,8 +20,10 @@ pcie: pcie@2000000000 { #interrupt-cells = <0x1>; #size-cells = <0x2>; device_type = "pci"; - reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; + reg = <0x30 0x0 0x0 0x8000000>, + <0x0 0x43008000 0x0 0x00002000>, + <0x0 0x4300a000 0x0 0x00002000>; + reg-names = "cfg", "bridge", "ctrl"; bus-range = <0x0 0x7f>; interrupt-parent = <&plic>; interrupts = <119>;