From patchwork Tue Jun 11 13:33:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13693782 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DD6CBC25B76 for ; Tue, 11 Jun 2024 13:33:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3801110E0AA; Tue, 11 Jun 2024 13:33:53 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="U+uk/wdL"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id DA11889101 for ; Tue, 11 Jun 2024 13:33:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718112830; x=1749648830; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=hlwo8U10BrYu9e+MomKRzuaMh0C/RCBHcDE8WZ+xqDc=; b=U+uk/wdL8V9KFk/zDZoWACsXYwHYxKB6BfJXK0m7p9JXLq7d+tvKNZLy 4MgwOyI3xR1m5MRJKhq6WlY5OYt2Ab0AX9ZSg0q4RDdB8NHFv2Oehyq+Z lCNfNtHQ+jC54ulmwHZGSq4dCCGXhkbSwUpEzksr2vpaoB8weyOI3usMK K/cyiOfEAGM0qhYWuULM7+G++kgojG2jl2GyeX+Ceq/Szj6fhLEdwGZG3 6jcY2kO8XpfidseG7sO/33Gh+fu8k8jJ9C6l2xYrBXpTTPUeq3K9QMfLS SFg36OhjAi3wE419328YFBGPmrWeu8SxVroawxO88OtAsyfyUA0IhFFcb A==; X-CSE-ConnectionGUID: qJmVywKtRoOIO5JaNwF4Pw== X-CSE-MsgGUID: 0iM9mGXpT+Wik26WQJ6Gpg== X-IronPort-AV: E=McAfee;i="6600,9927,11099"; a="12018232" X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="12018232" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2024 06:33:50 -0700 X-CSE-ConnectionGUID: Sa+ElnW7QsGEmwoidLZY8g== X-CSE-MsgGUID: T9CpH6waSNqAcs6nZh2FNg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="39421352" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 11 Jun 2024 06:33:48 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 11 Jun 2024 16:33:47 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 01/11] drm/i915: Extract intel_crtc_arm_vblank_event() Date: Tue, 11 Jun 2024 16:33:34 +0300 Message-ID: <20240611133344.30673-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240611133344.30673-1-ville.syrjala@linux.intel.com> References: <20240611133344.30673-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We'll need to arm the vblank event also from the future DSB based codepath. Extract the function that does the whold dance for us. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_crtc.c | 29 +++++++++++++++-------- drivers/gpu/drm/i915/display/intel_crtc.h | 1 + 2 files changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 54b529bfc935..6831060a792a 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -560,6 +560,23 @@ static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) {} #endif +void intel_crtc_arm_vblank_event(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + unsigned long irqflags; + + if (!crtc_state->uapi.event) + return; + + drm_WARN_ON(crtc->base.dev, drm_crtc_vblank_get(&crtc->base) != 0); + + spin_lock_irqsave(&crtc->base.dev->event_lock, irqflags); + drm_crtc_arm_vblank_event(&crtc->base, crtc_state->uapi.event); + spin_unlock_irqrestore(&crtc->base.dev->event_lock, irqflags); + + crtc_state->uapi.event = NULL; +} + /** * intel_pipe_update_end() - end update of a set of display registers * @state: the atomic state @@ -601,16 +618,8 @@ void intel_pipe_update_end(struct intel_atomic_state *state, drm_vblank_work_schedule(&new_crtc_state->vblank_work, drm_crtc_accurate_vblank_count(&crtc->base) + 1, false); - } else if (new_crtc_state->uapi.event) { - drm_WARN_ON(&dev_priv->drm, - drm_crtc_vblank_get(&crtc->base) != 0); - - spin_lock(&crtc->base.dev->event_lock); - drm_crtc_arm_vblank_event(&crtc->base, - new_crtc_state->uapi.event); - spin_unlock(&crtc->base.dev->event_lock); - - new_crtc_state->uapi.event = NULL; + } else { + intel_crtc_arm_vblank_event(new_crtc_state); } /* diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h b/drivers/gpu/drm/i915/display/intel_crtc.h index 22d7993d1f0b..b615b7ab5ccd 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.h +++ b/drivers/gpu/drm/i915/display/intel_crtc.h @@ -28,6 +28,7 @@ struct intel_crtc_state; int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, int usecs); +void intel_crtc_arm_vblank_event(struct intel_crtc_state *crtc_state); u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state); int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe); struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc); From patchwork Tue Jun 11 13:33:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13693783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC9DCC25B76 for ; Tue, 11 Jun 2024 13:33:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 89E2F10E641; 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X-CSE-ConnectionGUID: onuvKL1EQAGGqlKmZCqVwQ== X-CSE-MsgGUID: G4GHy/TBQNGH6LCaZBuFcA== X-IronPort-AV: E=McAfee;i="6600,9927,11099"; a="12018234" X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="12018234" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2024 06:33:52 -0700 X-CSE-ConnectionGUID: kZOViAN1STeDz3s2L9Xgvg== X-CSE-MsgGUID: jZGO5av8T0KNpBYIO+FJFA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="39421365" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 11 Jun 2024 06:33:50 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 11 Jun 2024 16:33:50 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 02/11] drm/i915: Add async flip tracepoint Date: Tue, 11 Jun 2024 16:33:35 +0300 Message-ID: <20240611133344.30673-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240611133344.30673-1-ville.syrjala@linux.intel.com> References: <20240611133344.30673-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Add a separate tracepoint for async flips vs. sync plane updates to make it a bit easier to figure out what is happening. Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_atomic_plane.c | 22 +++++++++++---- .../gpu/drm/i915/display/intel_atomic_plane.h | 4 +++ drivers/gpu/drm/i915/display/intel_display.c | 4 +-- .../drm/i915/display/intel_display_trace.h | 27 +++++++++++++++++++ 4 files changed, 50 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 980c5dc70763..75b66998ddb2 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -801,18 +801,30 @@ void intel_plane_update_noarm(struct intel_plane *plane, plane->update_noarm(plane, crtc_state, plane_state); } +void intel_plane_async_flip(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state, + bool async_flip) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + trace_intel_plane_async_flip(plane, crtc, async_flip); + plane->async_flip(plane, crtc_state, plane_state, async_flip); +} + void intel_plane_update_arm(struct intel_plane *plane, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + if (crtc_state->do_async_flip && plane->async_flip) { + intel_plane_async_flip(plane, crtc_state, plane_state, true); + return; + } + trace_intel_plane_update_arm(plane, crtc); - - if (crtc_state->do_async_flip && plane->async_flip) - plane->async_flip(plane, crtc_state, plane_state, true); - else - plane->update_arm(plane, crtc_state, plane_state); + plane->update_arm(plane, crtc_state, plane_state); } void intel_plane_disable_arm(struct intel_plane *plane, diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h index e7a0699f17c8..84541d97c67b 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h @@ -32,6 +32,10 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state, struct intel_crtc *crtc); void intel_plane_copy_hw_state(struct intel_plane_state *plane_state, const struct intel_plane_state *from_plane_state); +void intel_plane_async_flip(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state, + bool async_flip); void intel_plane_update_noarm(struct intel_plane *plane, const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 5e0aa5a0b10c..0d1fbd05d655 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1160,8 +1160,8 @@ static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, * Apart from the async flip bit we want to * preserve the old state for the plane. */ - plane->async_flip(plane, old_crtc_state, - old_plane_state, false); + intel_plane_async_flip(plane, old_crtc_state, + old_plane_state, false); need_vbl_wait = true; } } diff --git a/drivers/gpu/drm/i915/display/intel_display_trace.h b/drivers/gpu/drm/i915/display/intel_display_trace.h index 49a5e6d9dc0d..34c223ace5ea 100644 --- a/drivers/gpu/drm/i915/display/intel_display_trace.h +++ b/drivers/gpu/drm/i915/display/intel_display_trace.h @@ -308,6 +308,33 @@ TRACE_EVENT(vlv_fifo_size, __entry->sprite0_start, __entry->sprite1_start, __entry->fifo_size) ); +TRACE_EVENT(intel_plane_async_flip, + TP_PROTO(struct intel_plane *plane, struct intel_crtc *crtc, bool async_flip), + TP_ARGS(plane, crtc, async_flip), + + TP_STRUCT__entry( + __string(dev, __dev_name_kms(plane)) + __field(enum pipe, pipe) + __field(u32, frame) + __field(u32, scanline) + __field(bool, async_flip) + __string(name, plane->base.name) + ), + + TP_fast_assign( + __assign_str(dev); + __assign_str(name); + __entry->pipe = crtc->pipe; + __entry->frame = intel_crtc_get_vblank_counter(crtc); + __entry->scanline = intel_get_crtc_scanline(crtc); + __entry->async_flip = async_flip; + ), + + TP_printk("dev %s, pipe %c, plane %s, frame=%u, scanline=%u, async_flip=%s", + __get_str(dev), pipe_name(__entry->pipe), __get_str(name), + __entry->frame, __entry->scanline, str_yes_no(__entry->async_flip)) +); + TRACE_EVENT(intel_plane_update_noarm, TP_PROTO(struct intel_plane *plane, struct intel_crtc *crtc), TP_ARGS(plane, crtc), From patchwork Tue Jun 11 13:33:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13693784 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9A8DEC25B76 for ; Tue, 11 Jun 2024 13:33:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F3C4110E636; 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X-CSE-ConnectionGUID: EjQ1CYMhTmypBf2VXKmMMg== X-CSE-MsgGUID: Z2+3/JThR4q7Ww1oqEZtDg== X-IronPort-AV: E=McAfee;i="6600,9927,11099"; a="12018235" X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="12018235" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2024 06:33:55 -0700 X-CSE-ConnectionGUID: H8WAZLvDRTO8ukVad3wW4w== X-CSE-MsgGUID: q9lDGWZBS4uM9ktQY5hlaQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="39421375" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 11 Jun 2024 06:33:53 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 11 Jun 2024 16:33:52 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 03/11] drm/i915: Add flip done tracepoint Date: Tue, 11 Jun 2024 16:33:36 +0300 Message-ID: <20240611133344.30673-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240611133344.30673-1-ville.syrjala@linux.intel.com> References: <20240611133344.30673-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Add a tracepoint to see exactly when async flips complete. Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_display_irq.c | 1 + .../drm/i915/display/intel_display_trace.h | 23 +++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 82e1369e5d76..cf886b9edeb8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -346,6 +346,7 @@ static void flip_done_handler(struct drm_i915_private *i915, spin_lock(&i915->drm.event_lock); if (crtc->flip_done_event) { + trace_intel_crtc_flip_done(crtc); drm_crtc_send_vblank_event(&crtc->base, crtc->flip_done_event); crtc->flip_done_event = NULL; } diff --git a/drivers/gpu/drm/i915/display/intel_display_trace.h b/drivers/gpu/drm/i915/display/intel_display_trace.h index 34c223ace5ea..c734ef1fba3c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_trace.h +++ b/drivers/gpu/drm/i915/display/intel_display_trace.h @@ -78,6 +78,29 @@ TRACE_EVENT(intel_pipe_disable, __entry->frame[PIPE_C], __entry->scanline[PIPE_C]) ); +TRACE_EVENT(intel_crtc_flip_done, + TP_PROTO(struct intel_crtc *crtc), + TP_ARGS(crtc), + + TP_STRUCT__entry( + __string(dev, __dev_name_kms(crtc)) + __field(enum pipe, pipe) + __field(u32, frame) + __field(u32, scanline) + ), + + TP_fast_assign( + __assign_str(dev); + __entry->pipe = crtc->pipe; + __entry->frame = intel_crtc_get_vblank_counter(crtc); + __entry->scanline = intel_get_crtc_scanline(crtc); + ), + + TP_printk("dev %s, pipe %c, frame=%u, scanline=%u", + __get_str(dev), pipe_name(__entry->pipe), + __entry->frame, __entry->scanline) +); + TRACE_EVENT(intel_pipe_crc, TP_PROTO(struct intel_crtc *crtc, const u32 *crcs), TP_ARGS(crtc, crcs), From patchwork Tue Jun 11 13:33:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13693785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9EC54C27C5E for ; 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X-CSE-ConnectionGUID: YFlLXD5NTRiQXAOFJWdW8Q== X-CSE-MsgGUID: E1LPztFkQnGj2NZhIRTt0w== X-IronPort-AV: E=McAfee;i="6600,9927,11099"; a="12018237" X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="12018237" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2024 06:33:58 -0700 X-CSE-ConnectionGUID: WtT8YpZAT4amEkwZYHMKfA== X-CSE-MsgGUID: uqoQq5EDTdmC4h++bBiZRg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="39421386" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 11 Jun 2024 06:33:56 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 11 Jun 2024 16:33:55 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 04/11] drm/i915: Introduce intel_mode_vdisplay() Date: Tue, 11 Jun 2024 16:33:37 +0300 Message-ID: <20240611133344.30673-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240611133344.30673-1-ville.syrjala@linux.intel.com> References: <20240611133344.30673-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The DSB code will need to know the hardware's idea of vertical active, as that is also what defines the start of undelayed vblank. Introduce a helper that gives us that information, in line with the other intel_mode_v*() functions. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vblank.c | 10 ++++++++++ drivers/gpu/drm/i915/display/intel_vblank.h | 1 + 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index e5db54b1c632..5b065e1cd4e4 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -557,6 +557,16 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state, spin_unlock_irqrestore(&i915->drm.vblank_time_lock, irqflags); } +int intel_mode_vdisplay(const struct drm_display_mode *mode) +{ + int vdisplay = mode->crtc_vdisplay; + + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + vdisplay = DIV_ROUND_UP(vdisplay, 2); + + return vdisplay; +} + int intel_mode_vblank_start(const struct drm_display_mode *mode) { int vblank_start = mode->crtc_vblank_start; diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h index b51ae2c1039e..7e526f6861e4 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.h +++ b/drivers/gpu/drm/i915/display/intel_vblank.h @@ -20,6 +20,7 @@ struct intel_vblank_evade_ctx { bool need_vlv_dsi_wa; }; +int intel_mode_vdisplay(const struct drm_display_mode *mode); int intel_mode_vblank_start(const struct drm_display_mode *mode); int intel_mode_vblank_end(const struct drm_display_mode *mode); int intel_mode_vtotal(const struct drm_display_mode *mode); From patchwork Tue Jun 11 13:33:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13693786 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CDAFC25B76 for ; Tue, 11 Jun 2024 13:34:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9108410E648; Tue, 11 Jun 2024 13:34:03 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="F8d7h2j3"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id C49FC10E644 for ; Tue, 11 Jun 2024 13:34:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718112841; x=1749648841; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=CHw667NUCrAdOkph5zDSvKEBfhCGIeXVTUJenP62zBc=; b=F8d7h2j3Z2DL+vsqyJsM2vP3/1w7uUV/0w/X940V5l5iRbk6s6hYW4aI PsDbaEHwbRT9DrJNmHCemdLoTaueelO9oR++Mp+XcAnyGETpHczzqwBlf ve8zS/YkAbKGuSgGtIwL50lUGd3nl/hPN9GqDf2QgO1GgBszx/3tXAiOZ djV5XNVc5NXN7I9nbd54Ypde8VyrgWHYlQqM2mRC5D8qEKpEpadcRIE+P v65Uhb8Dq06WK1foWD/ls9pDoSEOvhYEBQCHTtpPNQu/2+Z3fnNH9U1sf BwLg7N4QUiyiE08MPJdoRXJBc38J9W1DRwHyeqWAou/0Fethji9II4O1z g==; X-CSE-ConnectionGUID: YML4wmpsS/2MIpdI/VrTHw== X-CSE-MsgGUID: O/uc88ZpSmyXBC78YTRm3g== X-IronPort-AV: E=McAfee;i="6600,9927,11099"; a="12018238" X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="12018238" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2024 06:34:00 -0700 X-CSE-ConnectionGUID: 8UF5k/wETvePVEBsRqBUwg== X-CSE-MsgGUID: A4MnJfrnSyijsDpsBP99vQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="39421391" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 11 Jun 2024 06:33:59 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 11 Jun 2024 16:33:58 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 05/11] drm/i915: Pass the whole atomic state to intel_color_prepare_commit() Date: Tue, 11 Jun 2024 16:33:38 +0300 Message-ID: <20240611133344.30673-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240611133344.30673-1-ville.syrjala@linux.intel.com> References: <20240611133344.30673-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We'll have need to examine both the old and new crtc states in intel_color_prepare_commit(), so let's just pass in the whole atomic state. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 11 ++++++++--- drivers/gpu/drm/i915/display/intel_color.h | 3 ++- drivers/gpu/drm/i915/display/intel_display.c | 8 +++----- 3 files changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 98553e8a5149..8cfd497c2a92 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1902,15 +1902,20 @@ void intel_color_post_update(const struct intel_crtc_state *crtc_state) i915->display.funcs.color->color_post_update(crtc_state); } -void intel_color_prepare_commit(struct intel_crtc_state *crtc_state) +void intel_color_prepare_commit(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state)) return; + if (!intel_crtc_needs_color_update(crtc_state)) + return; + if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut) return; diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h index 21ba4aa02e7b..79f230a1709a 100644 --- a/drivers/gpu/drm/i915/display/intel_color.h +++ b/drivers/gpu/drm/i915/display/intel_color.h @@ -19,7 +19,8 @@ int intel_color_init(struct drm_i915_private *i915); void intel_color_crtc_init(struct intel_crtc *crtc); int intel_color_check(struct intel_atomic_state *state, struct intel_crtc *crtc); -void intel_color_prepare_commit(struct intel_crtc_state *crtc_state); +void intel_color_prepare_commit(struct intel_atomic_state *state, + struct intel_crtc *crtc); void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state); bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state); void intel_color_wait_commit(const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0d1fbd05d655..0623cb5f4e26 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6684,7 +6684,7 @@ int intel_atomic_check(struct drm_device *dev, static int intel_atomic_prepare_commit(struct intel_atomic_state *state) { - struct intel_crtc_state *crtc_state; + struct intel_crtc_state __maybe_unused *crtc_state; struct intel_crtc *crtc; int i, ret; @@ -6692,10 +6692,8 @@ static int intel_atomic_prepare_commit(struct intel_atomic_state *state) if (ret < 0) return ret; - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { - if (intel_crtc_needs_color_update(crtc_state)) - intel_color_prepare_commit(crtc_state); - } + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) + intel_color_prepare_commit(state, crtc); return 0; } From patchwork Tue Jun 11 13:33:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13693787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22527C27C5E for ; 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X-CSE-ConnectionGUID: jpPM6A5xQXe7/mP0FD2CfA== X-CSE-MsgGUID: qPbPik/4Q6G75Lf5q0K78Q== X-IronPort-AV: E=McAfee;i="6600,9927,11099"; a="12018239" X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="12018239" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2024 06:34:03 -0700 X-CSE-ConnectionGUID: rZ/KEXbaQcOjPIexUBg2+w== X-CSE-MsgGUID: 3Gf+6Un9SuGoXyYZKEXdIg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="39421413" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 11 Jun 2024 06:34:01 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 11 Jun 2024 16:34:00 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 06/11] drm/i915/dsb: Plumb the whole atomic state into intel_dsb_prepare() Date: Tue, 11 Jun 2024 16:33:39 +0300 Message-ID: <20240611133344.30673-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240611133344.30673-1-ville.syrjala@linux.intel.com> References: <20240611133344.30673-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The DSB code will need to examine both the old and new crtc states. Pass in the whole atomic state so we can dig up what we need. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 2 +- drivers/gpu/drm/i915/display/intel_dsb.c | 11 +++++++---- drivers/gpu/drm/i915/display/intel_dsb.h | 4 +++- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 8cfd497c2a92..7ac50aacec73 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1919,7 +1919,7 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut) return; - crtc_state->dsb = intel_dsb_prepare(crtc_state, INTEL_DSB_0, 1024); + crtc_state->dsb = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 1024); if (!crtc_state->dsb) return; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 5180b9722046..8ae7bcfa8403 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -434,7 +434,8 @@ void intel_dsb_wait(struct intel_dsb *dsb) /** * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer. - * @crtc_state: the CRTC state + * @state: the atomic state + * @crtc: the CRTC * @dsb_id: the DSB engine to use * @max_cmds: number of commands we need to fit into command buffer * @@ -444,12 +445,14 @@ void intel_dsb_wait(struct intel_dsb *dsb) * Returns: * DSB context, NULL on failure */ -struct intel_dsb *intel_dsb_prepare(const struct intel_crtc_state *crtc_state, +struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, + struct intel_crtc *crtc, enum intel_dsb_id dsb_id, unsigned int max_cmds) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); intel_wakeref_t wakeref; struct intel_dsb *dsb; unsigned int size; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index 36fdb130af6e..bb42749f2ea4 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -10,6 +10,7 @@ #include "i915_reg_defs.h" +struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; struct intel_dsb; @@ -22,7 +23,8 @@ enum intel_dsb_id { I915_MAX_DSBS, }; -struct intel_dsb *intel_dsb_prepare(const struct intel_crtc_state *crtc_state, +struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, + struct intel_crtc *crtc, enum intel_dsb_id dsb_id, unsigned int max_cmds); void intel_dsb_finish(struct intel_dsb *dsb); From patchwork Tue Jun 11 13:33:40 2024 Content-Type: text/plain; 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11 Jun 2024 06:34:06 -0700 X-CSE-ConnectionGUID: byJ3+KSkRGeU3JOqVfw/hA== X-CSE-MsgGUID: mDBce+tbRu+1Xe6197kZZA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="39421426" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 11 Jun 2024 06:34:04 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 11 Jun 2024 16:34:03 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 07/11] drm/i915/dsb: Convert the DSB code to use intel_display rather than i915 Date: Tue, 11 Jun 2024 16:33:40 +0300 Message-ID: <20240611133344.30673-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240611133344.30673-1-ville.syrjala@linux.intel.com> References: <20240611133344.30673-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The future direction will be to mainly use intel_display rather than i915 in the display code. Start on that path for the DSB code. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb.c | 52 ++++++++++++------------ 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 8ae7bcfa8403..bee48ac419ce 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -85,10 +85,10 @@ struct intel_dsb { static bool assert_dsb_has_room(struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc->base.dev); /* each instruction is 2 dwords */ - return !drm_WARN(&i915->drm, dsb->free_pos > dsb->size - 2, + return !drm_WARN(display->drm, dsb->free_pos > dsb->size - 2, "[CRTC:%d:%s] DSB %d buffer overflow\n", crtc->base.base.id, crtc->base.name, dsb->id); } @@ -96,25 +96,25 @@ static bool assert_dsb_has_room(struct intel_dsb *dsb) static void intel_dsb_dump(struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc->base.dev); int i; - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] DSB %d commands {\n", + drm_dbg_kms(display->drm, "[CRTC:%d:%s] DSB %d commands {\n", crtc->base.base.id, crtc->base.name, dsb->id); for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4) - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", i * 4, intel_dsb_buffer_read(&dsb->dsb_buf, i), intel_dsb_buffer_read(&dsb->dsb_buf, i + 1), intel_dsb_buffer_read(&dsb->dsb_buf, i + 2), intel_dsb_buffer_read(&dsb->dsb_buf, i + 3)); - drm_dbg_kms(&i915->drm, "}\n"); + drm_dbg_kms(display->drm, "}\n"); } -static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe, +static bool is_dsb_busy(struct intel_display *display, enum pipe pipe, enum intel_dsb_id dsb_id) { - return intel_de_read_fw(i915, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY; + return intel_de_read_fw(display, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY; } static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw) @@ -343,27 +343,27 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, int dewake_scanline) { struct intel_crtc *crtc = dsb->crtc; - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc->base.dev); enum pipe pipe = crtc->pipe; u32 tail; tail = dsb->free_pos * 4; - if (drm_WARN_ON(&dev_priv->drm, !IS_ALIGNED(tail, CACHELINE_BYTES))) + if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES))) return; - if (is_dsb_busy(dev_priv, pipe, dsb->id)) { - drm_err(&dev_priv->drm, "[CRTC:%d:%s] DSB %d is busy\n", + if (is_dsb_busy(display, pipe, dsb->id)) { + drm_err(display->drm, "[CRTC:%d:%s] DSB %d is busy\n", crtc->base.base.id, crtc->base.name, dsb->id); return; } - intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id), + intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), ctrl | DSB_ENABLE); - intel_de_write_fw(dev_priv, DSB_CHICKEN(pipe, dsb->id), + intel_de_write_fw(display, DSB_CHICKEN(pipe, dsb->id), dsb_chicken(crtc)); - intel_de_write_fw(dev_priv, DSB_HEAD(pipe, dsb->id), + intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id), intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf)); if (dewake_scanline >= 0) { @@ -371,7 +371,7 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, hw_dewake_scanline = intel_crtc_scanline_to_hw(crtc, dewake_scanline); - intel_de_write_fw(dev_priv, DSB_PMCTRL(pipe, dsb->id), + intel_de_write_fw(display, DSB_PMCTRL(pipe, dsb->id), DSB_ENABLE_DEWAKE | DSB_SCANLINE_FOR_DEWAKE(hw_dewake_scanline)); @@ -380,12 +380,12 @@ static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, * or close to racing past the target scanline. */ diff = dewake_scanline - intel_get_crtc_scanline(crtc); - intel_de_write_fw(dev_priv, DSB_PMCTRL_2(pipe, dsb->id), + intel_de_write_fw(display, DSB_PMCTRL_2(pipe, dsb->id), (diff >= 0 && diff < 5 ? DSB_FORCE_DEWAKE : 0) | DSB_BLOCK_DEWAKE_EXTENSION); } - intel_de_write_fw(dev_priv, DSB_TAIL(pipe, dsb->id), + intel_de_write_fw(display, DSB_TAIL(pipe, dsb->id), intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + tail); } @@ -407,21 +407,21 @@ void intel_dsb_commit(struct intel_dsb *dsb, void intel_dsb_wait(struct intel_dsb *dsb) { struct intel_crtc *crtc = dsb->crtc; - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc->base.dev); enum pipe pipe = crtc->pipe; - if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) { + if (wait_for(!is_dsb_busy(display, pipe, dsb->id), 1)) { u32 offset = intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf); - intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id), + intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), DSB_ENABLE | DSB_HALT); - drm_err(&dev_priv->drm, + drm_err(display->drm, "[CRTC:%d:%s] DSB %d timed out waiting for idle (current head=0x%x, head=0x%x, tail=0x%x)\n", crtc->base.base.id, crtc->base.name, dsb->id, - intel_de_read_fw(dev_priv, DSB_CURRENT_HEAD(pipe, dsb->id)) - offset, - intel_de_read_fw(dev_priv, DSB_HEAD(pipe, dsb->id)) - offset, - intel_de_read_fw(dev_priv, DSB_TAIL(pipe, dsb->id)) - offset); + intel_de_read_fw(display, DSB_CURRENT_HEAD(pipe, dsb->id)) - offset, + intel_de_read_fw(display, DSB_HEAD(pipe, dsb->id)) - offset, + intel_de_read_fw(display, DSB_TAIL(pipe, dsb->id)) - offset); intel_dsb_dump(dsb); } @@ -429,7 +429,7 @@ void intel_dsb_wait(struct intel_dsb *dsb) /* Attempt to reset it */ dsb->free_pos = 0; dsb->ins_start_offset = 0; - intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id), 0); + intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), 0); } /** From patchwork Tue Jun 11 13:33:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13693788 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7BDB7C25B76 for ; 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X-CSE-ConnectionGUID: mgMYCpppTcCJX8bXuhL40w== X-CSE-MsgGUID: bMwnXMkwToqP/hmTM86EZA== X-IronPort-AV: E=McAfee;i="6600,9927,11099"; a="12018241" X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="12018241" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2024 06:34:09 -0700 X-CSE-ConnectionGUID: WuBsZewIQSujsqbh0wkhUA== X-CSE-MsgGUID: w2geA1x0TbyWSLc0beaBSg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="39421441" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 11 Jun 2024 06:34:07 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 11 Jun 2024 16:34:06 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 08/11] drm/i915/dsb: Add i915.enable_dsb module parameter Date: Tue, 11 Jun 2024 16:33:41 +0300 Message-ID: <20240611133344.30673-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240611133344.30673-1-ville.syrjala@linux.intel.com> References: <20240611133344.30673-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä As we extend the use of DSB for critical pipe/plane register programming, it'll be nice to have an escape valve at hand, in case things go very poorly. To that end, add a i915.enable_dsb modparam by which we can force the driver to take the pure mmio path instead. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display_params.c | 3 +++ drivers/gpu/drm/i915/display/intel_display_params.h | 1 + drivers/gpu/drm/i915/display/intel_dsb.c | 3 +++ 3 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c index aebdb7b59dbf..449a31767791 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.c +++ b/drivers/gpu/drm/i915/display/intel_display_params.c @@ -54,6 +54,9 @@ intel_display_param_named_unsafe(enable_dc, int, 0400, intel_display_param_named_unsafe(enable_dpt, bool, 0400, "Enable display page table (DPT) (default: true)"); +intel_display_param_named_unsafe(enable_dsb, bool, 0600, + "Enable display state buffer (DSB) (default: true)"); + intel_display_param_named_unsafe(enable_sagv, bool, 0400, "Enable system agent voltage/frequency scaling (SAGV) (default: true)"); diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h index 1208a62c16d2..48c29c55c939 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.h +++ b/drivers/gpu/drm/i915/display/intel_display_params.h @@ -31,6 +31,7 @@ struct drm_i915_private; param(int, vbt_sdvo_panel_type, -1, 0400) \ param(int, enable_dc, -1, 0400) \ param(bool, enable_dpt, true, 0400) \ + param(bool, enable_dsb, true, 0600) \ param(bool, enable_sagv, true, 0600) \ param(int, disable_power_well, -1, 0400) \ param(bool, enable_ips, true, 0600) \ diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index bee48ac419ce..2ab3765f6c06 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -460,6 +460,9 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, if (!HAS_DSB(i915)) return NULL; + if (!i915->display.params.enable_dsb) + return NULL; + /* TODO: DSB is broken in Xe KMD, so disabling it until fixed */ if (!IS_ENABLED(I915)) return NULL; From patchwork Tue Jun 11 13:33:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13693790 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E83AC25B76 for ; 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X-CSE-ConnectionGUID: vmGch0L2S4SH9PJg+FudAg== X-CSE-MsgGUID: K2jxOvMdQ52NG97X7Rkd4g== X-IronPort-AV: E=McAfee;i="6600,9927,11099"; a="12018243" X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="12018243" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2024 06:34:12 -0700 X-CSE-ConnectionGUID: +iaJo4PMQdKr6xr62rY0ag== X-CSE-MsgGUID: 68H9ZKjCQ4WCTqMTshF5zQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="39421452" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 11 Jun 2024 06:34:10 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 11 Jun 2024 16:34:09 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 09/11] drm/i915: Drop useless intel_dsb.h include Date: Tue, 11 Jun 2024 16:33:42 +0300 Message-ID: <20240611133344.30673-10-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240611133344.30673-1-ville.syrjala@linux.intel.com> References: <20240611133344.30673-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä intel_crtc.c doens't need intel_dsb.h so don't include it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_crtc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 6831060a792a..a2b8953d7283 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -24,7 +24,6 @@ #include "intel_display_trace.h" #include "intel_display_types.h" #include "intel_drrs.h" -#include "intel_dsb.h" #include "intel_dsi.h" #include "intel_fifo_underrun.h" #include "intel_pipe_crc.h" From patchwork Tue Jun 11 13:33:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13693792 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8B59C25B76 for ; Tue, 11 Jun 2024 13:34:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AE45910E656; Tue, 11 Jun 2024 13:34:26 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="LYbfhGT+"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9892410E64D for ; Tue, 11 Jun 2024 13:34:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718112854; x=1749648854; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ra7aSyiq3clf7at0XaiCmvtZUqIe7t5yZbN2oxGLqHc=; b=LYbfhGT+xzNMhVRsxB+WSpKSCCQEInzXb0qy6YlX5X2MGkAptaOosZAv 5K0/JU0eX8M6eLnuZCkFTAEBI64LQd4je+GH+VUMFnaZyfPx2qOhs9+uX Pm4Rck/Nv83Z4FK2mtEVJhTlnZImpvjZ9V+fGp2Wpl+YELMHK3Qw4GxYH GfYBi9O0C3OpmE/DXY6MXuQ4NZEYq9k/vR4B4S3cocjaQ8BJLOwueVFry foXeNHOCuZ/ON+wqJT4Zu9cSxEd60uIzSemI0w5ySi8GgmJj5bM6oWHkZ cFhLt7tM8YSJv2BaUjqV8ztMBSETm7FHYpw+/WCQE+DbpRdU3l+RbLKoV g==; X-CSE-ConnectionGUID: /w9smXOSTPuN9acmqjhUOg== X-CSE-MsgGUID: vrfa6IozRdKYSMkRIiJ9Tg== X-IronPort-AV: E=McAfee;i="6600,9927,11099"; a="12018244" X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="12018244" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2024 06:34:14 -0700 X-CSE-ConnectionGUID: SWZNw52USTiq40e1aUHL0Q== X-CSE-MsgGUID: 8wg9skZCRrGoiXgKywIjLA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="39421460" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 11 Jun 2024 06:34:12 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 11 Jun 2024 16:34:12 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 10/11] drm/i915/dsb: Document that the ATS fault bits are for mtl+ Date: Tue, 11 Jun 2024 16:33:43 +0300 Message-ID: <20240611133344.30673-11-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240611133344.30673-1-ville.syrjala@linux.intel.com> References: <20240611133344.30673-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The ATS faults have something to do with some new iommu stuff on mtl+. Document that the relevant DSB interrupt bits aren't valid for earlier platforms. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb_regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb_regs.h b/drivers/gpu/drm/i915/display/intel_dsb_regs.h index 210e2665441d..9c2664ff519a 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dsb_regs.h @@ -51,12 +51,12 @@ #define DSB_RESET_SM_STATE_MASK REG_GENMASK(5, 4) #define DSB_RUN_SM_STATE_MASK REG_GENMASK(2, 0) #define DSB_INTERRUPT(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x28) -#define DSB_ATS_FAULT_INT_EN REG_BIT(20) +#define DSB_ATS_FAULT_INT_EN REG_BIT(20) /* mtl+ */ #define DSB_GTT_FAULT_INT_EN REG_BIT(19) #define DSB_RSPTIMEOUT_INT_EN REG_BIT(18) #define DSB_POLL_ERR_INT_EN REG_BIT(17) #define DSB_PROG_INT_EN REG_BIT(16) -#define DSB_ATS_FAULT_INT_STATUS REG_BIT(4) +#define DSB_ATS_FAULT_INT_STATUS REG_BIT(4) /* mtl+ */ #define DSB_GTT_FAULT_INT_STATUS REG_BIT(3) #define DSB_RSPTIMEOUT_INT_STATUS REG_BIT(2) #define DSB_POLL_ERR_INT_STATUS REG_BIT(1) From patchwork Tue Jun 11 13:33:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13693791 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0BB00C27C5E for ; Tue, 11 Jun 2024 13:34:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5B99C10E653; Tue, 11 Jun 2024 13:34:20 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="n7XGTkNw"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5DAFF10E658 for ; Tue, 11 Jun 2024 13:34:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718112857; x=1749648857; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ehrsDO4DNcnoO8J/mEL8WLstZhyknBPwxQMsVmBbYLo=; b=n7XGTkNwOq5oZkRLLMuFmHvS2AoXO+GcG1ohMCOd/hVptSGMzXwkYv58 XAJn7UUZKL9f2FeRT57CO6qfg7ZTdfMq5MRxJvfIGoFhcfptZFWunfuZY KI7vKMr0+yOvgmAl9n6rAPL5Gnt3nhuZal/IsIHeI79uomiUfQ5RgauJo w3/2K35Lr1ejoraRYL5fesLoJggHXAO34j03edgjYJXb51FcF5531E6cb pVnbJuYpUBPOEO0oi4dXf/Zeo7KYsYCkV7xh94DGqMKqScyvP80mh1c73 2l3XTgQleB3MQuFdP//3ba3cRoPDVvU6+8H3s//U8UQK9y9iz1+PrxYnK g==; X-CSE-ConnectionGUID: UCrV5uPRQIWZJOOovODe/A== X-CSE-MsgGUID: 08zbZz1sT/WkSk0KBMilbQ== X-IronPort-AV: E=McAfee;i="6600,9927,11099"; a="12018246" X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="12018246" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2024 06:34:17 -0700 X-CSE-ConnectionGUID: uhSS5fftRNCv+SGNeXyTwA== X-CSE-MsgGUID: qO/V4bC9Q9Gp1Pn3NgPahw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,230,1712646000"; d="scan'208";a="39421467" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 11 Jun 2024 06:34:15 -0700 Received: by stinkbox (sSMTP sendmail emulation); Tue, 11 Jun 2024 16:34:14 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Subject: [PATCH 11/11] drm/i915/dsb: Try to document that DSB_STATUS bit 16 is level triggered Date: Tue, 11 Jun 2024 16:33:44 +0300 Message-ID: <20240611133344.30673-12-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240611133344.30673-1-ville.syrjala@linux.intel.com> References: <20240611133344.30673-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä DSB_STATUS bit 16 is supposed to be a sticky bit informing us whether the DSB was idle or not when the pipe's delayed vblank (when double buffered registers latch) occurred. Unfortunately it turns out this is a level triggred signal, ie. the bit will be set whenever the DSB is busy during the scanline window between start of delayed vblank and vtotal. Try to document that fact by renaming the bit. Sadly this also thwarts my plan to use this bit to sanity check that the (to be introduced) DSB based vblank evasion did its job correctly. That would require an edge triggered signal instead. So looks like we'll have to rely mostly on luck instead :( Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dsb_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb_regs.h b/drivers/gpu/drm/i915/display/intel_dsb_regs.h index 9c2664ff519a..cb6e0e5624a6 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dsb_regs.h @@ -45,7 +45,7 @@ #define DSB_TLBTRANS_SM_STATE_MASK REG_GENMASK(21, 20) #define DSB_SAFE_WINDOW REG_BIT(19) #define DSB_POINTERS_SM_STATE_MASK REG_GENMASK(18, 17) -#define DSB_BUSY_ON_DELAYED_VBLANK REG_BIT(16) +#define DSB_BUSY_DURING_DELAYED_VBLANK REG_BIT(16) #define DSB_MMIO_ARB_SM_STATE_MASK REG_GENMASK(15, 13) #define DSB_MMIO_INST_SM_STATE_MASK REG_GENMASK(11, 7) #define DSB_RESET_SM_STATE_MASK REG_GENMASK(5, 4)