From patchwork Tue Jun 11 17:44:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fred Griffoul X-Patchwork-Id: 13694070 Received: from smtp-fw-9102.amazon.com (smtp-fw-9102.amazon.com [207.171.184.29]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92E5A502A9; Tue, 11 Jun 2024 17:45:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=207.171.184.29 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718127935; cv=none; b=VgO4be7ceo+2094YU/oVtDsc0rZVSYMymKnLCrsS/5aqEcZ34eBP5mwt/YjipBeKVAi8daTaX7DyVRCSnELYuN92Pm+Bjfl6g7Wcqf0IecUqWaq8LL0wEbyiwb+fzI0xrwhK068g0FJULiX+V+65vcskrQdfyJst/+fNbDaAK44= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718127935; c=relaxed/simple; bh=zTaBAcIgu8FzEpJSI1r+QourCEvxKKmgr6F8JlwIUR0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mYVspONKak8GJbEdGS5ALDu2FBZrnqwU+TalHuOoCq0HZUj/dXZGohBW5cfDkeTOthsU8b3VQvdAv0/BPJp4oKjmjYos4DduO0BoXT8/enn/94ACPcISRF2Y7xAob7WG67Nw6UfBN8OrVqYsP37AoAUQDw6GYEFL9nt6Ym7dIZg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.co.uk; spf=pass smtp.mailfrom=amazon.co.uk; dkim=pass (1024-bit key) header.d=amazon.co.uk header.i=@amazon.co.uk header.b=NORoAM53; arc=none smtp.client-ip=207.171.184.29 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.co.uk Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amazon.co.uk Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amazon.co.uk header.i=@amazon.co.uk header.b="NORoAM53" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.co.uk; i=@amazon.co.uk; q=dns/txt; s=amazon201209; t=1718127930; x=1749663930; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GKre/lXeLq2FkbVhYcoGJbiGx0tXQ6v9fNnBOIMJeLw=; b=NORoAM53ue9g4Hl1e4uAFcXinqGhm6NEyN8BQdmDfJqu7hv0Ih0IfSEU nPmNAVO/k5qrsMAnBiUM4up3bGJoTCZdJYD23OTFokUbfBWbnh/bejIoZ 7JS1lasJoFWs6KmoksxzF+SSbcDyaARIu3CTnGLcxJf2od3IV/DsBfIpK 8=; X-IronPort-AV: E=Sophos;i="6.08,230,1712620800"; d="scan'208";a="425558126" Received: from pdx4-co-svc-p1-lb2-vlan3.amazon.com (HELO smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.25.36.214]) by smtp-border-fw-9102.sea19.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2024 17:45:22 +0000 Received: from EX19MTAEUC001.ant.amazon.com [10.0.10.100:42655] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.31.105:2525] with esmtp (Farcaster) id bb066631-9c9a-4482-b062-2f22bedf3b3d; Tue, 11 Jun 2024 17:45:21 +0000 (UTC) X-Farcaster-Flow-ID: bb066631-9c9a-4482-b062-2f22bedf3b3d Received: from EX19D007EUA001.ant.amazon.com (10.252.50.133) by EX19MTAEUC001.ant.amazon.com (10.252.51.155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34; Tue, 11 Jun 2024 17:45:21 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA001.ant.amazon.com (10.252.50.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34; Tue, 11 Jun 2024 17:45:21 +0000 Received: from dev-dsk-fgriffo-1c-69b51a13.eu-west-1.amazon.com (10.13.244.152) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34 via Frontend Transport; Tue, 11 Jun 2024 17:45:16 +0000 From: Fred Griffoul To: CC: Fred Griffoul , kernel test robot , Catalin Marinas , Will Deacon , Alex Williamson , Waiman Long , Zefan Li , Tejun Heo , Johannes Weiner , Mark Rutland , Marc Zyngier , Oliver Upton , Mark Brown , Ard Biesheuvel , Joey Gouly , Ryan Roberts , Jeremy Linton , "Jason Gunthorpe" , Yi Liu , Kevin Tian , Eric Auger , Stefan Hajnoczi , Christian Brauner , Ankit Agrawal , Reinette Chatre , Ye Bin , , , , Subject: [PATCH v6 1/2] cgroup/cpuset: export cpuset_cpus_allowed() Date: Tue, 11 Jun 2024 17:44:24 +0000 Message-ID: <20240611174430.90787-2-fgriffo@amazon.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240611174430.90787-1-fgriffo@amazon.co.uk> References: <20240611174430.90787-1-fgriffo@amazon.co.uk> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 A subsequent patch calls cpuset_cpus_allowed() in the vfio driver pci code. Export the symbol to be able to build the vfio driver as a kernel module. This is not enough, however: when CONFIG_CPUSETS is _not_ defined cpuset_cpus_allowed() is an inline function returning task_cpu_possible_mask(). For the arm64 architecture this function is also inline: it checks the arm64_mismatched_32bit_el0 static key and calls system_32bit_el0_cpumask(). We need to export those symbols as well. Signed-off-by: Fred Griffoul Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202406060731.L3NSR1Hy-lkp@intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202406070659.pYu6zNrx-lkp@intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202406101154.iaDyTRwZ-lkp@intel.com/ Acked-by: Waiman Long Acked-by: Catalin Marinas --- arch/arm64/kernel/cpufeature.c | 2 ++ kernel/cgroup/cpuset.c | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 56583677c1f2..2f1de6343bee 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -127,6 +127,7 @@ static bool __read_mostly allow_mismatched_32bit_el0; * seen at least one CPU capable of 32-bit EL0. */ DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); +EXPORT_SYMBOL_GPL(arm64_mismatched_32bit_el0); /* * Mask of CPUs supporting 32-bit EL0. @@ -1614,6 +1615,7 @@ const struct cpumask *system_32bit_el0_cpumask(void) return cpu_possible_mask; } +EXPORT_SYMBOL_GPL(system_32bit_el0_cpumask); static int __init parse_32bit_el0_param(char *str) { diff --git a/kernel/cgroup/cpuset.c b/kernel/cgroup/cpuset.c index 4237c8748715..9fd56222aa4b 100644 --- a/kernel/cgroup/cpuset.c +++ b/kernel/cgroup/cpuset.c @@ -4764,6 +4764,7 @@ void cpuset_cpus_allowed(struct task_struct *tsk, struct cpumask *pmask) rcu_read_unlock(); spin_unlock_irqrestore(&callback_lock, flags); } +EXPORT_SYMBOL_GPL(cpuset_cpus_allowed); /** * cpuset_cpus_allowed_fallback - final fallback before complete catastrophe. From patchwork Tue Jun 11 17:44:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fred Griffoul X-Patchwork-Id: 13694071 Received: from smtp-fw-80006.amazon.com (smtp-fw-80006.amazon.com [99.78.197.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6656C1CD2B; Tue, 11 Jun 2024 17:45:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=99.78.197.217 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718127946; cv=none; b=bj1QcTXc0dtenLzEOjOJIo2lCpz3bjGMKGIoTyM1J9TEK/mV3130/q7leH9JvHJYvaVRM6EjGmQ8c+abg/DC3RneVh9VZ7qYCQVXEauGCVTMu3DctIuMBYZHD9rMQDTKZS0AJyjnH5ta5KcnRgUpLi2w/23D4e0DWTlw6kwI4cA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718127946; c=relaxed/simple; bh=TffUeohfdPQLAp43LWsakEtSlD8OSmDCAxIkjWVpEbs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZpsqtkBOO+NZVMgoCTJ2yyd6EkNBNLFdk1DZf/Y5Ptgk2mJzG5SSdNsD8mfNEbK8tixQLDLRjsojQ9K+QJsMwnO7g35oFfglVBAnBh6WzuoYU6n4nqpyLJvtBSJkVTfYB6qNq6/TI3ezz/AfePSCtYMKv3PO9KxQy2XioSZ4V4g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.co.uk; spf=pass smtp.mailfrom=amazon.co.uk; dkim=pass (1024-bit key) header.d=amazon.co.uk header.i=@amazon.co.uk header.b=eeTgkTSF; arc=none smtp.client-ip=99.78.197.217 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.co.uk Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amazon.co.uk Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amazon.co.uk header.i=@amazon.co.uk header.b="eeTgkTSF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.co.uk; i=@amazon.co.uk; q=dns/txt; s=amazon201209; t=1718127944; x=1749663944; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CxIP1cX8RbojJf0gUvwYsfGSNOxjOtjKBPayNFENtxw=; b=eeTgkTSFHjaAptcChgpZtETTnqCmOtefy+70qL9glHGRAdSNQSXhytHa rsVHUDTrOzHLx8vrWRJ3x04YMBMLsawexq/enmtED/8u8rdvhlffNdWUR jECB8Eq6WJgVobhfY3TNcOCbcsE/E0eMeYlXuOjFzG6JycKYI0/NDSiW4 A=; X-IronPort-AV: E=Sophos;i="6.08,230,1712620800"; d="scan'208";a="301492498" Received: from pdx4-co-svc-p1-lb2-vlan3.amazon.com (HELO smtpout.prod.us-east-1.prod.farcaster.email.amazon.dev) ([10.25.36.214]) by smtp-border-fw-80006.pdx80.corp.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2024 17:45:40 +0000 Received: from EX19MTAEUA001.ant.amazon.com [10.0.17.79:20292] by smtpin.naws.eu-west-1.prod.farcaster.email.amazon.dev [10.0.35.119:2525] with esmtp (Farcaster) id 704b2958-af5b-40c0-9dea-ba1a9127a023; Tue, 11 Jun 2024 17:45:38 +0000 (UTC) X-Farcaster-Flow-ID: 704b2958-af5b-40c0-9dea-ba1a9127a023 Received: from EX19D007EUA002.ant.amazon.com (10.252.50.68) by EX19MTAEUA001.ant.amazon.com (10.252.50.192) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34; Tue, 11 Jun 2024 17:45:38 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D007EUA002.ant.amazon.com (10.252.50.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34; Tue, 11 Jun 2024 17:45:38 +0000 Received: from dev-dsk-fgriffo-1c-69b51a13.eu-west-1.amazon.com (10.13.244.152) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34 via Frontend Transport; Tue, 11 Jun 2024 17:45:34 +0000 From: Fred Griffoul To: CC: Fred Griffoul , Catalin Marinas , Will Deacon , Alex Williamson , Waiman Long , Zefan Li , Tejun Heo , Johannes Weiner , Mark Rutland , Marc Zyngier , Oliver Upton , Mark Brown , Ard Biesheuvel , Joey Gouly , Ryan Roberts , Jeremy Linton , Jason Gunthorpe , Yi Liu , Kevin Tian , Eric Auger , Stefan Hajnoczi , "Christian Brauner" , Ankit Agrawal , "Reinette Chatre" , Ye Bin , , , , Subject: [PATCH v6 2/2] vfio/pci: add interrupt affinity support Date: Tue, 11 Jun 2024 17:44:25 +0000 Message-ID: <20240611174430.90787-3-fgriffo@amazon.co.uk> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240611174430.90787-1-fgriffo@amazon.co.uk> References: <20240611174430.90787-1-fgriffo@amazon.co.uk> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The usual way to configure a device interrupt from userland is to write the /proc/irq//smp_affinity or smp_affinity_list files. When using vfio to implement a device driver or a virtual machine monitor, this may not be ideal: the process managing the vfio device interrupts may not be granted root privilege, for security reasons. Thus it cannot directly control the interrupt affinity and has to rely on an external command. This patch extends the VFIO_DEVICE_SET_IRQS ioctl() with a new data flag to specify the affinity of interrupts of a vfio pci device. The CPU affinity mask argument must be a subset of the process cpuset, otherwise an error -EPERM is returned. The vfio_irq_set argument shall be set-up in the following way: - the 'flags' field have the new flag VFIO_IRQ_SET_DATA_CPUSET set as well as VFIO_IRQ_SET_ACTION_TRIGGER. - the variable-length 'data' field is a cpu_set_t structure, as for the sched_setaffinity() syscall, the size of which is derived from 'argsz'. Signed-off-by: Fred Griffoul --- drivers/vfio/pci/vfio_pci_core.c | 2 +- drivers/vfio/pci/vfio_pci_intrs.c | 41 +++++++++++++++++++++++++++++++ drivers/vfio/vfio_main.c | 15 ++++++++--- include/uapi/linux/vfio.h | 15 ++++++++++- 4 files changed, 67 insertions(+), 6 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index 80cae87fff36..fbc490703031 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -1174,7 +1174,7 @@ static int vfio_pci_ioctl_get_irq_info(struct vfio_pci_core_device *vdev, return -EINVAL; } - info.flags = VFIO_IRQ_INFO_EVENTFD; + info.flags = VFIO_IRQ_INFO_EVENTFD | VFIO_IRQ_INFO_CPUSET; info.count = vfio_pci_get_irq_count(vdev, info.index); diff --git a/drivers/vfio/pci/vfio_pci_intrs.c b/drivers/vfio/pci/vfio_pci_intrs.c index 8382c5834335..b339c42cb1c0 100644 --- a/drivers/vfio/pci/vfio_pci_intrs.c +++ b/drivers/vfio/pci/vfio_pci_intrs.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "vfio_pci_priv.h" @@ -82,6 +83,40 @@ vfio_irq_ctx_alloc(struct vfio_pci_core_device *vdev, unsigned long index) return ctx; } +static int vfio_pci_set_affinity(struct vfio_pci_core_device *vdev, + unsigned int start, unsigned int count, + struct cpumask *irq_mask) +{ + cpumask_var_t allowed_mask; + int irq, err = 0; + unsigned int i; + + if (!alloc_cpumask_var(&allowed_mask, GFP_KERNEL)) + return -ENOMEM; + + cpuset_cpus_allowed(current, allowed_mask); + if (!cpumask_subset(irq_mask, allowed_mask)) { + err = -EPERM; + goto finish; + } + + for (i = start; i < start + count; i++) { + irq = pci_irq_vector(vdev->pdev, i); + if (irq < 0) { + err = -EINVAL; + break; + } + + err = irq_set_affinity(irq, irq_mask); + if (err) + break; + } + +finish: + free_cpumask_var(allowed_mask); + return err; +} + /* * INTx */ @@ -665,6 +700,9 @@ static int vfio_pci_set_intx_trigger(struct vfio_pci_core_device *vdev, if (!is_intx(vdev)) return -EINVAL; + if (flags & VFIO_IRQ_SET_DATA_CPUSET) + return vfio_pci_set_affinity(vdev, start, count, data); + if (flags & VFIO_IRQ_SET_DATA_NONE) { vfio_send_intx_eventfd(vdev, vfio_irq_ctx_get(vdev, 0)); } else if (flags & VFIO_IRQ_SET_DATA_BOOL) { @@ -713,6 +751,9 @@ static int vfio_pci_set_msi_trigger(struct vfio_pci_core_device *vdev, if (!irq_is(vdev, index)) return -EINVAL; + if (flags & VFIO_IRQ_SET_DATA_CPUSET) + return vfio_pci_set_affinity(vdev, start, count, data); + for (i = start; i < start + count; i++) { ctx = vfio_irq_ctx_get(vdev, i); if (!ctx) diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c index e97d796a54fb..2e4f4e37cf89 100644 --- a/drivers/vfio/vfio_main.c +++ b/drivers/vfio/vfio_main.c @@ -1505,23 +1505,30 @@ int vfio_set_irqs_validate_and_prepare(struct vfio_irq_set *hdr, int num_irqs, size = 0; break; case VFIO_IRQ_SET_DATA_BOOL: - size = sizeof(uint8_t); + size = size_mul(hdr->count, sizeof(uint8_t)); break; case VFIO_IRQ_SET_DATA_EVENTFD: - size = sizeof(int32_t); + size = size_mul(hdr->count, sizeof(int32_t)); + break; + case VFIO_IRQ_SET_DATA_CPUSET: + size = hdr->argsz - minsz; + if (size < cpumask_size()) + return -EINVAL; + if (size > cpumask_size()) + size = cpumask_size(); break; default: return -EINVAL; } if (size) { - if (hdr->argsz - minsz < hdr->count * size) + if (hdr->argsz - minsz < size) return -EINVAL; if (!data_size) return -EINVAL; - *data_size = hdr->count * size; + *data_size = size; } return 0; diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 2b68e6cdf190..d2edf6b725f8 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -530,6 +530,10 @@ struct vfio_region_info_cap_nvlink2_lnkspd { * Absence of the NORESIZE flag indicates that vectors can be enabled * and disabled dynamically without impacting other vectors within the * index. + * + * The CPUSET flag indicates the interrupt index supports setting + * its affinity with a cpu_set_t configured with the SET_IRQ + * ioctl(). */ struct vfio_irq_info { __u32 argsz; @@ -538,6 +542,7 @@ struct vfio_irq_info { #define VFIO_IRQ_INFO_MASKABLE (1 << 1) #define VFIO_IRQ_INFO_AUTOMASKED (1 << 2) #define VFIO_IRQ_INFO_NORESIZE (1 << 3) +#define VFIO_IRQ_INFO_CPUSET (1 << 4) __u32 index; /* IRQ index */ __u32 count; /* Number of IRQs within this index */ }; @@ -580,6 +585,12 @@ struct vfio_irq_info { * * Note that ACTION_[UN]MASK specify user->kernel signaling (irqfds) while * ACTION_TRIGGER specifies kernel->user signaling. + * + * DATA_CPUSET specifies the affinity for the range of interrupt vectors. + * It must be set with ACTION_TRIGGER in 'flags'. The variable-length 'data' + * array is the CPU affinity mask represented as a 'cpu_set_t' structure, as + * for the sched_setaffinity() syscall argument: the 'argsz' field is used + * to check the actual cpu_set_t size. */ struct vfio_irq_set { __u32 argsz; @@ -587,6 +598,7 @@ struct vfio_irq_set { #define VFIO_IRQ_SET_DATA_NONE (1 << 0) /* Data not present */ #define VFIO_IRQ_SET_DATA_BOOL (1 << 1) /* Data is bool (u8) */ #define VFIO_IRQ_SET_DATA_EVENTFD (1 << 2) /* Data is eventfd (s32) */ +#define VFIO_IRQ_SET_DATA_CPUSET (1 << 6) /* Data is cpu_set_t */ #define VFIO_IRQ_SET_ACTION_MASK (1 << 3) /* Mask interrupt */ #define VFIO_IRQ_SET_ACTION_UNMASK (1 << 4) /* Unmask interrupt */ #define VFIO_IRQ_SET_ACTION_TRIGGER (1 << 5) /* Trigger interrupt */ @@ -599,7 +611,8 @@ struct vfio_irq_set { #define VFIO_IRQ_SET_DATA_TYPE_MASK (VFIO_IRQ_SET_DATA_NONE | \ VFIO_IRQ_SET_DATA_BOOL | \ - VFIO_IRQ_SET_DATA_EVENTFD) + VFIO_IRQ_SET_DATA_EVENTFD | \ + VFIO_IRQ_SET_DATA_CPUSET) #define VFIO_IRQ_SET_ACTION_TYPE_MASK (VFIO_IRQ_SET_ACTION_MASK | \ VFIO_IRQ_SET_ACTION_UNMASK | \ VFIO_IRQ_SET_ACTION_TRIGGER)