From patchwork Thu Jun 13 16:19:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shay Drori X-Patchwork-Id: 13697119 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2050.outbound.protection.outlook.com [40.107.236.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFEFD145FFA; Thu, 13 Jun 2024 16:20:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.236.50 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718295651; cv=fail; b=ercqcAhLMBvZIeCS6GlUWDlYWfE2vVirvcW3JKFyvmkunAo/BHRI0YgHAx+xAVtbs/kcb7z+Uz+JPiObT05SvTWjRErZEPTog9ZfzN8fvDx39hLNMTAY3xSxNHuttAe3m1ldxUUQS9SFIkE1EA8wG0UWWkTy1fIjzxmxGcF2KeM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718295651; c=relaxed/simple; bh=vunm7dTNqU+5RweOiadIS9i/qyF52gHsEGJAFIPwxQk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QLTi29/+aM2o0MZhF8dZ82zVGyK69rG0gkzv6fhjkzQTTdG+/1Tpqh/tty1u+BR0KeTX2TGr7rj2+U1zRq+pJIJP79ZwjcGjlIsEZJOi3gZiuAh8+zjzREP1hz9A0GybQlks4/2XAfD8vSpk40uUy52zT8q/GcmNLHl8XnP7JvQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=jsUYa83p; arc=fail smtp.client-ip=40.107.236.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="jsUYa83p" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=GBkuJ/4YZqJl0xzZ9MC4Zv55bSCgYhW9Syxwjj3G9wU4iwK/SxuTPWyAfin3DCR5g8rmgvf+jrpRterTmggv4p2qFi/fgwJtN7m/KuDmeUsrQgw0Xcmdw03dNsH+lqodEkJ1ZQzsLBT0uyFKXP2j6RaosQNWShLIcFvIFqc7tRFiAexcFwbJ8C0ZH/P6ZbTGvqlZM3Z+4QjNCbZf/k7LQpqH2NLreQOPQkdPuJ91MNKco5IHDSJTatuSWGpq1+MhxxxvN/bvOa86XFA1GfYzwr2vzRhOsv0xEBMINv2vFWTLtDxYDXJvu5PegI7krl8bMxNkQ46rhouZvv1eLSfSUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=jtTXyjERU28Wk/GcorWoIQ5GPwcw1c1SAZkK149ebSM=; b=T9I4V7NzFdAEi5itK8T4ZujnU/jYtX7oL+GuheQV7aP9RRPBqh/WcyCNW2WMmenAVxjYMoWLwyIAb6gzvnwCBezpkycIA76rOVPGs3Ln6eT/Xe4h9uanq0ct4XeD8woxkbLGdskMtgXmrAYdAEuLo2I9HzVS8h5JYGd9q4GbxJZpXXZxUcmXu083cVlhZYygsDris1SfnCoh+MQtqHiOtaQQMWN3u723625FFxVBxHvMto3+Kmy1ylyziCacVqrlaUF79fy8yiJaVIrdbh9Xq9duKZHNP6/xMsgplFPNAoWTSN9/9SEpP1AWaJBrbo3q6wObfLkJW+lBNk06EbmtfA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jtTXyjERU28Wk/GcorWoIQ5GPwcw1c1SAZkK149ebSM=; b=jsUYa83pj4Kr6Zf04SqFM7Cur5oYU2S4XpCA2VB2HYsysR+1rEenpwsuJkEBiJW+x9utL2CXgcR+UaoJH3Feo7AUZgB/ZNlmwFvhJ7r76SDrzukn5KEQ9LsekH8PjGadfk5fEbAIcBxJ6ShihbPhCRN55pFltGpee0HlA3ajKpd2R+k+QpN8qA49o/2Ky0H/9kPr2tapog5N2f1Wr41BNREEiBfhUax3wH6Lcw0yXBHVRakS9imaOsuSi9djHLaLcfEQzuT7gadaD1TAOIKQoRaMTi/zbQlLoL3g5u3ibXOSXcfOHJWj3DwgrKCHxLuizIkBN2yH6RFu7msi2voiaQ== Received: from PH7PR10CA0013.namprd10.prod.outlook.com (2603:10b6:510:23d::9) by PH7PR12MB7842.namprd12.prod.outlook.com (2603:10b6:510:27a::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7677.24; Thu, 13 Jun 2024 16:20:46 +0000 Received: from SA2PEPF000015C8.namprd03.prod.outlook.com (2603:10b6:510:23d:cafe::65) by PH7PR10CA0013.outlook.office365.com (2603:10b6:510:23d::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7677.25 via Frontend Transport; Thu, 13 Jun 2024 16:20:45 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SA2PEPF000015C8.mail.protection.outlook.com (10.167.241.198) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7677.15 via Frontend Transport; Thu, 13 Jun 2024 16:20:44 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 13 Jun 2024 09:20:25 -0700 Received: from nps-server-23.mtl.labs.mlnx (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 13 Jun 2024 09:20:21 -0700 From: Shay Drory To: , , , , , , CC: , , , , , Shay Drory , "Parav Pandit" Subject: [PATCH net-next v6 1/2] driver core: auxiliary bus: show auxiliary device IRQs Date: Thu, 13 Jun 2024 19:19:11 +0300 Message-ID: <20240613161912.300785-2-shayd@nvidia.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20240613161912.300785-1-shayd@nvidia.com> References: <20240613161912.300785-1-shayd@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C8:EE_|PH7PR12MB7842:EE_ X-MS-Office365-Filtering-Correlation-Id: a100fbca-40ae-4d14-acc3-08dc8bc4c721 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230035|376009|7416009|1800799019|82310400021|36860700008; X-Microsoft-Antispam-Message-Info: Ahp3bpXQYwAXEvNIZP5SwuwECC8F14UIhT7cjF0lBOseNXHUHcLizVJ+f5LvkdRhri9YEaw75HP9jbBMvI1bTGxlL7uo7HRje8YK+E9Xtrse1uEbRsk3E11G9YSMv7Sbv9RnGhe4ZFehWHTbe3Ylc069/vx7WC/OvRBdwiuRhSdoTrbHYwIc4NrucWWtnWg3TssM27mkPvQ9YZKaPONQEkhRf0SQqbp2QlVTswNoGUHAQI9UBh08eC5bDyisZmH2ZNQ5zetIuE8oexnvLxchG0y7W+Q8ou5iLbHuoTLkLXq6X0Apkud9RYF68ZkEq7y6BV122BTO6qLNVgthn/XHbMUniDHLQlViRVcAfNyP6Ab/5psO4an1vaNEgQftIVWslM3oOGIpAn+YMK5Uyqf/FZUqNSZhzP96rgNKfcIqxe+kHmvdeSRwC/D9SMlOeoJQTw87uiyPi8kdDmzLjCdEdV0fzMpuj8wa/OG92krxP0rugDqf5jTjoXUxlYvH7LufIJ5kVbRdbMk7SCuLnOiZCF1qZJ/E6nE1m29RghH/lAdGuorCurjUvFliZNI2HMMGQWfWYKbyosZD0pCyJIgF8c2ZuV6QnNcYLOe3TutJd5MpMg7aCwrRbRMhBxQS/o8bSSfNCmkEgm8ZYlGdehm164eTbdWnuhYB8fJLcL82Uf6a0y3ezwVwoMuUIM9p/9aI3pMpo/AM7aYovIuvkMfUEWfNJRGqKnPV/hExQ5mTuQoDXvae4P5v9A9eS0AwKFwrNCwY2drrM0xUxbTA4mZAr1TJbMwaZMAdr77StdJiqhRsPZdLe8IXw0roVTzztBbtqLWIOOt8TeIvyqa11v1WcCfq+3BuLkBT9TgwtZv3Yx8NC8H8hloTeZ4QSG1byQ3zGpvF6D2g0LlD7JSPjpwI1BPQFReYHPZdyD3xBafZd2YVgDGh15m3x8NXlN7EMF1k17Xg+sYdpq/JNocZf8Zil67BaYfnKQgKaOUw8cDNTwou9HJ4D7PG7u1x045J98lUg9kZzybAYa1uRA5ExIIMlNpKVJz4r9Bz+KIlb2h9dUukLl4MIWwsargQgK5Cr1h1kNwBXxOcEdNG/njrNtfK/MJfjkGDYg6O3/HYBGTBLUcpmFu9GuL8ujC54HHtglH8FAj3FNhQpUi65PN2AOwjxU1f4uLkgCrNoLkHRveLdUSw0TKIbYNv7nhrlWLW44gIBk38Wc3NoCeuLV5JyCDXvoB84xwIUjUdpINPbxtJ1Cm+52szO4Avp9P61v4LzUPIekz4V27WOYnt2TpgR34mWbUi2zevpcMrjsHFy8AQfgt/1CwpMqfHHSAb76Zel76Tk7s/f1YnVH7b2ATTwsr+YAycmOVMSKewIhUa8BUf3/Cgwwm31p1BQBnpuSTZJCOi1MMgTwE+Q6wFGlyIc+RQGg== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230035)(376009)(7416009)(1800799019)(82310400021)(36860700008);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jun 2024 16:20:44.9085 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a100fbca-40ae-4d14-acc3-08dc8bc4c721 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7842 X-Patchwork-Delegate: kuba@kernel.org PCI subfunctions (SF) are anchored on the auxiliary bus. PCI physical and virtual functions are anchored on the PCI bus. The irq information of each such function is visible to users via sysfs directory "msi_irqs" containing files for each irq entry. However, for PCI SFs such information is unavailable. Due to this users have no visibility on IRQs used by the SFs. Secondly, an SF can be multi function device supporting rdma, netdevice and more. Without irq information at the bus level, the user is unable to view or use the affinity of the SF IRQs. Hence to match to the equivalent PCI PFs and VFs, add "irqs" directory, for supporting auxiliary devices, containing file for each irq entry. For example: $ ls /sys/bus/auxiliary/devices/mlx5_core.sf.1/irqs/ 50 51 52 53 54 55 56 57 58 Reviewed-by: Parav Pandit Signed-off-by: Shay Drory --- v5-v6: - removed concept of shared and exclusive and hence global xarray (Greg) v4-v5: - restore global mutex and replace refcount_t with simple integer (Greg) v3->4: - remove global mutex (Przemek) v2->v3: - fix function declaration in case SYSFS isn't defined v1->v2: - move #ifdefs from drivers/base/auxiliary.c to include/linux/auxiliary_bus.h (Greg) - use EXPORT_SYMBOL_GPL instead of EXPORT_SYMBOL (Greg) - Fix kzalloc(ref) to kzalloc(*ref) (Simon) - Add return description in auxiliary_device_sysfs_irq_add() kdoc (Simon) - Fix auxiliary_irq_mode_show doc (kernel test boot) --- Documentation/ABI/testing/sysfs-bus-auxiliary | 7 ++ drivers/base/auxiliary.c | 96 ++++++++++++++++++- include/linux/auxiliary_bus.h | 24 ++++- 3 files changed, 124 insertions(+), 3 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-auxiliary diff --git a/Documentation/ABI/testing/sysfs-bus-auxiliary b/Documentation/ABI/testing/sysfs-bus-auxiliary new file mode 100644 index 000000000000..e8752c2354bc --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-auxiliary @@ -0,0 +1,7 @@ +What: /sys/bus/auxiliary/devices/.../irqs/ +Date: April, 2024 +Contact: Shay Drory +Description: + The /sys/devices/.../irqs directory contains a variable set of + files, with each file is named as irq number similar to PCI PF + or VF's irq number located in msi_irqs directory. diff --git a/drivers/base/auxiliary.c b/drivers/base/auxiliary.c index d3a2c40c2f12..fcd7dbf20f88 100644 --- a/drivers/base/auxiliary.c +++ b/drivers/base/auxiliary.c @@ -158,6 +158,94 @@ * }; */ +#ifdef CONFIG_SYSFS +struct auxiliary_irq_info { + struct device_attribute sysfs_attr; +}; + +static struct attribute *auxiliary_irq_attrs[] = { + NULL +}; + +static const struct attribute_group auxiliary_irqs_group = { + .name = "irqs", + .attrs = auxiliary_irq_attrs, +}; + +static const struct attribute_group *auxiliary_irqs_groups[] = { + &auxiliary_irqs_group, + NULL +}; + +/** + * auxiliary_device_sysfs_irq_add - add a sysfs entry for the given IRQ + * @auxdev: auxiliary bus device to add the sysfs entry. + * @irq: The associated interrupt number. + * + * This function should be called after auxiliary device have successfully + * received the irq. + * + * Return: zero on success or an error code on failure. + */ +int auxiliary_device_sysfs_irq_add(struct auxiliary_device *auxdev, int irq) +{ + struct device *dev = &auxdev->dev; + struct auxiliary_irq_info *info; + int ret; + + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + sysfs_attr_init(&info->sysfs_attr.attr); + info->sysfs_attr.attr.name = kasprintf(GFP_KERNEL, "%d", irq); + if (!info->sysfs_attr.attr.name) { + ret = -ENOMEM; + goto name_err; + } + + ret = xa_insert(&auxdev->irqs, irq, info, GFP_KERNEL); + if (ret) + goto auxdev_xa_err; + + ret = sysfs_add_file_to_group(&dev->kobj, &info->sysfs_attr.attr, + auxiliary_irqs_group.name); + if (ret) + goto sysfs_add_err; + + return 0; + +sysfs_add_err: + xa_erase(&auxdev->irqs, irq); +auxdev_xa_err: + kfree(info->sysfs_attr.attr.name); +name_err: + kfree(info); + return ret; +} +EXPORT_SYMBOL_GPL(auxiliary_device_sysfs_irq_add); + +/** + * auxiliary_device_sysfs_irq_remove - remove a sysfs entry for the given IRQ + * @auxdev: auxiliary bus device to add the sysfs entry. + * @irq: the IRQ to remove. + * + * This function should be called to remove an IRQ sysfs entry. + */ +void auxiliary_device_sysfs_irq_remove(struct auxiliary_device *auxdev, int irq) +{ + struct auxiliary_irq_info *info = xa_load(&auxdev->irqs, irq); + struct device *dev = &auxdev->dev; + + sysfs_remove_file_from_group(&dev->kobj, &info->sysfs_attr.attr, + auxiliary_irqs_group.name); + xa_erase(&auxdev->irqs, irq); + kfree(info->sysfs_attr.attr.name); + kfree(info); +} +EXPORT_SYMBOL_GPL(auxiliary_device_sysfs_irq_remove); +#endif + static const struct auxiliary_device_id *auxiliary_match_id(const struct auxiliary_device_id *id, const struct auxiliary_device *auxdev) { @@ -295,6 +383,7 @@ EXPORT_SYMBOL_GPL(auxiliary_device_init); * __auxiliary_device_add - add an auxiliary bus device * @auxdev: auxiliary bus device to add to the bus * @modname: name of the parent device's driver module + * @irqs_sysfs_enable: whether to enable IRQs sysfs * * This is the third step in the three-step process to register an * auxiliary_device. @@ -310,7 +399,8 @@ EXPORT_SYMBOL_GPL(auxiliary_device_init); * parameter. Only if a user requires a custom name would this version be * called directly. */ -int __auxiliary_device_add(struct auxiliary_device *auxdev, const char *modname) +int __auxiliary_device_add(struct auxiliary_device *auxdev, const char *modname, + bool irqs_sysfs_enable) { struct device *dev = &auxdev->dev; int ret; @@ -325,6 +415,10 @@ int __auxiliary_device_add(struct auxiliary_device *auxdev, const char *modname) dev_err(dev, "auxiliary device dev_set_name failed: %d\n", ret); return ret; } + if (irqs_sysfs_enable) { + dev->groups = auxiliary_irqs_groups; + xa_init(&auxdev->irqs); + } ret = device_add(dev); if (ret) diff --git a/include/linux/auxiliary_bus.h b/include/linux/auxiliary_bus.h index de21d9d24a95..760fadb26620 100644 --- a/include/linux/auxiliary_bus.h +++ b/include/linux/auxiliary_bus.h @@ -58,6 +58,7 @@ * in * @name: Match name found by the auxiliary device driver, * @id: unique identitier if multiple devices of the same name are exported, + * @irqs: irqs xarray contains irq indices which are used by the device, * * An auxiliary_device represents a part of its parent device's functionality. * It is given a name that, combined with the registering drivers @@ -138,6 +139,7 @@ struct auxiliary_device { struct device dev; const char *name; + struct xarray irqs; u32 id; }; @@ -209,8 +211,26 @@ static inline struct auxiliary_driver *to_auxiliary_drv(struct device_driver *dr } int auxiliary_device_init(struct auxiliary_device *auxdev); -int __auxiliary_device_add(struct auxiliary_device *auxdev, const char *modname); -#define auxiliary_device_add(auxdev) __auxiliary_device_add(auxdev, KBUILD_MODNAME) +int __auxiliary_device_add(struct auxiliary_device *auxdev, const char *modname, + bool irqs_sysfs_enable); +#define auxiliary_device_add(auxdev) __auxiliary_device_add(auxdev, KBUILD_MODNAME, false) +#define auxiliary_device_add_with_irqs(auxdev) \ + __auxiliary_device_add(auxdev, KBUILD_MODNAME, true) + +#ifdef CONFIG_SYSFS +int auxiliary_device_sysfs_irq_add(struct auxiliary_device *auxdev, int irq); +void auxiliary_device_sysfs_irq_remove(struct auxiliary_device *auxdev, + int irq); +#else /* CONFIG_SYSFS */ +static inline int +auxiliary_device_sysfs_irq_add(struct auxiliary_device *auxdev, int irq) +{ + return 0; +} + +static inline void +auxiliary_device_sysfs_irq_remove(struct auxiliary_device *auxdev, int irq) {} +#endif static inline void auxiliary_device_uninit(struct auxiliary_device *auxdev) { From patchwork Thu Jun 13 16:19:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shay Drori X-Patchwork-Id: 13697120 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2048.outbound.protection.outlook.com [40.107.94.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22C52146D68; Thu, 13 Jun 2024 16:20:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.48 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718295655; cv=fail; b=EkUy9rDGTcBGbVaWasxfh0Fdy1qmiSzJw+2ueL+H/swZdZjcQt2kFsMm4qy1eMkwpo/IuRrSOpqcTaFHuF2x2Mxushz/EPG2tQfyWcCVQmBpeER/B1iAxILbv8bWpe+z6KsB6aYt28XSn9FVLoOxW95mMPT6fSIadOymK62GUi0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718295655; c=relaxed/simple; bh=LG6vDOSbe28cJzGdu6NQ29M47/EUeXJ+VHxswYfzJjY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fGQOpbEtb8223JD5BQh1cOv/67Vf3gWqAz5lCvlwI0KlKJvQW+EOV4mh8zmXL7bDVeDIWT0qJ/AaXG3w8l8wpbnSj9hOD4E3IPm3L8F2bkfLQcomYFu+Mz7hToiCJMwZziaEGpq6uCoCfXkWKKtbOmoNCZGofjJnGn47i138cHU= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=HfntwMKS; arc=fail smtp.client-ip=40.107.94.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="HfntwMKS" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=c5YOxyy8pDE1cqJosAjdMzD1b/6YKJ1mO7R/kVHOc46/xOVNcEwCruY1vFmm7llCAg7Et37AOw3mEP/UAIpznTNwLH4ILbP3WaVDMtUyMM1gr2L0zDRKCbUtOjTFwZwViG2CJ8XmkV24H4gN4mZDf6FK5vYmOUBWAfvy+oKtYC5V9Nl+XctEkFPUUnYYaSEV5H8deMQ2H51TZcILXvk3SgrpKDG8qAlKj9lPJhKsDIQxizEXA6PA1170gx8f9PMG5w1CgCU6ylc2TXPPy9dxmjNGjj5dXNQYLZjAwCM2DPHn08FUvU6dwTRDb42s6efQgCAPHG2YYB9OSbKznFLv7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Ya44U+ik57YqgFGF1fpVlBRJNIJ9riluAzX+fgUsAhw=; b=C4cnMLh0FnMbU4Mnp4QksFRcIYWt1W/ypa9vREOu4nYLZpJyYSxjtY5zjEbeCdahPLnggBsop5fvFVNTXE0X2SskW0Q50Wjtk2oct3ywivUVLEFLteOb9MfDkys7HpK14gP1oHNJMyJXspldrSvdB+sQvJesSg62BUHELXioXyykCS5I+Fl+AE4OGQ/RnXvgeQZDjwf6T6V193vADuXZBHjlhbIittGMn8KqxmElNJ4Fd/TWgk9e9FWxkZVXYvo4W/IuQYzzpu+Foa2FBlwbPuN+00pMjsRyb1Rqrn2LTNPpcDTznK1KaQ/rMq5qNXSCB9U04M23jWE++ZV7dtlL7A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Ya44U+ik57YqgFGF1fpVlBRJNIJ9riluAzX+fgUsAhw=; b=HfntwMKS4Rz1xPWxf3ZdvY6F6A0lt8aUlBqL3RN6Dtj/8h4jlOE9cXzt9gBod34wUd52IE/77IY6iuy3xqUP6FSa2LAMcYnZwo/nNBLKe8mNfqjiHZmJ12GIc847ox22eXFQW8RalUYJcYgFuRZjoe984NnqYmM0yc4Ad2/CwBLuIOpn8gfd6env3l8x3T9C7jzmWPYh7tTBcy70U9eSaGtmP1ofW3bXgnpwRllgiI9JWMmbDshbC7LrI1naTd1XXZVtyjKnH4sovx7jEYeS6yjr1BRRiWfrbnlOXuo2laWIlJA0zLdeQKApBq3fZnMQGQzbPb3AyDm4AXaTnqxopg== Received: from PH7PR10CA0021.namprd10.prod.outlook.com (2603:10b6:510:23d::20) by DS0PR12MB7898.namprd12.prod.outlook.com (2603:10b6:8:14c::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7677.25; Thu, 13 Jun 2024 16:20:48 +0000 Received: from SA2PEPF000015C8.namprd03.prod.outlook.com (2603:10b6:510:23d:cafe::6f) by PH7PR10CA0021.outlook.office365.com (2603:10b6:510:23d::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7677.25 via Frontend Transport; Thu, 13 Jun 2024 16:20:48 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SA2PEPF000015C8.mail.protection.outlook.com (10.167.241.198) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7677.15 via Frontend Transport; Thu, 13 Jun 2024 16:20:48 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 13 Jun 2024 09:20:30 -0700 Received: from nps-server-23.mtl.labs.mlnx (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 13 Jun 2024 09:20:25 -0700 From: Shay Drory To: , , , , , , CC: , , , , , Shay Drory , "Parav Pandit" Subject: [PATCH net-next v6 2/2] net/mlx5: Expose SFs IRQs Date: Thu, 13 Jun 2024 19:19:12 +0300 Message-ID: <20240613161912.300785-3-shayd@nvidia.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20240613161912.300785-1-shayd@nvidia.com> References: <20240613161912.300785-1-shayd@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C8:EE_|DS0PR12MB7898:EE_ X-MS-Office365-Filtering-Correlation-Id: be1a647e-7164-4220-bc94-08dc8bc4c937 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230035|376009|7416009|1800799019|82310400021|36860700008; X-Microsoft-Antispam-Message-Info: OYQwj/LiY/W3FM6u+LfB8VGp/BQcJKO10HXtXxqR8E774Nx/eFU1Q2gKrqQODRuHtJ0RFd8sQqUKAVWjHAhprwfMVV5hnyyCXfPZiv8BV3kJPsK85jNUJAvRWahXmn2bUBDWSCdHliT+fb+wG9mYr2SVtahsuBUZjE9ayoFxRjEgIL+hOTLT1FtWwdy6GvXG2beXM+eiqhTjrE9oh7AeffO6/RNHZ9Zw/sfU4teAhHE9SUohVhMWf/OYf3sqTvdDOkHnQ1LqYP8NQbQHUfd+g6IsSfi8NFpKOB0MrSjnfybr7pOBTdtCXJeyzCj/Pkgxj+JdpbbhZEkKMlA1ja/hCLmTajuTSDoQ2pj2XjL+seeFt3+r1Bsels4dKUD47z0gafH37em6+8cLmp0wdDyi7l65kY3ya5MxQO6/SA6BDFo2kzDhlQKo8BpBxbcTM15eT8NuHksINWYYZ3LQpAkjlUfZZvAm1sl/BTZsKoaW5hPlUf3Vliam/SJJ7TtjLOjlhBbKXpkI7j+rvD2ykbdFo30MIkOdrCUAQ5JOhKlJDlD2b74ZTSs1j9Sf25qX3NrowqwmCEvScyhbrIF/PSX9ZmMIJT82Jy2EP2m94C2UxoBgn2h/3t6GlW7LPvbVNtIg4AXZ3QiOkQflF8oMf4TqamKDebmjOVzNm/eez5XDBiS590u8hsr1B/syB3eNbHjnao36AJP1s4orV1YWebH84iCcNL0mAryypEluPwL62g9rUf+ugyKRZLmYZn55f38X0BJiMRgXGVq9otk6hJdl+EwmLAAQxxSL8oRTp+VWOFZeXvzRrE8L0w3/BB8Pc/VE82MZfD9sO9ocwDMGNlHYY0oJJ+BkiwiqhMYggoMSoO2lT9a4iBs/1QRKKIGQrhL/WkwCU3jF/+J7CJDb81DzhYa1GsmYN/aYlPkNouNIJNuun0yAuBNU9kqVnz/uSiZ0tSbUjttW8clX1NcyOHFkxSfxtM9D4/F+0sfNkp82e0PCQB690g1G47GqLn3OY5UnPhtSA2Qrug4AzA6ttdmChyCWlJpxuyYlo1aCtUtS46U1VvM9mk1RiPZLNN9+yKdNYHF6tlfjEJ9MU9dvm3Cg8XibIVpQyuQXqcnbZIqG+OcW+l6eaG7bDHOgSsL+x796pHdy/QTOSx+lDFp/VSJZSDlwG0qM+lJOwWpCmDUbm4zfAYFGYB8V23e4CYxgJzRVpuVtUa4wyeVNdmg0uaH3vLI/dRvOgTEG3PH/uKEq/72r8D8U1AB2QEVX68IpP2nXQZ0lWT/DFGGzIPXK3Wtg0peHQjQgMZM4u844FErA0sKY3/bTt7M0JBABpgIQjU/w8NxhdNogGBGCvVhDTEIslNWUVd1WbFU25DR6If7kx0tzrndb/7bzU+mIG5NHvxHnpJ/W1FZk5KtF2pI6+VJtkg== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230035)(376009)(7416009)(1800799019)(82310400021)(36860700008);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jun 2024 16:20:48.4085 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be1a647e-7164-4220-bc94-08dc8bc4c937 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7898 X-Patchwork-Delegate: kuba@kernel.org Expose the sysfs files for the IRQs that the mlx5 PCI SFs are using. These entries are similar to PCI PFs and VFs in 'msi_irqs' directory. Reviewed-by: Parav Pandit Signed-off-by: Shay Drory --- v5->v6: - fail IRQ creation in case auxiliary_device_sysfs_irq_add() failed (Parav and Przemek) v2->v3: - fix mlx5 sfnum SF sysfs --- drivers/net/ethernet/mellanox/mlx5/core/eq.c | 6 +++--- .../ethernet/mellanox/mlx5/core/irq_affinity.c | 18 +++++++++++++++++- .../ethernet/mellanox/mlx5/core/mlx5_core.h | 6 ++++++ .../net/ethernet/mellanox/mlx5/core/mlx5_irq.h | 12 ++++++++---- .../net/ethernet/mellanox/mlx5/core/pci_irq.c | 12 +++++++++--- .../ethernet/mellanox/mlx5/core/sf/dev/dev.c | 16 +++++++--------- 6 files changed, 50 insertions(+), 20 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c index 5693986ae656..5661f047702e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c @@ -714,7 +714,7 @@ static int create_async_eqs(struct mlx5_core_dev *dev) err1: mlx5_cmd_allowed_opcode(dev, CMD_ALLOWED_OPCODE_ALL); mlx5_eq_notifier_unregister(dev, &table->cq_err_nb); - mlx5_ctrl_irq_release(table->ctrl_irq); + mlx5_ctrl_irq_release(dev, table->ctrl_irq); return err; } @@ -730,7 +730,7 @@ static void destroy_async_eqs(struct mlx5_core_dev *dev) cleanup_async_eq(dev, &table->cmd_eq, "cmd"); mlx5_cmd_allowed_opcode(dev, CMD_ALLOWED_OPCODE_ALL); mlx5_eq_notifier_unregister(dev, &table->cq_err_nb); - mlx5_ctrl_irq_release(table->ctrl_irq); + mlx5_ctrl_irq_release(dev, table->ctrl_irq); } struct mlx5_eq *mlx5_get_async_eq(struct mlx5_core_dev *dev) @@ -918,7 +918,7 @@ static int comp_irq_request_sf(struct mlx5_core_dev *dev, u16 vecidx) af_desc.is_managed = 1; cpumask_copy(&af_desc.mask, cpu_online_mask); cpumask_andnot(&af_desc.mask, &af_desc.mask, &table->used_cpus); - irq = mlx5_irq_affinity_request(pool, &af_desc); + irq = mlx5_irq_affinity_request(dev, pool, &af_desc); if (IS_ERR(irq)) return PTR_ERR(irq); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c b/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c index 612e666ec263..f7b01b3f0cba 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/irq_affinity.c @@ -112,15 +112,18 @@ irq_pool_find_least_loaded(struct mlx5_irq_pool *pool, const struct cpumask *req /** * mlx5_irq_affinity_request - request an IRQ according to the given mask. + * @dev: mlx5 core device which is requesting the IRQ. * @pool: IRQ pool to request from. * @af_desc: affinity descriptor for this IRQ. * * This function returns a pointer to IRQ, or ERR_PTR in case of error. */ struct mlx5_irq * -mlx5_irq_affinity_request(struct mlx5_irq_pool *pool, struct irq_affinity_desc *af_desc) +mlx5_irq_affinity_request(struct mlx5_core_dev *dev, struct mlx5_irq_pool *pool, + struct irq_affinity_desc *af_desc) { struct mlx5_irq *least_loaded_irq, *new_irq; + int ret; mutex_lock(&pool->lock); least_loaded_irq = irq_pool_find_least_loaded(pool, &af_desc->mask); @@ -153,6 +156,16 @@ mlx5_irq_affinity_request(struct mlx5_irq_pool *pool, struct irq_affinity_desc * mlx5_irq_read_locked(least_loaded_irq) / MLX5_EQ_REFS_PER_IRQ); unlock: mutex_unlock(&pool->lock); + if (mlx5_irq_pool_is_sf_pool(pool)) { + ret = auxiliary_device_sysfs_irq_add(mlx5_sf_coredev_to_adev(dev), + mlx5_irq_get_irq(least_loaded_irq)); + if (ret) { + mlx5_core_err(dev, "Failed to create sysfs entry for irq %d, ret = %d\n", + mlx5_irq_get_irq(least_loaded_irq), ret); + mlx5_irq_put(least_loaded_irq); + least_loaded_irq = ERR_PTR(ret); + } + } return least_loaded_irq; } @@ -164,6 +177,9 @@ void mlx5_irq_affinity_irq_release(struct mlx5_core_dev *dev, struct mlx5_irq *i cpu = cpumask_first(mlx5_irq_get_affinity_mask(irq)); synchronize_irq(pci_irq_vector(pool->dev->pdev, mlx5_irq_get_index(irq))); + if (mlx5_irq_pool_is_sf_pool(pool)) + auxiliary_device_sysfs_irq_remove(mlx5_sf_coredev_to_adev(dev), + mlx5_irq_get_irq(irq)); if (mlx5_irq_put(irq)) if (pool->irqs_per_cpu) cpu_put(pool, cpu); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h index c38342b9f320..e764b720d9b2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -320,6 +320,12 @@ static inline bool mlx5_core_is_sf(const struct mlx5_core_dev *dev) return dev->coredev_type == MLX5_COREDEV_SF; } +static inline struct auxiliary_device * +mlx5_sf_coredev_to_adev(struct mlx5_core_dev *mdev) +{ + return container_of(mdev->device, struct auxiliary_device, dev); +} + int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx); void mlx5_mdev_uninit(struct mlx5_core_dev *dev); int mlx5_init_one(struct mlx5_core_dev *dev); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_irq.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_irq.h index 1088114e905d..0881e961d8b1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_irq.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_irq.h @@ -25,7 +25,7 @@ int mlx5_set_msix_vec_count(struct mlx5_core_dev *dev, int devfn, int mlx5_get_default_msix_vec_count(struct mlx5_core_dev *dev, int num_vfs); struct mlx5_irq *mlx5_ctrl_irq_request(struct mlx5_core_dev *dev); -void mlx5_ctrl_irq_release(struct mlx5_irq *ctrl_irq); +void mlx5_ctrl_irq_release(struct mlx5_core_dev *dev, struct mlx5_irq *ctrl_irq); struct mlx5_irq *mlx5_irq_request(struct mlx5_core_dev *dev, u16 vecidx, struct irq_affinity_desc *af_desc, struct cpu_rmap **rmap); @@ -36,13 +36,15 @@ int mlx5_irq_attach_nb(struct mlx5_irq *irq, struct notifier_block *nb); int mlx5_irq_detach_nb(struct mlx5_irq *irq, struct notifier_block *nb); struct cpumask *mlx5_irq_get_affinity_mask(struct mlx5_irq *irq); int mlx5_irq_get_index(struct mlx5_irq *irq); +int mlx5_irq_get_irq(const struct mlx5_irq *irq); struct mlx5_irq_pool; #ifdef CONFIG_MLX5_SF struct mlx5_irq *mlx5_irq_affinity_irq_request_auto(struct mlx5_core_dev *dev, struct cpumask *used_cpus, u16 vecidx); -struct mlx5_irq *mlx5_irq_affinity_request(struct mlx5_irq_pool *pool, - struct irq_affinity_desc *af_desc); +struct mlx5_irq * +mlx5_irq_affinity_request(struct mlx5_core_dev *dev, struct mlx5_irq_pool *pool, + struct irq_affinity_desc *af_desc); void mlx5_irq_affinity_irq_release(struct mlx5_core_dev *dev, struct mlx5_irq *irq); #else static inline @@ -53,7 +55,8 @@ struct mlx5_irq *mlx5_irq_affinity_irq_request_auto(struct mlx5_core_dev *dev, } static inline struct mlx5_irq * -mlx5_irq_affinity_request(struct mlx5_irq_pool *pool, struct irq_affinity_desc *af_desc) +mlx5_irq_affinity_request(struct mlx5_core_dev *dev, struct mlx5_irq_pool *pool, + struct irq_affinity_desc *af_desc) { return ERR_PTR(-EOPNOTSUPP); } @@ -61,6 +64,7 @@ mlx5_irq_affinity_request(struct mlx5_irq_pool *pool, struct irq_affinity_desc * static inline void mlx5_irq_affinity_irq_release(struct mlx5_core_dev *dev, struct mlx5_irq *irq) { + mlx5_irq_release_vector(irq); } #endif #endif /* __MLX5_IRQ_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c index fb8787e30d3f..ac7c3a76b4cf 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c @@ -367,6 +367,11 @@ struct cpumask *mlx5_irq_get_affinity_mask(struct mlx5_irq *irq) return irq->mask; } +int mlx5_irq_get_irq(const struct mlx5_irq *irq) +{ + return irq->map.virq; +} + int mlx5_irq_get_index(struct mlx5_irq *irq) { return irq->map.index; @@ -440,11 +445,12 @@ static void _mlx5_irq_release(struct mlx5_irq *irq) /** * mlx5_ctrl_irq_release - release a ctrl IRQ back to the system. + * @dev: mlx5 device that releasing the IRQ. * @ctrl_irq: ctrl IRQ to be released. */ -void mlx5_ctrl_irq_release(struct mlx5_irq *ctrl_irq) +void mlx5_ctrl_irq_release(struct mlx5_core_dev *dev, struct mlx5_irq *ctrl_irq) { - _mlx5_irq_release(ctrl_irq); + mlx5_irq_affinity_irq_release(dev, ctrl_irq); } /** @@ -473,7 +479,7 @@ struct mlx5_irq *mlx5_ctrl_irq_request(struct mlx5_core_dev *dev) /* Allocate the IRQ in index 0. The vector was already allocated */ irq = irq_pool_request_vector(pool, 0, &af_desc, NULL); } else { - irq = mlx5_irq_affinity_request(pool, &af_desc); + irq = mlx5_irq_affinity_request(dev, pool, &af_desc); } return irq; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.c b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.c index 99219ea52c4b..27dfa56c27db 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.c @@ -60,11 +60,6 @@ static const struct attribute_group sf_attr_group = { .attrs = sf_device_attrs, }; -static const struct attribute_group *sf_attr_groups[2] = { - &sf_attr_group, - NULL -}; - static void mlx5_sf_dev_release(struct device *device) { struct auxiliary_device *adev = container_of(device, struct auxiliary_device, dev); @@ -111,7 +106,6 @@ static void mlx5_sf_dev_add(struct mlx5_core_dev *dev, u16 sf_index, u16 fn_id, sf_dev->adev.name = MLX5_SF_DEV_ID_NAME; sf_dev->adev.dev.release = mlx5_sf_dev_release; sf_dev->adev.dev.parent = &pdev->dev; - sf_dev->adev.dev.groups = sf_attr_groups; sf_dev->sfnum = sfnum; sf_dev->parent_mdev = dev; sf_dev->fn_id = fn_id; @@ -127,18 +121,22 @@ static void mlx5_sf_dev_add(struct mlx5_core_dev *dev, u16 sf_index, u16 fn_id, goto add_err; } - err = auxiliary_device_add(&sf_dev->adev); + err = auxiliary_device_add_with_irqs(&sf_dev->adev); if (err) { auxiliary_device_uninit(&sf_dev->adev); goto add_err; } + err = devm_device_add_group(&sf_dev->adev.dev, &sf_attr_group); + if (err) + goto add_group_err; + err = xa_insert(&table->devices, sf_index, sf_dev, GFP_KERNEL); if (err) - goto xa_err; + goto add_group_err; return; -xa_err: +add_group_err: mlx5_sf_dev_remove_aux(dev, sf_dev); add_err: mlx5_core_err(dev, "SF DEV: fail device add for index=%d sfnum=%d err=%d\n",