From patchwork Sat Jun 15 08:15:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13699243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00268C27C4F for ; Sat, 15 Jun 2024 08:16:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=A8rt51C5aTHmQ/FVzZRM4ATnvo2alvUHzxR40z95+Ak=; b=bqSXcjOzAsPXJdN6VxbWVoE6Cg 7dOuC14wvdFFPHKp0Lf64TKsl0Ub41qTCusxFtNuLWk2O4dLP7/awl7lO4znBAZ6H8Qz4Am2aKD8y dpoxTSOZiZX6vQMVrNmNasiIk6C2V9cB9pgJlJGFxkxn34U/KwKwUKep/9dGqouyvmJLRMKm1xMRw A9NSIEGTgC8QSaT4gTra/qSj7ZwxnsuAbPU5yllhinpcfH6PI6syHEYDjFQD1tB3BlwVYPlOi+fXi lnOYISdGDHYitN30hlzPbZYM2/LIdkOT+Cx29d7MGwc/cR+XB7AV/691mxKw/nyOUmwvb0o88ZrLj ByTfaEVA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOaC-00000004yyY-3UaC; Sat, 15 Jun 2024 08:16:20 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOa7-00000004yxF-2OBV for linux-arm-kernel@lists.infradead.org; Sat, 15 Jun 2024 08:16:17 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45F8GAuP069665; Sat, 15 Jun 2024 03:16:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718439370; bh=A8rt51C5aTHmQ/FVzZRM4ATnvo2alvUHzxR40z95+Ak=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=P1WFzETprRFG35pRcAM0kRLtGYqdUh9Rcu+e7Z3rklgBpD7ygKPk6AqP90TtstB0G D3vPgDqHvgbILxgu1MwtsRzkpq7zBYhyeT8udo4Ucg78rtSCYihVATag7dYfNi9M4R 1bPcr4JNBey9hSqCTeGqEPDm33kYQutKRBt5FxzQ= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45F8GAOM078410 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 15 Jun 2024 03:16:10 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 15 Jun 2024 03:16:10 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 15 Jun 2024 03:16:10 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45F8G1QV024463; Sat, 15 Jun 2024 03:16:06 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v7 1/8] arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi Date: Sat, 15 Jun 2024 13:45:53 +0530 Message-ID: <20240615081600.3602462-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240615081600.3602462-1-s-vadapalli@ti.com> References: <20240615081600.3602462-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240615_011615_734145_2F681948 X-CRM114-Status: UNSURE ( 9.88 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The AM62P and J722S SoCs share most of the peripherals. With the aim of reusing the existing k3-am62p-{mcu,main,thermal,wakeup}.dtsi files for J722S SoC, rename them to indicate that they are shared with the J722S SoC. The peripherals that are not shared will be moved in the upcoming patches to the respective k3-{soc}-{mcu,main,wakeup}.dtsi files without "common" in the filename, emphasizing that they are not shared. Signed-off-by: Siddharth Vadapalli Acked-by: Andrew Davis Acked-by: Roger Quadros --- v6: https://lore.kernel.org/r/20240612132409.2477888-2-s-vadapalli@ti.com/ Changes since v6: - Collected Acked-by tag from Roger Quadros ...k3-am62p-main.dtsi => k3-am62p-j722s-common-main.dtsi} | 3 ++- .../{k3-am62p-mcu.dtsi => k3-am62p-j722s-common-mcu.dtsi} | 3 ++- ...2p-thermal.dtsi => k3-am62p-j722s-common-thermal.dtsi} | 0 ...m62p-wakeup.dtsi => k3-am62p-j722s-common-wakeup.dtsi} | 3 ++- arch/arm64/boot/dts/ti/k3-am62p.dtsi | 8 ++++---- 5 files changed, 10 insertions(+), 7 deletions(-) rename arch/arm64/boot/dts/ti/{k3-am62p-main.dtsi => k3-am62p-j722s-common-main.dtsi} (99%) rename arch/arm64/boot/dts/ti/{k3-am62p-mcu.dtsi => k3-am62p-j722s-common-mcu.dtsi} (98%) rename arch/arm64/boot/dts/ti/{k3-am62p-thermal.dtsi => k3-am62p-j722s-common-thermal.dtsi} (100%) rename arch/arm64/boot/dts/ti/{k3-am62p-wakeup.dtsi => k3-am62p-j722s-common-wakeup.dtsi} (97%) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi similarity index 99% rename from arch/arm64/boot/dts/ti/k3-am62p-main.dtsi rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index eed06506f617..ff97e4a59e3b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Device Tree file for the AM62P main domain peripherals + * Device Tree file for the MAIN domain peripherals shared by AM62P and J722S + * * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ diff --git a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi similarity index 98% rename from arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi index b973b550eb9d..1d4e5fc8b4e0 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Device Tree file for the AM62P MCU domain peripherals + * Device Tree file for the MCU domain peripherals shared by AM62P and J722S + * * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ diff --git a/arch/arm64/boot/dts/ti/k3-am62p-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-thermal.dtsi similarity index 100% rename from arch/arm64/boot/dts/ti/k3-am62p-thermal.dtsi rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-thermal.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi similarity index 97% rename from arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi index 71784e10b4f1..315d0092e736 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only OR MIT /* - * Device Tree file for the AM62P wakeup domain peripherals + * Device Tree file for the WAKEUP domain peripherals shared by AM62P and J722S + * * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi index 94babc412575..2d11c80107b5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -116,10 +116,10 @@ cbass_wakeup: bus@b00000 { }; }; - #include "k3-am62p-thermal.dtsi" + #include "k3-am62p-j722s-common-thermal.dtsi" }; /* Now include peripherals for each bus segment */ -#include "k3-am62p-main.dtsi" -#include "k3-am62p-mcu.dtsi" -#include "k3-am62p-wakeup.dtsi" +#include "k3-am62p-j722s-common-main.dtsi" +#include "k3-am62p-j722s-common-mcu.dtsi" +#include "k3-am62p-j722s-common-wakeup.dtsi" From patchwork Sat Jun 15 08:15:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13699245 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00626C2BA12 for ; Sat, 15 Jun 2024 08:16:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Q3U5k6GG52V0GJuK2Hqmuiq5GKnG0BK75tPCOVYvyHQ=; b=Bt7r5npqVhKzs+MlbWelDH5bGJ F/dUsp3lqB3ffZyz5Q2P8mIQjTrwfDpPL2fLdwMFmTLaA58jwPxXh0H07U41o4MJZW431cwcreaVI G+CnQPgMx3z086Ov1B+JH6GpqPCn8UvaXphvAdDF/vTuke/RODsXwqfU6PZEqKIMy9HzMKIDXc8Gd pf2Ol1aXLPVu2f8y+GS0qXW2wGPSX9zJhrZTXm4InaC1CAzNyvgYadD7dsALiEw7kkSr1H8JNX3ws 5dWmKkYKZi/g9YgUUKhKgSql8WvCPFSLu2GvYymqDZ7366hPuEBJYHLcaGTGT8gPrRjGz37fyxJNj 8P6y/Ogw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOaI-00000004z0f-2exD; Sat, 15 Jun 2024 08:16:26 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOaA-00000004yy2-2s6S for linux-arm-kernel@lists.infradead.org; Sat, 15 Jun 2024 08:16:20 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45F8GFsF108560; Sat, 15 Jun 2024 03:16:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718439375; bh=Q3U5k6GG52V0GJuK2Hqmuiq5GKnG0BK75tPCOVYvyHQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bjJUzJklJ8WDb91u5LB10DAFNWbCstcIz3RrCMId5NyM5+cMM/tAx1xFyda67oYhE ZuR7MgYy0eM/QGV6PPlVqQvYfweJd8CTvU7i7uXtdLj07l/toR2SHv5hy8c0T/gbrB dWqgNeF6OceRb2XN0vvD1tNl61st3wK8DKEdw6+c= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45F8GFkM063833 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 15 Jun 2024 03:16:15 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 15 Jun 2024 03:16:14 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 15 Jun 2024 03:16:14 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45F8G1QW024463; Sat, 15 Jun 2024 03:16:10 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v7 2/8] arm64: dts: ti: k3-am62p-j722s: Move AM62P specific USB1 to am62p-main.dtsi Date: Sat, 15 Jun 2024 13:45:54 +0530 Message-ID: <20240615081600.3602462-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240615081600.3602462-1-s-vadapalli@ti.com> References: <20240615081600.3602462-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240615_011618_834180_3BC0CA89 X-CRM114-Status: GOOD ( 14.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The USB1 instance of USB controller on AM62P is different from the USB1 instance of USB controller on J722S. Thus, move the USB1 instance from the shared "k3-am62p-j722s-common-main.dtsi" file to the AM62p specific "k3-am62p-main.dtsi" file. Include "k3-am62p-main.dtsi" in "k3-am62p.dtsi". Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros --- v6: https://lore.kernel.org/r/20240612132409.2477888-3-s-vadapalli@ti.com/ No changes since v6. .../dts/ti/k3-am62p-j722s-common-main.dtsi | 26 -------------- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 34 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62p.dtsi | 3 ++ 3 files changed, 37 insertions(+), 26 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index ff97e4a59e3b..870c95081ef5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -662,32 +662,6 @@ usb0: usb@31000000 { }; }; - usbss1: usb@f910000 { - compatible = "ti,am62-usb"; - reg = <0x00 0x0f910000 0x00 0x800>, - <0x00 0x0f918000 0x00 0x400>; - clocks = <&k3_clks 162 3>; - clock-names = "ref"; - ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; - #address-cells = <2>; - #size-cells = <2>; - power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; - ranges; - status = "disabled"; - - usb1: usb@31100000 { - compatible = "snps,dwc3"; - reg = <0x00 0x31100000 0x00 0x50000>; - interrupts = , /* irq.0 */ - ; /* irq.0 */ - interrupt-names = "host", "peripheral"; - maximum-speed = "high-speed"; - dr_mode = "otg"; - snps,usb2-gadget-lpm-disable; - snps,usb2-lpm-disable; - }; - }; - fss: bus@fc00000 { compatible = "simple-bus"; reg = <0x00 0x0fc00000 0x00 0x70000>; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi new file mode 100644 index 000000000000..9caab7db5440 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree file for the AM62P MAIN domain peripherals + * + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + usbss1: usb@f910000 { + compatible = "ti,am62-usb"; + reg = <0x00 0x0f910000 0x00 0x800>, + <0x00 0x0f918000 0x00 0x400>; + clocks = <&k3_clks 162 3>; + clock-names = "ref"; + ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + ranges; + status = "disabled"; + + usb1: usb@31100000 { + compatible = "snps,dwc3"; + reg = <0x00 0x31100000 0x00 0x50000>; + interrupts = , /* irq.0 */ + ; /* irq.0 */ + interrupt-names = "host", "peripheral"; + maximum-speed = "high-speed"; + dr_mode = "otg"; + snps,usb2-gadget-lpm-disable; + snps,usb2-lpm-disable; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi index 2d11c80107b5..75a15c368c11 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -123,3 +123,6 @@ cbass_wakeup: bus@b00000 { #include "k3-am62p-j722s-common-main.dtsi" #include "k3-am62p-j722s-common-mcu.dtsi" #include "k3-am62p-j722s-common-wakeup.dtsi" + +/* Include AM62P specific peripherals */ +#include "k3-am62p-main.dtsi" From patchwork Sat Jun 15 08:15:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13699244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B95DC27C4F for ; Sat, 15 Jun 2024 08:16:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=/nMNn/Q9Pl1TR9MHJwmz0h5ZACHUGbgRIKUcIWqHir4=; b=03yf7sNIvs42kyPKiPdreqGdip PlTN7VdWf8ka1imIqT9OKsIXRFB53MWDCI5zsnYcIgW/tbUpVzXx940LXtvwFcGJkRGT6ScEWe4AI iQRCVzMYYRZZtMEEkov1Vy/CVK+7hZ0thhqeOfvntUX+zHF/nOIClm8mhbMLic6jT8D/gyRw0yyR9 xVxDtHPM7Q6B0WDW4KJQTIHI1f5uq+Tyf/Z7DkoanAaMJwFLq/IkW7Zy628p4/LZPDRk8evyhfznP nv/NlhkSiU9vBsq6A80YeRKIq9TR6lQ4kRjwBe+FWNuSssR1X04SU+wY3Qi3np18Z2A/kt0Px4vkj bEJIMFKw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOaJ-00000004z1J-20FZ; Sat, 15 Jun 2024 08:16:27 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOaD-00000004yyw-47rF for linux-arm-kernel@lists.infradead.org; Sat, 15 Jun 2024 08:16:23 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45F8GJel052871; Sat, 15 Jun 2024 03:16:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718439379; bh=/nMNn/Q9Pl1TR9MHJwmz0h5ZACHUGbgRIKUcIWqHir4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=QCLyKXMc61rUpmxfc1qvlwSlQHF5vtqeUwQUuUUM5Aw0l+rJDpTOLM0BGYrB+FnBc 64d5DI9ftxI58cAMim26NI5TzPOoUTnwOCMTEj3IsSLYAOM5Bz1wcdmFxZ1ToR+S3h E/6p7SqApD0Xqu1T3VZhsZaDQyWeYeEAaPSR3Lz0= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45F8GJP8063852 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 15 Jun 2024 03:16:19 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 15 Jun 2024 03:16:18 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 15 Jun 2024 03:16:19 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45F8G1QX024463; Sat, 15 Jun 2024 03:16:15 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v7 3/8] arm64: dts: ti: k3-j722s: Add main domain peripherals specific to J722S Date: Sat, 15 Jun 2024 13:45:55 +0530 Message-ID: <20240615081600.3602462-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240615081600.3602462-1-s-vadapalli@ti.com> References: <20240615081600.3602462-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240615_011622_158601_1FC17F52 X-CRM114-Status: GOOD ( 13.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce the "k3-j722s-main.dtsi" file to contain main domain peripherals that are specific to J722S SoC and are not shared with AM62P. The USB1 instance of the USB controller on J722S is different from that on AM62P. Thus, add the USB1 node in "k3-j722s-main.dtsi". Co-developed-by: Ravi Gunasekaran Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros --- v6: https://lore.kernel.org/r/20240612132409.2477888-4-s-vadapalli@ti.com/ No changes since v6. arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 40 +++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi new file mode 100644 index 000000000000..84378fc839d6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Device Tree file for the J722S MAIN domain peripherals + * + * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + usbss1: usb@f920000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x0f920000 0x00 0x100>; + power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 278 3>, <&k3_clks 278 1>; + clock-names = "ref", "lpm"; + assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */ + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb1: usb@31200000{ + compatible = "cdns,usb3"; + reg = <0x00 0x31200000 0x00 0x10000>, + <0x00 0x31210000 0x00 0x10000>, + <0x00 0x31220000 0x00 0x10000>; + reg-names = "otg", + "xhci", + "dev"; + interrupts = , /* irq.0 */ + , /* irq.6 */ + ; /* otgirq */ + interrupt-names = "host", + "peripheral", + "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; +}; From patchwork Sat Jun 15 08:15:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13699247 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11E00C2BA12 for ; Sat, 15 Jun 2024 08:16:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=oWCAyJiUbdmOaB8n1cIRjfNO6l/uRaCqWw+L8h3apJg=; b=S7Jb/rByh82qadzQZcpIKeLz7O gnrlNdu2sIfRnyhJ3bqDzbOj7TQ/U+n2ULU3Ridq+LooyTv0xquLudpDLL6Xhha4jChsmCkBFi012 NlXGqSFvTc3pVKy4QsdF0TJxVxMmL4BjbX3Lap1FP2K18EVowaTqa673k3+hpg4eV7NTOoY6yBoqb FZMH1S91bhp1pjDZsemRfkxdNcPEWXfV4EuBjbk6ebUi1ML9iLoBujMsSbDFFHqOijuHEfYUTKpIH C7N+ZbR386nfgmfPO+yl2ftdIH6lw8wzCy9ERC9MhlCDt0xMuzu0lazUbMFs8UwSr/SOOVNMr8lD7 SNsPo9Yg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOaX-00000004zAN-0hp8; Sat, 15 Jun 2024 08:16:41 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOaI-00000004z0U-1cEd for linux-arm-kernel@lists.infradead.org; Sat, 15 Jun 2024 08:16:28 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45F8GNa1069716; Sat, 15 Jun 2024 03:16:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718439383; bh=oWCAyJiUbdmOaB8n1cIRjfNO6l/uRaCqWw+L8h3apJg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=yxRioMUw+DGI8+Li5FNrbHqQ8VvbGGhMlCXgNfarteXO3byoT8/MFoZ+9f6QUq1jb htsVaUMXnZNhqKtaVdinEALP/aponHP+KCJd00hBVQk81ZhLXYHANyKPRtXMxbcFny LBgXhGOjEoKMM9uteVlc0ZjJB4jszEfsFp85zETE= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45F8GNdF032317 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 15 Jun 2024 03:16:23 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 15 Jun 2024 03:16:23 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 15 Jun 2024 03:16:23 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45F8G1QY024463; Sat, 15 Jun 2024 03:16:19 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v7 4/8] arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common-{}.dtsi includes Date: Sat, 15 Jun 2024 13:45:56 +0530 Message-ID: <20240615081600.3602462-5-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240615081600.3602462-1-s-vadapalli@ti.com> References: <20240615081600.3602462-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240615_011626_544807_06FCEB54 X-CRM114-Status: GOOD ( 12.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Update "k3-j722s.dtsi" to include "k3-am62p-j722s-common-{}".dtsi files in order to reuse the nodes shared with AM62P. Also include the J722S specific "k3-j722s-main.dtsi". Since the J7 family of SoCs has the k3-{soc}.dtsi file organized as: k3-{soc}.dtsi = CPU + Cache + CBASS-Ranges + "Peripheral-Includes" switch the "k3-j722s.dtsi" file to the same convention. Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros --- v6: https://lore.kernel.org/r/20240612132409.2477888-5-s-vadapalli@ti.com/ Changes since v6: - Collected Acked-by tag from Roger Quadros arch/arm64/boot/dts/ti/k3-j722s.dtsi | 158 ++++++++++++++++++++++++++- 1 file changed, 157 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi index 9132b0232b0b..705b99e35f05 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -10,11 +10,133 @@ #include #include -#include "k3-am62p5.dtsi" +#include "k3-pinctrl.h" / { model = "Texas Instruments K3 J722S SoC"; compatible = "ti,j722s"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 135 0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 136 0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 137 0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 138 0>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; cbass_main: bus@f0000 { compatible = "simple-bus"; @@ -74,9 +196,43 @@ cbass_main: bus@f0000 { <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; + + cbass_mcu: bus@4000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */ + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */ + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */ + bootph-all; + }; + + cbass_wakeup: bus@b00000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */ + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ + bootph-all; + }; }; + + #include "k3-am62p-j722s-common-thermal.dtsi" }; +/* Include peripherals shared with AM62P */ +#include "k3-am62p-j722s-common-main.dtsi" +#include "k3-am62p-j722s-common-mcu.dtsi" +#include "k3-am62p-j722s-common-wakeup.dtsi" + +/* Include J722S specific peripherals */ +#include "k3-j722s-main.dtsi" + /* Main domain overrides */ &inta_main_dmss { From patchwork Sat Jun 15 08:15:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13699248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8FAF4C27C53 for ; Sat, 15 Jun 2024 08:16:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ToP5EKkVGa1u0JhGEFQvR0WDOaWbVtUSajWl2oNi+AY=; b=PDqPbouxdvEJcsA4yEY/EEYmlp eSMxKs53KeHKN2zcxgc8LjV5HF8uVfo8rVhbG+9rHvUzZ2n6R/VQf4BRJMm/9H7XM0tIYbhn9Yoil zCQCBFL95RSFEn5G+zmwZ1KUrryCJUns76gW342APYmCgW8fYd38p4VhSJuLbwS/eiwRwxyioS9qi UwQI2lWv8wXmPOM5R/xA3j/NLto26MdGV4amlVDyh/oUnTEedLeWv0m+/ZfMhXpXD1gz8wHuGFBja imZqvajgLtHUzsgRRczUVLjSVNI1rNi4wqxRIe2fC5ano2DZlk/v1syVrYMhgB2bqRp0itP6gMg6R MVANj4NA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOab-00000004zD9-0rx1; Sat, 15 Jun 2024 08:16:45 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOaT-00000004z7L-0dYI for linux-arm-kernel@lists.infradead.org; Sat, 15 Jun 2024 08:16:38 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45F8GSPU102747; Sat, 15 Jun 2024 03:16:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718439388; bh=ToP5EKkVGa1u0JhGEFQvR0WDOaWbVtUSajWl2oNi+AY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lnqYIkkCZ2qbWhWBtGWK8YtyvYuNl0AKhwbVx+PKwMntSU7fw1LMi0S/UqgI2YrBA KVB+ap587R+rZnndBv0UzjglzkQUbeifBBHgbmR8Grbpm/COGnmv/K4W8O+LNj30wZ uAlsi5Z0+pxU3OgEat5+6+BJZOCd2sFJz1uxSTo8= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45F8GSvm084490 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 15 Jun 2024 03:16:28 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 15 Jun 2024 03:16:27 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 15 Jun 2024 03:16:27 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45F8G1QZ024463; Sat, 15 Jun 2024 03:16:23 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v7 5/8] arm64: dts: ti: k3-serdes: Add SERDES0/SERDES1 lane-muxing macros for J722S Date: Sat, 15 Jun 2024 13:45:57 +0530 Message-ID: <20240615081600.3602462-6-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240615081600.3602462-1-s-vadapalli@ti.com> References: <20240615081600.3602462-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240615_011637_338737_39798902 X-CRM114-Status: UNSURE ( 9.57 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The SERDES0 and SERDES1 instances of SERDES on J722S are single lane SERDES which are individually muxed across different peripherals. LANE0 of SERDES0 is muxed between USB and CPSW while LANE0 of SERDES1 is muxed between PCIe and CPSW. Define the lane-muxing macros to be used as the idle state values. Co-developed-by: Ravi Gunasekaran Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli Reviewed-by: Roger Quadros --- v6: https://lore.kernel.org/r/20240612132409.2477888-7-s-vadapalli@ti.com/ No changes since v6. arch/arm64/boot/dts/ti/k3-serdes.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h index a011ad893b44..ef3606068140 100644 --- a/arch/arm64/boot/dts/ti/k3-serdes.h +++ b/arch/arm64/boot/dts/ti/k3-serdes.h @@ -201,4 +201,12 @@ #define J784S4_SERDES4_LANE3_USB 0x2 #define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3 +/* J722S */ + +#define J722S_SERDES0_LANE0_USB 0x0 +#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1 + +#define J722S_SERDES1_LANE0_PCIE0_LANE0 0x0 +#define J722S_SERDES1_LANE0_QSGMII_LANE1 0x1 + #endif /* DTS_ARM64_TI_K3_SERDES_H */ From patchwork Sat Jun 15 08:15:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13699246 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A50D1C27C4F for ; Sat, 15 Jun 2024 08:16:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=cOGfn+WQ9Qkc1II1QmjpQH+0HgchFr0QbwsNxHccKo4=; b=ZJt5V4H4GxMbUAK582yMLNH02d fHGFCuLlogyu/+xs2HVJFy1LdxS31y9ONhG/R40v2J8Q3ALVbWwd+uDoGkTEsvFkzFLzfub2oxqfk ySxUhud1bxXeLLdq8cdBMufqjbKIEPACUwVA82YPS5mCZEUyqYAFInWSGEiBLB9mNO0qXPzJbjiZi xF0Qj003pqX1CoBwpKKbXmXIawcW1QpG8/RYtf//03xuciWuMmthIbpHmp5Kd+i6wGvoDd4WCXR8i Fnttn/VFk8ji27iQPMY7biF1pW7CuIEYVDTaigxG7aXY/0l49/htnonqStmvWnpsWY9JBLmcfSrVf xDr/UzuA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOaY-00000004zB9-0hra; Sat, 15 Jun 2024 08:16:42 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOaR-00000004z60-0nXi for linux-arm-kernel@lists.infradead.org; Sat, 15 Jun 2024 08:16:37 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45F8GWgt052896; Sat, 15 Jun 2024 03:16:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718439392; bh=cOGfn+WQ9Qkc1II1QmjpQH+0HgchFr0QbwsNxHccKo4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jljXnzFNl79WoGFr7yI5mVNI99AgoLE5icpq6dd16ICD/azuUQjV4dBi5iXXMlx0C 5cwXhrtfdW2S/578aeBqcnm+6ZTAlzpbPCBHl6wWA5Uz0S0YqU6SJiU0PWLF8HwLPA kZxRiNOzq3cQux2JrAimkbR4mcOStHGAyJ0jLtPg= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45F8GWIj084509 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 15 Jun 2024 03:16:32 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 15 Jun 2024 03:16:31 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 15 Jun 2024 03:16:32 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45F8G1Qa024463; Sat, 15 Jun 2024 03:16:28 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v7 6/8] arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe support Date: Sat, 15 Jun 2024 13:45:58 +0530 Message-ID: <20240615081600.3602462-7-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240615081600.3602462-1-s-vadapalli@ti.com> References: <20240615081600.3602462-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240615_011635_500323_88E107C6 X-CRM114-Status: GOOD ( 10.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org J722S SoC has two instances of SERDES namely SERDES0 and SERDES1 and one instance of PCIe namely PCIe0. Both SERDES0 and SERDES1 are single lane SERDES. The PCIe0 instance of PCIe is a Gen3 single lane PCIe controller. Since SERDES and PCIe are not present on AM62P SoC, add the device-tree nodes corresponding to them in the J722S SoC specific "k3-j722s-main.dtsi" file. Co-developed-by: Ravi Gunasekaran Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros --- v6: https://lore.kernel.org/r/20240612132409.2477888-8-s-vadapalli@ti.com/ No changes since v6. arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 133 ++++++++++++++++++++++ 1 file changed, 133 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 84378fc839d6..b16f3a7cb109 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -5,7 +5,123 @@ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ */ +#include +#include + +/ { + serdes_refclk: clk-0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; +}; + &cbass_main { + serdes_wiz0: phy@f000000 { + compatible = "ti,am64-wiz-10g"; + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <1>; + #reset-cells = <1>; + #clock-cells = <1>; + + assigned-clocks = <&k3_clks 279 1>; + assigned-clock-parents = <&k3_clks 279 5>; + + serdes0: serdes@f000000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x0f000000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 279 1>, + <&k3_clks 279 1>, + <&k3_clks 279 1>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; /* Needs lane config */ + }; + }; + + serdes_wiz1: phy@f010000 { + compatible = "ti,am64-wiz-10g"; + ranges = <0x0f010000 0x0 0x0f010000 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <1>; + #reset-cells = <1>; + #clock-cells = <1>; + + assigned-clocks = <&k3_clks 280 1>; + assigned-clock-parents = <&k3_clks 280 5>; + + serdes1: serdes@f010000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x0f010000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz1 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 280 1>, + <&k3_clks 280 1>, + <&k3_clks 280 1>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; /* Needs lane config */ + }; + }; + + pcie0_rc: pcie@f102000 { + compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x0f102000 0x00 0x1000>, + <0x00 0x0f100000 0x00 0x400>, + <0x00 0x0d000000 0x00 0x00800000>, + <0x00 0x68000000 0x00 0x00001000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, + <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + max-link-speed = <3>; + num-lanes = <1>; + power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>; + clock-names = "fck", "pcie_refclk"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb010>; + cdns,no-bar-match-nbits = <64>; + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + status = "disabled"; + }; + usbss1: usb@f920000 { compatible = "ti,j721e-usb"; reg = <0x00 0x0f920000 0x00 0x100>; @@ -38,3 +154,20 @@ usb1: usb@31200000{ }; }; }; + +&main_conf { + serdes_ln_ctrl: mux-controller@4080 { + compatible = "reg-mux"; + reg = <0x4080 0x14>; + #mux-control-cells = <1>; + mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */ + <0x10 0x3>; /* SERDES1 lane0 select */ + }; +}; + +&wkup_conf { + pcie0_ctrl: pcie0-ctrl@4070 { + compatible = "ti,j784s4-pcie-ctrl", "syscon"; + reg = <0x4070 0x4>; + }; +}; From patchwork Sat Jun 15 08:15:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13699250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B568EC27C4F for ; Sat, 15 Jun 2024 08:17:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=0ziaYmVur7op8ucU8cI+8HtuOL9QhJ+JrBtiZA7l/Tc=; b=sNlqk6CvfHkdF5QvOVtCZTQiY8 6d++sPKYPNBnboGr7rLIng3nEqCDI6h7FkY08DaCs/OWCQmepKfs9VMUZCFqeVeA6FbcYimWOwW5D +tb9J2SUerpLChAgrZ46uXDnxfcp37XBVdUdymxrX6Kuu/6/J9ciFkrvADqck8YTA6VRAnhjhYH9W AwcvKcBVU58q6smUbqxFYaHyQ+57Tt1M2b9FzH67OGFvw+HiumKpvaMkefThDSCiX0tXlC9zIbber rJrqsCxuK62EWap0EsVO473v9GtxbTp9bJ0AefZEyE4tHhJRn0Imy3blqL5Gv9yNvXHeAPYdcfcDs x94jfVlw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOb3-00000004zV2-3S5v; Sat, 15 Jun 2024 08:17:13 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOaV-00000004z8l-1OV0 for linux-arm-kernel@lists.infradead.org; Sat, 15 Jun 2024 08:16:40 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45F8Gan8102762; Sat, 15 Jun 2024 03:16:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718439396; bh=0ziaYmVur7op8ucU8cI+8HtuOL9QhJ+JrBtiZA7l/Tc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LnfcB8dDm4KcFjS4NxnGDHaC92gT7yGH9msHSQAIFItTJXX4AxggZmpgKC3tS5CET ZoSyk/R8fW4ORwC01z4jGHrwSC+OObF6sA2fxJBfthj5pdFsr4aYdd5watXNvjrGhs dKUi+dlelScwLuW2sjnwG2BMJGMUgadELh8ufBfA= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45F8Gamt032382 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 15 Jun 2024 03:16:36 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 15 Jun 2024 03:16:36 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 15 Jun 2024 03:16:36 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45F8G1Qb024463; Sat, 15 Jun 2024 03:16:32 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v7 7/8] arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM Date: Sat, 15 Jun 2024 13:45:59 +0530 Message-ID: <20240615081600.3602462-8-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240615081600.3602462-1-s-vadapalli@ti.com> References: <20240615081600.3602462-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240615_011639_491993_7577A792 X-CRM114-Status: GOOD ( 11.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable PCIe0 instance of PCIe in Root Complex mode of operation with Lane 0 of the SERDES1 instance of SERDES. Also enable USB0 instance of USB to interface with the Type-C port via the USB hub, by configuring the pin P05 of the GPIO expander on the EVM. Enable USB1 instance of USB in SuperSpeed mode of operation with Lane 0 of the SERDES0 instance of SERDES. Co-developed-by: Ravi Gunasekaran Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros --- v6: https://lore.kernel.org/r/20240612132409.2477888-9-s-vadapalli@ti.com/ No changes since v6. arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 73 +++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index bf3c246d13d1..253b02f0437d 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -9,7 +9,9 @@ /dts-v1/; #include +#include #include "k3-j722s.dtsi" +#include "k3-serdes.h" / { compatible = "ti,j722s-evm", "ti,j722s"; @@ -202,6 +204,12 @@ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ >; }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */ + >; + }; }; &cpsw3g { @@ -301,6 +309,13 @@ exp1: gpio@23 { "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#", "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN", "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ"; + + p05-hog { + /* P05 - USB2.0_MUX_SEL */ + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + }; }; }; @@ -384,3 +399,61 @@ &sdhci1 { status = "okay"; bootph-all; }; + +&serdes_ln_ctrl { + idle-states = , + ; +}; + +&serdes0 { + status = "okay"; + serdes0_usb_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes1 { + status = "okay"; + serdes1_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz1 1>; + }; +}; + +&pcie0_rc { + reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + status = "okay"; +}; + +&usbss0 { + ti,vbus-divider; + status = "okay"; +}; + +&usb0 { + dr_mode = "otg"; + usb-role-switch; +}; + +&usbss1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; + ti,vbus-divider; + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; From patchwork Sat Jun 15 08:16:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13699249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E8A32C27C53 for ; Sat, 15 Jun 2024 08:17:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=wYV0w24FLbCMNWLBLOQScHdj5lLyqEpYd5opKjq9pi4=; b=Noi5k46AOspwk4VFM30rWD51c+ FGTP7Um2xPt3c90JcKqyX/zE8CPhKZsQITFgIS6aGC47/axGzhFuUPS25wAeicfV7aDRR6dUsB86a AflrpWSgoO4dPTlvuIb6TXvA1VLcecx+gUvAlxGjCeAigBQhK+wa0j/QzM2X9UQDQHSwnGVPOES5f Tc9ZqKvYAyHwzvA0F/0beShGOhXg9cD0PIqnTmy7L+VFgSnNfwXBOKX2IYmfOlDk7q1geX1RZMz59 f0hR/UYhwhFehJ2XSW5QSoMnjwhUjFrFyjDpdzlynN/tVwTNrY3iXJbS4wBxANsTqEV+8bWhty4ae kwQoX3dA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOb4-00000004zVp-2iTY; Sat, 15 Jun 2024 08:17:14 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOay-00000004zS1-10dY for linux-arm-kernel@bombadil.infradead.org; Sat, 15 Jun 2024 08:17:08 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Type:Content-Transfer-Encoding :MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From: Sender:Reply-To:Content-ID:Content-Description; bh=wYV0w24FLbCMNWLBLOQScHdj5lLyqEpYd5opKjq9pi4=; b=QdGVuSOUL8VVN+FXZGY5/MbGV6 ubloAdD19IhFQgINXswdHW4FK8EtC8SlibU2OHOygvEh94Z0MQO9gvnpAefLp6snDXdtzs0ltCfDn /ZgajBbYvMizbGuawNFjAwIXRX9HUTglDDgGh2yD/EQz0t909f4Irekv1d5JGfCESd9XPPMeTs5vW L/RuYsbxdWp0dVvutK7jPOY1VBIe6BfIT/YAMevUSJdJh8u7YC3RTwfL8cyce/ulc0SW2YQec00hz ICz8LyINhXk1AUy4zSvnfJljQ7N2FeEol4eJrmUjDZpyHbwCCzFSqWHK1ilXLmevbvEOwKtk/ycba YNPS4uAg==; Received: from fllv0016.ext.ti.com ([198.47.19.142]) by desiato.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sIOah-00000004tMf-1mfu for linux-arm-kernel@lists.infradead.org; Sat, 15 Jun 2024 08:17:06 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45F8GeIE102773; Sat, 15 Jun 2024 03:16:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718439400; bh=wYV0w24FLbCMNWLBLOQScHdj5lLyqEpYd5opKjq9pi4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tZlGK7eI0CCXEekWn6MhTVN3prvDPm/9yrJ1uVSbIzMerGR9CwYglJ8LKw9DvwpwH Y946dxYUMKqBwI3gAyraU5eIowX+U05dCBFfsEQ59FWaSBJhF/Wqn1Alb9/QRdIAgZ /leUfA6PmAMzseLpJkHP0iEZtIHDN81wCSIl9JoY= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45F8GeDJ063961 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 15 Jun 2024 03:16:40 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 15 Jun 2024 03:16:40 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 15 Jun 2024 03:16:40 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45F8G1Qc024463; Sat, 15 Jun 2024 03:16:36 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v7 8/8] arm64: dts: ti: k3-am62p-j722s: Move SoC-specific node properties Date: Sat, 15 Jun 2024 13:46:00 +0530 Message-ID: <20240615081600.3602462-9-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240615081600.3602462-1-s-vadapalli@ti.com> References: <20240615081600.3602462-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240615_091658_181682_91942F30 X-CRM114-Status: GOOD ( 10.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Certain device-tree node properties of shared device-tree nodes are different between the AM62P and J722S SoCs. To avoid overriding the properties and to avoid redefining the nodes in the k3-{soc}-main.dtsi having such SoC specific properties, move the properties to the SoC specific k3-{soc}-main.dtsi files. Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros --- This patch has been introduced in this series and hence doesn't have a Changelog. This patch replaces the v6 patch: arm64: dts: ti: k3-j722s: Move MAIN domain overrides to k3-j722s-main.dtsi based on Roger's suggestion at: https://lore.kernel.org/r/d4c33ee4-1e91-40e5-90c8-bd793bcf34ff@kernel.org/ .../dts/ti/k3-am62p-j722s-common-main.dtsi | 5 ----- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-j722s.dtsi | 19 ------------------- 4 files changed, 34 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 870c95081ef5..e787f9386eb5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -8,10 +8,8 @@ &cbass_main { oc_sram: sram@70000000 { compatible = "mmio-sram"; - reg = <0x00 0x70000000 0x00 0x10000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x00 0x00 0x70000000 0x10000>; }; gic500: interrupt-controller@1800000 { @@ -92,7 +90,6 @@ inta_main_dmss: interrupt-controller@48000000 { msi-controller; ti,sci = <&dmsc>; ti,sci-dev-id = <28>; - ti,interrupt-ranges = <5 69 35>; ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; }; @@ -539,7 +536,6 @@ main_gpio0: gpio@600000 { <193>, <194>, <195>; interrupt-controller; #interrupt-cells = <2>; - ti,ngpio = <92>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 77 0>; @@ -556,7 +552,6 @@ main_gpio1: gpio@601000 { <183>, <184>, <185>; interrupt-controller; #interrupt-cells = <2>; - ti,ngpio = <52>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 78 0>; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index 9caab7db5440..f8a7f0cbd327 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -32,3 +32,20 @@ usb1: usb@31100000 { }; }; }; + +&oc_sram { + reg = <0x00 0x70000000 0x00 0x10000>; + ranges = <0x00 0x00 0x70000000 0x10000>; +}; + +&inta_main_dmss { + ti,interrupt-ranges = <5 69 35>; +}; + +&main_gpio0 { + ti,ngpio = <92>; +}; + +&main_gpio1 { + ti,ngpio = <52>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index b16f3a7cb109..228c6c89245c 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -171,3 +171,20 @@ pcie0_ctrl: pcie0-ctrl@4070 { reg = <0x4070 0x4>; }; }; + +&oc_sram { + reg = <0x00 0x70000000 0x00 0x40000>; + ranges = <0x00 0x00 0x70000000 0x40000>; +}; + +&inta_main_dmss { + ti,interrupt-ranges = <7 71 21>; +}; + +&main_gpio0 { + ti,ngpio = <87>; +}; + +&main_gpio1 { + ti,ngpio = <73>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi index 705b99e35f05..14c6c6a332ef 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -232,22 +232,3 @@ cbass_wakeup: bus@b00000 { /* Include J722S specific peripherals */ #include "k3-j722s-main.dtsi" - -/* Main domain overrides */ - -&inta_main_dmss { - ti,interrupt-ranges = <7 71 21>; -}; - -&main_gpio0 { - ti,ngpio = <87>; -}; - -&main_gpio1 { - ti,ngpio = <73>; -}; - -&oc_sram { - reg = <0x00 0x70000000 0x00 0x40000>; - ranges = <0x00 0x00 0x70000000 0x40000>; -};