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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044F3.mail.protection.outlook.com (10.167.241.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7677.15 via Frontend Transport; Mon, 17 Jun 2024 20:04:35 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 17 Jun 2024 15:04:34 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , CC: Bjorn Helgaas , Subject: [RFC PATCH 1/9] PCI/AER: Update AER driver to call root port and downstream port UCE handlers Date: Mon, 17 Jun 2024 15:04:03 -0500 Message-ID: <20240617200411.1426554-2-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240617200411.1426554-1-terry.bowman@amd.com> References: <20240617200411.1426554-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F3:EE_|DS0PR12MB7771:EE_ X-MS-Office365-Filtering-Correlation-Id: e58444e7-03bc-45b9-5c50-08dc8f08b63a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|376011|7416011|36860700010|1800799021|82310400023|921017; X-Microsoft-Antispam-Message-Info: iD7a1SFXbbi2gOuYIOFa8M/2RtMT0ZA2kuz2Qo5SnypwJZ8/SeCtucrZU02otwHs057ziJLqLqevlYrCdW40mlvCFaxOEBTSAk7ScW8IPM7f66dtvPsHkhdEnQ6/YFXV7tXgLwbr/Z7S1nOF582w3o/PEGY20GsBaHjQUrVmd8H94cyaclbLgbdSMa3aP2lBMqkTx9vkKmRV5hpf/bmbLii+dCSZiD+q68pa+KWbNU8UHTgDbPy0NucOSGLl8zygA/Ao1FVSmT7a37NpHudwXF7NeFDd5GYNXfVWnAm/PDSCGynsEf0jCwGRAHpGUOzAqYzjkP/dCShK2ygxdKksHOri2QpWJEkdo3w8yJIZRj5KEOD2dDzKpyUtcPBuKrZNWSMgV3dJKnyuzMpMsppYi8rjL7fD3comybDzecC3Idp9jvL6E9VtmI0KMxoA9vpOMCCIYz9Zbb0J2KVfpJnJSJ5crmTkV5x9nMReVh4l8OZn0izMwHqUyJ6AYfMkdvLiaalld9/p47SUidWgXhWsMlFYzKCM0uGNJ67PYxbiR2GFDg0U751OSGerRSJXLcQ9qUzlrKZvgirk0JhJ9nsxuQe5cXhP595JCPHRcfD32D4ecFp24Xs4QRQvaUZ3wqX3AM03nrBNDQ7VgfLpcLjeAnArWkx/SSSzbzuEf6FmcPmWWOo+NdGEH5R0mnYq7k02JMYyZqch32WH7oJr380qgO4wQcA593PUWfywyZ783uSaD0CL4BR6oRl3CCAft/ZVaIu5Kl8cuKen9HuGLIjvGG6P9lJVBA0EevJj7v0eUcLQIvzVB5DT4wt5om399jTyV7upkud70E9bztB5kQ5SoO0WRY697pNwd+Z+wAdbbuVN4iZucpO/FCsetG8/YfF6HOxx/QIJpUQuohjguxvRMXvRDgvYgAziGoGuMPzK1xD5NF5lcLh0cVktYRwMEFjgQ1mrzSPKg5ErSamesw1pkfNJ9ghWsAE2/5TFXLqyynqLPam+//dL12oOaDSa04x1V8YMM90FHH+sUps3th5z+9tweTocmfNUk3Oay+ZUFUTEBoSLsj5AYZmAAlQTU56w57w/1nDkz3z7GmxZ1NSkwHOCgf7o5bQU0Tn1AW9PDzz6DKZpP2FlHJbQwEI0qi93uMELyEJlPZYHHgms0lpwLIVpRrhWZQb+XpDWVzPSdwbZI4bU+iKz032F7pW6xA9BSbz4lDXMWu9M10N5N/t6/BJpMmBDzF9Ffk8ru1XxyiYlzSmIssmOCV593QjudLASMhwcpImZ7EPodmuaCqrSZ2CPS3q52sAL4yy0MaUJjCVIHR+EE4XEc5S2IeMRp4y/h+E/rF3yXfpszv2mXLEuJ3OYX6CTwrAmka+wOZOhPiKRyimH1hKlg5mOE2w0un0rtPWoZy+6dXFrHF8kCfU1uKvpVNIzfUhF2TixJoRnKno= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(376011)(7416011)(36860700010)(1800799021)(82310400023)(921017);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2024 20:04:35.7993 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e58444e7-03bc-45b9-5c50-08dc8f08b63a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7771 The AER service driver does not currently call a handler for AER uncorrectable errors (UCE) detected in root ports or downstream ports. This is not needed in most cases because common PCIe port functionality is handled by portdrv service drivers. CXL root ports include CXL specific RAS registers that need logging before starting do_recovery() in the UCE case. Update the AER service driver to call the UCE handler for root ports and downstream ports. These PCIe port devices are bound to the portdrv driver that includes a CE and UCE handler to be called. Signed-off-by: Terry Bowman Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org --- drivers/pci/pcie/err.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c index 705893b5f7b0..a4db474b2be5 100644 --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c @@ -203,6 +203,26 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, pci_ers_result_t status = PCI_ERS_RESULT_CAN_RECOVER; struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); + /* + * PCIe ports may include functionality beyond the standard + * extended port capabilities. This may present a need to log and + * handle errors not addressed in this driver. Examples are CXL + * root ports and CXL downstream switch ports using AER UIE to + * indicate CXL UCE RAS protocol errors. + */ + if (type == PCI_EXP_TYPE_ROOT_PORT || + type == PCI_EXP_TYPE_DOWNSTREAM) { + struct pci_driver *pdrv = dev->driver; + + if (pdrv && pdrv->err_handler && + pdrv->err_handler->error_detected) { + const struct pci_error_handlers *err_handler; + + err_handler = pdrv->err_handler; + status = err_handler->error_detected(dev, state); + } + } + /* * If the error was detected by a Root Port, Downstream Port, RCEC, * or RCiEP, recovery runs on the device itself. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2024 20:04:50.0057 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eefab12b-fdee-46f4-7899-08dc8f08beb4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066E6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6949 The AER service driver clears the AER correctable error (CE) status before calling the correctable error handler. This results in the error's status not correctly reflected if read from the CE handler. The AER CE status is needed by the portdrv's CE handler. The portdrv's CE handler is intended to only call the registered notifier callbacks if the CE error status has correctable internal error (CIE) set. This is not a problem for AER uncorrrectbale errors (UCE). The UCE status is still present in the AER capability and available for reading, if needed, when the UCE handler is called. Change the order of clearing the CE status and calling the CE handler. Make it to call the CE handler first and then clear the CE status after returning. Signed-off-by: Terry Bowman Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org Reviewed-by: Jonathan Cameron Acked-by: Dan Williams --- drivers/pci/pcie/aer.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index ac6293c24976..4dc03cb9aff0 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1094,9 +1094,6 @@ static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info) * Correctable error does not need software intervention. * No need to go through error recovery process. */ - if (aer) - pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, - info->status); if (pcie_aer_is_native(dev)) { struct pci_driver *pdrv = dev->driver; @@ -1105,6 +1102,10 @@ static void pci_aer_handle_error(struct pci_dev *dev, struct aer_err_info *info) pdrv->err_handler->cor_error_detected(dev); pcie_clear_device_status(dev); } + if (aer) + pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, + info->status); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2024 20:04:58.0713 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a44170a4-087f-413c-cbfa-08dc8f08c380 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8294 PCIe port devices are bound to portdrv, the PCIe port bus driver. portdrv does not implement an AER correctable handler (CE) but does implement the AER uncorrectable error (UCE). The UCE handler is fairly straightforward in that it only checks for frozen error state and returns the next step for recovery accordingly. As a result, port devices relying on AER correctable internal errors (CIE) and AER uncorrectable internal errors (UIE) will not be handled. Note, the PCIe spec indicates AER CIE/UIE can be used to report implementation specific errors.[1] CXL root ports, CXL downstream switch ports, and CXL upstream switch ports are examples of devices using the AER CIE/UIE for implementation specific purposes. These CXL ports use the AER interrupt and AER CIE/UIE status to report CXL RAS errors.[2] Add an atomic notifier to portdrv's CE/UCE handlers. Use the atomic notifier to report CIE/UIE errors to the registered functions. This will require adding a CE handler and updating the existing UCE handler. For the UCE handler, the CXL spec states UIE errors should return need reset: "The only method of recovering from an Uncorrectable Internal Error is reset or hardware replacement."[1] [1] PCI6.0 - 6.2.10 Internal Errors [2] CXL3.1 - 12.2.2 CXL Root Ports, Downstream Switch Ports, and Upstream Switch Ports Signed-off-by: Terry Bowman Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org --- drivers/pci/pcie/portdrv.c | 32 ++++++++++++++++++++++++++++++++ drivers/pci/pcie/portdrv.h | 2 ++ 2 files changed, 34 insertions(+) diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c index 14a4b89a3b83..86d80e0e9606 100644 --- a/drivers/pci/pcie/portdrv.c +++ b/drivers/pci/pcie/portdrv.c @@ -37,6 +37,9 @@ struct portdrv_service_data { u32 service; }; +ATOMIC_NOTIFIER_HEAD(portdrv_aer_internal_err_chain); +EXPORT_SYMBOL_GPL(portdrv_aer_internal_err_chain); + /** * release_pcie_device - free PCI Express port service device structure * @dev: Port service device to release @@ -745,11 +748,39 @@ static void pcie_portdrv_shutdown(struct pci_dev *dev) static pci_ers_result_t pcie_portdrv_error_detected(struct pci_dev *dev, pci_channel_state_t error) { + if (dev->aer_cap) { + u32 status; + + pci_read_config_dword(dev, dev->aer_cap + PCI_ERR_UNCOR_STATUS, + &status); + + if (status & PCI_ERR_UNC_INTN) { + atomic_notifier_call_chain(&portdrv_aer_internal_err_chain, + AER_FATAL, (void *)dev); + return PCI_ERS_RESULT_NEED_RESET; + } + } + if (error == pci_channel_io_frozen) return PCI_ERS_RESULT_NEED_RESET; return PCI_ERS_RESULT_CAN_RECOVER; } +static void pcie_portdrv_cor_error_detected(struct pci_dev *dev) +{ + u32 status; + + if (!dev->aer_cap) + return; + + pci_read_config_dword(dev, dev->aer_cap + PCI_ERR_COR_STATUS, + &status); + + if (status & PCI_ERR_COR_INTERNAL) + atomic_notifier_call_chain(&portdrv_aer_internal_err_chain, + AER_CORRECTABLE, (void *)dev); +} + static pci_ers_result_t pcie_portdrv_slot_reset(struct pci_dev *dev) { size_t off = offsetof(struct pcie_port_service_driver, slot_reset); @@ -780,6 +811,7 @@ static const struct pci_device_id port_pci_ids[] = { static const struct pci_error_handlers pcie_portdrv_err_handler = { .error_detected = pcie_portdrv_error_detected, + .cor_error_detected = pcie_portdrv_cor_error_detected, .slot_reset = pcie_portdrv_slot_reset, .mmio_enabled = pcie_portdrv_mmio_enabled, }; diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index 12c89ea0313b..8a39197f0203 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -121,4 +121,6 @@ static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {} #endif /* !CONFIG_PCIE_PME */ struct device *pcie_port_find_device(struct pci_dev *dev, u32 service); + +extern struct atomic_notifier_head portdrv_aer_internal_err_chain; #endif /* _PORTDRV_H_ */ From patchwork Mon Jun 17 20:04:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bowman, Terry" X-Patchwork-Id: 13701342 X-Patchwork-Delegate: bhelgaas@google.com Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2045.outbound.protection.outlook.com [40.107.94.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E21518FDCD; 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Mon, 17 Jun 2024 15:05:52 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , CC: Bjorn Helgaas , Subject: [RFC PATCH 8/9] PCI/AER: Export pci_aer_unmask_internal_errors() Date: Mon, 17 Jun 2024 15:04:10 -0500 Message-ID: <20240617200411.1426554-9-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240617200411.1426554-1-terry.bowman@amd.com> References: <20240617200411.1426554-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066ED:EE_|SA3PR12MB7878:EE_ X-MS-Office365-Filtering-Correlation-Id: 3fb1fedb-f156-4aca-6fc1-08dc8f08e47b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|36860700010|376011|7416011|1800799021|82310400023|921017; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2024 20:05:53.3854 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3fb1fedb-f156-4aca-6fc1-08dc8f08e47b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7878 AER correctable internal errors (CIE) and AER uncorrectable internal errors (UIE) are disabled through the AER mask register by default.[1] CXL PCIe ports use the CIE/UIE to report RAS errors and as a result need CIE/UIE enabled.[2] Change pci_aer_unmask_internal_errors() function to be exported for the CXL driver and other drivers to use. [1] PCI6.0 - 7.8.4.3 Uncorrectable [2] CXL3.1 - 12.2.2 CXL Root Ports, Downstream Switch Ports, and Upstream Switch Ports Signed-off-by: Terry Bowman Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org --- drivers/pci/pcie/aer.c | 3 ++- include/linux/aer.h | 6 ++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 4dc03cb9aff0..d7a1982f0c50 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -951,7 +951,7 @@ static bool find_source_device(struct pci_dev *parent, * Note: AER must be enabled and supported by the device which must be * checked in advance, e.g. with pcie_aer_is_native(). */ -static void pci_aer_unmask_internal_errors(struct pci_dev *dev) +void pci_aer_unmask_internal_errors(struct pci_dev *dev) { int aer = dev->aer_cap; u32 mask; @@ -964,6 +964,7 @@ static void pci_aer_unmask_internal_errors(struct pci_dev *dev) mask &= ~PCI_ERR_COR_INTERNAL; pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); } +EXPORT_SYMBOL_GPL(pci_aer_unmask_internal_errors); static bool is_cxl_mem_dev(struct pci_dev *dev) { diff --git a/include/linux/aer.h b/include/linux/aer.h index 4b97f38f3fcf..a4fd25ea0280 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -50,6 +50,12 @@ static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev) static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; } #endif +#ifdef CONFIG_PCIEAER_CXL +void pci_aer_unmask_internal_errors(struct pci_dev *dev); +#else +static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { } +#endif + void pci_print_aer(struct pci_dev *dev, int aer_severity, struct aer_capability_regs *aer); int cper_severity_to_aer(int cper_severity);